Image coding method, apparatus, electronic device, and computer storage medium

Abstract

The application discloses an image coding method and device, electronic equipment and computer storage medium, and belongs to the technical field of image processing. The method comprises the following steps: reading a pixel value group of a current clock cycle from a binary image of a defect image; determining a first coding result corresponding to the pixel value group of the current clock cycle according to a corresponding relationship between the pixel value group and a preset coding result; performing in-group merging on each first coding result of an image unit according to an ending bit sequence of the highest bit and a starting bit sequence of the lowest bit in each first coding result, to obtain a second coding result of the image unit; and determining a target coding result of the defect image according to the second coding result of each image unit. Through data reading in units of pixel value groups and coding based on the corresponding relationship between the pixel value groups and the preset coding result, the effect of parallel coding can be achieved, a plurality of pixel data can be processed in one clock cycle, the delay is small, and the real-time performance is high.

Description

Technical Field

[0001] This application belongs to the field of image processing technology, and in particular relates to an image encoding method, apparatus, electronic device and computer storage medium. Background Technology

[0002] In the field of industrial defect detection, it is necessary to extract defect features. Defect images typically contain a large amount of data. To reduce the storage space occupied by defect images and decrease the computational burden on computers, run-length encoding algorithms have been introduced. The principle of run-length encoding is to merge defect data from adjacent regions and represent them with length, thereby compressing the data.

[0003] Run-length encoding schemes in related technologies are usually serial processing, which results in significant delays and poor real-time performance. Summary of the Invention

[0004] This application aims to address at least one of the technical problems existing in related technologies. To this end, this application proposes an image encoding method, apparatus, electronic device, and computer storage medium that can achieve parallel encoding with minimal latency.

[0005] In a first aspect, this application provides an image encoding method, the method comprising:

[0006] Read the pixel value group for the current clock cycle from the binarized image of the defective image; the pixel value group includes the pixel values ​​of multiple pixels read in the current cycle;

[0007] Based on the correspondence between pixel value groups and preset encoding results, the first encoding result corresponding to the pixel value group in this clock cycle is determined; the first encoding result includes at least one set of encoding pairs or is empty; each set of encoding pairs corresponds to a connected region composed of defective pixels, and each set of encoding pairs includes the start bit sequence and end bit sequence of the corresponding connected region; the start bit sequence and end bit sequence are represented by hexadecimal encoding;

[0008] When the pixel value group in this clock cycle is the last pixel value group of the image unit, the first encoding results of the image unit are merged within the group according to the end bit order of the highest bit and the start bit order of the lowest bit in each first encoding result to obtain the second encoding result of the image unit.

[0009] The target encoding result of the defective image is determined based on the second encoding result of each image unit.

[0010] According to the image encoding method of this application, in each clock cycle, the pixel value group of the current clock cycle is read from the binarized image of the defective image. By determining the first encoding result corresponding to the pixel value group of the current clock cycle based on the correspondence between the pixel value group and the preset encoding result, the effect of parallel encoding can be achieved by reading data in units of pixel value groups and encoding based on the correspondence between the pixel value group and the preset encoding result. This enables the processing of multiple pixel data in one clock cycle, resulting in less latency and higher real-time performance.

[0011] Furthermore, by merging the first encoding results of each image unit within each group according to the end order of the highest bit and the start order of the lowest bit in each first encoding result of each pixel value group, the segmented connected regions can be merged, thereby improving the image compression effect.

[0012] According to one embodiment of this application, determining the first encoding result corresponding to the pixel value group in the current clock cycle based on the correspondence between pixel value groups and preset encoding results includes:

[0013] A first target data table is determined from multiple first data tables to have a mapping relationship with the group identifier of the pixel value group; the first data table includes a first number of first data rows, which are used to record the correspondence between the pixel value group and the preset encoding result; the group identifier is generated based on the start position and end position of each pixel in the corresponding pixel value group; the first number is determined according to the number of pixel values ​​contained in the pixel value group;

[0014] Using the pixel value group of the current clock cycle as the first index, query the first target data row from the first target data table;

[0015] The preset encoding result in the first target data row is determined to be the first encoding result corresponding to the pixel value group in this clock cycle.

[0016] According to one embodiment of this application, the first encoding results of an image unit are merged within a group based on the end order of the most significant bit and the start order of the least significant bit in each first encoding result, including:

[0017] When an image unit corresponds to at least two first encoding results, the first encoding results of two adjacent clock cycles are traversed based on the order of clock cycles; each traversal of the two clock cycles includes the first clock cycle and the second clock cycle; the first clock cycle is earlier than the second clock cycle.

[0018] If the end position of the most significant bit in the first encoding result of the first clock cycle and the start position of the least significant bit in the first encoding result of the second clock cycle are adjacent, the first encoding results of the two clock cycles are merged to obtain a new first encoding result for the new clock cycle. The new first encoding result does not include the first encoding pair and the second encoding pair. The first encoding pair is the encoding pair containing the end position of the most significant bit in the first encoding result of the first clock cycle. The second encoding pair is the encoding pair containing the start position of the least significant bit in the first encoding result of the second clock cycle. The new first encoding result includes a third encoding pair. The start position of the third encoding pair is the start position of the first encoding pair. The end position of the third encoding pair is the end position of the second encoding pair.

[0019] If the end order of the most significant bit in the first encoding result corresponding to the first clock cycle is not adjacent to the start order of the least significant bit in the first encoding result corresponding to the second clock cycle, the first encoding result of the next set of clock cycles is traversed.

[0020] With the first encoding result of the last clock cycle of the image unit already traversed, the first encoding results of each image unit are concatenated and arranged to obtain the second encoding result of the image unit.

[0021] According to one embodiment of this application, determining the target coding result of a defective image based on the second coding result of each image unit includes:

[0022] For the second encoding result of the image unit obtained in each clock cycle, add the encoding corresponding to the unit identifier of the image unit to the least significant bit of the second encoding result, and add the encoding corresponding to the end identifier of the unit encoding of the image unit to the most significant bit to obtain the third encoding result;

[0023] The third encoding results of all image units in the binarized image are concatenated to obtain the fourth encoding result;

[0024] Add the image end identifier corresponding to the high-order bits of the fourth encoding result to obtain the target encoding result of the defective image.

[0025] According to one embodiment of this application, each third encoding result is written to a register group of the FPGA; each register group includes multiple registers;

[0026] The third encoding results of all image units in the binarized image are concatenated, including:

[0027] Based on the order from least significant bit to most significant bit, each pair of register groups is accessed sequentially; each pair of register groups consists of two adjacent register groups.

[0028] The accessed register pairs are bit-merged to concatenate the third-encoded results.

[0029] According to one embodiment of this application, after obtaining the target encoding result of the defect image, the method further includes:

[0030] Obtain the length of the target defect in the filtering rules;

[0031] Based on the start and end positions of each coding pair in the target coding result, determine the defect length of the corresponding connectivity defect for each coding pair;

[0032] The corresponding encoding pairs of connected regions whose defect length is less than the target defect length are identified as the fourth encoding pairs to be deleted.

[0033] The fourth coding pair is removed from the target coding result to obtain the filtered target coding result.

[0034] According to one embodiment of this application, before reading the pixel value group of the current clock cycle from the binarized image of the defective image, the method further includes:

[0035] Obtain the defect image to be processed;

[0036] The defect image is binarized to obtain a binary image;

[0037] In the binarized image, there is at least one defective pixel.

[0038] Secondly, this application provides an image encoding apparatus, the apparatus comprising:

[0039] The first processing module is used to read the pixel value group for the current clock cycle from the binarized image of the defect image; the pixel value group includes the pixel values ​​of multiple pixels read in the current cycle;

[0040] The second processing module is used to determine the first encoding result corresponding to the pixel value group in the current clock cycle based on the correspondence between the pixel value group and the preset encoding result; the first encoding result includes at least one set of encoding pairs or is empty; each set of encoding pairs is for a connected region composed of defective pixels, and each set of encoding pairs includes the start position and end position of the corresponding connected region; the start position and end position are represented by hexadecimal encoding;

[0041] The third processing module is used to merge the first encoding results of the image unit within the group according to the end order of the highest bit and the start order of the lowest bit in each first encoding result when the pixel value group in the current clock cycle is the last pixel value group of the image unit, so as to obtain the second encoding result of the image unit.

[0042] The fourth processing module is used to determine the target encoding result of the defective image based on the second encoding result of each image unit.

[0043] According to the image encoding apparatus of this application, in each clock cycle, the pixel value group of the current clock cycle is read from the binarized image of the defective image. By determining the first encoding result corresponding to the pixel value group of the current clock cycle based on the correspondence between the pixel value group and the preset encoding result, the parallel encoding effect can be achieved by reading data in units of pixel value groups and encoding based on the correspondence between the pixel value group and the preset encoding result. This enables the processing of multiple pixel data in one clock cycle, resulting in less latency and higher real-time performance.

[0044] Furthermore, by merging the first encoding results of each image unit within each group according to the end order of the highest bit and the start order of the lowest bit in each first encoding result of each pixel value group, the segmented connected regions can be merged, thereby improving the image compression effect.

[0045] Thirdly, this application provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the image encoding method provided in the first aspect above.

[0046] Fourthly, this application provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the image encoding method provided in the first aspect above.

[0047] Fifthly, this application provides a chip including a processor and a communication interface coupled to the processor, the processor being used to run programs or instructions to implement the image encoding method provided in the first aspect.

[0048] In a sixth aspect, this application provides a computer program product, including a computer program that, when executed by a processor, implements the image encoding method provided in the first aspect above.

[0049] The above-described one or more technical solutions in the embodiments of this application have at least one of the following technical effects:

[0050] In each clock cycle, the pixel value group of the current clock cycle is read from the binarized image of the defect image. By determining the correspondence between the pixel value group and the preset encoding result, the first encoding result corresponding to the pixel value group of the current clock cycle is determined. That is, by reading data in units of pixel value groups and encoding based on the correspondence between pixel value groups and preset encoding results, the effect of parallel encoding can be achieved, enabling multiple pixel data to be processed in one clock cycle, resulting in less latency and higher real-time performance.

[0051] Furthermore, by merging the first encoding results of each image unit within each group according to the end order of the highest bit and the start order of the lowest bit in each first encoding result of each pixel value group, the segmented connected regions can be merged, thereby improving the image compression effect.

[0052] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0053] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0054] Figure 1 This is one of the flowcharts illustrating the image encoding method provided in the embodiments of this application;

[0055] Figure 2 This is a schematic diagram of a binarized image provided in an embodiment of this application;

[0056] Figure 3 This is a schematic diagram of the encoding format of the image encoding provided in the embodiments of this application;

[0057] Figure 4 This is a schematic diagram illustrating the effective bit merging of each register group provided in an embodiment of this application;

[0058] Figure 5 This is a second schematic flowchart of the image encoding method provided in the embodiments of this application;

[0059] Figure 6 This is a schematic diagram of the structure of the image encoding device provided in the embodiments of this application;

[0060] Figure 7 This is a schematic diagram of the structure of the electronic device provided in the embodiments of this application. Detailed Implementation

[0061] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0062] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0063] The image encoding method, image encoding device, electronic device, and readable storage medium provided in this application will be described in detail below with reference to the accompanying drawings and through specific embodiments and application scenarios.

[0064] The image encoding method can be applied to the terminal, and can be executed by the hardware or software in the terminal.

[0065] The image encoding method provided in this application embodiment can be executed by an electronic device or a functional module or entity in an electronic device that can implement the image encoding method. The electronic devices mentioned in this application embodiment include, but are not limited to, mobile phones, tablets, computers, cameras, and wearable devices. The image encoding method provided in this application embodiment will be described below using an electronic device as the execution subject as an example.

[0066] like Figure 1 As shown, the image encoding method includes steps 110, 120, 130 and 140.

[0067] Step 110: Read the pixel value group for the current clock cycle from the binarized image of the defect image; the pixel value group includes the pixel values ​​of multiple pixels read in the current cycle; the pixel value of the defect pixel is the first pixel value.

[0068] The defect image in this application refers to an image of a target object exhibiting a defect. In the field of industrial inspection, the target object can be an industrial product. Defects can include cracks, fissures, and holes, etc.

[0069] In this embodiment of the application, a binarized image can be obtained by binarizing the defect image. The binarized image is a black and white image.

[0070] Specifically, a defect threshold can be set. For any pixel in the defective image, if the pixel value of the pixel is higher than the pixel value threshold, the pixel at the same position in the binarized image can be set to the first pixel value, which is 1. If the pixel value of the pixel is not higher than the pixel value threshold, the pixel at the same position in the binarized image can be set to the second pixel value, which is 0.

[0071] A clock cycle refers to a complete oscillation cycle of a clock signal in a computer system. It is typically defined as the time interval between the rising edge (or falling edge) and the next edge of the same type (the next rising edge). It is the most basic unit of time in CPUs and digital circuits, used to synchronize all hardware operations.

[0072] Image compression can be achieved by encoding the binarized image. At each clock cycle, the pixel value group for that clock cycle is read from the binarized image.

[0073] Pixel value groups can be read according to image units. An image unit can include multiple pixel value groups, such as 10. A pixel value group includes the pixel values ​​of multiple pixels. The number of multiple pixel values ​​is determined based on the number of taps in the FPGA. The number of taps is usually 4, 8, 16, and 32, etc. When the number of taps in the FPGA is 8, the number of pixel values ​​in a pixel value group is also 8.

[0074] An image unit can be a row or column of pixels. Typically, pixel values ​​are read row by row, meaning an image unit is usually a row of pixels.

[0075] Each pixel in the pixel value group is either a defective pixel or a normal pixel (non-defective pixel). The pixel value of a defective pixel is the first pixel value, which is 1. The pixel value of a non-defective pixel is the second pixel value, which is 0.

[0076] See Figure 2 This application provides a schematic diagram of a binarized image, wherein the first data row, the second data row, and the third data row are 11000011, 11111111, and 11000011, respectively, where "1" represents the pixel value of a defective pixel and "0" represents the pixel value of a normal pixel.

[0077] Step 120: Based on the correspondence between pixel value groups and preset encoding results, determine the first encoding result corresponding to the pixel value group in this clock cycle; the first encoding result includes at least one set of encoding pairs or is empty; each set of encoding pairs corresponds to a connected region composed of defective pixels, and each set of encoding pairs includes the start position and end position of the corresponding connected region; the start position and end position are represented by hexadecimal encoding.

[0078] The embodiments of this application establish a correspondence between pixel value groups and preset encoding results, and the preset encoding result that has this correspondence with the pixel value group of the current clock cycle can be used as the first encoding result corresponding to the pixel value group of the current clock cycle.

[0079] As described in the foregoing embodiments, the pixel value of the defective pixel is the first pixel value. If there is at least one first pixel value in the pixel value group of the current clock cycle, then the first encoding result includes at least one set of encoding pairs. Each set of encoding pairs corresponds to a set of connected regions. The region composed of connected defective pixels is called a connected region. There are no pixels corresponding to the second pixel value in the connected region. Each connected region includes at least one defective pixel.

[0080] Suppose a pixel value group is "0011001". Following the order of the rightmost bit being the least significant bit and the leftmost bit being the most significant bit, we can find that the "1" in the first bit (least significant bit) is a separate connected region, while the "1"s in the fourth and fifth bits belong to a connected region, and the "0"s in the other bits belong to normal pixels.

[0081] Following the order from most significant bit to least significant bit, each coded pair includes the start and end bit sequences of the corresponding connected region. The start bit sequence is the bit sequence of the least significant defective pixel in the corresponding connected region, and the end bit sequence is the bit sequence of the most significant defective pixel. Both the start and end bit sequences are represented using hexadecimal encoding.

[0082] It should be noted that if a connected region has only one defective pixel, then the starting and ending position orders of that connected region are the same.

[0083] Specifically, assuming the pixel value of each pixel in a certain row is "1000 0011 1111 1111 11000011", the pixel value of 8 pixels is read in one clock cycle (a pixel value group includes 8 pixel values).

[0084] So, the pixel value group read in the first clock cycle is "1100 0011". With the right side being the low-order bit and the left side being the high-order bit, we can see that the 1st and 2nd pixels belong to one connected region, and the 7th and 8th pixels belong to another connected region. Encoding them in hexadecimal order from low-order bit to high-order bit gives us "0008-0007-0000-0000-0000-0000-0002-0001" ("-" has no special meaning, it's just for easy reading). 0001 and 0002 belong to one connected region, and 0007 and 0008 belong to another connected region.

[0085] The above process pertains to the encoding principle. To save encoding time, the first encoding result corresponding to the pixel value group "1100 0011" in the first clock cycle can be directly queried. This first encoding result is "0008-0007-0002-0001", which contains two sets of encoding pairs. The first set of encoding pairs is 0002-0001, representing the starting position of the least significant defective pixel in the first set of encoding pairs as 0001 and the ending position of the most significant defective pixel as 0002. The second set of encoding pairs is 0008-0007, representing the starting position of the least significant defective pixel in the second set of encoding pairs as 0007 and the ending position of the most significant defective pixel as 0008.

[0086] The pixel value group read in the second clock cycle is "1111 1111". It can be seen that the pixels corresponding to the entire pixel value group are all defective pixels, belonging to a connected group of defective pixels. Encoding them in hexadecimal order from low to high bits yields "0010-000F-000E-000D-000C-000B-000A-0009". In this case, from an encoding perspective, to save data storage space, only the starting bit sequence of the least significant defective pixel (0009, corresponding to 9 in decimal) and the ending bit sequence of the most significant defective pixel (16, corresponding to 16 in decimal) need to be recorded. Therefore, its hexadecimal encoding can be simplified to "0010-0000-0000-0000-0000-0000-0000-0009".

[0087] The above process belongs to the encoding principle. In order to save encoding time, the first encoding result corresponding to the pixel value group "1111 1111" in the second clock cycle can be directly queried. The first encoding result is "0010-0009". The first encoding result includes a set of encoding pairs. The starting position of the encoding pair is 0009 (decimal corresponding to 9), and the ending position of the encoding pair is 0010 (decimal corresponding to 16). The encoding pair indicates that the 9th to 16th pixels are all defective pixels.

[0088] The pixel value read in the third clock cycle is "1000 0011". It can be observed that pixels at positions 17, 18, and 24 are defective pixels. Pixels at positions 17 and 18 belong to a connected defect region, while pixel 24 belongs to a separate connected defect region. Encoding this in hexadecimal order from least significant bit to most significant bit yields "0018-0000-0000-0000-0000-0000-0012-0011", where 0011, 0012, and 0018 represent the bit order of the defective pixels at positions 17, 18, and 24, respectively.

[0089] The first encoding result corresponding to the pixel value group "1000 0011" in the second clock cycle can be directly queried. This first encoding result is "0018-0018-0012-0011", corresponding to two sets of encoding pairs. The first set of encoding pairs is 0012-0011, with the starting bit sequence being 0011 (decimal equivalent to 17) and the ending bit sequence being 0012 (decimal equivalent to 18). The second set of encoding pairs is 0018-0018 (decimal equivalent to 24), meaning that both the starting and ending bit sequences of the second set of encoding pairs are 0018. This indicates that when the connected region contains only one defective pixel, its starting and ending bit sequences are the same.

[0090] Furthermore, if there is no first pixel value in the pixel value group of this clock cycle, that is, if each pixel value in the pixel value group is the second pixel value (the second pixel value can be 0), it means that the pixels read in this clock cycle are not defective pixels, and the corresponding first encoding result is empty.

[0091] Any combination of pixel values ​​can be obtained through enumeration, and a preset encoding result corresponding to each pixel value group can be obtained in advance. A correspondence between the pixel value group and the corresponding preset encoding result can then be established. Subsequently, a preset encoding result corresponding to any pixel value group can be obtained based on this correspondence, and the queried preset encoding result can be used as the first encoding result. Further examples are not provided here.

[0092] Step 130: If the pixel value group in this clock cycle is the last pixel value group of the image unit, merge the first encoding results of the image unit within the group according to the end order of the highest bit and the start order of the lowest bit in each first encoding result to obtain the second encoding result of the image unit.

[0093] When there is only one first encoding result for an image unit (such as a pixel row or pixel column), there is no need to merge the various encoding results.

[0094] However, it is understandable that since the number of pixels read in one clock cycle is limited, for example, 8 pixels are read in one clock cycle, and a pixel row usually has more pixels, such as 480 pixels, it means that a pixel row usually requires multiple clock cycles to read. In this case, there are multiple first encoding results. The pixel value groups of two adjacent clock cycles may originally be connected, but because they belong to different clock cycles, they may belong to different encoding pairs in different first encoding results. In this case, it is necessary to merge the first encoding results of these two adjacent clock cycles.

[0095] For example, a pixel row can be represented as "1111 1111 1111 0001". Following the order from least significant bit to most significant bit, the first clock cycle reads the pixel value group "1111 0001", and its corresponding first encoding result is "0008-0005-0001-0001". The second clock cycle reads the pixel value group "1111 1111", and its corresponding first encoding result is "0010-0009". It can be seen that the pixel values ​​from the 5th to the 16th bit of this pixel row are all the first pixel value 1, that is, the 5th to 16th bits belong to a connected region. However, due to the limitation on the number of pixel values ​​read in a clock cycle, this data row is read in two clock cycles, and a connected region is split into two. In this case, the first encoding results of the two clock cycles need to be merged.

[0096] Based on the order of clock cycles, the first encoding result of two adjacent clock cycles is traversed; each traversal of two clock cycles includes the first clock cycle and the second clock cycle; the first clock cycle is earlier than the second clock cycle.

[0097] It is understandable that determining whether the first encoding results of two adjacent clock cycles can be merged is equivalent to determining whether the ending bit sequence of the most significant bit in the first encoding result of the first clock cycle and the starting bit sequence of the least significant bit in the first encoding result of the second clock cycle are adjacent.

[0098] When the two are adjacent, it means that the first coding pair containing the end of the highest bit in the first coding result of the first clock cycle and the second coding pair containing the start of the lowest bit in the first coding result of the second clock cycle are connected. The defective pixels corresponding to the first coding pair and the second coding pair belong to the same defective region. In this case, it is necessary to merge the first coding result of the first clock cycle and the first coding result of the second clock cycle to obtain a new first coding result corresponding to the new clock cycle. Then, it is determined whether the new clock cycle and the next adjacent clock cycle can be merged. The principle is the same as that of the first clock cycle and the second clock cycle, and will not be repeated here.

[0099] If the two are not adjacent, it means that the first coding pair containing the end of the highest bit in the first coding result of the first clock cycle and the coding pair containing the start of the lowest bit in the first coding result of the second clock cycle are not connected. In this case, the defective pixels corresponding to the first coding pair and the second coding pair do not belong to the same defective region. In this case, there is no need to merge them, and the first coding result of the next set of clock cycles can be traversed.

[0100] With the first encoding result of the last clock cycle of the image unit already traversed, the first encoding results of each image unit are concatenated and arranged to obtain the second encoding result of the image unit.

[0101] Step 140: Determine the target encoding result of the defective image based on the second encoding result of each image unit; the defective image includes at least one image unit, and the image unit is a pixel row or pixel column.

[0102] In this embodiment of the application, after obtaining the second encoding result of each image unit, a unit identifier and a unit encoding end identifier can be added to the second encoding result of each image unit. The unit identifier and the encoding end identifier can both be represented by hexadecimal encoding.

[0103] A cell identifier is an identifier used to uniquely indicate an image cell. For example, the cell identifier for a pixel row is called the row identifier, and the cell identifier for a pixel column is called the column identifier. For example, for an 8-tap FPGA, the row identifier for a pixel row is usually composed of 16 bits of data.

[0104] The cell encoding end marker is used to indicate the end of encoding for a certain image cell. The cell encoding end marker can be a preset structure. For example, for an 8-tap FPGA, the cell encoding end marker consists of eight 16-bit data structures, each of which is "EEEE".

[0105] In addition, an image encoding end marker needs to be added during image data stream processing to distinguish different defective images.

[0106] In practical applications, assuming that FPGA run-length encoding is processed in parallel by 8 taps, that is, 8 pixels of data are processed in parallel in one clock cycle, with a clock frequency of 250MHz, the equivalent maximum data processing volume is 1.862GB / s (compared to 0.83GB / s in traditional processing schemes).

[0107] After obtaining the target encoding result, the target encoding result can be stored, and the defect binarized image can be restored based on the target encoding result.

[0108] In this embodiment, the pixel value group of the current clock cycle is read from the binarized image of the defect image in each clock cycle. The first encoding result corresponding to the pixel value group of the current clock cycle is determined by the correspondence between the pixel value group and the preset encoding result. That is, by reading data in units of pixel value groups and encoding based on the correspondence between the pixel value group and the preset encoding result, the effect of parallel encoding can be achieved, realizing the processing of multiple pixel data in one clock cycle, resulting in less latency and higher real-time performance.

[0109] Furthermore, by merging the first encoding results of each image unit within each group according to the end order of the highest bit and the start order of the lowest bit in each first encoding result of each pixel value group, the segmented connected regions can be merged, thereby improving the image compression effect.

[0110] In some embodiments, determining the first encoding result corresponding to the pixel value group in the current clock cycle based on the correspondence between pixel value groups and preset encoding results includes:

[0111] A first target data table is determined from multiple first data tables to have a mapping relationship with the group identifier of the pixel value group; the first data table includes a first number of first data rows, which are used to record the correspondence between the pixel value group and the preset encoding result; the group identifier is generated based on the start position and end position of each pixel in the corresponding pixel value group; the first number is determined according to the number of pixel values ​​contained in the pixel value group;

[0112] Using the pixel value group of the current clock cycle as the first index, query the first target data row from the first target data table;

[0113] The preset encoding result in the first target data row is determined to be the first encoding result corresponding to the pixel value group in this clock cycle.

[0114] The embodiments of this application can use a data table to store the correspondence between the above pixel value groups and the preset encoding results.

[0115] Specifically, the group identifier of the pixel value group can be determined first. The group identifier is generated based on the start and end position of the pixel value group. For example, the group identifier can be obtained by concatenating the start and end position. It can also be obtained based on other methods, and there are no restrictions on this.

[0116] This embodiment includes multiple first data tables. The first data packet includes a first number of first data rows. The first data rows are used to record the aforementioned correspondence, that is, to record the correspondence between pixel value groups and preset encoding results.

[0117] The first quantity is determined based on the number of pixel values ​​contained within a pixel value set. Specifically, assuming a pixel value set contains 8 pixel values, each with a value of 0 or 1, then a pixel value set has 2... 8 =256 combinations, so the first number is 256; similarly, assuming a pixel value group contains 4 pixel values, then a pixel value group has 2 4 =16 combinations.

[0118] There is a mapping relationship between the first data table and the group identifier. For the current clock cycle, the first data table that has the above mapping relationship with the group identifier of the pixel value group in the current clock cycle can be identified as the first target data table.

[0119] Next, the pixel value group of the clock cycle can be used as the first index to query the first target data row from the first target data table; the preset encoding result in the first target row is the first encoding result corresponding to the pixel value group of this clock cycle.

[0120] Using the above method, the first encoding result corresponding to the pixel value group of the current clock cycle can be obtained quickly within one clock cycle, with good real-time performance.

[0121] In some embodiments, the first encoding results of the image unit are merged within a group according to the end order of the most significant bit and the start order of the least significant bit in each first encoding result, including:

[0122] When an image unit corresponds to at least two first encoding results, the first encoding results of two adjacent clock cycles are traversed based on the order of clock cycles; each traversal of the two clock cycles includes the first clock cycle and the second clock cycle; the first clock cycle is earlier than the second clock cycle.

[0123] If the end position of the most significant bit in the first encoding result of the first clock cycle and the start position of the least significant bit in the first encoding result of the second clock cycle are adjacent, the first encoding results of the two clock cycles are merged to obtain a new first encoding result for the new clock cycle. The new first encoding result does not include the first encoding pair and the second encoding pair. The first encoding pair is the encoding pair containing the end position of the most significant bit in the first encoding result of the first clock cycle. The second encoding pair is the encoding pair containing the start position of the least significant bit in the first encoding result of the second clock cycle. The new first encoding result includes a third encoding pair. The start position of the third encoding pair is the start position of the first encoding pair. The end position of the third encoding pair is the end position of the second encoding pair.

[0124] If the end order of the most significant bit in the first encoding result corresponding to the first clock cycle is not adjacent to the start order of the least significant bit in the first encoding result corresponding to the second clock cycle, the first encoding result of the next set of clock cycles is traversed.

[0125] With the first encoding result of the last clock cycle of the image unit already traversed, the first encoding results of each image unit are concatenated and arranged to obtain the second encoding result of the image unit.

[0126] As explained in the foregoing embodiments, determining whether the first encoding results of two adjacent clock cycles can be merged is to determine whether the ending bit sequence of the highest bit in the first encoding result of the first clock cycle and the starting bit sequence of the lowest bit in the first encoding result of the second clock cycle are adjacent.

[0127] When the two are adjacent, it means that the first coding pair containing the end position of the most significant bit in the first coding result of the first clock cycle and the second coding pair containing the start position of the least significant bit in the first coding result of the second clock cycle are connected. The defective pixels corresponding to the first coding pair and the second coding pair belong to the same defective region. In this case, it is necessary to merge the first coding result of the first clock cycle and the first coding result of the second clock cycle to obtain a new first coding result. That is, to merge the first coding pair and the second coding pair to obtain a third coding pair. The new first coding result includes the third coding pair, but does not include the first coding pair and the second coding pair. The start position of the third coding pair is the start position of the first coding pair; the end position of the third coding pair is the end position of the second coding pair.

[0128] Specifically, assuming the first coding pair is "0008-0005" and the second coding pair is "0010-0009", it can be found that the highest end position "0008" of the first coding pair and the lowest start position "0009" of the second coding pair are adjacent. Therefore, it can be determined that the connected regions corresponding to the first coding pair and the second coding pair belong to a larger connected region. Thus, the first coding pair and the second coding pair can be merged to obtain a third coding pair, which is "0010-0005".

[0129] Next, it is determined whether the new clock cycle and the next adjacent clock cycle can be merged. The process is similar to that of the first clock cycle and the second clock cycle, and will not be repeated here.

[0130] If the end position of the most significant bit in the first encoding result of the first clock cycle and the start position of the least significant bit in the first encoding result of the second clock cycle are not adjacent, it means that the first encoding pair containing the end position of the most significant bit in the first encoding result of the first clock cycle and the encoding pair containing the start position of the least significant bit in the first encoding result of the second clock cycle are not connected. In this case, the defective pixel points corresponding to the first encoding pair and the second encoding pair do not belong to the same connected region. In this case, there is no need to merge, and the first encoding result of the next set of clock cycles can be traversed.

[0131] After the first encoding result of the last clock cycle of the image unit has been traversed, the remaining first encoding results of the image unit can be spliced ​​and arranged, that is, integrated, to obtain the second encoding result of the image unit.

[0132] Specifically, assuming that the remaining first encoding results of a certain image unit are “0010-0006”, “0004-0003” and “0001-0001”, then the second encoding result of the image unit is “0010-0006-0004-0003-0001-0001”.

[0133] The embodiments of this application merge the first encoding results of each image unit within a group, which can effectively reduce the space occupied by the encoding results without affecting the image compression effect.

[0134] In some embodiments, determining the target coding result of the defective image based on the second coding result of each image unit includes:

[0135] For the second encoding result of the image unit obtained in each clock cycle, add the encoding corresponding to the unit identifier of the image unit to the least significant bit of the second encoding result, and add the encoding corresponding to the end identifier of the unit encoding of the image unit to the most significant bit to obtain the third encoding result;

[0136] The third encoding results of all image units in the binarized image are concatenated to obtain the fourth encoding result;

[0137] Add the image end identifier corresponding to the high-order bits of the fourth encoding result to obtain the target encoding result of the defective image.

[0138] Since an image has multiple image units, after obtaining the second encoding results of the image units corresponding to each clock cycle, the second encoding results of each image unit need to be spliced ​​together to obtain the target encoding result of the defective image.

[0139] Specifically, in order to clearly distinguish each image unit and for the purpose of image restoration, when stitching together the second encoding results of each image unit, it is necessary to add the encoding corresponding to the unit identifier of the image unit and the encoding end identifier of the unit to the second encoding results of each image unit.

[0140] As explained in the foregoing embodiments, a unit identifier is an identifier used to uniquely indicate an image unit, such as a row identifier or a column identifier; a unit encoding end identifier is used to indicate the end of encoding for a certain image unit. The unit encoding end identifier can be a preset structure, such as consisting of eight 16-bit data structures, each of which is “EEEE”.

[0141] The third encoding result can be obtained by adding the unit identifier of the image unit to the least significant bit of the second encoding result and the unit encoding end identifier of the image unit to the most significant bit.

[0142] Next, the third encoding results of all image units in the binarized image can be concatenated to obtain the fourth encoding result.

[0143] In addition, an image encoding end marker needs to be added during image data stream processing to distinguish different defective images.

[0144] See Figure 3 This application provides a schematic diagram of an image encoding format. This encoding method also belongs to run-length encoding. The image unit is a pixel row. The encoding format includes the run-length encoding of each pixel row and the image end identifier Frame_end. Each row of run-length encoding includes a row identifier Yi (Y represents the pixel row, and i can be the row number), a defect flag bit (for example, a pixel value of 1 indicates that there is a defective pixel in the pixel row), each set of encoding pairs (including the start position X_start and the end position X_end), and the unit encoding end identifier Yi_End. Yi, X_start, X_end, Yi_End, and Frame_end can all be 16 bits, the highest bit of the defect flag bit is 1 bit, Yi_end can be 8 AAAAs, and Frame_end can be 8 FFFFs.

[0145] Figure 3 The run-length encoding for the first pixel row includes: Y1 (row identifier, representing the first pixel row), 1 (defect flag is 1), X1_start (start position of the first encoding pair), X1_end (end position of the first encoding pair), ..., Xp_start (start position of the p-th encoding pair), Xp_end (end position of the p-th encoding pair), Y1_End (end identifier of the row encoding for the first pixel row). The run-length encoding for the nth pixel row includes: Yn (row identifier, representing the nth pixel row), 1 (defect flag is 1), X1_start (start position of the first encoding pair), X1_end (end position of the first encoding pair), ..., Xm_start (start position of the m-th encoding pair), Xm_end (end position of the m-th encoding pair), Yn_End (end identifier of the row encoding for the n-th pixel row).

[0146] In some embodiments, each third encoding result is written to a register group of the FPGA; each register group includes multiple registers;

[0147] The third encoding results of all image units in the binarized image are concatenated, including:

[0148] Based on the order from least significant bit to most significant bit, each pair of register groups is accessed sequentially; each pair of register groups consists of two adjacent register groups.

[0149] The accessed register pairs are bit-merged to concatenate the third-encoded results.

[0150] Since each second encoding result is stored in a register, the size of the register is usually fixed, such as an 8-bit register, a 16-bit register, a 32-bit register, and a 64-bit register.

[0151] An 8-bit register can store 8 binary bits (1 byte); a 16-bit register can store 16 binary bits (2 bytes); a 32-bit register can store 32 binary bits (4 bytes); and a 64-bit register can store 64 binary bits (8 bytes).

[0152] Each second encoding result may correspond to a register set. A register set typically includes multiple registers, and the physical bit width of the register set is sufficient to store the second encoding result with the maximum encoding length, such as 10 16-bit registers. However, each second encoding result of an image unit occupies a valid bit in the register set. The number of valid bits in a register is not always equal to the physical bit width of the register. In this case, the corresponding memory set is not full, and there are invalid bits in the register set. Invalid bits in a register refer to bits in the register that are not used or do not participate in the operation.

[0153] To reduce memory space waste, this application embodiment performs effective bit merging on each memory group. Specifically, each pair of register groups can be accessed sequentially from low bit to high bit; each pair of register groups includes two adjacent register groups; effective bit merging is performed on each accessed pair of register groups, thereby splicing the third encoding results.

[0154] Merging of valid bits between register groups refers to treating the valid bits of the lower register group as valid bits of the higher register group.

[0155] See Figure 4 This application provides a schematic diagram of merging valid bits in each register group. The register groups include a first register group D1, a second register group D2, and a third register group D3. The valid bits in the first register group D1 occupy 1 / 2 of the physical bit width of the entire register group, the valid bits in the second register group D2 occupy 2 / 5 of the physical bit width of the entire register group, and the valid bits in the third register group D3 occupy 3 / 10 of the physical bit width of the entire register group. After merging the valid bits of the first register group D1 and the second register group D2, the valid bits can occupy 9 / 10 of the physical bit width of the first register group D1, and the second register group D2 can be left empty. Then, after merging the first register group D1 and the third register group D3, the first register group D1 is filled, and at the same time, it occupies 1 / 5 of the physical bit width of the second register group D2, and the third register group is left empty.

[0156] The above methods can be used to merge register groups, and will not be elaborated further here.

[0157] In some embodiments, after obtaining the target encoding result of the defect image, the method further includes:

[0158] Obtain the length of the target defect in the filtering rules;

[0159] Based on the start and end positions of each coding pair in the target coding result, determine the defect length of the corresponding connectivity defect for each coding pair;

[0160] The corresponding encoding pairs of connected regions whose defect length is less than the target defect length are identified as the fourth encoding pairs to be deleted.

[0161] The fourth coding pair is removed from the target coding result to obtain the filtered target coding result.

[0162] In practical applications, for reasons such as saving space and fault tolerance, smaller defective connected regions may be directly filtered out. Usually, the filtering rules specify the target defect length, which is the minimum length of the defect that can be retained. For connected regions with a length smaller than the target defect length, the corresponding encoding pairs will be filtered out.

[0163] The target defect length is a preset value, specifically, it can be 2, meaning that the encoded pairs of connected regions with a defect length less than 2 will be filtered out.

[0164] Specifically, based on the start and end positions of each coding pair in the target coding result, the defect length of the corresponding connected region for each coding pair can be determined. The coding pairs of connected regions whose defect length is less than the target defect length can be designated as the fourth coding pairs to be deleted. Then, the fourth coding pairs are deleted from the target coding result to obtain the filtered target coding result.

[0165] Furthermore, since the filtered target encoding result is also stored in the register group, effective bits can be merged in the register where the filtered target encoding result is located. The principle is similar to that of the aforementioned embodiments, and will not be repeated here.

[0166] The final output of the FIFO buffer can be either the target encoding result or the filtered target encoding result, which can be set according to requirements and there are no restrictions on this.

[0167] In some embodiments, before reading the pixel value group for the current clock cycle from the binarized image of the defective image, the method further includes:

[0168] Obtain the defect image to be processed;

[0169] The defect image is binarized to obtain a binary image;

[0170] In the binarized image, there is at least one defective pixel.

[0171] The foregoing embodiments have already described this, and will not be repeated here.

[0172] See Figure 5 This application provides a second schematic flowchart of an image encoding method, including the following steps:

[0173] Acquire a defect image to be processed; the defect image includes at least one defect region; perform binarization processing on the defect image to obtain a binarized image; read the pixel value group for the current clock cycle from the binarized image of the defect image; determine the first encoding result corresponding to the pixel value group for the current clock cycle according to the correspondence between the pixel value group and the preset encoding result; the first encoding result includes at least one set of encoding pairs or is empty; each encoding pair corresponds to a connected region composed of defect pixels, and each encoding pair includes the start position and end position of the corresponding connected region; the start position and end position are represented by hexadecimal encoding; if the pixel value group for the current clock cycle is the last pixel value group of its respective image unit, merge the first encoding results of each image unit within the group according to the end position of the highest bit and the start position of the lowest bit in each first encoding result to obtain an image. The second encoding result of the unit; for the second encoding result of the image unit obtained in each clock cycle, add the encoding corresponding to the unit identifier of the image unit to the least significant bit of the second encoding result, and add the encoding corresponding to the end identifier of the unit encoding of the image unit to the most significant bit to obtain the third encoding result; concatenate the third encoding results of all image units in the binarized image to obtain the fourth encoding result; add the encoding corresponding to the end identifier of the image to the high significant bit of the fourth encoding result to obtain the target encoding result of the defect image; obtain the target defect length in the filtering rules; determine the defect length of the corresponding connected defect of each encoding pair according to the start and end position of each encoding pair in the target encoding result; determine the encoding pairs corresponding to the connected regions whose defect length is less than the target defect length as the fourth encoding pairs to be deleted; delete the fourth encoding pairs from the target encoding result to obtain the filtered target encoding result.

[0174] The detailed implementation process of the above steps can be found in the aforementioned embodiments, and will not be repeated here.

[0175] The image encoding method provided in this application can be executed by an image encoding device. This application uses an image encoding device executing the image encoding method as an example to illustrate the image encoding device provided in this application.

[0176] This application also provides an image encoding device.

[0177] like Figure 6 As shown, the image encoding device includes:

[0178] The first processing module 610 is used to read the pixel value group of the current clock cycle from the binarized image of the defect image; the pixel value group includes the pixel values ​​of multiple pixels read in the current cycle;

[0179] The second processing module 620 is used to determine the first encoding result corresponding to the pixel value group in the current clock cycle according to the correspondence between the pixel value group and the preset encoding result; the first encoding result includes at least one set of encoding pairs or is empty; each set of encoding pairs is for a connected region composed of defective pixels, and each set of encoding pairs includes the start position and end position of the corresponding connected region; the start position and end position are represented by hexadecimal encoding;

[0180] The third processing module 630 is used to merge the first encoding results of the image unit within the group according to the end order of the highest bit and the start order of the lowest bit in each first encoding result when the pixel value group in the current clock cycle is the last pixel value group of the image unit, so as to obtain the second encoding result of the image unit.

[0181] The fourth processing module 640 is used to determine the target encoding result of the defective image based on the second encoding result of each image unit.

[0182] According to the image encoding device provided in the embodiments of this application, the pixel value group of the current clock cycle is read from the binarized image of the defective image in each clock cycle, and the first encoding result corresponding to the pixel value group of the current clock cycle is determined according to the correspondence between the pixel value group and the preset encoding result. That is, by reading data in units of pixel value groups and encoding based on the correspondence between the pixel value group and the preset encoding result, the effect of parallel encoding can be achieved, and multiple pixel data can be processed in one clock cycle, resulting in less latency and higher real-time performance.

[0183] Furthermore, by merging the first encoding results of each image unit within each group according to the end order of the highest bit and the start order of the lowest bit in each first encoding result of each pixel value group, the segmented connected regions can be merged, thereby improving the image compression effect.

[0184] In some embodiments, the second processing module 620 is configured to:

[0185] A first target data table is determined from multiple first data tables to have a mapping relationship with the group identifier of the pixel value group; the first data table includes a first number of first data rows, which are used to record the correspondence between the pixel value group and the preset encoding result; the group identifier is generated based on the start position and end position of each pixel in the corresponding pixel value group; the first number is determined according to the number of pixel values ​​contained in the pixel value group;

[0186] Using the pixel value group of the current clock cycle as the first index, query the first target data row from the first target data table;

[0187] The preset encoding result in the first target data row is determined to be the first encoding result corresponding to the pixel value group in this clock cycle.

[0188] In some embodiments, the third processing module 630 is configured to:

[0189] When an image unit corresponds to at least two first encoding results, the first encoding results of two adjacent clock cycles are traversed based on the order of clock cycles; each traversal of the two clock cycles includes the first clock cycle and the second clock cycle; the first clock cycle is earlier than the second clock cycle.

[0190] If the end position of the most significant bit in the first encoding result of the first clock cycle and the start position of the least significant bit in the first encoding result of the second clock cycle are adjacent, the first encoding results of the two clock cycles are merged to obtain a new first encoding result for the new clock cycle. The new first encoding result does not include the first encoding pair and the second encoding pair. The first encoding pair is the encoding pair containing the end position of the most significant bit in the first encoding result of the first clock cycle. The second encoding pair is the encoding pair containing the start position of the least significant bit in the first encoding result of the second clock cycle. The new first encoding result includes a third encoding pair. The start position of the third encoding pair is the start position of the first encoding pair. The end position of the third encoding pair is the end position of the second encoding pair.

[0191] If the end order of the most significant bit in the first encoding result corresponding to the first clock cycle is not adjacent to the start order of the least significant bit in the first encoding result corresponding to the second clock cycle, the first encoding result of the next set of clock cycles is traversed.

[0192] With the first encoding result of the last clock cycle of the image unit already traversed, the first encoding results of each image unit are concatenated and arranged to obtain the second encoding result of the image unit.

[0193] In some embodiments, the fourth processing module 640 is configured to:

[0194] For the second encoding result of the image unit obtained in each clock cycle, add the encoding corresponding to the unit identifier of the image unit to the least significant bit of the second encoding result, and add the encoding corresponding to the end identifier of the unit encoding of the image unit to the most significant bit to obtain the third encoding result;

[0195] The third encoding results of all image units in the binarized image are concatenated to obtain the fourth encoding result;

[0196] Add the image end identifier corresponding to the high-order bits of the fourth encoding result to obtain the target encoding result of the defective image.

[0197] In some embodiments, each third encoding result is written to a register group of the FPGA; each register group includes multiple registers;

[0198] The fourth processing module 640 is also specifically used for:

[0199] Based on the order from least significant bit to most significant bit, each pair of register groups is accessed sequentially; each pair of register groups consists of two adjacent register groups.

[0200] The accessed register pairs are bit-merged to concatenate the third-encoded results.

[0201] In some embodiments, the image encoding module further includes:

[0202] The fifth processing module is used for:

[0203] Obtain the length of the target defect in the filtering rules;

[0204] Based on the start and end positions of each coding pair in the target coding result, determine the defect length of the corresponding connectivity defect for each coding pair;

[0205] The corresponding encoding pairs of connected regions whose defect length is less than the target defect length are identified as the fourth encoding pairs to be deleted.

[0206] The fourth coding pair is removed from the target coding result to obtain the filtered target coding result.

[0207] In some embodiments, the image encoding apparatus further includes:

[0208] The sixth encoding module is used to acquire the defect image to be processed;

[0209] The defect image is binarized to obtain a binary image;

[0210] In the binarized image, there is at least one defective pixel.

[0211] The image encoding device in this application embodiment can be an electronic device or a component within an electronic device, such as an integrated circuit or a chip. The electronic device can be a terminal or other devices besides a terminal. For example, the electronic device can be a mobile phone, tablet computer, laptop computer, PDA, in-vehicle electronic device, mobile internet device (MID), augmented reality (AR) / virtual reality (VR) device, robot, wearable device, ultra-mobile personal computer (UMPC), netbook, or personal digital assistant (PDA), etc. It can also be a server, network attached storage (NAS), personal computer (PC), television (TV), ATM, or self-service machine, etc. This application embodiment does not specifically limit the device.

[0212] The image encoding device in this application embodiment can be a device with an operating system. This operating system can be a Microsoft (Windows) operating system, an Android operating system, an iOS operating system, or other possible operating systems; this application embodiment does not specifically limit the specific operating system.

[0213] The image encoding device provided in this application embodiment can achieve... Figures 1 to 5 The various processes implemented in the method implementation examples will not be described again here to avoid repetition.

[0214] In some embodiments, such as Figure 7 As shown, this application embodiment also provides an electronic device 700, including a processor 701, a memory 702, and a computer program stored in the memory 702 and executable on the processor 701. When the program is executed by the processor 701, it implements the various processes of the above-described image encoding method embodiment and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0215] Processor 701 may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It can implement or execute the various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure of this application. Processor 701 may also be a combination that implements computational functions, such as including one or more microprocessor combinations, a combination of a DSP and a microprocessor, etc.

[0216] The memory 702 may be ROM (Read Only Memory) or other types of static storage devices capable of storing static information and instructions, RAM (Random Access Memory) or other types of dynamic storage devices capable of storing information and instructions, or EEPROM (Electrically Erasable Programmable Read Only Memory), CD-ROM (Compact Disc Read Only Memory) or other optical disc storage, optical disc storage (including compressed optical discs, laser discs, optical discs, digital universal optical discs, Blu-ray discs, etc.), magnetic disk storage media, other magnetic storage devices, or any other medium capable of carrying or storing computer programs and capable of being read by a computer, without limitation herein.

[0217] The memory 702 is used to store computer programs that execute the embodiments of this application, and the execution is controlled by the processor 701. The processor 701 is used to execute the computer programs stored in the memory 702 to implement the steps shown in the foregoing method embodiments.

[0218] It should be noted that the electronic devices in the embodiments of this application include the mobile electronic devices and non-mobile electronic devices described above.

[0219] This application also provides a non-transitory computer-readable storage medium storing a computer program. When the computer program is executed by a processor, it implements the various processes of the above-described image encoding method embodiments and achieves the same technical effect. To avoid repetition, it will not be described again here.

[0220] The processor is the processor in the electronic device described in the above embodiments. The readable storage medium includes computer-readable storage media, such as computer read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk.

[0221] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the above-described image encoding method.

[0222] This application embodiment also provides a chip, which includes a processor and a communication interface. The communication interface is coupled to the processor. The processor is used to run programs or instructions to implement the various processes of the above-described image encoding method embodiments and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0223] It should be understood that the chip mentioned in the embodiments of this application may also be referred to as a system-on-a-chip, system chip, chip system, or system-on-a-chip, etc.

[0224] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0225] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the related technology, can be embodied in the form of a computer software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0226] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

[0227] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0228] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

Claims

1. An image coding method characterized by, The method comprises the following steps: reading a pixel value group of the current clock cycle from a binary image of the defect image; the pixel value group comprises pixel values of a plurality of pixel points read in the current cycle; finding a first encoding result corresponding to the pixel value group of the current clock cycle according to a correspondence between pixel value groups of the clock cycle and preset encoding results created in advance; the first encoding result comprises at least one encoding pair or is empty; each encoding pair is for a connected region composed of defect pixel points, and each encoding pair comprises a start bit sequence and an end bit sequence of the corresponding connected region; the start bit sequence and the end bit sequence are represented by hexadecimal encoding; in the case where the pixel value group of the current clock cycle is the last pixel value group of the image unit, performing in-group merging on each first encoding result of the image unit according to the end bit sequence of the highest bit and the start bit sequence of the lowest bit in each first encoding result, to obtain a second encoding result of the image unit; determining a target encoding result of the defect image according to the second encoding result of each image unit; the method comprises the following steps: determining a first target data table having a mapping relationship with the group identifier of the pixel value group from a plurality of first data tables; the first data table comprises a first number of first data rows, and the first data rows are used to record the correspondence between the pixel value group and the preset encoding result; the group identifier is generated based on the start bit sequence and the end bit sequence of each pixel point corresponding to the pixel value group; the first number is determined according to the number of pixel values contained in the pixel value group; querying a first target data row from the first target data table by taking the pixel value group of the current clock cycle as a first index; determining the preset encoding result in the first target data row as the first encoding result corresponding to the pixel value group of the current clock cycle.

2. The image coding method of claim 1, wherein the method comprises the following steps: in the case where the image unit corresponds to at least two first encoding results, traversing the first encoding results of adjacent two clock cycles based on the order of the clock cycles; each time of traversal comprises a first clock cycle and a second clock cycle; the first clock cycle is earlier than the second clock cycle; In a case that the end bit sequence of the highest bit in the first clock cycle corresponding first encoding result and the start bit sequence of the lowest bit in the second clock cycle corresponding first encoding result are adjacent, the first encoding results of the two clock cycles are merged to obtain a new first encoding result corresponding to a new clock cycle; the new first encoding result does not include a first encoding pair and a second encoding pair; the first encoding pair is an encoding pair in which the end bit sequence of the highest bit in the first clock cycle corresponding first encoding result is located; the second encoding pair is an encoding pair in which the start bit sequence of the lowest bit in the second clock cycle corresponding first encoding result is located; the new first encoding result includes a third encoding pair; the start bit sequence of the third encoding pair is the start bit sequence of the first encoding pair; the end bit sequence of the third encoding pair is the end bit sequence of the second encoding pair; In a case that the end bit sequence of the highest bit in the first clock cycle corresponding first encoding result and the start bit sequence of the lowest bit in the second clock cycle corresponding first encoding result are not adjacent, the first encoding result of the next group of clock cycles is traversed; In a case that the first encoding result of the last group of clock cycles of the image unit has been traversed, the first encoding results of the image unit are arranged to obtain the second encoding result of the image unit.

3. The image coding method of claim 1, wherein, The method further comprises: For the second encoding result of the image unit obtained for each clock cycle, an encoding corresponding to the unit identifier of the image unit is added to the lowest bit of the second encoding result, and an encoding corresponding to the unit encoding end identifier of the image unit is added to the highest bit to obtain a third encoding result; The third encoding results of all image units in the binary image are spliced to obtain a fourth encoding result; An encoding corresponding to an image end identifier is added to the high bit of the fourth encoding result to obtain the target encoding result of the defect image.

4. The image coding method according to claim 3, characterized by, Each third encoding result is written in a register group of an FPGA; each register group includes a plurality of registers; The method further comprises: Based on the order from low bit to high bit, each pair of register groups is accessed in turn; each pair of register groups includes two adjacent register groups; The effective bit of each pair of register groups accessed is merged to splice each third encoding result.

5. The image coding method of claim 1, wherein After the target encoding result of the defect image is obtained, the method further comprises: Obtaining a target defect length in a filtering rule; According to the start bit sequence and the end bit sequence of each encoding pair in the target encoding result, the defect length of the corresponding connected defect of each encoding pair is determined; The encoding pair corresponding to the connected region with a defect length smaller than the target defect length is determined as a fourth encoding pair to be deleted; The fourth encoding pair is deleted from the target encoding result to obtain a filtered target encoding result.

6. The image coding method according to any one of claims 1 to 5, characterized by, Before the pixel value group of the current clock cycle is read from the binary image of the defect image, the method further comprises: Obtaining a defect image to be processed; The defect image is binarized to obtain the binary image; The target encoding result of the defect image is obtained. The binarized image has at least one pixel point as the defective pixel point.

7. An image coding apparatus characterized by comprising: The method comprises: The first processing module is configured to read a pixel value group of a current clock cycle from a binarized image of a defective image; The pixel value group comprises pixel values of a plurality of pixel points read in the current cycle; The second processing module is configured to find a first encoding result corresponding to the pixel value group of the current clock cycle according to a correspondence between pixel value groups of the clock cycle and preset encoding results created in advance; the first encoding result comprises at least one encoding pair or is empty; each encoding pair is for a connected region composed of defective pixel points, and each encoding pair comprises a start bit sequence and an end bit sequence of the corresponding connected region; the start bit sequence and the end bit sequence are represented by hexadecimal encoding; The third processing module is configured to, in a case where the pixel value group of the current clock cycle is the last pixel value group of a corresponding image unit, perform in-group merging on each first encoding result of the image unit according to the end bit sequence of the highest bit and the start bit sequence of the lowest bit in each first encoding result, to obtain a second encoding result of the image unit; The fourth processing module is configured to determine a target encoding result of the defective image according to the second encoding result of each image unit; The second processing module is configured to determine a first target data table having a mapping relationship with a group identifier of the pixel value group from a plurality of first data tables; the first data table comprises a first number of first data rows, and the first data rows are used to record the correspondence between the pixel value group and the preset encoding result; the group identifier is generated based on start bit sequences and end bit sequences of each pixel point corresponding to the pixel value group; and the first number is determined according to a number of pixel values contained in the pixel value group; The pixel value group of the current clock cycle is used as a first index to query a first target data row from the first target data table; The preset encoding result in the first target data row is determined as the first encoding result corresponding to the pixel value group of the current clock cycle.

8. An electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, The processor executes the computer program to implement the image encoding method of any one of claims 1-6. 9.A non-transitory computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by the processor to implement the image encoding method of any one of claims 1-6.

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