Pixelized capacitor sensor charge sharing readout system

Abstract

A pixelated capacitive sensor system and a method of operating a pixelated capacitive sensor system are provided. A pixelated capacitive sensor system includes: a sensor array including a plurality of sensing capacitors and a top plate; a comparator operably connected to each sensing capacitor of the sensor array and the top plate; a switch matrix operably connected to each sensing capacitor of the sensor array and the top plate; and a digital controller operably connected to the comparator and the switch matrix. Readout circuitry may be formed from a sensor array, a comparator, a digital controller, and the switch matrix. A method of operating a pixelated capacitive sensor system includes: providing a capacitive sensor system; sampling through a capacitive sensor system; switching the sensing capacitor by a digital controller; and running the conversion algorithm by the digital controller.

Description

Technical Field

[0001] The present disclosure relates to a pixelated capacitive sensor system, and more particularly, to a pixelated capacitive sensor system having a sensor readout circuit that re-uses capacitive sensing cells for quantization. Background Art

[0002] Capacitive sensors using complementary metal oxide semiconductor (CMOS) technology are used in various applications, such as life science applications. Currently known pixelated capacitive sensors consist of a number of pixel arrays and dedicated analog-to-digital converters (ADCs) for each row / column of pixels. Such ADCs are costly in terms of area, power, and complexity.

[0003] For at least one or more of these reasons, or one or more other reasons, it would be advantageous if new or improved systems and / or improved methods of operation or implementation could be developed to address any one or more of the above problems or address one or more other problems or provide one or more benefits. Summary of the Invention

[0004] According to one aspect of the present application, there is provided a capacitive sensor system, comprising: a sensor array including a plurality of sensing capacitors and a top plate; a comparator operably connected to the top plate of the sensor array; a switch matrix operably connected to each sensing capacitor of the sensor array; and a digital controller operably connected to the comparator and the switch matrix.

[0005] According to one or more embodiments, the capacitive sensor system further includes a readout circuit formed by the sensor array, the comparator, the digital controller, and the switch matrix.

[0006] According to one or more embodiments, the sensor array includes at least two segments: a first array segment including a first group of sensing capacitors and a second array segment including a second group of sensing capacitors; and wherein the first array segment has a first ink on the first group of sensing capacitors, and the second array segment has a second ink on the second group of sensing capacitors.

[0007] According to one or more embodiments, the first ink includes a first chemical reagent formulated to detect a first analyte, and the second ink includes a second chemical reagent formulated to detect a second analyte different from the first analyte.

[0008] According to one or more embodiments, the sensor array includes at least three segments: a first array segment including a first set of sensing capacitors, a second array segment including a second set of sensing capacitors, and a third array segment including a third set of sensing capacitors; and wherein the first array segment has a first ink on the first set of sensing capacitors, the second array segment has a second ink on the second set of sensing capacitors, and the third array segment has a third ink on the third set of sensing capacitors.

[0009] According to one or more embodiments, the first ink includes a first chemical reagent formulated to detect a first analyte, the second ink includes a second chemical reagent formulated to detect a second analyte different from the first analyte, and the third ink includes a third chemical reagent formulated to detect a third analyte different from both the first analyte and the second analyte.

[0010] According to one or more embodiments, the digital controller includes a conversion logic engine that controls test operations of the capacitive sensor system.

[0011] According to one or more embodiments, the digital controller further includes a discovery phase logic engine that controls an initial discovery phase to at least determine the positions of the sensing capacitors in the first array segment having the first ink.

[0012] According to a second aspect of the present application, there is provided a capacitive sensor system, comprising: a sensor array including a plurality of sensing capacitors and a top plate; a comparator operably connected to the top plate of the sensor array; a switch matrix operably connected to each sensing capacitor of the sensor array; a digital controller operably connected to the comparator and the switch matrix; and a readout circuit formed by the sensor array, the comparator, the digital controller, and the switch matrix.

[0013] According to one or more embodiments, the sensor array includes at least two segments: a first array segment including a first set of sensing capacitors and a second array segment including a second set of sensing capacitors; and wherein the first array segment has a first ink on the first set of sensing capacitors, and the second array segment has a second ink on the second set of sensing capacitors.

[0014] According to one or more embodiments, the first ink includes a first chemical reagent formulated to detect a first analyte, and the second ink includes a second chemical reagent formulated to detect a second analyte different from the first analyte.

[0015] According to one or more embodiments, the sensor array includes at least three sections: a first array section including a first set of sensing capacitors, a second array section including a second set of sensing capacitors, and a third array section including a third set of sensing capacitors; and wherein the first array section has a first ink on the first set of sensing capacitors, the second array section has a second ink on the second set of sensing capacitors, and the third array section has a third ink on the third set of sensing capacitors.

[0016] According to one or more embodiments, the first ink includes a first chemical reagent formulated to detect a first analyte, the second ink includes a second chemical reagent formulated to detect a second analyte different from the first analyte, and the third ink includes a third chemical reagent formulated to detect a third analyte different from both the first analyte and the second analyte.

[0017] According to one or more embodiments, the digital controller includes a conversion logic engine that controls the test operation of the capacitive sensor system, and a discovery phase logic engine that controls an initial discovery phase to at least determine the positions of the sensing capacitors in the first array section having the first ink.

[0018] According to a third aspect of the present application, a method of operating a capacitive sensor system is provided. The method includes: providing a capacitive sensor system including: a sensor array including a plurality of sensing capacitors and a top plate; a comparator operatively connected to the top plate of the sensor array; a switch matrix operatively connected to each sensing capacitor of the sensor array; and a digital controller operatively connected to the comparator and the switch matrix; wherein the sensor array includes at least two sections: a first array section including a first group of sensing capacitors and a second array section including a second group of sensing capacitors; and wherein the first array section has a first ink on the first group of sensing capacitors and the second array section has a second ink on the second group of sensing capacitors; sampling by the digital controller, including connecting the top plate to a reference equal to the comparator reference voltage, and setting each sensing capacitor of the first array section to a first value and each sensing capacitor of the second array section to a second value opposite to the first value; switching the sensing capacitors by the digital controller, including setting the top plate to floating and operating the switch matrix to switch the value of each sensing capacitor of the first array section from the first value to the second value and the value of each sensing capacitor of the second array section from the second value to the first value; and running a conversion algorithm by the digital controller, including determining by the digital controller which ratios of the first array section and the second array section need to be set to make the capacitances equal to each other.

[0019] According to one or more embodiments, running the conversion algorithm includes the digital controller performing a plurality of iterative stages, where each stage includes the digital controller comparing the average capacitance of a portion of the sensing capacitors of the first array section with the average capacitance of a portion of the sensing capacitors of the second array section.

[0020] According to one or more embodiments, during a first subset of the plurality of iterative stages, the portion of the sensing capacitors of the second array section is equal to all the sensing capacitors of the second array section.

[0021] According to one or more embodiments, the iterative stage includes a second subset of iterative stages after the first subset of iterative stages, where the portion of the sensing capacitors of the second array section is variable.

[0022] According to one or more embodiments, the method further includes: before sampling by the digital controller, a discovery phase is performed by a discovery phase logic engine of the digital controller to at least determine the positions of the sense capacitors in a first array section having a first ink.

[0023] According to one or more embodiments, performing the discovery phase includes: a first block of sense capacitors is selected by a block size control logic module of the discovery phase logic within an area that can contain the first array section having the first ink; the conversion algorithm is run on the first block by a block scan control logic module of the discovery phase logic engine; a subsequent block of sense capacitors is selected by the block size control logic module of the discovery phase logic within the area that can contain the first array section having the first ink; and the conversion algorithm is run on the subsequent block by the block scan control logic module of the discovery phase logic engine. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Specific examples have been selected for purposes of illustration and description and are shown in the accompanying drawings that form a part of the specification.

[0025] Figure 1 An example of a pixelated capacitive sensor system showing the technology of the present invention is shown.

[0026] Figure 2 Showing Figure 1 An exploded view of the pixelated capacitive sensor system, where the housing has been removed.

[0027] Figure 3 (Prior art) A diagram showing an example of the operating components of a prior art pixelated capacitive sensor system.

[0028] Figure 4 Showing an example of the operating components of an embodiment of the pixelated capacitive sensor system of the technology of the present invention that can be used in Figure 1 The pixelated capacitive sensor system.

[0029] Figure 5 Showing Figure 4 A top view of the pixelated capacitive sensor array of the pixelated capacitive sensor system.

[0030] Figure 6 Showing the operating components of a second embodiment of the pixelated capacitive sensor system of the technology of the present invention, the operating components can be used in Figure 1 The pixelated capacitive sensor system and include sense capacitors having two sections with different inks thereon.

[0031] Figure 7 Showing Figure 6Top view of the capacitive sensor array of a pixelated capacitive sensor system.

[0032] Figure 8 Illustrates an operation Figure 6 An example of a method for a pixelated capacitive sensor system.

[0033] Figure 9 Is during Figure 8 Graph of the top plate voltage during the method.

[0034] Figure 10 Illustrates the operating components of a third embodiment of a pixelated capacitive sensor system of the present invention, the operating components being usable in Figure 1 A pixelated capacitive sensor system and including three sensing capacitor segments having different inks thereon.

[0035] Figure 11 Illustrates Figure 10 Top view of the capacitive sensor array of a pixelated capacitive sensor system.

[0036] Figure 12 Illustrates used in Figure 6 Or Figure 10 Diagram of the discovery phase logic engine in a pixelated capacitive sensor system.

[0037] Figure 13 Illustrates performing Figure 6 Or Figure 10 An example of a method for the discovery phase of a pixelated capacitive sensor system.

[0038] Although the various embodiments discussed herein are susceptible to modification and alternative forms, aspects of these embodiments have been shown by way of example in the figures and are described in detail herein. However, it should be understood that the present disclosure is not limited to the specific embodiments described, but is intended to cover all modifications, equivalents, and alternatives falling within the scope of the present disclosure. Additionally, the terms "example" and "embodiment" used throughout this application are for illustrative purposes only and not limiting, the drawings are not necessarily to scale, and like reference numerals are used in different drawings to indicate similar or identical items unless otherwise noted. The term "configured to" as used herein with respect to a component that is configured to have certain structural characteristics or perform a function in a specified situation means that the component is structurally formed such that the component meets the structural characteristics or performs the function in the specified situation without further modification. The term "about" as used herein in reference to any measured value or physical property means approximately and includes the measured value or physical property plus or minus an amount within an acceptable error tolerance or other variance amount that maintains the desired function. Detailed Description

[0039] The pixelated capacitive sensor system of the present technology can be used in various applications, particularly non-imaging applications, such as sampling a certain amount of substance over time. Compared with the previously known charge redistribution (CR) successive approximation register (SAR), the pixelated capacitive sensor system of the present technology can reuse capacitive sensing units instead of dedicated ADCs for quantization. Such a pixelated capacitor sensor charge sharing readout system can achieve the sampling and partial quantization functions by reusing the pixel sensor as a capacitive digital-to-analog converter (DAC).

[0040] Figure 1 and 2 FIG. shows an example of a pixelated capacitive sensor system 100 of the present technology. The pixelated capacitive sensor system 100 can be in the form of a packaged chip 102 including a housing 104. For illustrative purposes, Figure 2 the housing 104 is not shown. As Figure 2 shown, the pixelated capacitive sensor system 100 includes: a CMOS chip 106 having a digital controller 108 which can be a microcontroller, and a sensing field 110 including a sensing capacitor array 112. The sensing capacitor array 112 includes a plurality of individual sensing capacitors 116. One or more sensing inks 114 can be applied to the sensing field 110. As Figure 1 shown, one or more sensing inks 114 can be applied as dots on the sensing field 110. In other examples, including the examples discussed below, one or more sensing inks 114 can be applied in an area of any shape on the sensing field 110. In some examples, one or more sensing inks 114 can be printed on the sensing field 110, for example, by inkjet printing. As Figure 1 shown, the housing 104 can include an access hole configured to expose the sensing field 110 but otherwise at least surround the top of the CMOS chip 106.

[0041] Figure 3 FIG. is a diagram of an example of the operating components of a prior art pixelated capacitive sensor system 200. The prior art pixelated capacitive sensor system 200 includes a sensor array 202, a readout circuit 204, and a digital controller 206. The sensor array includes a plurality of sensing capacitors 208 arranged in rows. The readout circuit 204 includes a plurality of ADCs that act as Σ-Δ ADCs and perform decimation. Each row of the sensing capacitors 208 is operatively connected to one of the plurality of ADCs. The plurality of ADCs are each operatively connected to the digital controller 206. Each sensing capacitor 208 is operatively connected to a switch matrix 212, and the switch matrix 212 is operatively connected to the digital controller 206. As Figure 3As can be seen, in the capacitive sensor system 200 of the prior art, the sensor array 202 and the readout circuit 204 are two completely different circuits. During the operation of the prior art pixelated capacitive sensor system 200, an input is sampled on the sensor array 202, and the resulting voltage is compared with a known reference voltage, and the digital controller 206 repeatedly switches the sensor array 202 to determine the input sampled voltage. Two sensing capacitors 208 are selected by the digital controller 206 to form a capacitor 214 and the capacitance between the two sensing capacitors 208 is measured using a designated ADC to measure the capacitance.

[0042] Figure 4 and 5 FIG. showing a portion of an example of a pixelated capacitive sensor system 300 of the present invention that can be used in a pixelated capacitive sensor system 100. Figure 4 Showing the operating components of the pixelated capacitive sensor system 300. Figure 5 Showing a top view of the capacitive sensor array of the pixelated capacitive sensor system 300.

[0043] As Figure 4 shown, the pixelated capacitive sensor system 300 includes a sensor array 302, a comparator 304, and a digital controller 306. As Figure 4 and 5 shown, the sensor array 302 includes a plurality of sensing capacitors 308 and a top plate 310, and the top plate is part of the sensing capacitor 308. Returning to reference Figure 4 , the top plate 310 is operatively connected to the comparator 304. The comparator 304 is operatively connected to the digital controller 306. Each sensing capacitor 308 is also operatively connected to a switch matrix 312, and the switch matrix 312 is operatively connected to the digital controller 306.

[0044] The readout circuit of the pixelated capacitive sensor system 300 is formed by the sensor array 302, the comparator 304, the digital controller 306, and the switch matrix 312. The digital controller includes conversion logic 314 and additional logic 316, and the conversion logic 314 includes a conversion algorithm. The additional logic 316 may include discovery phase logic that controls an initial discovery phase (discussed in further detail below) in an example where the sensor array 302 has sections of sensing capacitors 308 and different inks on each section. The readout circuit of the pixelated capacitive sensor system 300 is formed by reusing the sensor array 302 as a capacitance digital-to-analog converter (DAC) and using the top plate 310 to provide the input voltage to be sensed.

[0045] During operation of the pixelated capacitive sensor system 300, a single or multiple sensing capacitors 308 and a top plate 310 are selected by the digital controller 306 to create a capacitor. Then, the digital controller 306 measures the capacitance using the comparator 304 and the sensor array 302 by successive approximation.

[0046] Use of two inks

[0047] Figure 6 and 7 Part showing an example of a pixelated capacitive sensor system 400 of the present invention's technology, where the sensor array has two sections of sensing capacitors 408. Figure 6 Showing the operating components of the pixelated capacitive sensor system 400. Figure 7 Showing a top view of the capacitive sensor array 402 of the pixelated capacitive sensor system 400. Figure 6 and 7 The components of the pixelated capacitive sensor system 400 shown in can be used in the pixelated capacitive sensor system 100.

[0048] As Figure 6 shown, the pixelated capacitive sensor system 400 includes a sensor array 402, a comparator 404, and a digital controller 406. As Figure 6 and 7 shown, the sensor array 402 includes a plurality of sensing capacitors 408 and a top plate 410, and the top plate is part of the sensing capacitor 408. Return reference Figure 6 , each top plate 410 is operably connected to the comparator 404. The comparator 404 is operably connected to the digital controller 406. Each sensing capacitor 408 is also operably connected to a switch matrix 412, and the switch matrix 412 is operably connected to the digital controller 406.

[0049] The digital controller 406 includes at least one processor and at least one non-transitory computer-readable memory, and the at least one non-transitory computer-readable memory includes logic for controlling the process of the pixelated capacitive sensor system 400. The digital controller 406 may include a conversion logic engine 414, and the conversion logic engine 414 may control the test operation of the capacitive sensor system 400. The digital controller 406 may also include additional logic engines, and the additional logic engines may include a discovery phase logic engine 416 for controlling the initial discovery phase.

[0050] The readout circuitry of the pixelated capacitive sensor system 400 is formed by the sensor array 402, the comparator 404, the digital controller 406, and the switch matrix 412. The readout circuitry of the pixelated capacitive sensor system 400 is formed by repurposing the sensor array 402 as a capacitive digital-to-analog converter (DAC) and using the top plate 410 to create a voltage that is compared to a reference voltage.

[0051] refer to Figure 6 and 7 , the sensor array 402 includes at least two sections: a first array section 418 and a second array section 420. The first array section 418 has a first set of sensing capacitors 408, and a first ink 422 is present on the first set of sensing capacitors 408 within the first array section 418. The second array section 420 has a second set of sensing capacitors 408, and a second ink 424 is present on the second set of sensing capacitors 408 within the second array section 420. The second array section 420 can be a reference array. Each ink can be printed on its corresponding array section and can include a chemical reagent formulated to detect a preselected analyte. In at least one example, the first ink includes a first chemical reagent formulated to detect a first analyte, and the second ink includes a second chemical reagent formulated to detect a second analyte different from the first analyte. Therefore, in the case of changing the dielectric properties of the ink, the sensor capacitance is expected to change accordingly due to the interaction of the ink with the analyte.

[0052] During operation of the pixelated capacitive sensor system 400, the average of the capacitance of the capacitors in the first array section 418 may be compared as a function of the capacitance of the capacitors in the second array section 420, and vice versa. The algorithm used may be similar to a calibration sequence, where the weight of the first array section 418 is evaluated compared to the second array section 420 by successive approximation.

[0053] Conversion Method

[0054] Figure 8 A method 500 of operating a pixelated capacitive sensor system is shown in FIG. The method 500 begins at step 502, which includes providing a capacitive sensor system. Figure 6, the provided capacitive sensor system is a pixelated capacitive sensor system 400, which includes: a sensor array 402 including a plurality of sensing capacitors 408 and a top plate 410; a comparator 404 operatively connected to the top plate 410 of the sensor array 402; a switch matrix 412 operatively connected to each sensing capacitor 408 of the sensor array 402; and a digital controller 406 operatively connected to the comparator 404 and the switch matrix 412. The sensor array 402 includes at least two sections: a first array section 418 including a first group of sensing capacitors and a second array section 420 including a second group of sensing capacitors. Additionally, refer Figure 7 , the first array section 418 has a first ink 422 on the first group of sensing capacitors, and the second array section 420 has a second ink 424 on the second group of sensing capacitors.

[0055] Return reference Figure 8 , the method proceeds to step 504, which includes sampling by the digital controller 406. During sampling, the sensing array 402 is exposed to the substance being tested, such as a gas. Refer Figure 7 , during sampling, the digital controller 406 sets each sensing capacitor 408 of the first array section 418 to a first value and sets each sensing capacitor 408 of the second array section 420 to a second value opposite to the first value, where the two complementary values are defined in the context of the entire system 400. Since the system is a binary system, the first value and the second value can be 1 or 0. Thus, in one example, each sensing capacitor 408 of the first array section 418 is set to the value 0, and each sensing capacitor 408 of the second array section 420 is set to the value 1. At the same time, during sampling, the top plate 410 is connected to a reference equal to the comparator reference voltage.

[0056] Return reference Figure 8 , the method then proceeds to step 506, which includes switching the bottom plate. Refer Figure 7 , during the step of switching the bottom plate, the top plate 410 is set to floating but still connected to the comparator. Switching the bottom plate also includes the digital controller 406 operating the switch matrix 412 to switch the values of each sensing capacitor 408 of the first array section 418 and each sensing capacitor 408 of the second array section 420. Thus, in the current example, during step 504, each sensing capacitor 408 of the first array section 418 is set to the value 1, and each sensing capacitor 408 of the second array section 420 is set to the value 0. If the capacitances of the first array section 418 and the second array section 420 are different, this will result in a voltage increment.

[0057] Return reference Figure 8, the method then proceeds to step 508, which includes running a conversion algorithm. Refer to Figure 7 , running the conversion algorithm includes the digital controller 406 determining which ratios of the first array section and the second array section need to be set such that the capacitances are equal to each other, which occurs when the top plate voltage is equal to the reference voltage. As an example, if when all the sense capacitors 408 in the second array section 420 (reference array section) remain switched and 76% of the sense capacitors 408 in the first array section 418 are switched, and the digital controller 406 determines that the capacitance of the first array section 418 is equal to the capacitance of the second array section 420, this indicates that the second array section 420 is 76% the size of the first array section 418 in terms of capacitance.

[0058] Conversion logic

[0059] Refer to Figure 6 , 7 and 8, the digital controller 406 includes at least one non - transitory computer - readable memory, the at least one non - transitory computer - readable memory including conversion logic 414 and at least one processor. When executed, the conversion logic causes the digital controller 406 to perform step 506, thereby running the conversion algorithm. Running the conversion algorithm includes the digital controller 406 performing an iterative comparison of the average capacitance of a portion of the sense capacitors 408 of the first array section 418 with the average capacitance of a portion of the sense capacitors 408 of the second array section 420. During a first subset of the iterative phase, the portion of the sense capacitors 408 of the second array section 420 can be equal to all the sense capacitors of the second array section.

[0060] Figure 9 is during use Figure 6 and 7 an example of the conversion logic 414 in the pixelated capacitive sensor system 400 shown in (where the first array section 418 and the second array section 420 each have 8 sense capacitors 408) is performed Figure 8 of the method during a graph of the top plate voltage. As Figure 9 shown in the graph of, during step 508, running the conversion algorithm includes four phases: a first phase 1, a second phase 2, a third phase 3, and a fourth phase 4. The four shown iterative phases can be a first subset of the total number of iterative phases. During each of the shown iterative phases, the digital controller 406 performs an iterative comparison of the average capacitance of a portion of the sense capacitors 408 of the first array section 418 with the average capacitance of all the sense capacitors 408 of the second array section 420 as follows, where "C unit A" is the average capacitance of the portion of the first array section 418 indicated by the number preceding the item, and "C unit B" is the average capacitance of the portion of the second array section 420 indicated by the number preceding the item:

[0061] Stage 1: Is 8 * C unit A > 8 * C unit B?

[0062] Stage 2: Is 4 * C unit A > 8 * C unit B?

[0063] Stage 3: Is 6 * C unit A > 8 * C unit B?

[0064] Stage 4: Is 5 * C unit A > 8 * C unit B?

[0065] As shown above for the four illustrated iterative stages, the number of sense capacitors in the portion of the sense capacitors of the second array portion remains the same, all eight sense capacitors of the second array portion in each stage. In contrast, the number of sense capacitors in the sense capacitor portion of the first array portion starts with all eight sense capacitors of the first array section in Stage 1 and decreases by one sense capacitor in each successive iterative stage. As Figure 9 shown, the result of the four illustrated iterative stages is that the average capacitance of the second array section is approximately between 5 / 8 and 6 / 8 of the average capacitance of the first array section, approximately between 62.5% and 75% of the average capacitance of the first array section.

[0066] The iterative stages may also include a second subset of iterative stages after a first subset of iterative stages, wherein the portion of the sense capacitors of the second array section is varied. For example, referring to Figure 9 , other iterative stages may be:

[0067] Stage 5: Is 5 * C unit A > 7 * C unit B?

[0068] Stage 6: Is 4 * C unit A > 6 * C unit B?

[0069] In Stage 5 above, the digital controller 406 will determine whether the average capacitance of the second array section is greater than or less than 71.4% of the average capacitance of the first array section. If the answer is "no", then the value must be between 62.5% and 71.4%. In Stage 6, the digital controller 406 then determines whether the average capacitance of the second array section is greater than or less than 66.7% of the average capacitance of the first array section. Thus, by using additional iterative stages that vary the portion of the sense capacitors of the second array section, a significantly more accurate value of the ratio between the unit capacitors in the first and second array sections is determined.

[0070] The above example is only for eight capacitors per array section. In examples with a higher number of sensing capacitors, a more accurate ratio between the capacitances in the first and second array sections can be obtained.

[0071] Use of more than two inks

[0072] The technology of the present invention is not limited to using only two inks with chemical reagents. Any number of inks can be used. The sensor array will be divided into several array sections corresponding to the number of ink types used.

[0073] Figure 10 and 11 Part showing an example of the pixelated capacitive sensor system 600 of the technology of the present invention, where the sensor array has three sections of sensing capacitors 608. In this example, three inks are used, thus resulting in three sections of sensing capacitors 608. It should be understood that any number of inks and any corresponding number of sensing capacitor sections can be used. Figure 10 Shows the operating components of the pixelated capacitive sensor system 600. Figure 11 Shows a top view of the capacitive sensor array 602 of the pixelated capacitive sensor system 600. Figure 10 and 11 The components of the pixelated capacitive sensor system 600 shown in can be used in the pixelated capacitive sensor system 100.

[0074] As Figure 10 shown in, the pixelated capacitive sensor system 600 includes a sensor array 602, a comparator 604, and a digital controller 606. As Figure 10 and 11 shown in and, the sensor array 602 includes a plurality of sensing capacitors 608 and a top plate 610. Returning to the reference Figure 10 , the top plate 610 is operably connected to the comparator 604. The comparator 604 is operably connected to the digital controller 606. Each sensing capacitor 608 is operably connected to a switch matrix 612, and the switch matrix 612 is operably connected to the digital controller 606.

[0075] The digital controller 606 includes at least one processor and at least one non - transitory computer - readable memory, and the at least one non - transitory computer - readable memory includes logic for controlling the process of the pixelated capacitive sensor system 600. The digital controller 606 may include a conversion logic engine 614, and the conversion logic engine 614 can control the test operation of the capacitive sensor system 600. The digital controller 606 may also include additional logic engines, and the additional logic engines may include a discovery - phase logic engine 616 for controlling the initial discovery phase.

[0076] The readout circuitry of the pixelated capacitive sensor system 600 is formed by the sensor array 602, the comparator 604, the digital controller 606, and the switch matrix 612. The readout circuitry of the pixelated capacitive sensor system 600 is formed by repurposing the sensor array 602 as a capacitive digital-to-analog converter (DAC) and using the top plate 610 to create a voltage that is compared to a reference voltage.

[0077] refer to Figure 10 and 11 , the sensor array 602 includes at least three sections: a first array section 618, a second array section 620, and a third array section 622. Figure 11 , a first array section 618 has a first set of sensing capacitors 608, and a first ink 624 is present on the first set of sensing capacitors 608 within the first array section 618. A second array section 620 has a second set of sensing capacitors 608, and a second ink 626 is present on the second set of sensing capacitors 608 within the second array section 620. The second ink 626 may be different from the first ink 624. A third array section 622 has a third set of sensing capacitors 608, and a third ink 628 is present on the third set of sensing capacitors 608 within the third array section 622. The third ink 628 may be different from each of the first ink 624 and the second ink 626. One of the array sections, such as the second array section 620, may be a reference array. Each ink may be printed on its respective array section and may include a chemical reagent formulated to detect a preselected analyte. In at least one example, the first ink 624 includes a first chemical reagent formulated to detect a first analyte, the second ink 624 includes a second chemical reagent formulated to detect a second analyte different from the first analyte, and the third ink 628 includes a third chemical reagent formulated to detect a third analyte different from the first analyte and the second analyte.

[0078] During operation of the pixelated capacitive sensor system 600, the Figure 8 Conversion logic similar to that described in the illustrated method 500 of operating a pixelated capacitive sensor system determines the average value of the capacitance of the sensing capacitors in any one array segment as a fraction of the average capacitance of either of the other two array segments.

[0079] Discovery Phase Logic

[0080] As long as the position of each ink on the sensor array is known, Figure 8Method 500 as shown. Such prior knowledge may be substantially constant during manufacturing when the ink is applied accurately, but such accuracy may not be achievable, or may not be known at all during application. In practice, a discovery phase may be required after the application of ink including chemical reagents. Basically, the discovery phase includes scanning the entire sensor array and locating the different ink positions, and then storing the ink positions in the memory of the digital controller.

[0081] Thus, as Figure 7 and 10 shown, the digital controller 406 / 606 may include a discovery phase logic engine 416 / 616 that controls the initial discovery phase. Figure 12 Shown is a diagram of a discovery phase logic engine 700, such as the discovery phase logic engine 416 in a pixelated capacitive sensor system 400 used in the technology of the present invention and serving as Figure 6 or the discovery phase logic engine 616 in a pixelated capacitive sensor system 600 serving as Figure 10 in the pixelated capacitive sensor system 600.

[0082] As Figure 12 shown, the discovery phase logic engine 700 may include a block size control logic module 702 and a block scan control logic module 704. The block scan control logic module 704 may include a row and column decoder 706, and the row and column decoder 706 may include a timing unit 708 and a local memory unit 710. The local memory unit 710 may at least partially include a local look-up table that stores the average block capacitance of each sensing capacitor for further arithmetic operations. The look-up table may provide a reference capacitance value for future calibration and may also be used to determine the incremental change in capacitance once the sensor array is exposed to the substance being tested during the operation of the pixelated capacitive sensor system.

[0083] Operation Figure 8 The method 500 of the pixelated capacitive sensor system as shown may include one or more steps of the discovery phase after step 502 and before step 504. Such steps are shown as method 800 in Figure 13 shown.

[0084] Regarding Figure 7 the example of the pixelated capacitive sensor system 400 of Figure 13The method 800 for performing the discovery phase as shown, in this example, the second array section 420 is a reference array section including sensing capacitors with a second ink at predetermined known positions. To ensure that the first ink is not applied to any of the sensing capacitors in the second array area 420, the position of the second array section 420 can be defined to be outside the printable area of the first ink. There may also be sensing capacitors that do not contain any ink, and at least some of the sensing capacitors may have known positions. Method 800 describes performing a discovery to determine the positions of the sensing capacitors in the first array section 418 with the first ink 422.

[0085] Method 800 may start from step 802, which includes selecting a first block of sensing capacitors within an area that may include the first array section 418 with the first ink 422. Refer Figure 12 , the step of selecting the first block of sensing capacitors may be performed by the block size control logic module 702. In Figure 7 the example shown, the first block may be a small number of sensing capacitors 408, such as three or four. The block size may vary depending on the required spatial resolution of the position of the deposited chemical reagent.

[0086] Return reference Figure 13 , method 800 may continue to step 804, which includes running a conversion algorithm for the selected block, and specifically includes running the conversion algorithm to determine the average capacitance of the first block in this step. Running the conversion algorithm during the discovery phase may be similar to Figure 8 step 508 in Figure 12 , and includes comparing the average capacitance of the first block with the average capacitance of the second array section 420. Refer

[0087] Return reference Figure 13 , method 800 may continue to step 806, which includes selecting a subsequent block of sensing capacitors within an area that may include the first array section 418 with the first ink 422. Generally, the sensing capacitors of the subsequent block may include one or more sensing capacitors that are different from the sensing capacitors of the first block, but the sensing capacitors of the subsequent block may also include one or more sensing capacitors that are the same as the sensing capacitors included in the first block. Refer Figure 12, the step of selecting subsequent sub - blocks of the sensing capacitor can be performed by the sub - block size control logic module 702.

[0088] Return reference Figure 13 , method 800 can then return to step 804 and run the conversion algorithm (or run an additional conversion algorithm) on subsequent sub - blocks. Method 800 can loop repeatedly between steps 806 and 804 to respectively select one or more subsequent sub - blocks and run the conversion algorithm (or run an additional conversion algorithm) on each subsequent sub - block as long as there are additional sensing capacitors that may be within the first array section 418.

[0089] During the discovery phase, a capacitance spatial map is constructed for the entire area of the sensing array, which can be included in the first array section 418 and has the first ink 422. Reference Figure 13 , once the discovery phase is complete, method 800 proceeds to step 808 and terminates. Reference Figure 12 , the completion of the discovery phase can include the discovery phase logic engine 700 determining that there are no other sensing capacitors in the sensing array that may contain the first ink 422.

[0090] Notwithstanding the foregoing, the present disclosure is intended to cover numerous embodiments including the embodiments disclosed herein as well as a variety of alternative embodiments.

[0091] In addition, in at least some of the example embodiments covered herein, the present disclosure relates to a pixelated capacitive sensor system and a method of operating a pixelated capacitive sensor system. In at least one aspect, a pixelated capacitive sensor system is provided, the pixelated capacitive sensor system including: a sensor array including a plurality of sensing capacitors and a top plate; a comparator operably connected to each sensing capacitor of the sensor array and the top plate; a switch matrix operably connected to each sensing capacitor of the sensor array and the top plate; and a digital controller operably connected to the comparator and the switch matrix. In at least some such embodiments, a read - out circuit can be formed by the sensor array, the comparator, the digital controller, and the switch matrix.

[0092] In at least some examples, the sensor array can include at least two sections: a first array section including a first group of sensing capacitors and a second array section including a second group of sensing capacitors. The first array section can have a first ink on the first group of sensing capacitors, and the second array section can have a second ink on the second group of sensing capacitors. In such examples, the first ink can include a first chemical reagent formulated to detect a first analyte, and the second ink includes a second chemical reagent formulated to detect a second analyte different from the first analyte.

[0093] In other examples, the sensor array may include at least three sections: a first array section including a first set of sensing capacitors, a second array section including a second set of sensing capacitors, and a third array section including a third set of sensing capacitors. In such examples, the first array section may have a first ink on the first set of sensing capacitors, the second array section may have a second ink on the second set of sensing capacitors, and the third array section may have a third ink on the third set of sensing capacitors. The first ink may include a first chemical reagent formulated to detect a first analyte, the second ink may include a second chemical reagent formulated to detect a second analyte different from the first analyte, and the third ink may include a third chemical reagent formulated to detect a third analyte different from both the first analyte and the second analyte. The digital controller may include a conversion logic engine that includes a conversion algorithm and controls the test operation of the capacitive sensor system; the digital controller may also include a discovery phase logic engine that controls an initial discovery phase to at least determine the positions of the sensing capacitors in the first array section having the first ink.

[0094] In another aspect, a method of operating a pixelated capacitive sensor system is provided, the method including: providing a capacitive sensor system; sampling through the capacitive sensor system; switching the sensing capacitors by the digital controller; and running a conversion algorithm by the digital controller. The provided capacitive sensor system may include: a sensor array including a plurality of sensing capacitors and a top plate; a comparator operatively connected to each sensing capacitor of the sensor array and the top plate; a switch matrix operatively connected to each sensing capacitor of the sensor array and the top plate; and a digital controller operatively connected to the comparator and the switch matrix. A readout circuit may be formed by the sensor array, the comparator, the digital controller, and the switch matrix.

[0095] In addition, in at least some such embodiments, sampling by the capacitive sensor system may include exposing the sensor array to at least one substance to be tested. Sampling may also include the digital controller connecting the top plate to a reference equal to the comparator reference voltage, setting each sense capacitor of the first array section to a first value and setting each sense capacitor of the second array section to a second value opposite to the first value. Switching the sense capacitors by the digital controller may include: setting the top plate to floating but still connected to the input of the comparator; and operating the switch matrix to switch the value of each sense capacitor of the first array section from the first value to the second value and switch the value of each sense capacitor of the second array section from the second value to the first value. Running the conversion algorithm by the digital controller may include the digital controller determining which ratios of the first array section and the second array section need to be set to make the capacitances equal to each other. Running the conversion algorithm may include the digital controller performing a plurality of iterative stages, where each stage includes the digital controller comparing the average capacitance of a portion of the sense capacitors of the first array section with the average capacitance of a portion of the sense capacitors of the second array section. During a first subset of the plurality of iterative stages, the portion of the sense capacitors of the second array section may be equal to all the sense capacitors of the second array section. The iterative stage may also include a second subset of iterative stages after the first subset of the iterative stage, where the portion of the sense capacitors of the second array section is variable.

[0096] The method may also include, before sampling by the digital controller, a discovery phase by the discovery phase logic engine of the digital controller to at least determine the positions of the sense capacitors in the first array section having the first ink. Performing the discovery phase may include: the block size control logic module of the discovery phase logic selecting a first block of sense capacitors within the area that may include the first array section having the first ink; the block scan control logic module of the discovery phase logic running the conversion algorithm on the first block; the block size control logic module of the discovery phase logic selecting a subsequent block of sense capacitors within the area that may include the first array section having the first ink; and the block scan control logic module of the discovery phase logic running the conversion algorithm on the subsequent block.

[0097] One or more embodiments covered by this document can be advantageous in any of a number of aspects. For example, the pixelated capacitive sensor system of the technology of the present invention can provide improvements related to occupying less area and / or having improved efficiency in power usage. An example embodiment of reusing a pixel sensor as a capacitive DAC can reduce the required hardware, which can lower the production cost. Additionally, one or more embodiments covered by this document can be implemented or used in various applications, such as biochemical applications and imaging applications. At least some such biochemical applications can involve biosensors, for example where a chemically active layer is printed on pixels that bind certain substances, and if the substance binds to the pixel, the capacitance will change and can thus be detected. Furthermore, at least some example embodiments covered by this document can be used as a general capacitive sensing interface, where for example chemical reagents are replaced by microelectromechanical systems (MEMS) (and can be gyroscopes).

[0098] Although the principles of the present invention have been described above in connection with specific devices, it should be clearly understood that this description is by way of example only and is not a limitation on the scope of the present invention. In particular, it is highly desirable that the present invention not be limited to the embodiments and illustrations contained herein, but rather include modifications of those embodiments, including embodiments portions within the scope of the appended claims and combinations of elements of different embodiments.

Claims

1. A capacitive sensor system, characterized in that: include: a sensor array comprising a plurality of sensing capacitors and a top plate; a comparator operably connected to the top plate of the sensor array; a switch matrix operably connected to each sensing capacitor of the sensor array; as well as A digital controller is operably connected to the comparator and the switch matrix.

2. The capacitive sensor system according to claim 1, characterized in that Also included is a readout circuit formed by the sensor array, the comparator, the digital controller and the switch matrix.

3. The capacitive sensor system according to claim 1, characterized in that The sensor array includes at least two sections: a first array section including a first set of sensing capacitors and a second array section including a second set of sensing capacitors; and Wherein the first array section has a first ink on the first set of sensing capacitors and the second array section has a second ink on the second set of sensing capacitors.

4. The capacitive sensor system according to claim 3, characterized in that The first ink includes a first chemical reagent formulated to detect a first analyte, and the second ink includes a second chemical reagent formulated to detect a second analyte different from the first analyte.

5. The capacitive sensor system according to claim 1, characterized in that: The sensor array includes at least three sections: a first array section including a first set of sensing capacitors, a second array section including a second set of sensing capacitors, and a third array section including a third set of sensing capacitors; and Wherein the first array section has a first ink on the first set of sensing capacitors, the second array section has a second ink on the second set of sensing capacitors, and the third array section has a third ink on the third set of sensing capacitors.

6. The capacitive sensor system according to claim 5, characterized in that The first ink includes a first chemical reagent formulated to detect a first analyte, the second ink includes a second chemical reagent formulated to detect a second analyte different from the first analyte, and the third ink includes a third chemical reagent formulated to detect a third analyte different from both the first analyte and the second analyte.

7. The capacitive sensor system according to claim 1, characterized in that: The digital controller includes a conversion logic engine that controls testing operations of the capacitive sensor system.

8. The capacitive sensor system according to claim 7, characterized in that The digital controller additionally includes a discovery phase logic engine that controls an initial discovery phase to at least determine a location of a sensing capacitor in a first array section having a first ink.

9. A capacitive sensor system, characterized in that: include: a sensor array comprising a plurality of sensing capacitors and a top plate; a comparator operably connected to the top plate of the sensor array; a switch matrix operably connected to each sensing capacitor of the sensor array; a digital controller operably connected to the comparator and the switch matrix; as well as A readout circuit is formed by the sensor array, the comparator, the digital controller and the switch matrix.

10. A method of operating a capacitive sensor system, characterized in that The method comprises: A capacitive sensor system is provided, the capacitive sensor system comprising: a sensor array comprising a plurality of sensing capacitors and a top plate; a comparator operably connected to the top plate of the sensor array; a switch matrix operably connected to each sensing capacitor of the sensor array; and a digital controller operably connected to the comparator and the switch matrix; wherein the sensor array comprises at least two sections: a first array section comprising a first set of sensing capacitors and a second array section comprising a second set of sensing capacitors; and wherein the first array section has a first ink on the first set of sensing capacitors and the second array section has a second ink on the second set of sensing capacitors; sampling by the digital controller, including connecting the top plate to a reference equal to a comparator reference voltage, and setting each sensing capacitor of a first array section to a first value and setting each sensing capacitor of a second array section to a second value opposite to the first value; switching the sensing capacitors by the digital controller includes setting the top plate to floating and operating the switch matrix to switch the value of each sensing capacitor of the first array section from the first value to the second value and to switch the value of each sensing capacitor of the second array section from the second value to the first value; and A conversion algorithm is run by the digital controller, including determining by the digital controller which ratios of the first array section and the second array section need to be set to make capacitances equal to each other.

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