Method for manufacturing oxram-type resistive memory cell and related oxram-type memory cell

Abstract

The invention relates to a method for manufacturing an OxRAM resistive memory cell, comprising the following steps:-forming a TiN lower electrode,-first implanting silicon atoms into the lower electrode with a primary implantation dose strictly positive and strictly below 0.7 * 1014 cm <-2 > and a primary implantation acceleration voltage,-second implanting silicon atoms into the lower electrode with a secondary implantation dose strictly positive and strictly below 0.7 * 1014 cm <-2 > and a primary implantation acceleration voltage. Silicon atoms are injected into the lower electrode according to the secondary injection dosage of silicon and the secondary injection acceleration voltage which is strictly greater than the primary injection acceleration voltage; the secondary implantation dose of silicon is strictly positive and strictly lower than 0.6 * 10 < 14 > cm <-2 >; the primary acceleration voltage and the secondary acceleration voltage are selected to have an implantation profile after the primary implantation and the secondary implantation, the implantation profile having a maximum silicon concentration at a depth of between 1 nm and 3 nm from the upper surface of the lower electrode,-depositing an active layer on the implanted lower electrode, and depositing an upper electrode on the active layer.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and the benefit of a French patent application No. FR2314400, filed with the French National Institute of Industrial Property on December 18, 2023, the entire content of which is incorporated herein by reference. Technical field

[0003] The present invention generally relates to the field of microelectronics. More specifically, the present invention relates to the field of filament-type non-volatile resistive memories.

[0004] Specifically, the present invention relates to a method for manufacturing a resistive memory cell of the OxRAM type. The present invention also relates to such a resistive memory cell of the OxRAM type obtained by this manufacturing method. Background art

[0005] Resistive memories, especially oxide-based random access memories (OxRAMs), are non-volatile memories that aim to replace flash-type memories. In addition to high integration density, they also have high operating speeds and good compatibility with the manufacturing methods currently used in the microelectronics industry, especially with the back-end-of-line (BEOL) technology of CMOS (Complementary Metal Oxide Semi-conductor) technology.

[0006] The OxRAM resistive memory includes a plurality of memory cells, also called memory dots. Each OxRAM memory cell is constituted by an M-I-M (Metal-Insulator-Metal) capacitor, which includes an active material with a variable resistance arranged between two metal electrodes, usually a transition metal oxide (e.g., HfO2, Ta2O5, TiO2,...). The memory cell reversibly switches between two resistance states, which correspond to the logical values "0" and "1" used to encode information bits. In some cases, more than two resistance states can be generated, enabling several bits of information to be stored in the same memory cell.

[0007] Information is written into a memory cell by switching the memory cell from a high resistance state (HRS) (also referred to as the “OFF” state) to a low resistance state (LRS) (or “ON” state). Conversely, to erase information from the memory cell, the memory cell is switched from the low resistance state (“OFF”) to the high resistance state (“ON”).

[0008] The change in resistance of the memory cell is determined by the formation and rupture of a conductive filament at the nanoscale cross-section between two electrodes. This conductive filament is generated by the presence of oxygen vacancies in the active layer of the memory cell. By changing the potential applied to the electrodes, the distribution of the filaments can be altered, thereby changing the conductivity between the two electrodes. In the active layer, during the cycle of writing and subsequently resetting the cell, to change the resistance level of the memory cell, the conductive filament either breaks or conversely reforms (by applying a SET voltage VSET or a RESET voltage VRESET to the electrodes respectively to perform a SET (set) operation that results in the LRS state when reshaping the conductive filament and a RESET (reset) operation that results in the HRS state when the conductive filament breaks again).

[0009] Immediately following fabrication, the resistive memory cell is in an original state, which is characterized by having a very high (so-called initial) resistance. When the cell is in the high resistance state, this initial resistance is much larger than the resistance of the cell. The oxide layer is indeed insulating in its initial state. To be able to use the memory cell, a step called “forming” must be implemented. This step consists in a partial reversible breakdown of the oxide in order to generate a conductive filament for the first time (and thus place the memory cell in the low resistance state). After this breakdown, the initially insulating oxide layer becomes active, and the cell can be switched between the low resistance state and the high resistance state by erase and write operations. The forming step is achieved by applying a (so-called “forming”) voltage between the two electrodes of the memory cell that has a value much larger than the nominal operating voltage (used during the next write / erase cycle), for example, applying a voltage on the order of about 2.5V for a nominal voltage on the order of about 1.5V.

[0010] The endurance limit requirements for OxRAM memory cells, which exceed 1,000 cycles or even up to 10,000 cycles (a cycle refers to a write / erase operation, and the endurance limit refers to the fact that it is still possible to distinguish between the HRS state and the LRS state after exceeding a given number of cycles), are crucial, especially for some applications that require very good endurance limits. Summary of the Invention

[0011] Therefore, the present invention aims to improve OxRAM-type resistive memory cells, especially to improve their endurance limits.

[0012] Then, the present invention relates to a method for manufacturing an OxRAM-type resistive memory cell, the method comprising the following steps:

[0013] - Forming a titanium nitride (titanium nitride) lower electrode (lower electrode),

[0014] - First, implanting silicon atoms into the lower electrode at a first implantation dose of silicon and a first implantation acceleration voltage, the first implantation dose of silicon being strictly positive and strictly less than 0.7×10 14 cm -2

[0015] - Second, implanting silicon atoms into the lower electrode at a second implantation dose of silicon and a second implantation acceleration voltage, the second implantation acceleration voltage being strictly greater than the first implantation acceleration voltage, the second implantation dose of silicon being strictly positive and strictly less than 0.6×10 14 cm -2

[0016] The first acceleration voltage and the second acceleration voltage are selected to have an implantation profile after the first implantation and the second implantation, the implantation profile having a maximum silicon concentration at a depth between 1 nm and 3 nm from the upper surface of the lower electrode,

[0017] - Depositing an active layer on the implanted lower electrode,

[0018] - Depositing an upper electrode (upper electrode) on the active layer.

[0019] Surprisingly, under certain conditions of injecting Si into TiN, doping the lower TiN electrode of an OxRAM cell with Si atoms can significantly improve the endurance limit of the cell. This unexpected technical effect is first hypothesized by performing two injections, one at a lower acceleration voltage of Si ions aimed at injecting Si at the surface of the lower electrode of the OxRAM cell, and the other at a higher acceleration voltage of Si ions aimed at injecting Si deeper into the lower electrode of the OxRAM cell. It is also hypothesized that a specific profile is injected into the lower electrode, which has a maximum silicon concentration at a depth between 1 nm and 3 nm from the upper surface of the lower electrode. As will be seen below, under such conditions, the bit error rate (BER) on the group of memory cells obtained by the method according to the invention decreases with the number of cycles, while for other types of cells, the bit error rate (BER) tends to increase and has an unsatisfactory value for applications requiring a significant endurance limit. The lower the error rate, the better the LRS and HRS states can be distinguished on the scale of the memory cell matrix.

[0020] By definition, this error rate corresponds to the percentage of memory cells in the considered group of memory cells that do not have satisfactory characteristics.

[0021] It should be noted that the order of the first injection and the second injection can be reversed, so that the first injection can be carried out before the second injection, or conversely, the second injection can be carried out before the first injection. However, preferably, the first injection is carried out before the second injection.

[0022] In addition to the features just discussed in the previous paragraph, the manufacturing method according to the invention may have one or more of the following additional features (considered separately or according to any technically possible combination):

[0023] - The first acceleration voltage and the second acceleration voltage are selected to have an injection profile after the first injection and the second injection, which has a maximum silicon concentration at a depth between 1 nm and 1.6 nm from the upper surface of the lower electrode, and the width of the injection profile at half the value of the maximum silicon injection concentration is between 1.6 nm and 2 nm.

[0024] - The first acceleration voltage and the second acceleration voltage are selected to have an injection profile after the first injection and the second injection, which has a maximum silicon concentration at a depth between 1.1 nm and 1.5 nm from the upper surface of the lower electrode, and the width of the injection profile at half the value of the maximum silicon injection concentration is between 1.7 nm and 1.9 nm.

[0025] - Depositing the upper electrode on the active layer includes:

[0026] - Deposit a first conductive layer that contacts the active layer and is selected to create oxygen vacancies in the active layer, and

[0027] - Deposit a second conductive layer disposed on the first conductive layer.

[0028] - The material of the first conductive layer is titanium, and the conductive material of the second conductive layer is titanium nitride.

[0029] - The primary acceleration voltage is between 0.3 kV and 0.7 kV, and the secondary acceleration voltage is between 1 kV and 2 kV.

[0030] - The primary acceleration voltage is equal to 0.5 kV, and the secondary acceleration voltage is equal to 1.5 kV.

[0031] - The primary implantation dose of silicon is equal to 0.5×10 14 cm -2 ², and the secondary implantation dose is equal to 0.3×10 14 cm -2

[0032] - Depositing an active layer on the implanted lower electrode includes the following steps:

[0033] - Deposit an active material layer on the implanted lower electrode,

[0034] - Deposit a dielectric oxide layer on the active material layer,

[0035] - Inject silicon atoms through the dielectric oxide layer, and the implantation dose and implantation acceleration voltage are selected such that the silicon atoms are at least partially implanted into the active material layer.

[0036] - The active material is based on hafnium dioxide.

[0037] - The dielectric oxide is based on aluminium oxide.

[0038] - The step of injecting silicon through the dielectric oxide layer is carried out with an implantation acceleration voltage between 1.5 kV and 3.5 kV and preferably equal to 2.5 kV, and a silicon implantation dose between 10 15 cm -2 ² and 5×10 15 cm -2 ² and preferably equal to 2×10 15 cm -2 ² of silicon implantation dose.

[0039] - The material of the first conductive layer is titanium, and the conductive material of the second conductive layer is titanium nitride.

[0040] - The thickness of the titanium nitride bottom electrode is selected to be between 10 nm and 200 nm.

[0041] The present invention also relates to an OxRAM type resistive memory cell obtainable by the method according to the present invention.

[0042] At this stage, it is not possible to structurally characterize the OxRAM type resistive memory cell according to the present invention other than by its manufacturing method. However, compared with the resistive OxRAM type memory cells of the prior art level, the manufacturing method according to the present invention imparts particularly advantageous endurance performance to the OxRAM type memory cell according to the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] With reference to the accompanying drawings, by way of illustration and not limitation, other features and advantages of the present invention will become apparent from the following description, including:

[0044] Figure 1 represents in the form of a logic diagram different steps of the method according to the present invention,

[0045] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 and Figure 8 represent different steps of the method of Figure 1 ,

[0046] Figure 9 represents different implantation profiles in the bottom electrode of the OxRAM type memory cell according to the present invention,

[0047] Figure 10 represents the BER error rate as a function of the number of cycles of different categories of OxRAM type memory cells (including the memory cells according to the present invention).

[0048] Figure 11 and Figure 12 represent the fraction (proportion) of memory cells that require one or more programming repetitions in set and reset, the process as a function of the number of cycles.

[0049] For clarity, the same or similar elements are identified by the same reference numerals throughout the drawings. DETAILED DESCRIPTION

[0050] Figure 1 represents a logic diagram showing different steps of the method for manufacturing a (100) OxRAM memory cell according to the present invention.

[0051] As​​​​​Figure 2 As shown in Figure 2 , method 100 starts with step 101 of forming a first electrode 1, which is formed of a titanium nitride layer corresponding to the lower electrode 1 of an OxRAM memory cell. Thus, this step aims to form the lower electrode 1 on a substrate (the substrate is not shown in the figure), for example. The thickness of the lower electrode 1 is, for example, between 10 nm and 200 nm, and here it is 60 nm.

[0052] In practice, the lower electrode 1 is formed, for example, by reactive sputtering in a vacuum deposition chamber.

[0053] Alternatively, the lower electrode 1 can be formed by chemical vapor deposition or according to a damascene structure (inlaid structure).

[0054] Method 100 continues with step 102 ( Figure 3 ) corresponding to a single implantation of silicon atoms Si into the lower electrode 1.

[0055] According to this single implantation, Si is implanted into the TiN layer of the lower electrode 1 according to a predetermined profile 201 as shown in Figure 9 . The implantation dose D1 and the implantation acceleration voltage V1 are selected to obtain an implantation at the surface of the lower electrode 1. The implantation dose D1 of silicon is strictly positive and strictly less than 0.7×10 14 cm -2 ; according to a preferred embodiment, the dose D1 is equal to 0.5×10 14 cm -2 . The acceleration voltage V1 of the silicon ions is between 0.3 kV and 0.7 kV; according to a preferred embodiment, the acceleration voltage is equal to 0.5 kV.

[0056] Figure 9 Particularly shown are different implantation profiles in the TiN layer of the lower electrode 1, the upper surface of which is defined by the dashed line 200: The single implantation with dose D1 and voltage V1 is represented by profile 201, which has a maximum silicon concentration at a depth of 1.2 nm from the upper surface of the lower electrode, and the width of the implantation profile 201 at half the value of the maximum silicon implantation concentration is equal to 1.5 nm. As a function of the depth in the implanted layer, the implantation profile represents, in a normalized manner, a representative value of the implanted ions (the ratio of the volume concentration of the implanted ions to the implantation ion dose).

[0057] Method 100 continues with step 103 ( Figure 4 ) corresponding to a second implantation of silicon atoms into the lower electrode 1.

[0058] According to this second implantation, according to Figure 9The given profile 202 shown in [description] injects silicon into the TiN layer of the lower electrode 1. The given profile has a maximum silicon concentration at a depth of 2.2 nm from the upper surface of the lower electrode, and the width of the injection profile at half the value of the maximum silicon injection concentration is equal to 3.0 nm. The injection dose D2 and the injection acceleration voltage V2 of this secondary injection are selected to obtain a deeper injection of the lower electrode 1. The injection dose D2 of silicon is strictly positive and strictly less than 0.6×10 14 cm -2 ; according to a preferred embodiment, the dose D2 is equal to 0.3×10 14 cm -2 . The acceleration voltage V2 of the silicon ions is between 1 kV and 2 kV; according to a preferred embodiment, the acceleration voltage is equal to 1.5 kV.

[0059] At the end of steps 102 and 103, the overall profile produced by the primary injection and the secondary injection is shown by reference numeral 203. This overall profile shows a maximum silicon concentration Cmax at a depth between 1 nm and 3 nm (and preferably between 1 nm and 1.6 nm, and also preferably between 1.1 nm and 1.5 nm, and here equal to 1.3 nm) from the upper surface of the lower electrode, and the width Wp of the injection profile at half the value of the maximum silicon injection concentration is between 1.6 nm and 2 nm (and preferably between 1.7 and 1.9 nm, and here equal to 1.86 nm). The injection regions of the primary injection and the secondary injection of the lower electrode 1 are as shown by the reference numeral ZA in Figure 4 the accompanying drawings.

[0060] Then, the method continues with step 104 ( Figure 5 ) of depositing the active material layer 2. The active material layer 2 is formed on the lower electrode 1. The active material layer 2 is deposited in such a way that it has a substantially constant thickness at all points. In this specification, "substantially constant" means that the variation does not exceed 20%, preferably does not exceed 10%, and also preferably does not exceed 5% of the thickness. Here, preferably, the active material layer 2 is based on amorphous hafnium dioxide HfO2. In this specification, the term "based on" means that the layer involved contains more than 50% of the element mentioned after this term (here, for example, this means that the active material layer 2 contains more than 50% of hafnium dioxide). The thickness of the active material layer 2 is between 3 nm and 10 nm, for example 5 nm here.

[0061] In fact, the atomic layer deposition (ALD) method is used to deposit the active material layer 2.

[0062] Alternatively, the active material layer can be deposited by sputtering. Also alternatively, the active material layer can be deposited by a Physical Vapour Deposition (PVD) method. Also alternatively, the active material layer can be deposited by an Ion Beam Deposition (IBD) method.

[0063] As Figure 6 shown, optionally, method 100 continues with step 105 of depositing a dielectric oxide layer 3. This dielectric oxide layer 3 is formed on the active material layer 2. The dielectric oxide layer 3 includes, for example, a metal oxide or a semiconductor oxide. Preferably, it is aluminum oxide Al2O3. Alternatively, it can also be silicon dioxide SiO2.

[0064] The dielectric oxide layer 3 has a thickness between 0.3 nm and 1.5 nm, for example 0.5 nm.

[0065] In fact, the dielectric oxide layer 3 is deposited by an atomic layer deposition (or ALD) method. Alternatively, the dielectric oxide layer 3 can be deposited by sputtering. Also alternatively, the dielectric oxide layer can be deposited by a physical vapour deposition (PVD) method. Also alternatively, the dielectric oxide layer can be deposited by an ion beam deposition (IBD) method.

[0066] The dielectric oxide layer 3 deposited on the layer including the active material is positioned between the layer including the active material and the layer forming the upper electrode. Then, this layer acts as a diffusion barrier against oxygen vacancies (with respect to the filaments) and subsequently improves the switching performance of the memory cell. Specifically, this configuration enables the improvement of the implementation of write and erase cycles. As previously mentioned, step 105 of depositing the dielectric oxide layer can be omitted, and directly proceed from step 104 of depositing the active material layer to step 106 of implanting silicon into the active material layer.

[0067] As Figure 7 shown, method 100 continues with step 106 of implanting silicon into the active layer, which is formed by the Al2O3 dielectric oxide layer 3 and the HfO2 active material layer 2 formed in steps 104 and 105. Silicon is implanted according to the specific profile shown by the reference numeral 204 in Figure 9 the figures. Thus, depending on whether the deposition 105 of the dielectric oxide layer occurs, the so-called active layer either includes only the active material layer 2 or includes a stack of the active material layer and the dielectric oxide layer 3.

[0068] Advantageously, for about 2×10 15 cm -2An implantation dose D3 of the order of magnitude is used to perform the implantation step 106 with an implantation acceleration voltage V3 between 1.5 kV and 3.5 kV (here equal to 2.5 kV).

[0069] As Figure 9 shown, the implantation profile 204 extends into the region ZA of the already implanted lower electrode 1.

[0070] Finally, the method continues with a step 107 of depositing a second electrode 4 that forms the upper electrode ( Figure 8 ). The upper electrode 4 is formed on the active layer formed by the active material layer 2 and the dielectric oxide layer 3 as described above. More specifically, the upper electrode 4 is deposited on the dielectric oxide layer 3.

[0071] The upper electrode 4 includes, for example, a first conductive layer 41 made of titanium Ti and a second conductive layer 42 made of titanium nitride TiN. Therefore, the step of depositing the upper electrode 4 here includes two sub-steps: a first sub-step of depositing the first conductive layer 41 and a second sub-step of depositing the second conductive layer 42.

[0072] Therefore, the first conductive layer 41 is first deposited on the dielectric oxide layer 3. The first conductive layer 41 is formed, for example, by sputtering in a vacuum deposition chamber.

[0073] The first Ti conductive layer 41 has the characteristic of a layer that is adapted to generate oxygen vacancies in the active layer when the first conductive layer 41 contacts the active layer. In accordance with commonly used terminology, the first conductive layer 41 is a layer of the "oxygen scavenging layer" type. Since the mechanism for forming conductive filaments in the dielectric oxide layer 3 generally involves reorganizing oxygen vacancies within the dielectric oxide, the first conductive layer 41 contributes to oxygen exchange with the active layer. It should be noted that the first conductive layer 41 enables the generation of oxygen vacancies in the active material layer 2 even when the first conductive layer is deposited on the dielectric oxide layer 3. In other words, the first conductive layer 41 generates oxygen vacancies in the active material layer 2 whether or not the dielectric oxide layer 3 is deposited.

[0074] Then, the second conductive layer 42 is deposited on the first conductive layer 41. The second conductive layer 42 is formed, for example, by reactive sputtering in a vacuum deposition chamber.

[0075] The thickness of the first conductive layer 41 is between 3 nanometers and 20 nanometers, here 5 nm. The thickness of the second conductive layer 42 is between 10 nanometers and 200 nanometers, here 150 nm.

[0076] At the end of this step 107, an OxRAM type memory cell 5 is obtained in the form of a stack of layers extending along the axis z. The lower electrode 1, the active material layer 2, the dielectric oxide layer 3 and the upper electrode 4 form different layers of this stack. The different layers extend parallel to each other (and parallel to the substrate (not shown) on which the memory cell 5 is mounted). The axis z here is perpendicular to the plane of the different layers of the stack forming the memory cell 5.

[0077] Now the advantages of the OxRAM type memory cell as shown in Figure 8 will be shown, in particular its better endurance performance.

[0078] For this purpose, an indicator, i.e., the bit error rate (BER), evaluated on a group of memory cells (here about 16,000 cells) will be used. By definition, this error rate corresponds to the percentage of memory cells in the considered group of memory cells that do not have satisfactory characteristics.

[0079] In practice, the error rate is evaluated by representing the distribution of the memory cells in the considered group as a function of the resistance R (in ohms Ω) for the LRS and HRS states. The distribution of the memory cells is considered to be cumulative here (it is the Cumulative Distribution Function or CDF). Then, the error rate corresponds to the intersection point of the distributions representing the LRS and HRS states.

[0080] Figure 10 Represent the BER error rates of six types of memory cells C1 to C6 as a function of the number of cycles performed on these cells. One cycle corresponds to the set and reset steps. The C6 type cell is an OxRAM type memory cell according to the present invention and is obtained at the end of the method 100 as shown in Figures 1 to 8 The other cells C1 to C5 have the same stack of layers as the C6 type cell and differ from the latter only in terms of the doping of the lower electrode. Here, the injection characteristics of the lower electrode of the cell C6 according to the present invention are reminded:

[0081] - One injection is performed with an acceleration voltage of 0.5 kV and an injection dose of 0.5×10 14 cm -2 .

[0082] - A second injection is performed with an acceleration voltage of 1.5 kV and an injection dose of 1.5 kV and 0.3×10 14 cm -2 .

[0083] The lower electrode of the C1 type cell undergoes a single implantation with a low acceleration voltage (here 0.5 kV) and an implantation dose of 1×10 14 cm -2 .

[0084] The C2 type cell has a lower electrode that undergoes a double implantation:

[0085] - One implantation is carried out with an acceleration voltage of 0.5 kV and an implantation dose of 1×10 14 cm -2 .

[0086] - A second implantation is carried out with an acceleration voltage of 1.5 kV and an implantation dose of 0.6×10 14 cm -2 .

[0087] The C3 type cell has a lower electrode that undergoes a double implantation:

[0088] - One implantation is carried out with an acceleration voltage of 0.5 kV and an implantation dose of 1×10 14 cm -2 .

[0089] - A second implantation is carried out with an acceleration voltage of 4 kV and an implantation dose of 7×10 14 cm -2 .

[0090] The C4 type cell has a lower electrode that undergoes a double implantation:

[0091] - One implantation is carried out with an acceleration voltage of 0.5 kV and an implantation dose of 2×10 14 cm -2 .

[0092] - A second implantation is carried out with an acceleration voltage of 1.5 kV and an implantation dose of 1.2×10 14 cm -2 .

[0093] The C5 type cell has a lower electrode that has not been implanted.

[0094] As Figure 10As shown, except for the C6-type cells according to the present invention, the error rates of all C1-type to C5-type cells decrease as the number of cycles increases. In contrast, the memory cells according to the present invention have an error rate that gradually decreases with the number of cycles until it stabilizes at around 100 cycles. Even after 10,000 cycles, the error rate of the memory cells according to the present invention remains substantially stable, while the error rate of C5-type cells including those with unimplanted lower electrodes decreases.

[0095] Surprisingly, it can be noted that a simple Si implantation of the lower electrode is not sufficient to improve the endurance performance of OxRAM-type memory cells, since C1 to C4-type cells also have an implantation of the lower electrode and have reduced endurance performance. Therefore, it is appropriate to perform the specific implantation conditions according to the method of the present invention in order to obtain the endurance performance of the memory cells according to the present invention, the inherent characteristics of which cannot be defined at this stage other than by its manufacturing method. It can also be noted that the error rate of the OxRAM-type memory cells according to the present invention begins to decrease as the number of cycles increases. Therefore, it may be of interest to perform a preliminary step (after manufacturing and before use) that includes cycling the memory cells according to the present invention N cycles (where N is an integer greater than or equal to 100) in order to obtain a lower error rate that is stable subsequently.

[0096] Figure 11 and 12 shows another advantage of the OxRAM-type memory cells according to the present invention. These numbers are all based on the so-called "intelligent programming" mechanism. The method includes checking after each operation that the memory cell has a resistance level corresponding to the state in which it has been programmed (set or reset). If this is not the case, the programming operation (set or reset) is repeated the number of times required until the desired resistance level is obtained: the number of iterations required is called the repetition. More precisely, in Figure 11 (set), the repetition consists of repeating the same set pulse. In Figure 12 (reset), the repetition consists of increasing the pulse voltage each time.

[0097] Therefore, Figure 11 shows the fraction of the memory cells C6 according to the present invention and the memory cells C5 without implantation of the lower electrode as a function of the number of cycles, which memory cells must be reprogrammed with a given number of repetitions (from 2 to 5) for the set operation. As an example, it can be seen that in the case where two repetitions are required, there is one cell out of approximately every 10,000 C5 or C6-type cells that is rewritten twice in the 100th cycle. Figure 12Shows the fraction of the memory cell C6 according to the invention and the memory cell C5 without the injection of the lower electrode as a function of the number of cycles, these memory cells having to be reprogrammed with a given number of repetitions (from 2 to 5 times) for the reset operation.

[0098] In the case of the reset operation ( Figure 12 ), it can be noted that the more cycle operations are performed on the memory cell C6 according to the invention, the fewer reprogramming pulses need to be added. Conversely, the C5 type memory cell with an undoped lower electrode requires more repetitions of more than about 100 cycles. This first result confirms that the memory cell according to the invention has a very good endurance limit. In fact, since the number of repetitions required is less, the "stress" on the memory cell is smaller, and this fact leads to better durability of the memory cell.

[0099] In the case of the setting operation ( Figure 11 ), some stability is observed, again confirming the endurance performance of the memory cell according to the invention.

Claims

1. A method for manufacturing an OxRAM type resistive memory cell, the method comprising the following steps: - forming a titanium nitride lower electrode, - First, silicon atoms are implanted into the lower electrode with a primary implantation dose of silicon and a primary implantation acceleration voltage, wherein the primary implantation dose of silicon is strictly positive and strictly lower than 0.7×10 14 cm -2 - Secondly, silicon atoms are implanted into the lower electrode with a secondary implantation dose of silicon and a secondary implantation acceleration voltage, wherein the secondary implantation acceleration voltage is strictly greater than the primary implantation acceleration voltage, and the secondary implantation dose of silicon is strictly positive and strictly lower than 0.6×10 14 cm -2 The primary acceleration voltage and the secondary acceleration voltage are selected to have an implantation profile after the primary implantation and the secondary implantation, the implantation profile having a maximum silicon concentration at a depth between 1 nm and 3 nm from the upper surface of the lower electrode, - depositing an active layer on the implanted lower electrode, - Deposition of the top electrode on the active layer.

2. The method according to claim 1, wherein: The primary acceleration voltage and the secondary acceleration voltage are selected to have an injection profile after the primary injection and the secondary injection, the injection profile having a maximum silicon concentration at a depth between 1nm and 1.6nm from the upper surface of the lower electrode, and a width of the injection profile at half the value of the maximum silicon injection concentration is between 1.6nm and 2nm.

3. The method according to claim 2, wherein: The primary acceleration voltage and the secondary acceleration voltage are selected to have an injection profile after the primary injection and the secondary injection, the injection profile having a maximum silicon concentration at a depth between 1.1 nm and 1.5 nm from the upper surface of the lower electrode, and a width of the injection profile at half the value of the maximum silicon injection concentration is between 1.7 nm and 1.9 nm.

4. The method according to any one of the preceding claims, characterized in that Depositing the upper electrode on the active layer comprises: - depositing a first conductive layer, said first conductive layer being in contact with said active layer and being selected to produce oxygen vacancies in said active layer, and - depositing a second conductive layer disposed on the first conductive layer.

5. The method according to claim 4, wherein: The material of the first conductive layer is titanium, and the conductive material of the second conductive layer is titanium nitride.

6. A method according to any one of the preceding claims, wherein: The primary accelerating voltage is between 0.3 kV and 0.7 kV, and the secondary accelerating voltage is between 1 kV and 2 kV.

7. A method according to any one of the preceding claims, wherein: The primary accelerating voltage is equal to 0.5 kV, and the secondary accelerating voltage is equal to 1.5 kV.

8. A method according to any one of the preceding claims, wherein: The silicon implantation dose is equal to 0.5×10 14 cm -2 , and the silicon secondary implantation dose is equal to 0.3×10 14 cm -2 .

9. A method according to any one of the preceding claims, wherein: Depositing the active layer on the implanted lower electrode comprises the following steps: - depositing a layer of active material on said implanted lower electrode, - depositing a dielectric oxide layer on said active material layer, - implanting silicon atoms through the dielectric oxide layer, the implantation dose and the implantation acceleration voltage being selected such that the silicon atoms are at least partially implanted into the active material layer.

10. The method according to claim 9, wherein: The active material is based on hafnium dioxide.

11. The method according to claim 9 or 10, wherein: The dielectric oxide is based on aluminum oxide.

12. The method according to any one of claims 6 to 8, wherein: The step of implanting silicon through the dielectric oxide layer is performed with an implant acceleration voltage between 1.5 kV and 3.5 kV and preferably equal to 2.5 kV, and a voltage between 10 15 cm -2 With 5×10 15 cm -2 Between and preferably equal to 2×10 15 cm -2 The implantation dose of silicon is carried out.

13. The method according to any one of the preceding claims, characterized in that The thickness of the titanium nitride bottom electrode is selected to be between 10 nm and 200 nm.

14. An OxRAM type memory cell obtainable by a method according to any one of claims 1 to 13.

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