23T4M anti-radiation TCAM storage unit circuit

Abstract

The invention discloses a 23T4M anti-radiation TCAM storage unit circuit which comprises a pre-charging module, an RH reading circuit module, a programmable logic module, a reconfigurable magnetic tunnel junction storage module, a discharging module and an output module. In the RH reading circuit module, the grid electrode of a transistor N7 is connected with the drain electrode of a transistor N8, the grid electrode of the transistor N8 is connected with the drain electrode of the transistor N7, a cross coupling structure is formed, a node S0 and a node S1 are controlled by a node Q and a node QB, meanwhile, the node S0 and the node S1 control the charging and discharging paths of the node Q and the node QB respectively, and after any node is overturned by high-energy particles, the charging and discharging paths of the node Q and the node QB are controlled by the node S0 and the node S1. All the nodes are maintained or charged to recover to the original logic level. According to the method, data upset at a single sensitive node can be completely resisted, and meanwhile, the search error rate of the TCAM is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit memory, and in particular to a 23T4M radiation-resistant TCAM memory cell circuit. Background Art

[0002] With the rapid development of semiconductor technology, the demand for electronic devices to operate in extreme environments is increasing, including space exploration, nuclear energy, and high-radiation medical environments. Under these extreme conditions, electronic devices embedded in SoCs must not only meet high performance and high integration requirements but also possess excellent radiation resistance to ensure system reliability and stability.

[0003] Memory is a crucial component of computer architecture, decisively impacting computer speed, integration, and power consumption. Ternary Content Addressable Memory (TCAM) is widely used in applications requiring high-speed data lookup due to its high-speed and fully parallel data search capabilities. However, current mainstream TCAM memory cells are based on CMOS processes and use charge to represent stored logic values, making them susceptible to radiation particles. When high-energy particles pass through the silicon substrate, they generate minority carriers, which can be diffused and collected by the source or drain. When transistors surrounding the storage node collect these carriers, they may cause changes in the data at the storage node. For CMOS-based TCAM circuits, the reverse-biased PN junction drain is a sensitive node. Radiation particles bombarding sensitive nodes generate localized currents. These transient currents can cause the logic value of the affected sensitive node to suddenly change, generating single-event transient (SET) voltage pulses. The logic change of this sensitive node can also cause the logic value of the memory cell to flip, ie, from '0' to '1' (or from '1' to '0'), which is called a single event upset (SEU).

[0004] Currently, mainstream TCAM memories mainly include those based on static random access memory (SRAM) and dynamic random access memory (DRAM). The term "static" refers to the fact that the data stored in this type of memory remains permanently as long as the power is on. In contrast, the data stored in DRAM requires periodic updating. However, both are volatile memories; when the power supply is cut off, the stored data disappears. The magnetic tunnel junctions (MTJs) used in magnetic random access memory (MRAM) are inherently unaffected by radiation. This is because the data stored in the MTJ is represented by the "up" and "down" directions of the electron spins rather than by charge, making it inherently radiation-resistant, making it an ideal choice for radiation-hardened TCAM applications.

[0005] However, although the core component of magnetic random access memory (MTJ) is a viable alternative storage element that can achieve resistance to soft errors, the charge induced by radiation can still affect the CMOS peripheral circuits, resulting in cell logic value errors. Summary of the Invention

[0006] To address the problem that the peripheral CMOS of TCAM storage elements is susceptible to high-energy particles in high-radiation environments, resulting in logical errors, the present invention proposes a 23T4M radiation-resistant TCAM storage unit circuit, which can completely resist data flipping at a single sensitive node and improve the search error rate of the TCAM.

[0007] In order to achieve the above technical objectives, the technical solution adopted by the present invention is:

[0008] A 23T4M radiation-resistant TCAM memory cell circuit, comprising a precharge module, an RH read circuit module, a programmable logic module, a reconfigurable magnetic tunnel junction memory module, a discharge module, and an output module;

[0009] The input end of the pre-charge module is connected to the pre-charge signal PRE, and the output end is connected to the first internal node Q and the second internal node QB of the RH reading circuit module;

[0010] The RH reading circuit module includes a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor and an eighth NMOS transistor;

[0011] The sources of the third PMOS transistor, the fourth PMOS transistor, the fifth PMOS transistor, and the sixth PMOS transistor are all connected to the power supply Vdd; the drain of the third PMOS transistor P3 is connected to the drain of the first NMOS transistor N1; the drain of the fourth PMOS transistor P4 is connected to the second internal node QB; the source of the first NMOS transistor is connected to the drain of the third NMOS transistor, and the gate is connected to the third internal node S0; the source of the second NMOS transistor is connected to the drain of the fourth NMOS transistor, and the gate is connected to the fourth internal node S1; the drain of the fifth PMOS transistor is connected to the drain of the fifth NMOS transistor; the drain of the sixth PMOS transistor is connected to the drain of the sixth NMOS transistor; the source of the fifth NMOS transistor is connected to the drain of the seventh NMOS transistor; the source of the sixth NMOS transistor is connected to the drain of the eighth NMOS transistor; the sources of the seventh NMOS transistor and the eighth NMOS transistor are connected connected to the ground voltage GND; the gates of the fourth PMOS transistor, the sixth PMOS transistor, the fourth NMOS transistor, and the fifth NMOS transistor are all connected to the first internal node Q; the gates of the third PMOS transistor, the fifth PMOS transistor, the third NMOS transistor, and the sixth NMOS transistor are all connected to the second internal node QB; the sources of the third NMOS transistor and the fourth NMOS transistor are respectively connected to two input terminals of the programmable logic module, each input terminal is respectively connected to two sets of magnetic tunnel junctions of the reconfigurable magnetic tunnel junction storage module; the third internal node S0 and the fourth internal node S1 are controlled by the first internal node Q and the second internal node QB, and the third internal node S0 and the fourth internal node S1 respectively control the charge and discharge paths of the first internal node Q and the second internal node QB, so that after any of the nodes is knocked over by high-energy particles, the logic level is maintained or charged back to the original level;

[0012] At the precharge node, the voltages of the first internal node Q and the second internal node QB are both precharged to VDD; during the data reading phase, the voltages of the first internal node Q and the second internal node QB depend on the resistance difference between the two sets of magnetic tunnel junctions connected to the two input terminals respectively;

[0013] The output end of the reconfigurable magnetic tunnel junction storage module is connected to the input end of the discharge module, and the output end of the discharge module is connected to the ground voltage GND;

[0014] An input terminal of the output module is connected to a second internal node QB of the RH reading circuit module.

[0015] The pre-charging module includes a first PMOS transistor and a second PMOS transistor; wherein the sources of the first PMOS transistor and the second PMOS transistor are both connected to the power supply Vdd, and the gates are both connected to the pre-charging signal PRE; the drains of the first PMOS transistor and the second PMOS transistor are respectively connected to the first internal node Q and the second internal node QB.

[0016] Furthermore, the programmable logic module includes a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, and a twelfth NMOS transistor;

[0017] The drains of the ninth NMOS transistor and the tenth NMOS transistor are both connected to the first output terminal of the RH read module, and the drains of the eleventh NMOS transistor and the twelfth NMOS transistor are both connected to the second output terminal of the RH read module; the gates of the ninth NMOS transistor and the twelfth NMOS transistor are both connected to the first search line signal SL; the gates of the tenth NMOS transistor and the eleventh NMOS transistor are both connected to the second search line signal SLB; the sources of the ninth NMOS transistor, the tenth NMOS transistor, the eleventh NMOS transistor, and the twelfth NMOS transistor are connected as output nodes C1, C2, C3, and C4 to the free layer electrodes of the four groups of magnetic tunnel junctions of the reconfigurable magnetic tunnel junction storage module respectively;

[0018] During the data search phase, the programmable logic module selects different magnetic tunnel junction combinations on the discharge path according to different search data, so that the first internal node Q and the second internal node QB have different discharge rates.

[0019] Furthermore, the reconfigurable magnetic tunnel junction storage module includes a thirteenth NMOS transistor, a fourteenth NMOS transistor, a first magnetic tunnel junction, a second magnetic tunnel junction, a third magnetic tunnel junction and a fourth magnetic tunnel junction;

[0020] The drain of the thirteenth NMOS transistor is connected to the free layer electrode of the first magnetic tunnel junction, and the connection point is C1; the source of the thirteenth NMOS transistor is connected to the free layer electrode of the fourth magnetic tunnel junction, and the connection point is C4; the source of the fourteenth NMOS transistor is connected to the free layer electrode of the second magnetic tunnel junction, and the connection point is C2; the drain of the fourteenth NMOS transistor is connected to the free layer electrode of the third magnetic tunnel junction, and the connection point is C3; the gate of the thirteenth NMOS transistor is connected to the first write line signal WL; the gate of the fourteenth NMOS transistor is connected to the second write line signal WLB; the fixed layer electrodes of the first magnetic tunnel junction and the second magnetic tunnel junction are both connected to the first bit line signal BL; the fixed layer electrodes of the third magnetic tunnel junction and the fourth magnetic tunnel junction are both connected to the second bit line signal BLB;

[0021] During the data writing phase, currents in different directions are passed through the first magnetic tunnel junction, the second magnetic tunnel junction, the third magnetic tunnel junction, and the fourth magnetic tunnel junction according to different written data, thereby changing the resistance of the magnetic tunnel junction.

[0022] Furthermore, the discharge module includes a fifteenth NMOS tube and a sixteenth NMOS tube;

[0023] The drain of the fifteenth NMOS tube is connected to the first bit line signal BL; the drain of the sixteenth NMOS tube is connected to the second bit line signal BLB; the sources of the fifteenth NMOS tube and the sixteenth NMOS tube are both connected to the ground signal GND, and the gates are both connected to the read / write control signal WS.

[0024] Furthermore, the output module includes an inverter and a seventeenth NMOS transistor;

[0025] The input end of the inverter is connected to the second internal node QB, and the output end is connected to the gate of the seventeenth NMOS transistor; the drain of the seventeenth NMOS transistor is connected to the matching line ML, and the source is connected to the ground voltage GND;

[0026] When the second internal node QB is at a low level, the match line ML is discharged to a low level, indicating that the stored data does not match the search data; when the second internal node QB is at a high level, ML remains at a high level, indicating that the stored data matches the search data.

[0027] Compared with the prior art, the present invention has the following beneficial effects:

[0028] First, the 23T4M radiation-resistant TCAM storage cell circuit of the present invention adopts an RH read circuit module based on a symmetrical latch structure. When any sensitive node is flipped by high-energy particle radiation, the logic level of the control output end can be restored, thereby achieving the function of resisting single-node flipping.

[0029] Secondly, the 23T4M radiation-resistant TCAM storage cell circuit of the present invention not only has the ability to resist single-node upset during data information reading, but also can realize the data information reading function with high speed and low power consumption.

[0030] Third, the 23T4M radiation-resistant TCAM storage cell circuit of the present invention, by increasing the number of transistors and data storage nodes on the discharge path, can not only achieve the effect of resisting single-node flipping, but also improve the fault tolerance of the circuit itself, solving the problem of high read error rate of the TCAM circuit.

[0031] Fourthly, the 23T4M radiation-resistant TCAM memory cell circuit of the present invention solves the problem of a discharge path during static operation, reduces the proportion of PMOS transistors, and improves circuit reliability and reading speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A circuit diagram of a 23T4M radiation-resistant TCAM memory cell according to the present invention;

[0033] Figure 2 This is a schematic diagram of the principle of the 23T4M radiation-resistant TCAM storage unit of the present invention;

[0034] Figure 3 This is the circuit diagram of the pre-charging module;

[0035] Figure 4 Read the circuit diagram of the module for RH;

[0036] Figure 5 A circuit diagram of a programmable logic module;

[0037] Figure 6 A circuit diagram of a reconfigurable magnetic tunnel junction memory module;

[0038] Figure 7 This is the circuit diagram of the discharge module;

[0039] Figure 8 This is the circuit diagram of the output module;

[0040] Figure 9 The waveforms of the written data are '0', '1', and 'X' respectively;

[0041] Figure 10 This is the reading waveform when the stored data is '0';

[0042] Figure 11 This is the reading waveform when the stored data is '1';

[0043] Figure 12 This is the reading waveform when the stored data is 'X';

[0044] Figure 13 This is a diagram of the process of restoring the level after a single particle flip when reading data. DETAILED DESCRIPTION

[0045] The embodiments of the present invention are described in further detail below with reference to the accompanying drawings.

[0046] See also Figure 2The present invention discloses a 23T4M radiation-resistant TCAM memory cell circuit, which includes a precharge module, an RH read circuit module, a programmable logic module, a reconfigurable magnetic tunnel junction memory module, a discharge module, and an output module. The input end of the precharge module is connected to a precharge signal PRE; the output end of the precharge module is connected to internal nodes Q and QB of the RH read circuit module. The output end of the RH read circuit module is connected to the input end of the programmable logic module. The output end of the programmable logic module is connected to the input end of the reconfigurable magnetic tunnel junction memory module. The output end of the reconfigurable magnetic tunnel junction memory module is connected to the input end of the discharge module. The output end of the discharge module is connected to a ground voltage GND. The input end of the output module is connected to the second internal node QB of the RH read circuit module.

[0047] Figure 1 This is the overall circuit diagram of one type of radiation-hardened TCAM memory cell circuit. The following describes each module circuit in detail.

[0048] (1) Pre-charging module

[0049] See also Figure 3 The pre-charge module includes two PMOS transistors; the two PMOS transistors are defined as P1 and P2 respectively; the sources of the transistors P1 and P2 are both connected to the power supply Vdd; the gates of the transistors P1 and P2 are both connected to the pre-charge signal PRE; the drains of the transistors P1 and P2 are connected to the internal nodes Q and QB respectively.

[0050] (2)RH reading circuit module

[0051] See also Figure 4The RH read module includes 4 PMOS transistors and 8 NMOS transistors; the 4 PMOS transistors are defined as P3 to P4 respectively; the 8 NMOS transistors are defined as N1 to N8 respectively. The sources of transistors P3, P4, P5 and P6 are all connected to the power supply Vdd; the drain of transistor P3 is connected to the drain of transistor N1; the drain of transistor P4 is connected to the drain of transistor N2; the source of transistor N1 is connected to the drain of transistor N3, and the connection point is the second internal node QB; the source of transistor N2 is connected to the drain of transistor N4, and the connection point is the internal node Q; the drain of transistor P5 is connected to the drain of transistor N5; the drain of transistor P6 is connected to the drain of transistor N6; transistor N5 The source of transistor N1 is connected to the drain of transistor N7, with the connection point being internal node S0. The source of transistor N6 is connected to the drain of transistor N8, with the connection point being internal node S1. The sources of transistors N7 and N8 are connected to ground voltage GND. The gates of transistors P3, P6, N3, and N5 are all connected to internal node Q. The gates of transistors P4, P5, N4, and N6 are all connected to a second internal node QB. The sources of transistors N3 and N4 are connected to the input of the programmable logic module, with connection points defined as A and B, respectively. Node S0 is provided on the line to which the gate of transistor N1, the source of transistor N5, the drain of transistor N7, and the gate of transistor N8 are connected. Node S1 is provided on the line to which the gate of transistor N2, the source of transistor N6, the gate of transistor N7, and the drain of transistor N8 are connected. In the present invention, the gate of transistor N7 is connected to the drain of transistor N8, and the gate of transistor N8 is connected to the drain of transistor N7, forming a cross-coupling structure. Node S0 and node S1 are controlled by node Q and node QB. At the same time, nodes S0 and S1 control the charge and discharge paths of nodes Q and QB, respectively, thereby achieving complete resistance to data flipping at a single sensitive node and improving the search error rate of the TCAM.

[0052] When the circuit operates in the data reading phase, if the internal node Q of the RH reading circuit module is '1', QB is '0', S0 is '1', and S1 is '0', then the drains of transistors P4, P6, N2, N3, N6, and N7 in the RH reading circuit module are all in a reverse biased state. The internal nodes Q and S0 of the RH reading circuit module are both radiation-sensitive nodes. Therefore, the following will analyze the recovery process of the internal node Q after being knocked over by high-energy particles and the recovery process of the internal node S0 after being knocked over by high-energy particles to illustrate the radiation resistance capability of the present invention, as follows:

[0053] (1) When the drain of transistor N3 is hit by high-energy particles, the state of the internal node Q is overturned and the logic level becomes '0', causing transistors N4 and N5 to turn off and transistor P4 to turn on; since transistors P3, P5, N1 and N8 are turned on, and transistors P6, N2, N3, N6 and N7 are turned off; therefore, path 1: the internal node S0 in transistors P5, N5, and N7 remains at a logic level '1', path 2: the internal node S1 in transistors P6, N6, and N8 remains at a logic level '0', path 4: the internal node QB in transistors P4, N2, and N4 remains at a logic level '0', and the internal node Q is charged and restored to a logic level '1' through path 3: transistors P3, N1, and N3.

[0054] (2) When the drain of transistor N7 is hit by high-energy particles, the state of internal node S0 is overturned and the logic level becomes '0', causing transistors N1 and N8 to turn off; since transistors P3, P5, N4 and N5 are turned on, and transistors P4, P6, N2, N3, N6 and N7 are turned off; therefore, path 2: internal node S1 in transistors P6, N6, N8 remains at logic level '0', path 3: internal node Q in transistors P4, N2, N4 remains at logic level '1', path 4: internal node QB in transistors P3, N1, N3 remains at logic level '0', and internal node S0 is charged and restored to logic level '1' through path 1: transistors P5, N5, N7.

[0055] When the circuit operates in the data reading phase, if the internal node Q of the RH reading circuit module is '0', QB is '1', S0 is '0', and S1 is '1', then the drains of transistors P3, P5, N1, N4, N5, and N8 in the RH reading circuit module are all in a reverse biased state. The internal node QB and the internal node S1 of the RH reading circuit module are both radiation-sensitive nodes. Therefore, the following will analyze the recovery process of the internal node QB after being knocked over by high-energy particles and the recovery process of the internal node S1 after being knocked over by high-energy particles to illustrate the radiation resistance capability of the present invention, as follows:

[0056] (1) When the drain of transistor N4 is hit by high-energy particles, the state of the internal node QB is overturned and the logic level becomes '0', causing transistors N3 and N6 to turn off and transistor P3 to turn on; since transistors P4, P6, N2 and N7 are turned on, and transistors P5, N1, N4, N5 and N8 are turned off; therefore, path 1: the internal node S0 in transistors P5, N5, and N7 remains at logic level '0', path 2: the internal node S1 in transistors P6, N6, and N8 remains at logic level '1', path 3: the internal node Q in transistors P4, N2, and N4 remains at logic level '0', and the internal node QB is charged and restored to logic level '1' through path 4: transistors P3, N1, and N3.

[0057] (2) When the drain of transistor N8 is hit by high-energy particles, the state of internal node S1 is overturned and the logic level becomes "0", causing transistors N2 and N7 to turn off; since transistors P4, P6, N3 and N6 are turned on, and transistors P3, P5, N1, N4, N5 and N8 are turned off; therefore, path 1: internal node S0 in transistors P5, N5, N7 remains at logic level "0", path 3: internal node Q in transistors P4, N2, N4 remains at logic level "0", path 4: internal node QB in transistors P3, N1, N3 remains at logic level '1', and internal node S1 is charged and restored to logic level '1' through path 2: transistors P6, N6, N8.

[0058] When the circuit operates in the data read phase, if internal nodes Q and QB of the RH read circuit module are both '1' and '1', the drains of transistors P3, P4, P5, and P6 in the RH read circuit module are all reverse biased, and internal nodes S0 and S1 of the RH read circuit module are both radiation-sensitive nodes. Due to the circuit's symmetry, the recovery process of internal node S0 after being knocked over by high-energy particles will be analyzed below to illustrate the radiation resistance of the present invention. The details are as follows:

[0059] When the drain of transistor N7 is hit by a high-energy particle, the state of the internal node S0 is upset, causing the switching states of transistors N1 and N8 to change; since transistors P3 and P4 of the RH read circuit module are turned off and transistors N9, N10, N11 and N12 of the programmable logic module are turned off, the internal node Q in path 3: transistors P4, N2, N4 remains at logic level '1', and the internal node in path 4: transistors P3, N1, N3 remains at logic level '1'.

[0060] Figure 13 This is a diagram of the process of restoring the level after a single particle flip when reading data.

[0061] (3) Programmable logic module

[0062] See also Figure 5 The programmable logic module includes four NMOS transistors, designated N9 through N12. The drains of transistors N9 and N10 are connected to the output terminal A of the RH read module; the drains of transistors N11 and N12 are connected to the output terminal B of the RH read module; the gates of transistors N9 and N12 are connected to the first search line signal SL; the gates of transistors N10 and N11 are connected to the second search line signal SLB; and the sources of transistors N9, N10, N11, and N12 are connected to internal nodes C1, C2, C3, and C4, respectively.

[0063] (4) Reconfigurable Magnetic Tunnel Junction Storage Module

[0064] See also Figure 6 The reconfigurable MTJ memory module includes two NMOS transistors and four magnetic tunnel junctions; the two NMOS transistors are defined as N13 and N14; the four magnetic tunnel junctions are defined as M1 to M4. The drain of transistor N13 is connected to the free layer electrode of magnetic tunnel junction M1, with the connection point being C1; the source of transistor N13 is connected to the free layer electrode of magnetic tunnel junction M4, with the connection point being C4; the source of transistor N14 is connected to the free layer electrode of magnetic tunnel junction M2, with the connection point being C2; the drain of transistor N14 is connected to the free layer electrode of magnetic tunnel junction M3, with the connection point being C3; the gate of transistor N13 is connected to the first write line signal WL; the gate of transistor N14 is connected to the second write line signal WLB; the fixed layer electrodes of magnetic tunnel junctions M1 and M2 are both connected to the first bit line signal BL; and the fixed layer electrodes of magnetic tunnel junctions M3 and M4 are both connected to the second bit line signal BLB.

[0065] (5) Discharge module

[0066] See also Figure 7 The discharge module includes two NMOS transistors, designated N15 and N16. The drain of transistor N15 is connected to the first bit line signal BL; the drain of transistor N16 is connected to the second bit line signal BLB; the sources of transistors N15 and N16 are both connected to the ground signal GND; and the gates of transistors N15 and N16 are both connected to the read / write control signal WS.

[0067] (6) Output module

[0068] See also Figure 8 The output module includes an inverter and an NMOS transistor, defined as I1 and N17, respectively. The input of the inverter I1 is connected to the second internal node QB, and the output is connected to the gate of the transistor N17. The drain of the transistor N17 is connected to the matching line ML, and the source is connected to the ground voltage GND.

[0069] It should be understood that the focus of the present invention is to propose a new structure of an RH reading circuit module with radiation resistance. Other modules can adopt circuit modules with equivalent functions in the field and are not limited to this embodiment.

[0070] Based on the above circuit diagram, the working principle of the radiation-resistant TCAM memory cell circuit of the present invention is as follows:

[0071] (1) Data writing stage

[0072] In the discharge module, the read / write control signal WS is connected to a low level, and transistors N15 and N16 are turned off.

[0073] The first search line signal SL and the second search line signal SLB are both at a low level, and the transistors N9, N10, N11, and N12 are turned off.

[0074] The first write line signal WL is high, turning on transistor N13. The second write line signal WLB is low, turning off transistor N14. The first bit line signal BL is low, and the second bit line signal BLB is high, causing magnetic tunnel junction M1 to be in an antiparallel state and magnetic tunnel junction M4 to be in a planar state. The first write line signal WL is low, turning off transistor N13. The second write line signal WLB is high, turning on transistor N14. The first bit line signal BL is high, and the second bit line signal BLB is low, causing magnetic tunnel junction M2 to be in a parallel state and magnetic tunnel junction M3 to be in an antiplanar state. Data '0' is stored in the reconfigurable magnetic tunnel junction memory module.

[0075] The first write line signal WL is high, turning on transistor N13. The second write line signal WLB is low, turning off transistor N14. The first bit line signal BL is high, and the second bit line signal BLB is low, setting magnetic tunnel junction M1 to a parallel state and magnetic tunnel junction M4 to an antiparallel state. The first write line signal WL is low, turning off transistor N13. The second write line signal WLB is high, turning on transistor N14. The first bit line signal BL is low, and the second bit line signal BLB is high, setting magnetic tunnel junction M2 to an antiparallel state and magnetic tunnel junction M3 to a planar state. Data '1' is stored in the reconfigurable magnetic tunnel junction memory module.

[0076] The first write line signal WL and the second write signal WLB are high, turning on transistors N13 and N14. The first bit line signal BL is high, and the second bit line signal BLB is low. Magnetic tunnel junctions M1 and M2 are parallel, and magnetic tunnel junctions M3 and M4 are inverted. Data 'X' is stored in the reconfigurable magnetic tunnel junction memory module. Figure 9 The waveforms are shown as follows: '0', '1', and 'X' are written data respectively.

[0077] (2) Pre-charge stage

[0078] In the discharge module, the read / write control signal WS is connected to a low level, and transistors N15 and N16 are turned off;

[0079] The first write line signal WL and the second write line signal WLB are both connected to a low level, and the transistors N13 and N14 are turned off;

[0080] The first search line signal SL and the second search line signal SLB are both connected to a low level, and transistors N9, N10, N11 and N12 are turned off;

[0081] The precharge signal PRE is connected to a low level, transistors P1 and P2 in the precharge module are turned on, and internal nodes Q and QB of the RH read module are precharged to Vdd; at this time, transistors N3 and N4 are turned on, and transistors P3 and P4 are turned off.

[0082] (3) Data reading stage

[0083] In the discharge module, the read / write control signal WS is connected to a high level, and transistors N15 and N16 are turned on;

[0084] The first write line signal WL and the second write line signal WLB are both connected to a low level, and the transistors N13 and N14 are turned off;

[0085] The precharge signal PRE is connected to a high level, and transistors P1 and P2 are turned off;

[0086] The voltages of the internal nodes Q and QB of the RH read circuit module depend on the resistance difference between two sets of magnetic tunnel junctions respectively connected to the output terminal A and the output terminal B of the RH read circuit module.

[0087] (1) The stored data is '0'

[0088] If the data stored in the reconfigurable magnetic tunnel junction memory module is '0', the states of the magnetic tunnel junctions M1 and M3 are in an antiparallel state, and the states of the magnetic tunnel junctions M2 and M4 are in a parallel state.

[0089] When searching for data '0', the first search line signal SL goes low, turning off transistors N9 and N12. The second search line signal SLB goes high, turning on transistors N10 and N11. Output terminal A is connected to a smaller resistor than output terminal B, and internal node Q discharges faster than QB. Consequently, "Q = S0 = 0, QB = S1 = 1," and the value read from the output module match line is '1'.

[0090] When searching for data '1', the first search line signal SL goes high, turning on transistors N9 and N12. The second search line signal SLB goes low, turning off transistors N10 and N11. Output terminal A is connected to a larger resistor than output terminal B, and internal node Q discharges more slowly than QB. Consequently, "Q = S0 = 1, QB = S1 = 0," and the value read from the output module match line is '0'.

[0091] When searching for data 'X', the first search line signal SL and the second search line signal are both low, and transistors N9, N12, N10, and N11 are turned off. Internal nodes Q and QB both remain high, and "Q=QB=1", and the value read from the output module match line is '1'. Figure 10 The waveform diagram is shown when the stored data is '0'.

[0092] (2) The stored data is '1'

[0093] If the data stored in the reconfigurable magnetic tunnel junction memory module is '1', the states of the magnetic tunnel junctions M1 and M3 are parallel, and the states of the magnetic tunnel junctions M2 and M4 are inverse parallel.

[0094] When searching for data '0', the first search line signal SL goes low, turning off transistors N9 and N12. The second search line signal SLB goes high, turning on transistors N10 and N11. Output terminal A is connected to a larger resistor than output terminal B, and internal node Q discharges more slowly than QB. Consequently, "Q = S0 = 1, QB = S1 = 0," and the value read from the output module match line is '0'.

[0095] When searching for data '1', the first search line signal SL goes high, turning on transistors N9 and N12. The second search line signal SLB goes low, turning off transistors N10 and N11. Output terminal A is connected to a smaller resistor than output terminal B, and internal node Q discharges faster than QB. Consequently, "Q = S0 = 0, QB = S1 = 1," and the value read from the output module match line is '1'.

[0096] When searching for data 'X', the first search line signal SL and the second search line signal are both low, and transistors N9, N12, N10, and N11 are turned off. Internal nodes Q and QB both remain high, and "Q=QB=1", and the value read from the output module match line is '1'. Figure 11 The waveform diagram is shown when the stored data is '1'.

[0097] (3) Store data as 'X'

[0098] If the data stored in the reconfigurable magnetic tunnel junction memory module is 'X', the states of the magnetic tunnel junctions M1 and M2 are parallel, and the states of the magnetic tunnel junctions M3 and M4 are inverse parallel.

[0099] When searching for data '0', the first search line signal SL goes low, turning off transistors N9 and N12. The second search line signal SLB goes high, turning on transistors N10 and N11. Output terminal A is connected to a smaller resistor than output terminal B, and internal node Q discharges faster than QB. Consequently, "Q = S0 = 0, QB = S1 = 1," and the value read from the output module match line is '1'.

[0100] When searching for data '1', the first search line signal SL goes high, turning on transistors N9 and N12. The second search line signal SLB goes low, turning off transistors N10 and N11. Output terminal A is connected to a smaller resistor than output terminal B, and internal node Q discharges faster than QB. Consequently, "Q = S0 = 0, QB = S1 = 1," and the value read from the output module match line is '1'.

[0101] When searching for data 'X', the first search line signal SL and the second search line signal are both low, and transistors N9, N12, N10, and N11 are turned off. Internal nodes Q and QB both remain high, and "Q=QB=1", and the value read from the output module match line is '1'. Figure 12 This is the read waveform when the stored data is 'X'.

[0102] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present application.

[0103] Obviously, those skilled in the art may make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalents, this application is intended to include these modifications and variations.

Claims

1. A 23T4M radiation-resistant TCAM memory cell circuit, characterized in that: The radiation-resistant TCAM memory cell circuit includes a precharge module, an RH reading circuit module, a programmable logic module, a reconfigurable magnetic tunnel junction memory module, a discharge module and an output module; The input end of the pre-charge module is connected to the pre-charge signal PRE, and the output end is connected to the first internal node Q and the second internal node QB of the RH reading circuit module; The RH reading circuit module includes a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor and an eighth NMOS transistor; The sources of the third PMOS transistor, the fourth PMOS transistor, the fifth PMOS transistor, and the sixth PMOS transistor are all connected to the power supply Vdd; the drain of the third PMOS transistor P3 is connected to the drain of the first NMOS transistor N1; the drain of the fourth PMOS transistor P4 is connected to the second internal node QB; the source of the first NMOS transistor is connected to the drain of the third NMOS transistor, and the gate is connected to the third internal node S0; the source of the second NMOS transistor is connected to the drain of the fourth NMOS transistor, and the gate is connected to the fourth internal node S1; the drain of the fifth PMOS transistor is connected to the drain of the fifth NMOS transistor; the drain of the sixth PMOS transistor is connected to the drain of the sixth NMOS transistor; the source of the fifth NMOS transistor is connected to the drain of the seventh NMOS transistor; the source of the sixth NMOS transistor is connected to the drain of the eighth NMOS transistor; the sources of the seventh NMOS transistor and the eighth NMOS transistor are connected to the ground voltage GND; the gates of the fourth PMOS transistor, the sixth PMOS transistor, the fourth NMOS transistor, and the fifth NMOS transistor are all connected to the first internal node Q; the gates of the third PMOS transistor, the fifth PMOS transistor, the third NMOS transistor, and the sixth NMOS transistor are all connected to the second internal node QB; the sources of the third NMOS transistor and the fourth NMOS transistor are respectively connected to two input terminals of the programmable logic module, each input terminal is respectively connected to two groups of magnetic tunnel junctions of the reconfigurable magnetic tunnel junction storage module; the third internal node S0 and the fourth internal node S1 are controlled by the first internal node Q and the second internal node QB, and at the same time, the third internal node S0 and the fourth internal node S1 respectively control the charge and discharge paths of the first internal node Q and the second internal node QB, so that after any one of the nodes is knocked over by high-energy particles, all nodes maintain or charge back to the original logic level; At the precharge node, the voltages of the first internal node Q and the second internal node QB are both precharged to VDD; In the data reading phase, the voltage of the first internal node Q and the second internal node QB depends on the resistance difference between the two groups of magnetic tunnel junctions connected to the two input terminals respectively; The output end of the reconfigurable magnetic tunnel junction storage module is connected to the input end of the discharge module, and the output end of the discharge module is connected to the ground voltage GND; An input terminal of the output module is connected to a second internal node QB of the RH reading circuit module.

2. The 23T4M radiation-resistant TCAM memory cell circuit according to claim 1, wherein: The pre-charging module includes a first PMOS transistor and a second PMOS transistor; wherein the sources of the first PMOS transistor and the second PMOS transistor are both connected to the power supply Vdd, and the gates are both connected to the pre-charging signal PRE; the drains of the first PMOS transistor and the second PMOS transistor are respectively connected to the first internal node Q and the second internal node QB.

3. The 23T4M radiation-resistant TCAM memory cell circuit according to claim 1, wherein: The programmable logic module includes a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor and a twelfth NMOS transistor; The drains of the ninth NMOS transistor and the tenth NMOS transistor are both connected to the first output terminal of the RH read module, and the drains of the eleventh NMOS transistor and the twelfth NMOS transistor are both connected to the second output terminal of the RH read module; the gates of the ninth NMOS transistor and the twelfth NMOS transistor are both connected to the first search line signal SL; the gates of the tenth NMOS transistor and the eleventh NMOS transistor are both connected to the second search line signal SLB; the sources of the ninth NMOS transistor, the tenth NMOS transistor, the eleventh NMOS transistor, and the twelfth NMOS transistor are connected as output nodes C1, C2, C3, and C4 to the free layer electrodes of the four groups of magnetic tunnel junctions of the reconfigurable magnetic tunnel junction storage module respectively; During the data search phase, the programmable logic module selects different magnetic tunnel junction combinations on the discharge path according to different search data, so that the first internal node Q and the second internal node QB have different discharge rates.

4. The 23T4M radiation-resistant TCAM memory cell circuit according to claim 1, wherein: The reconfigurable magnetic tunnel junction storage module includes a thirteenth NMOS transistor, a fourteenth NMOS transistor, a first magnetic tunnel junction, a second magnetic tunnel junction, a third magnetic tunnel junction and a fourth magnetic tunnel junction; The drain of the thirteenth NMOS transistor is connected to the free layer electrode of the first magnetic tunnel junction, and the connection point is C1; the source of the thirteenth NMOS transistor is connected to the free layer electrode of the fourth magnetic tunnel junction, and the connection point is C4; the source of the fourteenth NMOS transistor is connected to the free layer electrode of the second magnetic tunnel junction, and the connection point is C2; the drain of the fourteenth NMOS transistor is connected to the free layer electrode of the third magnetic tunnel junction, and the connection point is C3; the gate of the thirteenth NMOS transistor is connected to the first write line signal WL; the gate of the fourteenth NMOS transistor is connected to the second write line signal WLB; the fixed layer electrodes of the first magnetic tunnel junction and the second magnetic tunnel junction are both connected to the first bit line signal BL; the fixed layer electrodes of the third magnetic tunnel junction and the fourth magnetic tunnel junction are both connected to the second bit line signal BLB; During the data writing phase, currents in different directions are passed through the first magnetic tunnel junction, the second magnetic tunnel junction, the third magnetic tunnel junction, and the fourth magnetic tunnel junction according to different written data, thereby changing the resistance of the magnetic tunnel junction.

5. The 23T4M radiation-resistant TCAM memory cell circuit according to claim 1, wherein: The discharge module includes a fifteenth NMOS tube and a sixteenth NMOS tube; The drain of the fifteenth NMOS tube is connected to the first bit line signal BL; the drain of the sixteenth NMOS tube is connected to the second bit line signal BLB; the sources of the fifteenth NMOS tube and the sixteenth NMOS tube are both connected to the ground signal GND, and the gates are both connected to the read / write control signal WS.

6. The 23T4M radiation-resistant TCAM memory cell circuit according to claim 1, characterized in that: The output module includes an inverter and a seventeenth NMOS tube; The input end of the inverter is connected to the second internal node QB, and the output end is connected to the gate of the seventeenth NMOS transistor; the drain of the seventeenth NMOS transistor is connected to the matching line ML, and the source is connected to the ground voltage GND; When the second internal node QB is at a low level, the match line ML is discharged to a low level, indicating that the stored data does not match the search data; when the second internal node QB is at a high level, ML remains at a high level, indicating that the stored data matches the search data.

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