Semiconductor structure, preparation method and electronic equipment

Abstract

The invention relates to a semiconductor structure, a preparation method and electronic equipment. The preparation method of the semiconductor structure comprises the following steps: providing a substrate, wherein the substrate comprises a patterned mask layer; forming trenches arranged at intervals in the substrate along a first direction parallel to the top surface of the substrate to obtain an active region defined by the trenches; etching back a part of the second dielectric layer and increasing the size of the opening; at least oxidizing a part of the active region below the target top surface and a corner of the part of the active region into a corner oxide layer with a rounded arc surface; and after the second dielectric layer is removed, at least a third dielectric layer with a flush top surface is formed on the top surface of the first dielectric layer, and the first dielectric layer, the corner oxide layer and the third dielectric layer are used for forming a gate dielectric layer of the gate together. The gate dielectric layer is formed by steps, so that the top surface of the active region can be ensured to be flush, a rounded cambered surface is ensured to be formed at the corner of the active region, the problem of transistor electric leakage caused by warping of the edge of the active region is avoided, and the reliability and the electrical property of the semiconductor device are improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and particularly relates to a semiconductor structure, a preparation method and an electronic device. Background Art

[0002] When semiconductor devices are applied to high voltages, the gate insulating layer of high-voltage devices must have strong breakdown voltage resistance to avoid dielectric breakdown at high potentials. Compared with low-voltage devices, the gate insulating layer of high-voltage devices is generally designed to be thicker. In the semiconductor production process, dry oxidation and wet oxidation are two main oxidation methods for forming the gate oxide insulating layer. They react with silicon wafers through different processes to generate a silicon dioxide film to form the gate oxide insulating layer.

[0003] However, in the preparation process of the traditional gate oxide insulating layer, warping defects will occur at the edges of the active regions, which will further lead to leakage and reduced reliability of the transistors. Summary of the Invention

[0004] The purpose of the present application is to provide a semiconductor structure, a preparation method and an electronic device, which solve the problem that warping occurs at the edges of the active regions during the preparation of the gate oxide insulating layer of the semiconductor structure, thereby causing transistor leakage, and improve the reliability and electrical properties of the semiconductor structure. To achieve the purpose of the present application, the following technical solutions are provided:

[0005] In a first aspect, the present application provides a preparation method of a semiconductor structure, including:

[0006] Providing a substrate, wherein a patterned mask layer is included on the substrate, and the patterned mask layer includes an opening for defining a trench; the patterned mask layer includes a first dielectric layer and a second dielectric layer conformally covering the first dielectric layer; the thickness of the first dielectric layer is less than or equal to a preset value;

[0007] Etching the substrate based on the patterned mask layer to form trenches arranged at intervals in a first direction parallel to the top surface of the substrate in the substrate, and obtaining active regions defined by the trenches;

[0008] Etching back a part of the second dielectric layer and increasing the size of the opening to expose a target top surface of a part of the first dielectric layer;

[0009] At least oxidizing a part of the active region below the target top surface and a corner of a part of the active region into a corner oxide layer with a rounded arc surface, and the top surface of the corner oxide layer is higher than the top surface of the first dielectric layer;

[0010] After removing the second dielectric layer, a third dielectric layer flush with the top surface is formed at least on the top surface of the first dielectric layer. The first dielectric layer, the corner oxide layer, and the third dielectric layer are used to jointly form the gate dielectric layer of the gate.

[0011] In the method for manufacturing the semiconductor structure of the present application, by etching the substrate based on the patterned mask layer, while etching out the trench, the active region can be defined, and the patterned mask layer covers the top surface of the active region, which can protect the top surface of the active region from being damaged by etching. Further etching back a part of the second dielectric layer can expose the corner at the top of the active region. Further, by oxidizing the corner at the top surface of the active region, a corner oxide layer with a rounded arc surface can be formed at the corner of the active region. The corner oxide layer can prevent the situation where the top corner of the active region protrudes due to too slow oxidation rate during the formation of the gate dielectric layer. In addition, since the first dielectric layer covers the top surface of the active region, the top surface of the active region will not be oxidized, and thus the top surface of the active region can be ensured to be flush. Finally, removing the second dielectric layer, a third dielectric layer flush with the top surface is formed at least on the top surface of the first dielectric layer. The third dielectric layer, the first dielectric layer, and the corner oxide layer jointly form the gate dielectric layer. By forming the gate dielectric layer in steps, the top surface of the active region can be ensured to be flush, and a rounded arc surface can be ensured to be formed at the corner of the active region, avoiding the problem of transistor leakage caused by warping at the edge of the active region, and improving the reliability and electrical properties of the semiconductor device.

[0012] In some embodiments, the thickness of the first dielectric layer, the thickness of the third dielectric layer, is related to the thickness of the gate dielectric layer.

[0013] In some embodiments, the top surface of the third dielectric layer is not lower than the top surface of the corner oxide layer.

[0014] In some embodiments, etching back a part of the second dielectric layer and increasing the size of the opening includes:

[0015] Using the first dielectric layer as the stop layer, etching back a part of the second dielectric layer and increasing the size of the opening; or

[0016] During the process of etching back a part of the second dielectric layer and increasing the size of the opening, a part of the first dielectric layer is removed to expose the target top surface of the first dielectric layer with a target thickness.

[0017] In some embodiments, the substrate includes silicon; forming the corner oxide layer includes:

[0018] Oxidizing a part of the active region below the target top surface and the surface of the active region exposed by the trench to form the corner oxide layer including silicon oxide.

[0019] In some embodiments, during the process of forming the corner oxide layer, a part of the substrate and a part of the active region at the bottom corner of the trench are oxidized to form a corner silicon oxide layer.

[0020] In some embodiments, after forming the corner oxide layer and before removing the second dielectric layer, the following steps are further included:

[0021] A dielectric layer is filled in the trench, and the top surface of the dielectric layer is not lower than the top surface of the first dielectric layer.

[0022] In some embodiments, the first dielectric layer includes silicon oxide; and / or

[0023] The second dielectric layer includes silicon nitride.

[0024] In a second aspect, the present application further provides a semiconductor structure, which is prepared by using the preparation method of the semiconductor structure according to any one of the above embodiments;

[0025] The semiconductor structure includes:

[0026] A substrate, which includes trenches and active regions arranged alternately in a first direction parallel to the top surface of the substrate;

[0027] The top surface of the active region includes a first dielectric layer;

[0028] A corner oxide layer with a rounded arc surface is included between the first dielectric layer and the active region;

[0029] The corner of the active region has a rounded arc surface, and the corner of the active region is covered with the corner oxide layer.

[0030] The semiconductor structure of the present application includes a substrate, trenches, active regions, a first dielectric layer, and a corner oxide layer. By covering the top surface of the active region with the first dielectric layer, it can be ensured that the top surface of the active region will not be oxidized during the process of forming the corner oxide layer, and thus the top surface of the active region can be kept flat and the complete morphology of the top surface of the active region can be maintained. By covering the corner of the active region with the corner oxide layer, it can be ensured that a rounded arc surface is formed at the corner of the active region, avoiding the problem of transistor leakage caused by warping at the edge of the active region, and improving the reliability and electrical properties of the semiconductor device.

[0031] In a third aspect, the present application further provides an electronic device, including:

[0032] Prepared by using the preparation method of the semiconductor structure according to any one of the first aspects; or

[0033] The semiconductor structure according to the second aspect.

[0034] For the electronic device of the present application, by etching the substrate based on the patterned mask layer, while etching out the trenches, the active region can be defined, and the patterned mask layer covers the top surface of the active region, which can protect the top surface of the active region from being damaged by etching. Further, by etching back a part of the second dielectric layer, the corners at the top of the active region can be exposed. Further, by oxidizing the corners at the top surface of the active region, the corners of the active region can form a corner oxide layer with a rounded arc surface. The corner oxide layer can prevent the top surface corners of the active region from protruding at the corners due to the too slow oxidation rate during the formation of the gate dielectric layer. In addition, since the first dielectric layer covers the top surface of the active region, the top surface of the active region will not be oxidized, and thus the top surface of the active region can be ensured to be flat. Finally, the second dielectric layer is removed, and a third dielectric layer with a flat top surface is formed at least on the top surface of the first dielectric layer. The third dielectric layer, the first dielectric layer, and the corner oxide layer together constitute the gate dielectric layer. By forming the gate dielectric layer in steps, the top surface of the active region can be ensured to be flat, and a rounded arc surface can be ensured to be formed at the corners of the active region, avoiding the problem of transistor leakage caused by warping at the edge of the active region, and improving the reliability and electrical properties of the semiconductor device. Description of the Drawings

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0036] Figure 1 is a flowchart of a method for manufacturing a semiconductor structure provided in an embodiment;

[0037] Figure 2 is a cross-sectional structure schematic diagram of the structure obtained in step S11 in a method for manufacturing a semiconductor structure provided in an embodiment;

[0038] Figure 3 is a cross-sectional structure schematic diagram of the structure obtained in step S12 in a method for manufacturing a semiconductor structure provided in an embodiment;

[0039] Figure 4 is a cross-sectional structure schematic diagram of the structure obtained in step S13 in a method for manufacturing a semiconductor structure provided in an embodiment;

[0040] Figure 5 is a cross-sectional structure schematic diagram of the structure obtained in step S14 in a method for manufacturing a semiconductor structure provided in an embodiment;

[0041] Figure 6It is a schematic cross-sectional structure diagram of the structure obtained in step S16 in a method for preparing a semiconductor structure provided in an embodiment;

[0042] Figure 7 It is a schematic cross-sectional structure diagram of the structure obtained in step S15 in a method for preparing a semiconductor structure provided in an embodiment;

[0043] Figure 8 It is a schematic cross-sectional structure diagram of a semiconductor structure provided in another embodiment.

[0044] Description of the reference numerals

[0045] 10. Substrate; 20. Patterned mask layer; 201. First dielectric layer; 202. Second dielectric layer; 30. Trench; 40. Active region; 50. Corner oxide layer; 60. Third dielectric layer; 70. Dielectric layer. Detailed implementation manners

[0046] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0047] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used in the description of this application herein are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0048] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or portions, these elements, components, regions, layers, doping types and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or portion from another element, component, region, layer, doping type or portion. Thus, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or portion discussed below may be referred to as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0049] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. are used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as "under" or "beneath" or "underneath" another element or feature will be oriented "on" the other element or feature. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. In addition, the device may also include additional orientations (such as rotating 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0050] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that when the terms "comprises" and / or "includes" are used in this specification, the presence of the stated features, integers, steps, operations, elements and / or components can be determined, but one or more other features, integers, steps, operations, elements, components and / or groups are not excluded from the presence or addition. Also, as used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0051] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic illustrations of ideal embodiments (and intermediate structures) of the invention, such that variations in the shapes shown are to be expected, for example, due to manufacturing techniques and / or tolerances. Accordingly, embodiments of the invention should not be limited to the specific shapes of regions shown herein, but include shape deviations resulting, for example, from manufacturing techniques. For example, an implantation region shown as rectangular will typically have rounded or curved features at its edges and / or an implantation concentration gradient, rather than a binary change from the implantation region to the non-implantation region. Similarly, a buried region formed by implantation can result in some implantation in the region between the buried region and the surface through which the implantation occurs. Thus, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of the regions of the device and do not limit the scope of the invention.

[0052] In the case where semiconductor devices are applied to high voltages, the gate insulating layer of high-voltage devices must have strong breakdown voltage resistance to avoid dielectric breakdown at high potentials. Compared with low-voltage devices, the gate insulating layer of high-voltage devices is generally designed to be thicker. In the semiconductor manufacturing process, dry oxidation and wet oxidation are two main oxidation methods for forming the gate oxide insulating layer. They react with silicon wafers through different processes to generate a silicon dioxide film to form the gate oxide insulating gate layer.

[0053] However, in the conventional technology, during the process of forming a thicker gate oxide insulating layer, the growth of thick oxygen on the substrate surface is affected by the height of the STI (Shallow Trench Isolation) oxide. The closer to the edge of the active region, the smaller the oxidant concentration and the slower the oxidation rate, resulting in more consumption of the silicon substrate in the central region of the active region than in the edge region, thus causing warping defects at the edge of the active region. As the thickness of the gate oxide insulating layer increases, more silicon in the central region of the active region is consumed, and thus the phenomenon of warping at the edge of the active region becomes more serious. The warped morphology of the active region will cause leakage of the transistor, reduce the reliability of the semiconductor device, and increase the probability of device failure.

[0054] Embodiments of the present application provide a method for preparing a semiconductor structure. Please refer to Figure 1 , the method for preparing the semiconductor structure includes:

[0055] S11: Provide a substrate, on which a patterned mask layer is included. The patterned mask layer includes an opening for defining a trench; the patterned mask layer includes a first dielectric layer and a second dielectric layer conformally covering the first dielectric layer; the thickness of the first dielectric layer is less than or equal to a preset value.

[0056] Exemplarily, please refer to Figure 2, the substrate 10 may include but is not limited to at least one of a silicon substrate, a gallium nitride (GaN) substrate, a silicon carbide (SiC) substrate, a sapphire substrate, a silicon on insulator (SOI) substrate, a silicon on diamond (SOD) substrate, and a strained layer silicon substrate deposited on a germanium silicon wafer; in this embodiment, the substrate 10 is a silicon substrate.

[0057] Exemplarily, the patterned mask layer 20 includes a first dielectric layer 201 and a second dielectric layer 202 conformally covering the first dielectric layer 201. The second dielectric layer 202 can, while etching the opening of the trench 30, serve as a protective layer for the materials of the first dielectric layer 201 and the substrate 10 to prevent the materials of the first dielectric layer 201 and the substrate 10 from being damaged during the etching step. The preset value of the thickness of the first dielectric layer 201 can be set according to the thickness of the gate dielectric layer, and the thickness of the first dielectric layer 201 is positively correlated with the thickness of the gate dielectric layer.

[0058] S12: Etch the substrate based on the patterned mask layer to form trenches arranged at intervals in a first direction parallel to the top surface of the substrate within the substrate, and obtain an active region defined by the trenches.

[0059] Exemplarily, please refer to Figure 3 , it is possible to use but is not limited to a photolithography process to etch the substrate 10 based on the patterned mask layer 20 to form a trench 30 within the substrate 10 and obtain an active region 40 defined by the trench 30.

[0060] S13: Etch back a part of the second dielectric layer and increase the size of the opening to expose the target top surface of a part of the first dielectric layer.

[0061] Exemplarily, please refer to Figure 4 , it is possible to use but is not limited to a photolithography process to etch back a part of the second dielectric layer 202 and increase the size of the opening to expose the target top surface of a part of the first dielectric layer 201, so as to provide space for forming a corner oxide layer 50 at the corner of the active region 40 and the target top surface of the first dielectric layer 201 subsequently.

[0062] S14: At least oxidize the part of the active region below the target top surface and the corners of the part of the active region into a corner oxide layer with a rounded arc surface, and the top surface of the corner oxide layer is higher than the top surface of the first dielectric layer.

[0063] Exemplarily, please refer to Figure 5, a thermal oxidation process or other processes can be used to oxidize part of the active region 40 below the target top surface and the corners of part of the active region 40 into a corner oxide layer 50 with a rounded arc surface. The corner oxide layer 50 can compensate for the protrusions that occur at the corners of the active region 40 during the formation of the gate dielectric layer due to the too slow oxidation rate, thereby causing warping of the top surface of the active region 40 and avoiding the problem of leakage.

[0064] S16: After removing the second dielectric layer, form a third dielectric layer flush with the top surface at least on the top surface of the first dielectric layer. The first dielectric layer, the corner oxide layer, and the third dielectric layer are used to jointly form the gate dielectric layer of the gate.

[0065] Exemplarily, please refer to Figure 6 , a thermal oxidation process or other processes can be used to form a third dielectric layer 60 flush with the top surface on the top surface of the first dielectric layer 201. The first dielectric layer 201, the corner oxide layer 50, and the third dielectric layer 60 jointly form the gate dielectric layer of the gate. By forming the gate dielectric layer in steps, the corners of the active region can be rounded, avoiding the defect of warping of the top surface of the active region.

[0066] In the method for manufacturing the semiconductor structure of the present application, by etching the substrate 10 based on the patterned mask layer 20, the trench 30 can be etched out while defining the active region 40, and the patterned mask layer 20 covers the top surface of the active region 40, which can protect the top surface of the active region 40 from being damaged by etching. Further, part of the second dielectric layer 202 is etched back to expose the corners at the top of the active region 40. Further, by oxidizing the corners of the top surface of the active region 40, a corner oxide layer 50 with a rounded arc surface can be formed at the corners of the active region 40. The corner oxide layer 50 can prevent the corners at the top surface of the active region 40 from protruding at the corners due to the too slow oxidation rate during the formation of the gate dielectric layer. In addition, since the first dielectric layer 201 covers the top surface of the active region 40, the top surface of the active region 40 will not be oxidized, and thus the top surface of the active region 40 can be ensured to be flush. Finally, the second dielectric layer 202 is removed, and a third dielectric layer 60 flush with the top surface is formed at least on the top surface of the first dielectric layer 201. The third dielectric layer 60, the first dielectric layer 201, and the corner oxide layer 50 jointly form the gate dielectric layer. By forming the gate dielectric layer in steps, the top surface of the active region 40 can be ensured to be flush, and a rounded arc surface can be ensured to be formed at the corners of the active region 40, avoiding the problem of transistor leakage caused by warping at the edge of the active region 40, and improving the reliability and electrical properties of the semiconductor device.

[0067] In some embodiments, please continue to refer to Figure 6 , the thickness of the first dielectric layer 201, the thickness of the third dielectric layer 60, and the thickness of the gate dielectric layer.

[0068] Exemplarily, the thickness of the first dielectric layer 201 and the thickness of the third dielectric layer 60 are related to the thickness of the gate dielectric layer. When the thickness of the gate dielectric layer to be prepared is determined, the first dielectric layer 201 and the third dielectric layer 60 with corresponding thicknesses need to be prepared according to the thickness requirement of the gate dielectric layer to be prepared.

[0069] It should be noted that since the third dielectric layer 60 is formed on the basis of the first dielectric layer 201, the sum of the thickness of the first dielectric layer 201 and the thickness of the third dielectric layer 60 is determined by the thickness of the gate dielectric layer jointly constituted by the first dielectric layer 201, the corner oxide layer 50, and the third dielectric layer 60.

[0070] In the manufacturing method of the semiconductor structure provided in the embodiments of the present application, by jointly relating the thickness of the first dielectric layer 201 and the thickness of the third dielectric layer 60 to the thickness of the gate dielectric layer, on the premise of preparing a gate dielectric layer with a known thickness, the thickness of the gate dielectric layer can be controlled by setting the thickness of the first dielectric layer 201 and the thickness of the third dielectric layer 60, and the thickness of the gate dielectric layer can be controlled by preparing the thickness of the first dielectric layer 201 and preparing the thickness of the third dielectric layer 60. Therefore, during the process of preparing the gate dielectric layer, the thickness of the gate dielectric layer can be adjusted multiple times to improve the accuracy of the thickness of the gate dielectric layer.

[0071] In some embodiments, please continue to refer to Figure 6 , the top surface of the third dielectric layer 60 is not lower than the top surface of the corner oxide layer 50.

[0072] As an example, the top surface of the third dielectric layer 60 not being lower than the top surface of the corner oxide layer 50 can make the contact area between the third dielectric layer 60 and the corner oxide layer 50 flush, thereby making the top surface of the formed gate dielectric layer smooth, so that the surface morphology of the gate dielectric layer is uniform, dense, and defect-free.

[0073] In the manufacturing method of the semiconductor structure provided in the embodiments of the present application, by the top surface of the third dielectric layer 60 not being lower than the top surface of the corner oxide layer 50, a gate dielectric layer with a uniform morphology can be formed, so that the dielectric constant of the gate dielectric layer is more stable, the capacitance rate is increased, the electric field coupling between the gate and the channel is enhanced, and the switching performance of the transistor is improved. It can improve the durability of the device and reduce the degradation of the dielectric layer caused by factors such as electrochemical reaction and thermal stress. Improve the performance and reliability of semiconductor devices.

[0074] In some embodiments, please refer to Figure 4 , etch back a part of the second dielectric layer 202 and increase the size of the opening, including: using the first dielectric layer 201 as a stop layer, etching back a part of the second dielectric layer 202 and increasing the size of the opening.

[0075] Exemplarily, taking the first dielectric layer 201 as the stop layer, a lithography process or other processes can be used to etch back a part of the second dielectric layer 202 and increase the size of the opening.

[0076] In the manufacturing method of the semiconductor structure provided in the embodiments of the present application, by taking the first dielectric layer 201 as the stop layer, etching back a part of the second dielectric layer 202 and increasing the size of the opening, while increasing the size of the opening, the first dielectric layer 201 can be retained. Furthermore, a third dielectric layer 60 and a corner oxide layer 50 can be formed on the basis of the first dielectric layer 201, so that the first dielectric layer 201, the corner oxide layer 50, and the third dielectric layer 60 together constitute the gate dielectric layer. In this way, during the formation of the gate dielectric layer, the problem of the corner protrusion of the active region 40 can be avoided, and the reliability of the semiconductor device can be improved.

[0077] In some embodiments, please continue to refer to Figure 4 , etching back a part of the second dielectric layer 202 and increasing the size of the opening includes: during the process of etching back a part of the second dielectric layer 202 and increasing the size of the opening, removing a part of the first dielectric layer 201 to expose a target top surface of the first dielectric layer 201 with a target thickness.

[0078] Exemplarily, a lithography process or other processes can be used to etch back a part of the second dielectric layer 202.

[0079] In the manufacturing method of the semiconductor structure provided in the embodiments of the present application, by removing a part of the first dielectric layer 201 during the process of etching back a part of the second dielectric layer 202 and increasing the size of the opening to expose a target top surface of the first dielectric layer 201 with a target thickness, a first dielectric layer 201 with a target thickness can be obtained during the process of etching back the second dielectric layer 202, the thickness of the first dielectric layer can be accurately controlled, and further, a corner oxide layer 50 can be formed on the target top surface of the first dielectric layer 201. In this way, during the formation of the gate dielectric layer, the problem of the corner protrusion of the active region 40 can be avoided, and the reliability of the semiconductor device can be improved.

[0080] In some embodiments, please refer to Figure 5 , the substrate 10 includes silicon; forming the corner oxide layer 50 includes: oxidizing a part of the active region 40 below the target top surface and the surface of the active region 40 exposed by the trench 30 to form the corner oxide layer 50 including silicon oxide.

[0081] It should be noted that the substrate 10 including silicon enables the formation of the corner oxide layer 50 from the silicon substrate 10 and the oxygen in the oxidation atmosphere during the oxidation process.

[0082] Exemplarily, a thermal oxidation process or other processes may be used to oxidize a part of the active region 40 below the target top surface and the surface of the active region 40 exposed by the trench 30 to form a corner oxide layer 50 including silicon oxide.

[0083] In the method for manufacturing a semiconductor structure provided in the embodiment of the present application, by oxidizing a part of the active region 40 below the target top surface and the surface of the active region 40 exposed by the trench 30, the substrate 10 can directly react with oxygen during oxidation to form the corner oxide layer 50. Furthermore, it can be avoided that the top corner of the active region 40 bulges at the corner during the formation of the gate dielectric layer due to too slow oxidation rate. Thus, the problem of transistor leakage caused by warping at the edge of the active region 40 can be avoided, and the reliability and electrical properties of the semiconductor device can be improved.

[0084] In some embodiments, please continue to refer to Figure 5 During the process of forming the corner oxide layer 50, a part of the substrate 10 and a part of the active region 40 at the bottom corner of the trench 30 are oxidized to form a corner silicon oxide layer.

[0085] Exemplarily, during the process of forming the corner oxide layer 50, a thermal oxidation process or other processes may be used to oxidize a part of the substrate 10 and a part of the active region 40 at the bottom corner of the trench 30 to form a corner silicon oxide layer.

[0086] In the method for manufacturing a semiconductor structure provided in the embodiment of the present application, by oxidizing a part of the substrate 10 and a part of the active region 40 at the bottom corner of the trench 30 to form a corner silicon oxide layer during the process of forming the corner oxide layer 50, it can be avoided that the top corner of the active region 40 bulges at the corner during the formation of the gate dielectric layer due to too slow oxidation rate. Furthermore, the problem of transistor leakage caused by warping at the edge of the active region 40 can be avoided, and the reliability and electrical properties of the semiconductor device can be improved.

[0087] In some embodiments, after forming the corner oxide layer 50 and before removing the second dielectric layer 202, the following steps are further included:

[0088] S15: Filling a dielectric layer in the trench, and the top surface of the dielectric layer is not lower than the top surface of the first dielectric layer.

[0089] Exemplarily, please refer to Figure 7 A dielectric layer 70 is filled in the trench 30 by an oxidation process or other processes, and the top surface of the dielectric layer 70 is not lower than the top surface of the first dielectric layer 201. The filled dielectric layer 70 may include, but is not limited to, an insulating layer, such as an oxide layer.

[0090] In the embodiment of the present application, the method for preparing a semiconductor structure can effectively isolate different electrodes in a semiconductor device by filling a dielectric layer 70 in a trench 30, prevent short circuits between the electrodes, and ensure that the device can operate normally. Moreover, it can reduce the capacitance between the gate and the drain or source, and improve the switching speed of the power device.

[0091] In some embodiments, referring to Figure 1 , the first dielectric layer 201 includes silicon oxide.

[0092] It should be noted that since the first dielectric layer 201 includes silicon oxide, a corner oxide layer 50 and a third dielectric layer 60 can be formed on the basis of the silicon oxide, and then a gate dielectric layer jointly composed of the first dielectric layer 201, the corner oxide layer 50 and the third dielectric layer 60 is formed.

[0093] In the embodiment of the present application, in the method for preparing a semiconductor structure, by setting the first dielectric layer 201 as silicon oxide, during the subsequent formation of the corner oxide layer 50 and the third dielectric layer 60, the first dielectric layer 201 always covers the top surface of the active region 40, which can protect the top surface of the active region 40 from being oxidized. Furthermore, the top surface of the active region 40 can always maintain a complete morphology, avoiding the phenomenon that the top surface of the active region 40 is oxidized and deformed during the oxidation process, and further avoiding the problem of transistor leakage caused by warping at the edge of the active region 40, thereby improving the reliability and electrical properties of the semiconductor device.

[0094] In some embodiments, continue to refer to Figure 1 , the second dielectric layer 202 includes silicon nitride.

[0095] Exemplarily, the second dielectric layer 202 includes silicon nitride. Of course, in other examples, other materials can be used as the second dielectric layer 202 to define the opening of the trench 30 through the second dielectric layer 202 as a mask layer.

[0096] In the embodiment of the present application, in the method for preparing a semiconductor structure, by setting the second dielectric layer 202 as silicon nitride, when etching the substrate 10 based on the pattern of the second dielectric layer 202, the resolution of the pattern can be improved during the pattern transfer process, and the details of the pattern can be accurately defined. And it can resist the mechanical stress generated during the etching process, thereby maintaining the integrity of the mask layer, and further improving the performance and reliability of the semiconductor device.

[0097] The embodiment of the present application provides a semiconductor structure. Refer to Figure 8, prepared by using the preparation method of the semiconductor structure according to any one of the above embodiments; the semiconductor structure includes: a substrate 10, which includes trenches 30 and active regions 40 arranged alternately in a first direction parallel to the top surface of the substrate 10; the top surface of the active region 40 includes a first dielectric layer 201; between the first dielectric layer 201 and the active region 40, there is a corner oxide layer 50 with a rounded arc surface; the corners of the active region 40 have rounded arc surfaces, and the corners of the active region 40 are covered with the corner oxide layer 50.

[0098] Exemplarily, the substrate 10 may include but is not limited to at least one of a silicon substrate, a gallium nitride (GaN) substrate, a silicon carbide (SiC) substrate, a sapphire substrate, a silicon on insulator (SOI) substrate, a silicon on diamond (SOD) substrate, and a strained layer silicon substrate deposited on a germanium silicon wafer; in this embodiment, the substrate 10 is a silicon substrate.

[0099] Exemplarily, the first dielectric layer 201 may include but is not limited to a silicon oxide layer. The corner oxide layer may include but is not limited to an oxide layer.

[0100] The semiconductor structure of the present application includes a substrate 10, trenches 30, active regions 40, a first dielectric layer 201, and a corner oxide layer 50. By covering the top surface of the active region 40 with the first dielectric layer 201, it can be ensured that the top surface of the active region 40 will not be oxidized during the formation of the corner oxide layer 50, and thus the top surface of the active region 40 can be kept flat and the complete morphology of the top surface of the active region 40 can be maintained. By covering the corners of the active region 40 with the corner oxide layer 50, it can be ensured that rounded arc surfaces are formed at the corners of the active region 40, avoiding the problem of transistor leakage caused by warping at the edges of the active region 40, and improving the reliability and electrical properties of the semiconductor device.

[0101] The embodiment of the present application provides an electronic device, prepared by using the preparation method of the semiconductor structure according to any one of the above embodiments.

[0102] In the electronic device of the present application, by etching the substrate based on the patterned mask layer, a trench can be etched while defining an active region, and the patterned mask layer covers the top surface of the active region, which can protect the top surface of the active region from being damaged by etching. Further, by etching back a part of the second dielectric layer, the corner at the top of the active region can be exposed. Further, by oxidizing the corner at the top surface of the active region, a corner oxide layer with a rounded arc surface can be formed at the corner of the active region. The corner oxide layer can prevent the top corner of the active region from protruding at the corner due to too slow oxidation rate during the formation of the gate dielectric layer. In addition, since the first dielectric layer covers the top surface of the active region, the top surface of the active region will not be oxidized, and thus the top surface of the active region can be ensured to be flat. Finally, the second dielectric layer is removed, and a third dielectric layer with a flat top surface is formed at least on the top surface of the first dielectric layer. The third dielectric layer, the first dielectric layer, and the corner oxide layer together constitute the gate dielectric layer. By forming the gate dielectric layer in steps, the top surface of the active region can be ensured to be flat, and a rounded arc surface can be ensured to be formed at the corner of the active region, avoiding the problem of transistor leakage caused by warping at the edge of the active region, and improving the reliability and electrical properties of the semiconductor device.

[0103] An embodiment of the present application provides an electronic device, including the semiconductor structure in the above embodiment.

[0104] In the electronic device of the present application, since the top surface of the active region 40 is covered with the first dielectric layer 201, it can be ensured that the top surface of the active region 40 will not be oxidized during the formation of the corner oxide layer 50, and thus the top surface of the active region 40 can be ensured to be flat, maintaining the complete morphology of the top surface of the active region 40. Since the corner of the active region 40 is covered with the corner oxide layer 50, it can be ensured that a rounded arc surface is formed at the corner of the active region 40, avoiding the problem of transistor leakage caused by warping at the edge of the active region 40, and improving the reliability and electrical properties of the semiconductor device.

[0105] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0106] The above embodiments only represent several implementation manners of the present application, and the description thereof is relatively specific and detailed, but it should not be understood as a limitation to the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several deformations and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a patterned mask layer, the patterned mask layer comprising an opening for defining a groove; the patterned mask layer comprising a first dielectric layer and a second dielectric layer conformally covering the first dielectric layer; the thickness of the first dielectric layer is less than or equal to a preset value; Etching the substrate based on the patterned mask layer to form grooves arranged at intervals along a first direction parallel to the top surface of the substrate in the substrate, thereby obtaining an active area defined by the grooves; etching back a portion of the second dielectric layer and increasing the size of the opening to expose a portion of the target top surface of the first dielectric layer; Oxidizing at least a portion of the active area below the target top surface and a portion of the corners of the active area into a corner oxide layer having a rounded arc surface, wherein the top surface of the corner oxide layer is higher than the top surface of the first dielectric layer; After removing the second dielectric layer, a third dielectric layer having a top surface flush with at least the top surface of the first dielectric layer is formed. The first dielectric layer, the corner oxide layer and the third dielectric layer are used to jointly constitute a gate dielectric layer of a gate.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: The thickness of the first dielectric layer, the thickness of the third dielectric layer and the thickness of the gate dielectric layer are related.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that: A top surface of the third dielectric layer is not lower than a top surface of the corner oxide layer.

4. The method for preparing a semiconductor structure according to claim 1, characterized in that: The step of etching back a portion of the second dielectric layer and increasing the size of the opening comprises: Using the first dielectric layer as a stop layer, partially etching back the second dielectric layer and increasing the size of the opening; or In the process of etching back a portion of the second dielectric layer and increasing the size of the opening, a portion of the first dielectric layer is removed to expose a portion of the target top surface of the first dielectric layer having a target thickness.

5. The method for preparing a semiconductor structure according to any one of claims 1 to 4, characterized in that: The substrate comprises silicon; forming the corner oxide layer comprises: A portion of the active area below the target top surface and the surface of the active area exposed by the trench are oxidized to form the corner oxide layer including silicon oxide.

6. The method for preparing a semiconductor structure according to claim 5, characterized in that: In the process of forming the corner oxide layer, part of the substrate and part of the active area at the corner of the bottom of the trench are oxidized to form a corner silicon oxide layer.

7. The method for preparing a semiconductor structure according to any one of claims 1 to 4, characterized in that: After forming the corner oxide layer and before removing the second dielectric layer, the method further includes: A dielectric layer is filled in the trench, and a top surface of the dielectric layer is not lower than a top surface of the first dielectric layer.

8. The method for preparing a semiconductor structure according to any one of claims 1 to 4, characterized in that: The first dielectric layer comprises silicon oxide; and / or The second dielectric layer includes silicon nitride.

9. A semiconductor structure, characterized in that: Prepared by the method for preparing a semiconductor structure according to any one of claims 1 to 8; The semiconductor structure comprises: A substrate, comprising grooves and active areas alternately arranged along a first direction parallel to a top surface of the substrate; The top surface of the active region includes a first dielectric layer; A corner oxide layer having a rounded arc surface is included between the first dielectric layer and the active area; The corners of the active area have rounded arc surfaces, and the corners of the active area are covered with the corner oxide layer.

10. An electronic device, characterized in that: include: Prepared by the method for preparing a semiconductor structure according to any one of claims 1 to 8; or The semiconductor structure of claim 9.

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