Semiconductor device and method of forming semiconductor device

Abstract

The invention provides a semiconductor device and a method of forming the same. The semiconductor device includes a substrate, a first element and a second element. The substrate includes a first active region and a second active region defined by an element isolation structure. The first element is disposed in the first active region and includes a first gate structure. The first gate structure includes a first gate electrode and a first gate dielectric layer disposed between the substrate and the first gate electrode. The second element is disposed in the second active region and includes a second gate structure. The second gate structure includes a second gate electrode and a second gate dielectric layer disposed between the substrate and the second gate electrode. The first gate dielectric layer includes a first portion in contact with the substrate and a second portion protruding from the first portion in a vertical direction. A thickness of the first portion in the vertical direction is smaller than a thickness of the second gate dielectric layer in the vertical direction. A top surface of the second portion of the first gate dielectric layer is at the same level as a top surface of the second gate dielectric layer.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method of forming a semiconductor device. Background Art

[0002] Power semiconductor devices, such as metal oxide semiconductor field effect transistors (MOSFETs), are power devices commonly used in analog and / or digital circuits. They can be classified into planar power semiconductor devices and vertical power semiconductor devices according to the direction of current flow. In planar power semiconductor devices, common means to increase the operating voltage of the power semiconductor device include increasing the distance between the gate and the drain or the thickness of the gate dielectric layer.

[0003] However, in order to meet various requirements of users for electronic components, it is necessary to integrate power components and / or logic components with different operating voltages. However, integrating these components with different operating voltages requires a trade-off among component performance, complexity, feasibility, or stability of the manufacturing process. For example, a power device with an operating voltage of 32V (hereinafter referred to as the first power device) and a power device with an operating voltage of 20V (hereinafter referred to as the second power device) are designed to have different gate dielectric layer thicknesses. However, considering the complexity, feasibility, or stability of the manufacturing process, the gate dielectric layers of the first power device and the second power device are formed to have the same thickness, which will inevitably sacrifice the performance of one of the first power device and the second power device.

[0004] Therefore, those skilled in the art continue to strive to integrate power components and / or logic components with different operating voltages without sacrificing component performance and with good or acceptable manufacturing process complexity, stability, or feasibility. Summary of the Invention

[0005] The present invention provides a semiconductor device and a method of forming a semiconductor device. The first gate dielectric layer of the first component is designed to include a first portion in contact with the substrate and a second portion protruding from the first portion. The thickness of the first portion is less than the thickness of the second gate dielectric layer of the second component, and the top surface of the second portion is at the same horizontal height as the top surface of the second gate dielectric layer. In this way, the semiconductor device can integrate power components and / or logic components (such as the first component and the second component) with different operating voltages without sacrificing component performance and with good manufacturing process stability.

[0006] An embodiment of the present invention provides a semiconductor device, which includes a substrate, a first element, and a second element. The substrate includes a first active region and a second active region defined by an element isolation structure. The first element is disposed in the first active region and includes a first gate structure. The first gate structure includes a first gate electrode and a first gate dielectric layer disposed between the substrate and the first gate electrode. The second element is disposed in the second active region and includes a second gate structure. The second gate structure includes a second gate electrode and a second gate dielectric layer disposed between the substrate and the second gate electrode. The first gate dielectric layer includes a first portion in contact with the substrate and a second portion protruding from the first portion in a vertical direction. The thickness of the first portion in the vertical direction is less than the thickness of the second gate dielectric layer in the vertical direction, and the top surface of the second portion is at the same horizontal height as the top surface of the second gate dielectric layer.

[0007] In some embodiments, the top surface of the first gate electrode includes a groove recessed toward the substrate.

[0008] In some embodiments, the top surface of the first gate electrode in the region other than the groove is at the same horizontal height as the top surface of the second gate electrode.

[0009] In some embodiments, the horizontal area of the second element is larger than the horizontal area of the first element.

[0010] In some embodiments, the first element includes a first isolation structure. The first isolation structure is disposed in the first active region to define, together with the element isolation structure, a region of the first source / drain in which the first element is disposed and to define, under the first gate structure, a region of the first doped region in which the first element is disposed. The second portion of the first gate dielectric layer overlaps with the first isolation structure in the vertical direction.

[0011] In some embodiments, the first element includes a first gate spacer disposed on the sidewall of the first gate electrode, and the second portion of the first gate dielectric layer is disposed between the first gate electrode and the first gate spacer in the horizontal direction.

[0012] In some embodiments, the second element includes a second gate spacer disposed on the sidewall of the second gate electrode.

[0013] In some embodiments, the semiconductor device further includes a third element, which is disposed in a third active region different from the first active region and the second active region defined by the element isolation structure and includes a third gate structure. The third gate structure includes a third gate electrode, a third gate dielectric layer disposed between the substrate and the third gate electrode, and a third gate spacer disposed on the sidewall of the third gate electrode. The third gate spacer is in contact with the substrate.

[0014] In some embodiments, the horizontal area of the third element is smaller than the horizontal area of the first element and the horizontal area of the second element.

[0015] In some embodiments, the second element includes a second isolation structure, which is disposed in the second active region to define, together with the element isolation structure, a region where the second source / drain of the second element is formed and to define, under the second gate structure, a region where the second doped region of the second element is formed. The width of the second doped region in the horizontal direction is greater than the width of the first doped region in the horizontal direction.

[0016] An embodiment of the present invention provides a method for forming a semiconductor device, which includes the following steps: forming an element isolation structure in a substrate to define a first active region and a second active region; forming a dielectric material layer on the first active region and the second active region of the substrate; patterning the dielectric material layer on the first active region to form a first groove in the dielectric material layer on the first active region; forming a gate material layer on the dielectric material layer; and patterning the gate material layer and the dielectric material layer to form a first gate electrode on the first active region and a first gate dielectric layer disposed between the substrate and the first gate electrode, and to form a second gate electrode on the second active region and a second gate dielectric layer disposed between the substrate and the second gate electrode. The first gate dielectric layer includes a first portion in contact with the substrate and a second portion protruding from the first portion in the vertical direction. The thickness of the first portion in the vertical direction is smaller than the thickness of the second gate dielectric layer in the vertical direction. The top surface of the second portion is formed at the same horizontal height as the top surface of the second gate dielectric layer.

[0017] In some embodiments, the method for forming a semiconductor device further includes forming a first gate spacer and a second gate spacer on the sidewalls of the first gate electrode and the second gate electrode, respectively. The second portion of the first gate dielectric layer is disposed between the first gate electrode and the first gate spacer in the horizontal direction.

[0018] In some embodiments, the top surface of the first gate electrode includes a second groove that is recessed toward the substrate and above the first groove.

[0019] In some embodiments, the top surface of the first gate electrode is formed at the same horizontal height as the top surface of the second gate electrode in the region other than the second groove.

[0020] In some embodiments, the method for forming a semiconductor device further includes forming a first isolation structure in the first active region to define, together with the element isolation structure, a region where the first source / drain is formed and to define, under the first gate electrode, a region where the first doped region is formed. The second portion of the first gate dielectric layer overlaps with the first isolation structure in the vertical direction.

[0021] In some embodiments, the method of forming a semiconductor device further includes forming a second isolation structure in a second active region to define, together with the device isolation structure, a region in which a second source / drain is formed and to define, under a second gate electrode, a region in which a second doped region is formed. The width of the second doped region in the horizontal direction is greater than the width of the first doped region in the horizontal direction.

[0022] In some embodiments, the device isolation structure defines a third active region in the substrate, and in the step of forming a first groove in the dielectric layer on the first active region, the dielectric layer formed on the third active region is also removed.

[0023] In some embodiments, in the step of patterning the gate material layer and the dielectric material layer, a third gate electrode and a third gate dielectric layer disposed between the substrate and the third gate electrode are formed in the third active region. In the step of forming the first gate spacer and the second gate spacer, a third gate spacer is formed on the sidewall of the third gate electrode, and the third gate spacer contacts the substrate.

[0024] Based on the above, in the above semiconductor device and the method of forming a semiconductor device, the first gate dielectric layer is designed to include a first portion in contact with the substrate and a second portion protruding from the first portion, wherein the thickness of the first portion is less than the thickness of the second gate dielectric layer of the second device, and the top surface of the second portion is at the same horizontal height as the top surface of the second gate dielectric layer. In this way, the semiconductor device can integrate power elements and / or logic elements (such as the first element and the second element) with different operating voltages without sacrificing the performance of the first element or the second element and with good manufacturing process stability. Description of the Drawings

[0025] Figures 1 to 10 is a cross-sectional schematic view of a method of forming a semiconductor device according to an embodiment of the present invention;

[0026] Figure 11 is a cross-sectional schematic view of a first element according to an embodiment of the present invention;

[0027] Figure 12 is a cross-sectional schematic view of a first element according to another embodiment of the present invention.

[0028] Symbol Description

[0029] 10, 20, 30: Semiconductor device

[0030] 100: Substrate

[0031] 102a: First well region

[0032] 102b: Second well region

[0033] 104a: First doped region

[0034] 104b: Second doped region

[0035] 106a: Third well region

[0036] 106b: Fourth well region

[0037] 110: Element isolation structure

[0038] 112: First isolation structure

[0039] 114: Second isolation structure

[0040] 120, 120a: Dielectric material layer

[0041] 122a, 122b, 130, 140: Dielectric layer

[0042] 150: Gate material layer

[0043] GE1: First gate electrode

[0044] GE2: Second gate electrode

[0045] GE3: Third gate electrode

[0046] GE4: Fourth gate electrode

[0047] GOx_1: First gate dielectric layer

[0048] GOx_2: Second gate dielectric layer

[0049] GOx_3: Third gate dielectric layer

[0050] GOx_4: Fourth gate dielectric layer

[0051] GS1, GS1', GS1'': First gate structure

[0052] GS2: Second gate structure

[0053] GS3: Third gate structure

[0054] GS4: Fourth gate structure

[0055] HK1, HK2: High-k layer

[0056] HV1: First active region

[0057] HV2: Second active region

[0058] LV: Third active region

[0059] MV: Fourth active region

[0060] MG1, MG2: Metal Gate

[0061] OP1: First Opening

[0062] OP2: Second Opening

[0063] PR1, PR2, PR3: Mask Pattern

[0064] t1, t2: Thickness

[0065] r1: First Groove

[0066] r2: Second Groove

[0067] SD1: First Source / Drain

[0068] SD2: Second Source / Drain

[0069] SD3: Third Source / Drain

[0070] SD4: Fourth Source / Drain

[0071] SW1: First Gate Spacer

[0072] SW2: Second Gate Spacer

[0073] SW3: Third Gate Spacer

[0074] SW4: Fourth Gate Spacer Detailed Embodiments

[0075] The present invention will be described more fully with reference to the accompanying drawings of the embodiments. However, the present invention may be embodied in various different forms and should not be limited to the embodiments described herein. The thicknesses of the layers and regions in the drawings are exaggerated for clarity. Identical or similar reference numerals denote identical or similar elements, and will not be described repeatedly in the following paragraphs.

[0076] It should be understood that when an element is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element, or there may also be intervening elements. If an element is referred to as being "directly on" or "directly connected to" another element, then there are no intervening elements. As used herein, "connected" can refer to physical and / or electrical connection, and "electrically connected" or "coupled" can mean that there are other elements between two elements. "Electrically connected" as used herein can include physical connection (e.g., wired connection) and physical disconnection (e.g., wireless connection).

[0077] As used herein, "about," "approximate," or "substantially" includes the recited value and an average within an acceptable deviation range of a particular value that would be recognized by one of ordinary skill in the art, taking into account the particular amounts of the measurements discussed and the errors associated with the measurements (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations of the recited value, or within ±30%, ±20%, ±10%, or ±5%. Moreover, "about," "approximate," or "substantially" as used herein can be selected with respect to optical properties, etch properties, or other properties to choose a more acceptable deviation range or standard deviation, rather than applying a single standard deviation to all properties.

[0078] The terms used herein are for the purpose of describing exemplary embodiments only and are not intended to limit the invention. In such instances, unless the context dictates otherwise, the singular forms include the plural forms.

[0079] Figures 1 to 10 is a cross-sectional schematic view of a method for forming a semiconductor device according to an embodiment of the invention.

[0080] In some embodiments, a method for forming a semiconductor device (such as Figure 10 the semiconductor device 10 shown) may include the following steps.

[0081] First, refer to Figure 1 , and form an element isolation structure 110 in a substrate 100 that defines a first active region HV1 and a second active region HV2. In some embodiments, the element isolation structure 110 may define a third active region LV and a fourth active region MV in the substrate 100 that are different from the first active region HV1 and the second active region HV2. In some embodiments, the first active region HV1 and the second active region HV2 may be regions in which high-voltage semiconductor elements are disposed; the third active region LV may be a region in which low-voltage semiconductor elements are disposed; and the fourth active region MV may be a region in which medium-voltage semiconductor elements are disposed. In some embodiments, the operating voltage (e.g., 20V) of the high-voltage semiconductor element disposed in the first active region HV1 may be lower than the operating voltage (e.g., 32V) of the high-voltage semiconductor element disposed in the second active region HV2. In some embodiments, the operating voltage of the low-voltage semiconductor element disposed in the third active region LV may be lower than the operating voltage of the medium-voltage semiconductor element disposed in the fourth active region MV. In some embodiments, the operating voltage of the high-voltage semiconductor element disposed in the first active region HV1 may be higher than the operating voltage of the medium-voltage semiconductor element disposed in the fourth active region MV.

[0082] The substrate 100 may include a semiconductor substrate or a semiconductor on insulator (SOI) substrate. The semiconductor material in the semiconductor substrate or the SOI substrate may include an elemental semiconductor, an alloy semiconductor, or a compound semiconductor. For example, the elemental semiconductor may include Si or Ge. The alloy semiconductor may include SiGe, SiGeC, etc. The compound semiconductor may include SiC, group III-V semiconductor materials, or group II-VI semiconductor materials. The group III-V semiconductor materials may include GaN, GaP, GaAs, AlN, AlP, AlAs, InN, InP, InAs, GaNP, GaNAs, GaPAs, AlNP, AlNAs, AlPAs, InNP, InNAs, InPAs, GaAlNP, GaAlNAs, GaAlPAs, GaInNP, GaInNAs, GaInPAs, InAlNP, InAlNAs, or InAlPAs. The group II-VI semiconductor materials may include CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, HgS, HgSe, HgTe, CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnSe, CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe, or HgZnSTe. The semiconductor material may be doped with dopants of a first conductivity type or dopants of a second conductivity type complementary to the first conductivity type. For example, the first conductivity type may be P-type, and the second conductivity type may be N-type. In some embodiments, the substrate 100 may be doped with P-type dopants. In some embodiments, the element isolation structure 110 may include silicon oxide.

[0083] In some embodiments, a first isolation structure 112 may be formed in the first active region HV1 to define, together with the element isolation structure 110, a region for subsequently forming a first source / drain and to define, within the first isolation structure 112, a region for subsequently forming a first doped region. In some embodiments, a second isolation structure 114 may be formed in the second active region HV2 to define, together with the element isolation structure 110, a region for subsequently forming a second source / drain and to define, within the second isolation structure 114, a region for subsequently forming a second doped region. In some embodiments, the first isolation structure 112 and the second isolation structure 114 may include silicon oxide.

[0084] Next, please refer to Figure 2, a first well region 102a and a second well region 102b are respectively formed in a first active region HV1 and a second active region HV2 of a substrate 100. Then, a first doped region 104a is formed in a region defined by a first isolation structure 112 in the first active region HV1, and a second doped region 104b is formed in a region defined by a second isolation structure 114 in the second active region HV2. In some embodiments, the first doped region 104a may have a conductivity type different from that of the first well region 102a. In this way, the first doped region 104a can divide the first well region 102a into two parts. For example, the first well region 102a may be doped with dopants of a first conductivity type, while the first doped region 104a may be doped with dopants of a second conductivity type. In some embodiments, the second doped region 104b may have a conductivity type different from that of the second well region 102b. In this way, the second doped region 104b can divide the second well region 102b into two parts. For example, the second well region 102b may be doped with dopants of a first conductivity type, while the second doped region 104b may be doped with dopants of a second conductivity type. In some embodiments, the width of the second doped region 104b in the horizontal direction is greater than the width of the first doped region 104a in the horizontal direction.

[0085] Then, please refer to Figure 3 , a dielectric material layer 120 is formed on the first active region HV1 and the second active region HV2 of the substrate 100. In some embodiments, the dielectric material layer 120 covers the first active region HV1 and the second active region HV2 of the substrate 100 and exposes a third active region LV and a fourth active region MV of the substrate 100. In some embodiments, the dielectric material layer 120 may include a material for a gate dielectric layer such as silicon oxide.

[0086] After that, please refer to Figure 4 , a third well region 106a and a fourth well region 106b are respectively formed in the third active region LV and the fourth active region MV of the substrate 100. The third well region 106a and the fourth well region 106b may each be doped with dopants of a first conductivity type or a second conductivity type complementary to the first conductivity type.

[0087] Next, please refer to Figure 5 , a dielectric layer 130 is formed on the third active region LV and the fourth active region MV of the substrate 100. In some embodiments, the dielectric layer 130 may include a material for a gate dielectric layer such as silicon oxide.

[0088] Then, please refer to Figure 5 and Figure 6, pattern the dielectric material layer 120 on the first active region HV1 to form a first groove r1 in the dielectric material layer 120 on the first active region HV1. In some embodiments, the first groove r1 can be formed by the following steps. First, form a mask layer on the first active region HV1, the second active region HV2, and the fourth active region MV, where the mask layer includes a mask pattern PR1 formed on the first active region HV1 and exposing a part of the dielectric material layer 120 above it, a mask pattern PR2 formed on the second active region HV2 and completely covering the dielectric material layer 120 above it, and a mask pattern PR3 formed on the fourth active region MV and completely covering the dielectric layer 130 above it. Then, remove a part of the dielectric material layer 120 on the first active region HV1 exposed by the mask layer to form a dielectric material layer 120a including the first groove r1.

[0089] In some embodiments, the mask layer exposes the dielectric layer 130 on the third active region LV. Therefore, in the step of forming the first groove r1 in the dielectric material layer 120 on the first active region HV1, the dielectric layer 130 formed on the third active region LV is also removed accordingly.

[0090] Then, refer to Figure 6 and Figure 7 , remove the mask layer and form a dielectric layer 140 on the third active region LV. In some embodiments, the dielectric layer 140 can include a material for a gate dielectric layer such as silicon oxide. Then, form a gate material layer 150 on the dielectric layer 140, the dielectric layer 130, the dielectric material layer 120a, and the dielectric material layer 120. The gate material layer 150 can include a material for a gate electrode such as polysilicon. In some embodiments, the gate material layer 150 fills the first groove r1, such that the top surface of the gate material layer 150 includes a second groove r2 that is recessed toward the substrate 100 and above the first groove r1 in the first active region HV1.

[0091] After that, refer to Figure 7 and Figure 8, the patterned gate material layer 150 and the underlying dielectric layers 140, 130, dielectric material layer 120a, and dielectric material layer 120, so that a first gate electrode GE1 can be formed on the first active region HV1, and a first gate dielectric layer GOx_1 disposed between the substrate 100 and the first gate electrode GE1 and included in the dielectric layer 122a; a second gate electrode GE2 is formed on the second active region HV2, and a second gate dielectric layer GOx_2 disposed between the substrate 100 and the second gate electrode GE2 and included in the dielectric layer 122b; a third gate electrode GE3 is formed on the third active region LV, and a third gate dielectric layer GOx_3 disposed between the substrate 100 and the third gate electrode GE3; and a fourth gate electrode GE4 is formed on the fourth active region MV, and a fourth gate dielectric layer GOx_4 disposed between the substrate 100 and the fourth gate electrode GE4.

[0092] In some embodiments, the top surface of the first gate electrode GE1 includes a second groove r2 that is recessed toward the substrate 100 and above the first groove r1. In some embodiments, the top surface of the first gate electrode GE1 forms at the same horizontal height as the top surface of the second gate electrode GE2 in the region other than the second groove r2.

[0093] In some embodiments, the first gate dielectric layer GOx_1 includes a first portion in contact with the substrate 100 and a second portion protruding from the first portion in the vertical direction. The thickness of the first portion in the vertical direction (e.g., thickness t1) is less than the thickness of the second gate dielectric layer GOx_2 in the vertical direction (e.g., thickness t2), and the top surface of the second portion forms at the same horizontal height as the top surface of the second gate dielectric layer GOx_2. In this way, the semiconductor device can integrate power elements and / or logic elements (e.g., the first element and the second element) with different operating voltages without sacrificing the performance of the first element (the element corresponding to the first active region HV1) or the second element (the element corresponding to the second active region HV2) and having good manufacturing process stability.

[0094] In some embodiments, the height of the second portion of the first gate dielectric layer GOx_1 protruding from the first portion is approximately equal to the thickness of the dielectric layer 130 and / or the dielectric layer 140. That is, the height of the second portion of the first gate dielectric layer GOx_1 can be controlled by the thickness of the dielectric layer 130 and / or the dielectric layer 140.

[0095] In some embodiments, the dielectric layer 122a covers the region defined by the element isolation structure 110 and the first isolation structure 112 and extends onto the element isolation structure 110. The dielectric layer 122b covers the region defined by the element isolation structure 110 and the second isolation structure 114 and extends onto the element isolation structure 110.

[0096] After that, refer to Figure 9 to form a first opening OP1 and a second opening OP2 in the dielectric layer 122a and the dielectric layer 122b, respectively. The first opening OP1 exposes the region defined by the element isolation structure 110 and the first isolation structure 112. The second opening OP2 exposes the region defined by the element isolation structure 110 and the second isolation structure 114.

[0097] Then, refer to Figure 9 and Figure 10 to form a first source / drain SD1 in the region defined by the element isolation structure 110 and the first isolation structure 112 through the first opening OP1, and form a second source / drain SD2 in the region defined by the element isolation structure 110 and the second isolation structure 114 through the second opening OP2. In some examples, in the steps of forming the first source / drain SD1 and the second source / drain SD2, a third source / drain SD3 is also formed in the region defined by the third gate structure GS3 and the element isolation structure 110 of the third well region 106a, and a fourth source / drain SD4 is also formed in the region defined by the fourth gate structure GS4 and the element isolation structure 110 of the fourth well region 106b. In some embodiments, the first source / drain SD1, the second source / drain SD2, the third source / drain SD3, and the fourth source / drain SD4 may each include silicides such as tungsten silicide, titanium silicide, cobalt silicide, zirconium silicide, platinum silicide, molybdenum silicide, copper silicide, or nickel silicide, but are not limited thereto.

[0098] Afterward, refer to Figure 10 to form a first gate spacer SW1 and a second gate spacer SW2 on the sidewalls of the first gate electrode GE1 and the second gate electrode GE2, respectively, and form a third gate spacer SW3 and a fourth gate spacer SW4 on the sidewalls of the third gate electrode GE3 and the fourth gate electrode GE4, respectively. In some embodiments, the first gate spacer SW1, the second gate spacer SW2, the third gate spacer SW3, and the fourth gate spacer SW4 may each include silicon oxide, silicon nitride, or a combination thereof.

[0099] In some embodiments, a second portion of the first gate dielectric layer GOx_1 is disposed horizontally between the first gate electrode GE1 and the first gate spacer wall SW1. In some embodiments, the third gate spacer wall SW3 contacts the substrate 100. In some embodiments, the fourth gate spacer wall SW4 contacts the substrate 100. In some embodiments, the first gate spacer wall SW1 contacts the dielectric layer 122a and is vertically spaced apart from the first isolation structure 112 through the dielectric layer 122a. In some embodiments, the second portion of the first gate dielectric layer GOx_1 overlaps the first isolation structure 112 in the vertical direction. In some embodiments, the second gate spacer wall SW2 contacts the dielectric layer 122b and is vertically spaced apart from the second isolation structure 114 through the dielectric layer 122b.

[0100] Hereinafter, the semiconductor device 10 will be described by Figure 10 The semiconductor device 10 can be formed by the method described above, but the present invention is not limited thereto.

[0101] The semiconductor device 10 may include a substrate 100, a first element, and a second element. The substrate 100 includes a first active region HV1 and a second active region HV2 defined by the element isolation structure 110. The first element is disposed in the first active region HV1 and includes a first gate structure GS1. The first gate structure GS1 includes a first gate electrode GE1 and a first gate dielectric layer GOx_1 disposed between the substrate 100 and the first gate electrode GE1. The second element is disposed in the second active region HV2 and includes a second gate structure GS2. The second gate structure GS2 includes a second gate electrode GE2 and a second gate dielectric layer GOx_2 disposed between the substrate 100 and the second gate electrode GE2. The first gate dielectric layer GOx_1 includes a first portion in contact with the substrate 100 and a second portion protruding vertically from the first portion. The thickness of the first portion in the vertical direction (e.g., thickness t1) is less than the thickness of the second gate dielectric layer GOx_2 in the vertical direction (e.g., thickness t2), and the top surface of the second portion is at the same horizontal height as the top surface of the second gate dielectric layer.

[0102] In some embodiments, the top surface of the first gate electrode GE1 includes a groove (e.g., second groove r2) recessed toward the substrate 100. In some embodiments, the top surface of the first gate electrode GE1 is at the same horizontal height as the top surface of the second gate electrode GE2 in a region other than the groove (e.g., second groove r2).

[0103] In some embodiments, the horizontal area of the second element in the second active region HV2 is larger than the horizontal area of the first element in the first active region HV1.

[0104] In some embodiments, the first element includes a first isolation structure 112. The first isolation structure 112 is disposed in the first active region HV1 to define, together with the element isolation structure 110, a region where the first source / drain SD1 of the first element is disposed and to define, below the first gate structure GS1, a region where the first doped region 104a of the first element is disposed. A second portion of the first gate dielectric layer GOx_1 overlaps with the first isolation structure 112 in a vertical direction. In some embodiments, the first element includes a first gate spacer SW1 disposed on a sidewall of the first gate electrode GE1. The second portion of the first gate dielectric layer GOx_1 is disposed between the first gate electrode GE1 and the first gate spacer SW1 in a horizontal direction.

[0105] In some embodiments, the semiconductor device 10 further includes a third element, which is disposed in a third active region LV defined by the element isolation structure 110 and different from the first active region HV1 and the second active region HV2 and includes a third gate structure GS3. The third gate structure GS3 includes a third gate electrode GE3, a third gate dielectric layer GOx_3 disposed between the substrate 100 and the third gate electrode GE3, and a third gate spacer SW3 disposed on a sidewall of the third gate electrode GE3, wherein the third gate spacer SW3 is in contact with the substrate 100. In some embodiments, the horizontal area of the third element is smaller than the horizontal area of the first element and the horizontal area of the second element.

[0106] In some embodiments, the second element includes a second isolation structure 114, which is disposed in the second active region HV2 to define, together with the element isolation structure 110, a region where the second source / drain SD2 of the second element is disposed and to define, below the second gate structure GS2, a region where the second doped region 104b of the second element is disposed. The width of the second doped region 104b in a horizontal direction is greater than the width of the first doped region 104a in a horizontal direction.

[0107] Figure 11 is a cross-sectional schematic diagram of the first element according to an embodiment of the present invention. Figure 11 The first element of the semiconductor element 20 shown Figure 10 is similar to the first element of the semiconductor element 10 shown. The main difference is that the first gate structure GS1' includes a high-k layer HK1 and a metal gate MG1. Other identical or similar components / layers / patterns are denoted by the same or similar element symbols and will not be repeated here.

[0108] Please refer to Figure 11, in the first active region HV1 of the semiconductor element 20, the first gate structure GS1' of the first element includes a high-k dielectric layer HK1 and a metal gate MG1. The high-k dielectric layer HK1 is formed on the first gate dielectric layer GOx_1, and the metal gate MG1 is formed on the high-k dielectric layer HK1. In this embodiment, the metal gate MG1 includes a portion in contact with the first gate sidewall SW1.

[0109] In some embodiments, the high-k dielectric layer HK1 may include a dielectric material having a high dielectric constant. For example, the dielectric material having a high dielectric constant may be a material having a dielectric constant greater than that of silicon oxide (about 3.9). In some embodiments, the high-k dielectric layer 110 may include HfO2, TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, ZrSiO2, LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, Al2O3, Si3N4, SiON, or a combination thereof.

[0110] In some embodiments, the metal gate MG1 may include tantalum nitride (TaN), nickel silicide (NiSi), cobalt silicide (CoSi), molybdenum (Mo), copper (Cu), tungsten (W), aluminum (Al), cobalt (Co), zirconium (Zr), platinum (Pt), or other suitable materials.

[0111] Figure 12 is a cross-sectional schematic view of the first element of another embodiment of the present invention. Figure 12 The first element of the semiconductor element 30 shown Figure 11 is similar to the first element of the semiconductor element 20 shown. The main difference is that the high-k dielectric layer HK2 in the first gate structure GS1” separates the metal gate MG2 from the first gate sidewall SW1. Other identical or similar components / layers / patterns are denoted by the same or similar reference numerals and will not be repeated here.

[0112] In summary, in the above semiconductor device and the method of forming the semiconductor device, the first gate dielectric layer is designed to include a first portion in contact with the substrate and a second portion protruding from the first portion, wherein the thickness of the first portion is less than the thickness of the second gate dielectric layer of the second element, and the top surface of the second portion is at the same horizontal height as the top surface of the second gate dielectric layer. In this way, the semiconductor device can integrate power elements and / or logic elements (such as the first element and the second element) with different operating voltages without sacrificing the performance of the first element or the second element and with good manufacturing process stability.

Claims

1. A semiconductor device, comprising: A substrate, including a first active region and a second active region defined by an element isolation structure; A first element, disposed in the first active region and including a first gate structure, the first gate structure including a first gate electrode and a first gate dielectric layer disposed between the substrate and the first gate electrode; And A second element, disposed in the second active region and including a second gate structure, the second gate structure including a second gate electrode and a second gate dielectric layer disposed between the substrate and the second gate electrode, Wherein the first gate dielectric layer includes a first portion in contact with the substrate and a second portion protruding from the first portion in a vertical direction, the thickness of the first portion in the vertical direction being less than the thickness of the second gate dielectric layer in the vertical direction, and the top surface of the second portion being at the same horizontal height as the top surface of the second gate dielectric layer.

2. The semiconductor device according to claim 1, wherein a top surface of the first gate electrode includes a groove recessed toward the substrate.

3. The semiconductor device according to claim 2, wherein the top surface of the first gate electrode is at the same horizontal height as a top surface of the second gate electrode in a region other than the groove.

4. The semiconductor device according to claim 1, wherein a horizontal area of the second element is larger than a horizontal area of the first element.

5. The semiconductor device according to claim 1, wherein the first element includes a first isolation structure disposed in the first active region to define, together with the element isolation structure, a region of a first source / drain in which the first element is provided and to define, below the first gate structure, a region of a first doped region in which the first element is provided, wherein the second portion of the first gate dielectric layer overlaps with the first isolation structure in the vertical direction.

6. The semiconductor device according to claim 5, wherein the first element includes a first gate spacer disposed on a sidewall of the first gate electrode, and the second portion of the first gate dielectric layer is disposed between the first gate electrode and the first gate spacer in a horizontal direction.

7. The semiconductor device according to claim 6, wherein the second element includes a second gate spacer disposed on a sidewall of the second gate electrode.

8. The semiconductor device according to claim 7, further comprising: A third element, disposed in a third active region different from the first active region and the second active region defined by the element isolation structure and including a third gate structure, wherein the third gate structure includes a third gate electrode, a third gate dielectric layer disposed between the substrate and the third gate electrode, and a third gate spacer disposed on a sidewall of the third gate electrode, Wherein the third gate spacer is in contact with the substrate.

9. The semiconductor device according to claim 8, wherein a horizontal area of the third element is smaller than a horizontal area of the first element and a horizontal area of the second element.

10. The semiconductor device according to claim 5, wherein the second element includes a second isolation structure disposed in the second active region to define, together with the element isolation structure, a region of a second source / drain in which the second element is provided and to define, below the second gate structure, a region of a second doped region in which the second element is provided, Wherein, a width of the second doping region in a horizontal direction is greater than a width of the first doping region in the horizontal direction.

11. A method for forming a semiconductor device, comprising: Forming an element isolation structure in the substrate to define the first active region and the second active region; Forming a dielectric material layer on the first active region and the second active region of the substrate; Patterning the dielectric material layer on the first active region to form a first groove in the dielectric material layer on the first active region; Forming a gate material layer on the dielectric material layer; And Patterning the gate material layer and the dielectric material layer to form a first gate electrode on the first active region and a first gate dielectric layer disposed between the substrate and the first gate electrode, and to form a second gate electrode on the second active region and a second gate dielectric layer disposed between the substrate and the second gate electrode, Wherein the first gate dielectric layer includes a first portion in contact with the substrate and a second portion protruding from the first portion in a vertical direction, the thickness of the first portion in the vertical direction being less than the thickness of the second gate dielectric layer in the vertical direction, and the top surface of the second portion being formed at the same horizontal height as the top surface of the second gate dielectric layer.

12. The method according to claim 11, further comprising: Forming a first gate spacer and a second gate spacer on sidewalls of the first gate electrode and the second gate electrode, respectively, and Wherein the second portion of the first gate dielectric layer is disposed horizontally between the first gate electrode and the first gate spacer.

13. The method according to claim 11, wherein a top surface of the first gate electrode includes a second groove that is recessed toward the substrate and above the first groove.

14. The method according to claim 13, wherein the top surface of the first gate electrode forms at the same horizontal height as the top surface of the second gate electrode in a region other than the second groove.

15. The method according to claim 12, further comprising: Forming a first isolation structure in the first active region to define a region where a first source / drain is formed with the element isolation structure and to define a region where a first doped region is formed under the first gate electrode, The second portion of the first gate dielectric layer overlaps with the first isolation structure in the vertical direction.

16. The method according to claim 15, further comprising: A second isolation structure is formed in the second active region to define a region where a second source / drain is formed with the device isolation structure and to define a region where a second doped region is formed under the second gate electrode. The width of the second doped region in the horizontal direction is greater than the width of the first doped region in the horizontal direction.

17. The semiconductor device according to claim 12, wherein the element isolation structure defines a third active region in the substrate, and in the step of forming the first groove in the dielectric material layer on the first active region, a dielectric layer formed on the third active region is also removed.

18. The method according to claim 17, wherein in the step of patterning the gate material layer and the dielectric material layer, a third gate electrode and a third gate dielectric layer disposed between the substrate and the third gate electrode are formed in the third active region, in the step of forming the first gate spacer and the second gate spacer, a third gate spacer is formed on a sidewall of the third gate electrode, and the third gate spacer contacts the substrate.

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