Array substrate

Abstract

The invention discloses an array substrate which comprises a substrate body, a first pixel electrode, a second pixel electrode, a first scanning line, a second scanning line, a first wire, a second wire and a data line. The first pixel electrode and the second pixel electrode are arranged on the substrate and are arranged along a first direction. The first scanning line and the second scanning line are arranged on the substrate in the first direction, and the first pixel electrode and the second pixel electrode are arranged between the first scanning line and the second scanning line. The first wire and the second wire are arranged on the substrate along a second direction different from the first direction, the first wire is electrically connected with the first scanning line, the second wire is electrically connected with the second scanning line, the first wire crosses the second scanning line and is electrically insulated from the second scanning line, and the data line is arranged between the first wire and the second wire.

Description

Technical Field

[0001] The present invention relates to an array substrate, and more particularly to an array substrate applied to an electronic device with a narrow border. Background Art

[0002] In order to meet the requirements of aesthetics in appearance and space utilization, reducing the border width of a display device has become an inevitable development trend. Although there has been a development of using a trace that is formed by the same conductive layer as the data line to transfer the scan line and disposing it in the display area, this design not only increases the number of signal lines in the display area, resulting in an increase in the coupling capacitance between adjacent data lines, thereby affecting the display quality. Therefore, how to balance the requirements of a narrow border and maintain the display quality has been the goal that those skilled in the art have been constantly striving for. Summary of the Invention

[0003] According to an embodiment of the present invention, an array substrate is disclosed, which includes a substrate, a first pixel electrode, a second pixel electrode, a first scan line, a second scan line, a first trace, a second trace, and a data line. The first pixel electrode and the second pixel electrode are disposed on the substrate and arranged along a first direction. The first scan line and the second scan line are disposed on the substrate along the first direction, wherein the first pixel electrode and the second pixel electrode are disposed between the first scan line and the second scan line. The first trace and the second trace are disposed on the substrate along a second direction different from the first direction, wherein the first trace is electrically connected to the first scan line, the second trace is electrically connected to the second scan line, the first trace crosses the second scan line and is electrically insulated from the second scan line, and the first trace and the second trace are formed by a first conductive layer. The data line is disposed on the substrate along the second direction, wherein in a top view of the array substrate, the data line is disposed between the first pixel electrode and the second pixel electrode, the data line crosses the second scan line, the data line is formed by a second conductive layer different from the first conductive layer, and the data line is disposed between the first trace and the second trace.

[0004] According to another embodiment of the present invention, an array substrate is disclosed, which includes a substrate, a first scan line, a second scan line, a first trace, a second trace, and a data line. The first scan line and the second scan line are disposed on the substrate along a first direction, wherein each of the first scan line and the second scan line includes a plurality of line segments and a plurality of first bridging line segments. The first trace and the second trace are disposed on the substrate along a second direction different from the first direction, wherein the first trace is electrically connected to the first scan line, and the second trace is electrically connected to the second scan line. The data line is disposed on the substrate along the second direction, wherein the data line straddles one of the first bridging line segments of the first scan line and one of the first bridging line segments of the second scan line. The number of the first bridging line segments of the first scan line is the same as that of the first bridging line segments of the second scan line. In a top view of the array substrate, one of the first bridging line segments of the second scan line overlaps with the data line and the first trace. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 FIG. shows a top view schematic diagram of an array substrate according to a first embodiment of the present invention.

[0006] Figure 2 Shown is Figure 1 a cross-sectional schematic diagram along the cutting line A-A'.

[0007] Figure 3 FIG. shows a top view schematic diagram of an array substrate according to a second embodiment of the present invention.

[0008] Figure 4 Shown is Figure 3 a cross-sectional schematic diagram along the cutting line B-B'.

[0009] Figure 5 FIG. shows a top view schematic diagram of an array substrate according to a variant embodiment of the second embodiment of the present invention.

[0010] Figure 6 FIG. shows a top view schematic diagram of an array substrate according to another variant embodiment of the second embodiment of the present invention.

[0011] Figure 7 FIG. shows a top view schematic diagram of an array substrate according to a third embodiment of the present invention.

[0012] Figure 8 Shown is Figure 7 a cross-sectional schematic diagram along the cutting line C-C'.

[0013] Figure 9 FIG. shows a top view schematic diagram of an array substrate according to a variant embodiment of the third embodiment of the present invention.

[0014] Figure 10The figure shows a top view schematic diagram of an array substrate according to another variant embodiment of the third embodiment of the present invention.

[0015] Among them, the reference numerals are explained as follows:

[0016] 1, 2a, 2b, 2c, 3a, 3b, 3c array substrate

[0017] 12 substrate

[0018] 14, 14a, 14b, 14c, 14d, 14e pixel electrode

[0019] 16, 16a, 16b, 16c, 16d, 16e scanning line

[0020] 161 line segment

[0021] 162, 163 bridge line segment

[0022] 16P scanning line pair

[0023] 18, 18a, 18b trace

[0024] 20, 20a, 20b data line

[0025] 22, 22a, 22b, 22c, 22d switching element

[0026] 24 common line

[0027] AA active region

[0028] C1, C2, C3 conductive layer

[0029] D1 first direction

[0030] D2 second direction

[0031] IN1, IN2 insulating layer

[0032] PR peripheral region

[0033] S1 first side

[0034] S2 second side

[0035] S3 third side

[0036] TD top view direction

[0037] TH via Detailed implementation manner

[0038] The following describes the content of the present invention in detail in conjunction with specific embodiments and drawings. And in order to make the content of the present invention clearer and easier to understand, the elements in the following drawings may not be drawn to scale. Moreover, the number and size of each element in the drawings are only for illustration and are not used to limit the scope of the present invention.

[0039] In the present invention, the array substrate can be applied to an electronic device that needs to configure a pixel array. For example, the electronic device can be a display device, an image sensing device, an X-ray sensing device, or other suitable devices. The display device can be, for example, a non-self-luminous display device or a self-luminous display device. The non-self-luminous display device can include, for example, a liquid crystal display device or other suitable devices, and the self-luminous display device can include, for example, an organic light-emitting diode display device, an inorganic light-emitting diode display device, or other suitable devices. Depending on the type of the display device, in addition to the array substrate, the display device can also include other substrates and / or components. For example, when the display device is a liquid crystal display device, the display device can include an array substrate, a color filter substrate, and a liquid crystal layer, and the liquid crystal layer can be disposed between the color filter substrate and the array substrate, but not limited thereto. When the display device is a self-luminous display device, the display device can include an array substrate and a light-emitting diode and a packaging layer disposed on the array substrate, but not limited thereto. The array substrate in the following text takes the application to a display device as an example, but is not limited thereto.

[0040] Please refer to Figure 1 and Figure 2 , where Figure 1 FIG. shows a top view schematic diagram of the array substrate according to the first embodiment of the present invention, Figure 2 FIG. shows a Figure 1 cross-sectional schematic diagram along the section line A-A'. For the sake of clear illustration, Figure 1 and Figure 2 only show some elements of the array substrate, but the array substrate of the present invention is not limited thereto. As Figure 1 shown, when the array substrate 1 is applied to a display device, the array substrate 1 can have an active area AA for controlling image display and a peripheral area PR for setting peripheral circuits, where the peripheral area PR can be located on at least one side of the active area AA. In the Figure 1 embodiment, the peripheral area PR can surround the active area AA, but not limited thereto. The active area AA of the array substrate 1 can correspond to the display area of the display device, but not limited thereto.

[0041] In Figure 1In the embodiment, the array substrate 1 may be a dual-gate type array substrate, but is not limited thereto. Specifically, the array substrate 1 may include a substrate 12, a plurality of pixel electrodes 14, a plurality of scan lines 16, a plurality of routing lines 18, a plurality of data lines 20, and a plurality of switching elements 22, where the pixel electrodes 14, the scan lines 16, the routing lines 18, the data lines 20, and the switching elements 22 are disposed on the substrate 12 in the active area AA. The substrate 12 may be, for example, a flexible substrate or a non-flexible substrate. The substrate 12 may include, for example, glass, quartz, sapphire, acrylic, polyimide (PI), other suitable materials, or a combination of the above, but is not limited thereto.

[0042] As Figure 1 shown, each pixel electrode 14 may be electrically connected to a corresponding switching element 22 respectively. When the array substrate 1 is used in a display device, the pixel voltage provided to the pixel electrode 14 may be switched by the on / off of the switching element 22, and then the brightness of the pixels or sub-pixels of the display device may be adjusted, but is not limited thereto. In Figure 1 the embodiment, the pixel electrodes 14 may be arranged in an array in the active area AA, and the row direction of the pixel electrodes 14 may be the first direction D1, and the column direction may be the second direction D2, but is not limited thereto. The second direction D2 may be different from the first direction D1, for example, perpendicular to the first direction D1. For example, the pixel electrodes 14 may include a pixel electrode 14a, a pixel electrode 14b, a pixel electrode 14c, and a pixel electrode 14d, where the pixel electrode 14a and the pixel electrode 14b may be arranged along the first direction D1, the pixel electrode 14c and the pixel electrode 14d may be arranged along the first direction D1, the pixel electrode 14a and the pixel electrode 14c are arranged along the second direction D2, and the pixel electrode 14b and the pixel electrode 14d are arranged along the second direction D2. The arrangement of the pixel electrodes 14 of the present invention is not limited thereto.

[0043] The scan lines 16 can extend along the first direction D1 respectively and be arranged along the second direction D2. In this embodiment, the scan lines 16 can form a plurality of scan line pairs 16P, which are arranged along the second direction D2, and each scan line pair 16P can be constituted by two adjacent scan lines 16. Moreover, the pixel electrodes 14 of one row can be disposed between the scan lines 16 of the same scan line pair 16P, such that the pixel voltages on the pixel electrodes 14 of the same row can be switched through the scan lines 16 of the same scan line pair 16P. In this embodiment, the pixel voltages on the pixel electrodes 14 of the same row can be sequentially and alternately switched through different scan lines 16 of the same scan line pair 16P, but it is not limited thereto. For example, the scan lines 16 can include scan line 16a, scan line 16b, scan line 16c and scan line 16d, where scan line 16a and scan line 16b form the same scan line pair 16P, and scan line 16c and scan line 16d form another scan line pair 16P. The pixel electrodes 14a and pixel electrodes 14b can be disposed between scan line 16a and scan line 16b, and the pixel electrodes 14a and pixel electrodes 14b can be switched through scan line 16a and scan line 16b respectively. The pixel electrodes 14c and pixel electrodes 14d can be disposed between scan line 16c and scan line 16d, and the pixel electrodes 14c and pixel electrodes 14d can be switched through scan line 16c and scan line 16d respectively. In other words, among the pixel electrodes 14 of the same row, starting from the left side of the active region AA, the odd-numbered pixel electrodes 14 can be controlled by scan line 16a, and the even-numbered pixel electrodes 14 can be controlled by scan line 16b, but it is not limited thereto.

[0044] The traces 18 can be electrically connected to the corresponding scan lines 16 respectively and can extend from the corresponding scan lines 16 along the second direction D2 into the peripheral region PR on one side (such as the first side S1) of the active region AA, so as to electrically connect the scan lines 16 to the components (such as the gate driving circuit) located in the peripheral region PR. In this case, the trace 18 can cross the scan lines 16 between the corresponding scan line 16 and the first side S1 of the active region AA and be electrically insulated from them. For example, the traces 18 can include trace 18a and trace 18b, which are respectively connected to scan line 16a and scan line 16b, and trace 18a can cross scan line 16b and be electrically insulated from it. It should be noted that since the traces 18 respectively electrically connecting the scan lines 16 can extend into the peripheral region PR along the second direction D2, the two ends of the scan lines 16 do not need to be provided with traces, thereby reducing the number of traces on the left and right sides of the scan lines 16, so as to reduce the width of the peripheral regions PR on the second side S2 and the third side S3 of the active region AA, such that the display device can have a narrow border. In some embodiments, the trace 18 can cross the pixel electrodes 14 of the same column between the corresponding scan line 16 and the first side S1 of the active region AA, but it is not limited thereto.

[0045] InFigure 1 In embodiments, as the distance between the scanning line 16 and the first side S1 of the peripheral region PR varies, the lengths of the routing lines 18 in the second direction D2 may be different from each other. In one embodiment, the routing lines 18 may be arranged along the first direction D1 in the order of their lengths, for example, the longer the routing line 18, the closer it is to the second side S2 or the third side S3 of the peripheral region PR, but not limited thereto. In some embodiments, the order in which the routing lines 18 are arranged along the first direction D1 may not be in the order of their lengths.

[0046] In Figure 1 embodiments, at least one scanning line 16 may include at least two line segments 161 and at least one bridging line segment 162, and the bridging line segment 162 may be electrically connected between the line segments 161 such that the line segments 161 and the bridging line segment 162 can be connected to form the scanning line 16. For example, the scanning line 16 (e.g., Figure 1 the scanning line 16a) located on the first side S1 farthest from the active region AA may have at least one bridging line segment 162 between the scanning line 16 and the first side S1. In one embodiment, the scanning lines 16 located between the pixel electrodes 14 in two adjacent rows may include the same number of line segments 161 and the same number of bridging line segments 162, but not limited thereto. For example, the scanning line 16b and the scanning line 16c may each include two line segments 161 and one bridging line segment 162, and the scanning line 16d and the scanning line 16e may each include three line segments 161 and two bridging line segments 162, and so on.

[0047] As Figure 2 shown, since the routing line 18 and the bridging line segment 162 may be formed by different conductive layers, the routing line 18 may overlap with the bridging line segment 162 in the top view of the array substrate 1, so that the routing line 18 can cross the scanning line 16 in an electrically insulated state. For example, the line segment 161 and the routing line 18 may be formed by the conductive layer C1, and the bridging line segment 162 may be formed by a conductive layer C3 different from the conductive layer C1 and the conductive layer C2, such that the bridging line segment 162 of the scanning line 16b can cross and overlap the routing line 18a. In this case, Figure 1 the bridging line segment 162 of the scanning line 16c can cross the routing line 18a and the routing line 18b, and so on. In one embodiment, the line segment 161 and the bridging line segment 162 may be strip-shaped, but not limited thereto. In this document, the top view of the array substrate may be viewed, for example, along the top view direction TD perpendicular to the upper surface 12S of the substrate 1, such as Figure 2 shown.

[0048] In some embodiments, each scanning line 16 may include the same number of line segments 161 and the same number of bridging line segments 162. For example, the number of bridging line segments 162 of each scanning line 16 may be the same as the number of data lines 20 (e.g., Figure 3The scanning lines 16) shown. Through the design of the same number of jumper line segments 162, the resistance values of each scanning line 16 can be similar to each other, thereby reducing anomalies in the display device and improving the display quality. In this case, in some embodiments, the traces 18 in the active region AA can have the same length as each other, such that each trace 18 can cross the scanning lines 16 that are not electrically connected to it, which can help to equalize the coupling capacitance of each scanning line 16, but is not limited thereto.

[0049] As Figure 1 shown, the data lines 20 can extend along the second direction D2 and cross the scanning lines 16, and the data lines 20 and the scanning lines 16 are electrically insulated from each other. In Figure 1 and Figure 2 embodiments, the data lines 20 can be formed of a conductive layer C2 different from the conductive layer C1 and the conductive layer C3. Therefore, the jumper line segments 162 or the line segments 161 of the scanning lines 16 can cross the data lines 20 while being electrically insulated from the data lines 20, but is not limited thereto. For example, the data lines 20 can include data lines 20a and data lines 20b, arranged along the first direction D1, and the jumper line segment 162 of the scanning line 16b can cross the data line 20a. Also, one of the jumper line segments 162 of the scanning line 16c can cross the data line 20a, and the other jumper line segment 162 can cross the data line 20b. In some embodiments, when each scanning line 16 includes the same number of line segments 161 and the same number of jumper line segments 162, each data line 20 can cross one jumper line segment 162 of each scanning line 16b, but is not limited thereto.

[0050] In one embodiment, in a top view of the array substrate 1, one data line 20 can be disposed between two adjacent columns of pixel electrodes 14 and electrically connected to the pixel electrodes 14 of two adjacent columns, such that one data line 20 can be used to transmit the pixel voltages of the pixel electrodes 14 of two adjacent columns, thereby reducing the number of data lines 20. Also, two columns of pixel electrodes 14 can be disposed between two adjacent data lines 20. For example, the data line 20a can be disposed between the pixel electrode 14a and the pixel electrode 14b and between the pixel electrode 14c and the pixel electrode 14d, and electrically connected to the pixel electrodes 14a, 14b, and the pixel electrodes 14b and 14e arranged in the first direction D1 are disposed between two adjacent data lines 20a, 20b. Further, in a top view of the array substrate 1, one data line 20 can be disposed between the traces 18 connecting the same pair of scanning lines 16P. For example, the data line 20a can be disposed between the trace 18a and the trace 18b, but is not limited thereto.

[0051] As Figure 1As shown, the gate, source, and drain of each switching element 22 are electrically connected to the corresponding scanning line 16, data line 20, and pixel electrode 14, respectively. For example, the switching element 22 may include switching element 22a, switching element 22b, switching element 22c, and switching element 22d. The gate, source, and drain of switching element 22a may be electrically connected to scanning line 16a, data line 20a, and pixel electrode 14a, respectively; the gate, source, and drain of switching element 22b may be electrically connected to scanning line 16b, data line 20a, and pixel electrode 14b, respectively; the gate, source, and drain of switching element 22c may be electrically connected to scanning line 16c, data line 20a, and pixel electrode 14c, respectively; and the gate, source, and drain of switching element 22d may be electrically connected to scanning line 16d, data line 20a, and pixel electrode 14d, respectively.

[0052] As Figure 1 and Figure 2 shown, in a top view of the array substrate 1, when a trace 18 is provided between one of the switching elements 22 and the corresponding data line 20, the source of the switching element 22 may overlap the trace 18. For example, the source of switching element 22a may straddle and overlap trace 18a. The source of switching element 22c may straddle and overlap trace 18a. The source of switching element 22d may straddle and overlap trace 18b.

[0053] In Figure 1 and Figure 2 the embodiment of, the gate of the switching element 22 and the segment 161 of the scanning line 16 may be formed of the same conductive layer C1, and the source and drain of the switching element 22 may be formed of the same conductive layer C2 as the data line 20, but not limited thereto. Although not shown in the figure, the switching element 22 may further include a semiconductor layer and a gate insulating layer, where the gate insulating layer is disposed between the gate and the semiconductor layer, and both sides of the semiconductor layer are in contact with the source and the drain, respectively. The switching element 22 may be, for example, a bottom-gate thin-film transistor, but not limited thereto. In some embodiments, the switching element 22 may be other types of thin-film transistors according to design requirements.

[0054] As Figure 2As shown, a conductive layer C1, a conductive layer C2, and a conductive layer C3 may be sequentially disposed on a substrate 12. An insulating layer IN1 may be disposed between the conductive layer C1 and the conductive layer C2, and an insulating layer IN2 may be disposed between the conductive layer C2 and the conductive layer C3. The insulating layer IN1 and the insulating layer IN2 may have vias TH such that the bridge wiring segment 162 can be electrically connected to the corresponding segment 161 through the vias TH. Since the trace 18 is formed by the conductive layer C1 and the data line 20 is formed by the conductive layer C2, an insulating layer IN1 may exist between the trace 18 and the data line 20, thereby reducing the coupling capacitance between the trace 18 and the data line 20 and reducing anomalies in the display device. In one embodiment, the resistivity of the conductive layer C1 and the conductive layer C2 is less than the resistivity of the conductive layer C3. For example, the conductive layer C1 and the conductive layer C2 may include a metal, and the conductive layer C3 may include a transparent conductive material, but is not limited thereto. The transparent conductive material may include, for example, indium tin oxide or other suitable materials. In some embodiments, the pixel electrode 14 may be formed by the conductive layer C3, but is not limited thereto.

[0055] In some embodiments, the array substrate 1 may further include a common line (such as Figure 3 the common line 24 shown), disposed on the substrate 12 in the active region AA and used to transmit a common voltage. The common line may extend, for example, along the second direction D2 and be formed by the conductive layer C1, but is not limited thereto. The common line may overlap with the pixel electrodes 14 in the same column in a top view of the array substrate 1, but is not limited thereto.

[0056] As can be seen from the above, in the dual-gate type array substrate 1 of the present embodiment, since the number of traces 18 in the peripheral region PR on the second side S2 and the third side S3 of the active region AA can be significantly reduced, and the coupling capacitance between the trace 18 and the data line 20 can be reduced, the array substrate 1 can meet the requirements of a narrow border and improved display quality while reducing the data line 20.

[0057] The array substrate is not limited to the above embodiments and may have different embodiments. For simplicity of description, the same components in different embodiments below will be labeled with the same reference numerals as in the first embodiment. To easily compare the differences between the first embodiment and different embodiments, the differences in different embodiments will be highlighted below, and the repeated parts will not be described again.

[0058] Figure 3 The top view schematic diagram of the array substrate according to the second embodiment of the present invention is shown. Figure 4 Shown is Figure 3 the cross-sectional schematic diagram along the section line B-B'. As Figure 3 and Figure 4 shown, the array substrate 2a of the present embodiment and Figure 1The difference between the array substrate 1 lies in the way the pixel electrode 14 is coupled to the scan line 16 and the data line 20 through the switching element 22. Specifically, the array substrate 2a may include a substrate 12, a plurality of pixel electrodes 14, a plurality of scan lines 16, a plurality of routing lines 18, a plurality of data lines 20, and a plurality of switching elements 22, and the pixel electrodes 14, scan lines 16, routing lines 18, data lines 20, and switching elements 22 are disposed on the substrate 12 in the active area AA. Each pixel electrode 14 may be electrically connected to the drain of a corresponding one of the switching elements 22, but is not limited thereto. The arrangement of the pixel electrodes 14 in this embodiment may be similar to or the same as Figure 1 the pixel electrode 14 shown, and thus will not be elaborated herein.

[0059] In Figure 3 the embodiment, the scan lines 16 may be arranged along the second direction D2, and the pixel electrodes 14 in each row may be alternately arranged with each scan line 16 along the second direction D2. The data lines 20 may be arranged along the first direction D1, and the pixel electrodes 14 in each column may be alternately arranged with each data line 20 along the first direction D1. In this case, a pixel electrode 14 may be disposed in an area surrounded by two adjacent scan lines 16 and two adjacent data lines 20. Also, each scan line 16 may be electrically connected to the gates of the switching elements 22 corresponding to the pixel electrodes 14 in the same row, and each data line 20 may be electrically connected to the sources of the switching elements 22 corresponding to the pixel electrodes 14 in the same column, such that the pixel electrode 14 can be electrically connected to the corresponding data line 20 through the switching element 22. For example, the pixel electrodes 14a and 14b may be arranged along the second direction D2, the pixel electrode 14a may be electrically connected to the data line 20a through the switching element 22a, and the pixel electrode 14a may be electrically connected to the data line 20a through the switching element 22b, but is not limited thereto.

[0060] As Figure 3 shown, in the top view of the array substrate 2a, the scan lines 16 may extend along the first direction D1, and the routing lines 18 may extend along the second direction D2, wherein each routing line 18 may be electrically connected to a corresponding scan line 16, and at least one routing line 18 may cross and be electrically insulated from at least one other non-corresponding scan line 16 (that is, the scan line 16 not electrically connected thereto). For example, the routing line 18a may cross the scan line 16b and be electrically insulated from the scan line 16b. In Figure 3 the embodiment, each scan line 16 may include a plurality of line segments 161 and a plurality of bridging line segments 162, and the number of bridging line segments 162 of the scan line 16 may be the same as each other to help equalize the resistance value of each scan line 16. For example, the number of bridging line segments 162 of the scan lines 16a and 16b may be the same as each other. In one embodiment, the lengths of the bridging line segments 162 of the scan line 16 in the first direction D1 may also be the same as each other, but is not limited thereto.

[0061] In this embodiment, the trace 18 and the data line 20 may be alternately arranged along the first direction D1, but are not limited thereto. For example, one trace 18 and one data line 20 may be provided between two adjacent columns of pixel electrodes 14, but are not limited thereto. In Figure 3 it, the data lines 20 may be respectively provided on the right side of the pixel electrodes 14 corresponding to one column, but are not limited thereto. In some embodiments, at least one trace 18 may be provided between two adjacent data lines 20, but are not limited thereto.

[0062] In Figure 3 the embodiment of, in the top view of the array substrate 2a, the lengths of the traces 18 in the second direction D2 may be different from each other, so that at least one scanning line 16 may not overlap with at least one unconnected trace 18, but are not limited thereto. In this case, the bridging segments 162 of at least a part of the scanning lines 16 may overlap with the unconnected traces 18 and the data lines 20. For example, the scanning line 16a may not overlap with the trace 18b, and the bridging segment 162 of the scanning line 16b may overlap with the unconnected trace 18a and the data line 20a. In some embodiments, the bridging segments 162 of the scanning lines 16 may not overlap with the traces 18, and in this case, the scanning lines 16 also need to include bridging segments 163, such as Figure 7 shown.

[0063] In Figure 3 the embodiment of, similar to the above embodiment, the traces 18 may be arranged along the first direction D1 in the order of the length size, for example, the longer the trace 18, the closer it is to the second side S2 of the peripheral region PR, but are not limited thereto. In some embodiments, the order of the traces 18 arranged along the first direction D1 may not be in the order of the length size.

[0064] As Figure 3 and Figure 4 shown, the segment 161 may be formed by the conductive layer C1, the data line 20 may be formed by the conductive layer C2, and the bridging segment 162 may be formed by the conductive layer C3. Therefore, the bridging segment 162 may electrically connect the adjacent segments 161 while being electrically insulated from the traces 18 and the data lines 20. As Figure 4 shown, an insulating layer IN1 may be provided between the conductive layer C1 and the conductive layer C2, and an insulating layer IN2 may be provided between the conductive layer C2 and the conductive layer C3. In this embodiment, the insulating layer IN1 may, for example, serve as a gate insulating layer, but is not limited thereto. The stacking order of the conductive layers C1 - C3 and the insulating layers IN1 and IN2 may be similar to or the same as Figure 2In the embodiments, the coupling capacitance between the trace 18 and the data line 20 in this embodiment can also be reduced, thereby reducing the anomalies of the display device, which will not be elaborated here. And since the materials of the conductive layer C1, conductive layer C2, and conductive layer C3 in this embodiment can be similar to or the same as those of the conductive layer C1, conductive layer C2, and conductive layer C3 in the first embodiment, they will not be elaborated here.

[0065] It should be noted that since the bridging segment 162 is formed by the conductive layer C3 and the resistivity of the conductive layer C3 is greater than that of the conductive layer C1 forming the segment 161, having the same number of bridging segments 162 in the scan line 16 can help to equalize the resistance values of each scan line 16, thereby reducing the signal differences at different positions to improve the quality of the display screen. In addition, since the trace 18 and the bridging segment 162 can be formed by different first conductive layer C1 and third conductive layer C3 respectively, the interference between the signals of different scan lines 16 can be reduced.

[0066] As Figure 3 and Figure 4 shown, the array substrate 2a may further include a common line 24, which is disposed on the substrate 12 in the active region AA and is used to transmit a common voltage. The common line 24 may extend along the second direction D2, for example, and is formed by the conductive layer C2, but is not limited thereto. The common line 24 may overlap with the pixel electrodes 14 in the same column in the top view of the array substrate 2a to form a storage capacitor with the pixel electrodes 14, but is not limited thereto. In some embodiments, the common line 24 may also be formed by other conductive layers different from the conductive layers C1 - C3. Figure 3 and Figure 4 The other parts of the array substrate 2a shown may be similar to or the same as the array substrates in the above or below other embodiments, so they will not be elaborated here.

[0067] Figure 5 Shown is a top view schematic diagram of an array substrate according to a variant embodiment of the second embodiment of the present invention. As Figure 5 shown, the difference between the array substrate 2b of this variant embodiment and Figure 3 the array substrate 2a is that the lengths of the traces 18 in the active region AA in this embodiment can be the same as each other. For example, the lengths of the trace 18a and the trace 18b in the second direction D2 can be the same as each other. In this case, each trace 18a disposed in the active region AA can overlap with the bridging segments 162 of other scan lines 16 that are not electrically connected in the top view of the array substrate 2b. Therefore, the coupling capacitances between each scan line 16 and other scan lines 16 can be the same as each other, thereby equalizing the coupling capacitances of the scan lines 16 to reduce the anomalies of the display device and improve the display quality. Figure 5Other parts of the array substrate 2b shown may be similar to or the same as the array substrates of the above or below other embodiments, and thus will not be elaborated herein.

[0068] Figure 6 The following is a top view schematic diagram of an array substrate according to another variant embodiment of the second embodiment of the present invention. As Figure 6 shown, the difference between the array substrate 2c of this variant embodiment and Figure 3 the array substrate 2a is that the data lines 20 can be respectively arranged on the left side of the pixel electrodes 14 corresponding to a column (that is, a column of pixel electrodes 14 electrically connected thereto). In some embodiments, the traces 18 can be arranged along the opposite direction of the first direction D1 in the order of the length size. For example, the longer the trace 18, the closer it is to the third side S3 of the peripheral region PR, but it is not limited thereto. Figure 6 Other parts of the array substrate 2c shown may be similar to or the same as the array substrates of the above or below other embodiments, and thus will not be elaborated herein.

[0069] Figure 7 The following is a top view schematic diagram of an array substrate according to the third embodiment of the present invention, Figure 8 shown as Figure 7 a cross-sectional schematic diagram along the section line C-C'. As Figure 7 shown, the difference between the array substrate 3a of this embodiment and Figure 3 the array substrate 2a is that at least one trace 18 in the top view of the array substrate 3a can overlap with at least one pixel electrode 14. For example, the trace 18a is connected to the scan line 16a, and the pixel electrode 14b is located between the scan line 16a and the first side S1 of the active region AA. Therefore, the trace 18a can cross the pixel electrode 14a, and so on. In this case, at least one scan line 16 may further include at least one bridging segment 163 in addition to the segment 161 and the bridging segment 162. And in the top view of the array substrate 3a, the bridging segment 163 can overlap with a trace 18 and be electrically insulated. For example, the scan line 16b may further include a bridging segment 163 that overlaps with the trace 18a electrically connected to the scan line 16a. The scan line 16c may include two bridging segments 163, which overlap with the trace 18a and the trace 18b respectively, and so on.

[0070] In Figure 7 the embodiment of, in the top view of the array substrate 3a, a common line 24 can be arranged between a trace 18 and a data line 20 to reduce the influence of the signal of the trace 18 on the data signal transmitted by the data line 20, but it is not limited thereto. In some embodiments, the position of the bridging segment 163 can be adjusted with the position of the trace 18, rather than being limited to Figure 7 shown.

[0071] AsFigure 8 As shown, the bridge wiring segments 162 and 163 can be formed by the same conductive layer, for example, formed by the conductive layer C3, but not limited thereto. In some embodiments, Figure 7 and Figure 8 other parts of the array substrate 3a shown can be similar or the same as the array substrates of the above or below other embodiments, so details are not described herein again.

[0072] Figure 9 The following is a top view schematic diagram of an array substrate according to a variant embodiment of the third embodiment of the present invention. As Figure 9 shown, the difference between the array substrate 3b of this variant embodiment and Figure 7 the array substrate 3a is that the bridge wiring segment 163 and the bridge wiring segment 162 of this embodiment can be formed by different conductive layers. For example, the bridge wiring segment 163 and the data line 20 can be formed by the same conductive layer C2. Since the conductive layer C2 can include metal, the influence of the bridge wiring segment 163 on the resistance value of the scanning line 16 can be reduced, thereby improving the resistance uniformity of the scanning line 16. In some embodiments, Figure 9 other parts of the array substrate 3b can be similar or the same as the array substrates of the above or below other embodiments, so details are not described herein again.

[0073] Figure 10 The following is a top view schematic diagram of an array substrate according to another variant embodiment of the third embodiment of the present invention. As Figure 10 shown, the difference between the array substrate 3c of this variant embodiment and Figure 7 the array substrate 3a is that each scanning line 16 can further include a plurality of bridge wiring segments 163, and the number of bridge wiring segments 163 of the scanning line 16 can be the same as each other to help uniformize the resistance value of each scanning line 16. In one embodiment, the lengths of the bridge wiring segments 163 of the scanning line 16 in the first direction D1 can be the same as each other, but not limited thereto. In this case, the lengths of the traces 18 in the active area AA can be selectively the same as each other, so that one trace 18 can overlap with the bridge wiring segments 163 of each unconnected scanning line 16 in the top view of the array substrate 3c to help uniformize the coupling capacitance of the scanning line 16. For example, one of the bridge wiring segments 163 of the scanning line 16a can overlap with the trace 18b that electrically connects the scanning line 16b. In some embodiments, Figure 10 other parts of the array substrate 3c can be similar or the same as the array substrates of the above or below other embodiments, so details are not described herein again.

[0074] In summary, in the array substrate of the present invention, the scanning lines are electrically connected by the traces and extend from the first side of the active region to the peripheral region. Therefore, the number of traces in the peripheral regions located on the second side and the third side of the active region can be significantly reduced, enabling the display device to have a narrow border. Moreover, the traces and the data lines can be formed by different conductive layers, thereby reducing the coupling capacitance between the traces and the data lines and reducing abnormalities in the display device. In addition, by designing the scanning lines to have the same number of bridging segments, it is helpful to equalize the resistance values of each scanning line, thereby improving the quality of the display screen.

[0075] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. An array substrate, characterized in that, Comprising: A substrate; A first pixel electrode and a second pixel electrode, disposed on the substrate and arranged along a first direction; A first scan line and a second scan line, disposed on the substrate along the first direction, wherein the first pixel electrode and the second pixel electrode are disposed between the first scan line and the second scan line; A first trace and a second trace, disposed on the substrate along a second direction different from the first direction, wherein the first trace is electrically connected to the first scan line, the second trace is electrically connected to the second scan line, the first trace crosses the second scan line and is electrically insulated from the second scan line, and the first trace and the second trace are formed by a first conductive layer; and A data line, disposed on the substrate along the second direction, wherein in a top view of the array substrate, the data line is disposed between the first pixel electrode and the second pixel electrode, the data line crosses the second scan line, the data line is formed by a second conductive layer different from the first conductive layer, and the data line is disposed between the first trace and the second trace.

2. The array substrate according to claim 1, characterized in that, The second scan line includes at least two line segments and at least one bridging line segment, the at least one bridging line segment is electrically connected between the at least two line segments, the at least one bridging line segment is formed by a third conductive layer different from the first conductive layer and the second conductive layer, and in a top view of the array substrate, the at least one bridging line segment overlaps with the first trace, and the at least two line segments are formed by the first conductive layer.

3. The array substrate according to claim 1, characterized in that, Further comprising a first switching element and a second switching element, disposed on the substrate, wherein the gate, source and drain of the first switching element are respectively electrically connected to the first scan line, the data line and the first pixel electrode, the gate, source and drain of the second switching element are respectively electrically connected to the second scan line, the data line and the second pixel electrode, and in a top view of the array substrate, the source of the first switching element overlaps with the first trace.

4. The array substrate according to claim 1, characterized in that, Further comprising: A third pixel electrode and a fourth pixel electrode, disposed on the substrate and arranged along the first direction, and the first pixel electrode and the third pixel electrode are arranged along the second direction; A third scan line and a fourth scan line, disposed on the substrate along the first direction, wherein the third pixel electrode and the fourth pixel electrode are disposed between the third scan line and the fourth scan line; And A third switching element and a fourth switching element, disposed on the substrate, wherein the gate, source and drain of the third switching element are respectively electrically connected to the third scan line, the data line and the third pixel electrode, and the gate, source and drain of the fourth switching element are respectively electrically connected to the fourth scan line, the data line and the fourth pixel electrode, wherein in a top view of the array substrate, the source of the third switching element overlaps with the first trace, and the source of the fourth switching element overlaps with the second trace.

5. The array substrate according to claim 4, characterized in that, The third scan line includes at least two line segments and at least one bridging line segment. The at least one bridging line segment is electrically connected between the at least two line segments. In a top view of the array substrate, the at least one bridging line segment overlaps and is electrically insulated from the first trace and the second trace.

6. An array substrate, characterized in that, Comprising: a substrate; a first scan line and a second scan line disposed on the substrate along a first direction, wherein each of the first scan line and the second scan line includes a plurality of line segments and a plurality of first bridging line segments; a first trace and a second trace disposed on the substrate along a second direction different from the first direction, wherein the first trace is electrically connected to the first scan line, and the second trace is electrically connected to the second scan line; and a data line disposed on the substrate along the second direction, wherein the data line straddles one of the plurality of first bridging line segments of the first scan line and one of the plurality of first bridging line segments of the second scan line, wherein the number of the plurality of first bridging line segments of the first scan line is the same as the number of the plurality of first bridging line segments of the second scan line, wherein in a top view of the array substrate, one of the plurality of first bridging line segments of the second scan line overlaps with the data line and the first trace.

7. The array substrate according to claim 6, characterized in that, The plurality of line segments are formed by a first conductive layer, the data line is formed by a second conductive layer, the plurality of first bridging line segments are formed by a third conductive layer, and the first trace and the second trace have the same length in the second direction.

8. The array substrate according to claim 6, characterized in that, Further comprising: a first pixel electrode and a second pixel electrode disposed on the substrate and arranged along the second direction; and a first switching element and a second switching element disposed on the substrate, wherein the first pixel electrode is electrically connected to the data line through the first switching element, and the second pixel electrode is electrically connected to the data line through the second switching element.

9. The array substrate according to claim 6, characterized in that, In a top view of the array substrate, the first trace overlaps with the second pixel electrode. The second scan line further includes at least one second bridging line segment. In a top view of the array substrate, the first trace straddles the at least one second bridging line segment of the second scan line. The plurality of first bridging line segments and the at least one second bridging line segment of the second scan line are formed by the same conductive layer, and the plurality of first bridging line segments and the at least one second bridging line segment of the second scan line are formed by different conductive layers.

10. The array substrate according to claim 9, characterized in that, The first scan line further includes at least one second bridging line segment. The number of the at least one second bridging line segment of the first scan line is the same as the number of the at least one second bridging line segment of the second scan line, and the at least one second bridging line segment of the first scan line overlaps with the second trace.

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