Nonvolatile oxide heterojunction synaptic transistor and preparation method thereof

Abstract

The invention discloses a nonvolatile oxide heterojunction synapse transistor and a preparation method thereof, and belongs to the technical field of artificial synapses. The transistor comprises a substrate, a high-K gate dielectric layer, a P-type / N-type oxide semiconductor layer and a metal top electrode, through reasonable selection of P-type and N-type oxides and deep exploration of a device process level, a good built-in electric field can be formed after contact of the P-type and N-type oxides, and dynamic migration of oxygen vacancies and the width of a P-N junction barrier can be regulated and controlled by applying different pulse voltage modes to a grid electrode, so that channel resistance is influenced, the magnitude of source and drain currents is changed, and the performance of the device is improved. Dynamic switching and stable maintenance of long-term enhanced and inhibited synaptic plasticity behaviors are realized; the preparation process of the synaptic transistor device is simple, the production process is complete, the synaptic transistor device is highly compatible with the existing CMOS process, and a new thought is provided for developing a multi-stage tunable dynamic neuromorphic computing system based on a hardware level.

Description

Technical Field

[0001] The present invention belongs to the technical field of artificial synapses, and particularly relates to a non-volatile oxide heterojunction synaptic transistor, and a specific preparation method thereof is disclosed. Background Art

[0002] With the rapid development of artificial intelligence technology, artificial synaptic devices, as the core carriers for simulating the dynamic connections between biological neurons, play a key role in realizing the brain-like "learning - memory" function. These devices dynamically adjust the connection weights of neural networks by simulating the short-term plasticity (STP) and long-term plasticity (LTP / LTD) characteristics of biological synapses, providing hardware support for emerging technologies such as neuromorphic computing chips and spiking neural networks, and becoming an important breakthrough for breaking through the energy efficiency bottleneck of the traditional von Neumann computing architecture.

[0003] However, current mainstream artificial synaptic devices (such as memristors, ion-gated transistors) are generally limited by the dynamic characteristics of materials and the interfacial charge migration efficiency. Most of them can only achieve short-term synaptic plasticity, and there are still severe challenges in simulating the long-term potentiation (LTP) and depression (LTD) of biological synapses' long-term memory function. The core constraints stem from two aspects: the ion migration or interfacial charge accumulation mechanisms relied on by traditional devices are easily affected by the thermodynamic relaxation effect, resulting in rapid decay of weight information; at the same time, the non-linear mutation characteristics of the conductance state are difficult to achieve high-precision multi-level regulation, severely restricting the hardware mapping of complex learning rules.

[0004] To address the above challenges, there is an urgent need to develop a new device system with long-term memory retention ability, bidirectional plasticity regulation, and compatibility with CMOS (Complementary Metal Oxide Semiconductor) processes. Although amorphous oxide semiconductors (AOSs) and their heterostructures show potential, current research mainly focuses on the interfacial state regulation of N-type AOSs, and there is insufficient exploration of the integrated application of P-type amorphous oxide semiconductors in synaptic devices. Current research on transistors based on P-N heterojunctions generally has functional limitations: their working mechanism relies on the unidirectional modulation of the carrier concentration (holes / electrons) at the heterojunction interface by the gate voltage, which essentially belongs to the category of volatile devices and cannot meet the requirements of neural networks for non-volatile weights. The breakthrough direction should focus on the design of the heterojunction material system and process integration innovation, and key mechanisms such as the energy band matching engineering of P / N-type oxides and the precise regulation of oxygen vacancy trap states should be overcome. This technological breakthrough can not only solve the problem of simulating long-term plasticity, but also promote the evolution of neuromorphic systems from short-term memory to adaptive long-term learning, laying a foundation for constructing a biologically reasonable strong artificial intelligence hardware platform. Summary of the Invention

[0005] In view of the above problems, the present invention aims to provide a non-volatile oxide heterojunction synaptic transistor and a preparation method thereof. In this application, a specific P-type oxide and an N-type oxide are used to form a P-N junction and oxygen vacancy defects. Based on the synergistic regulation of the P-N junction rectification mechanism and the oxygen vacancy distribution, multi-level reversible switching and steady-state maintenance between the synaptic long-term potentiation (LTP) and inhibition (LTD) states can be achieved.

[0006] To achieve the above object, the technical solution adopted by the present invention is as follows: A non-volatile oxide heterojunction synaptic transistor includes a substrate, a high-K gate dielectric layer, a P-type oxide semiconductor layer, an N-type oxide semiconductor layer, and a metal top electrode, which are sequentially arranged from bottom to top; the P-type oxide semiconductor is selected from materials with rich oxygen vacancies, high mobility, and narrow bandgap; the N-type oxide semiconductor is selected from materials with high mobility and high switching ratio; a good built-in electric field is formed at the P / N interface after the P-type and N-type oxides are in contact; by applying different pulse voltage modes to the gate, the distribution of oxygen vacancies and the width of the P-N junction barrier are regulated, which can affect the channel resistance, change the magnitude of the source-drain current, and achieve reversible switching and stable maintenance of the synaptic weight between the two states of long-term potentiation and long-term depression.

[0007] Further, the different pulse voltage modes include different pulse magnitudes, different pulse numbers, and different pulse widths.

[0008] Further, the high-K gate dielectric is a hafnium-based, zirconium-based, aluminum-based, tantalum-based, or titanium-based material, which has strong gate control ability and low leakage current to ensure the stability of the device. Preferably, it is HfO2, and the thickness of the high-K gate dielectric layer is 15-25 nm.

[0009] Further, the P-type oxide semiconductor is selected from any one of TeSeO x , NiO, SnO, or Cu2O. Preferably, it is TeSeO x (Se content is 0%-30%), and the thickness of the P-type oxide semiconductor layer is 8-15 nm. Further, the N-type oxide semiconductor is selected from any one of indium zinc oxide (IZO), ZnO, In2O3, or indium gallium zinc oxide (IGZO), and the thickness of the N-type oxide semiconductor layer is 10-15 nm.

[0010] Further, the substrate material is P-type heavily doped silicon, the substrate thickness is 0.55-0.75 mm, and the thickness of the metal top electrode is 85-100 nm.

[0011] The preparation method of the above non-volatile oxide heterojunction synaptic transistor is as follows: 1) Pretreat the substrate; 2) After growing the high-K gate dielectric on the substrate, perform thermal annealing treatment; 3) A P-type oxide semiconductor front-channel layer is prepared on the gate dielectric layer by using the high-vacuum thermal evaporation method; 4) An N-type oxide semiconductor is sputtered on the front-channel layer by using the magnetron sputtering technique to prepare an N-type back-channel thin film, and annealing is performed to form a P-N junction; 5) A top electrode is prepared on the channel layer by using the vacuum thermal evaporation method.

[0012] Further, in step 2), the gate dielectric is grown on the substrate by using the atomic layer deposition technique. After the growth of the gate dielectric is completed, annealing is performed at 300 °C for 3 to 5 minutes to increase the capacitance of the HfO2 thin film and reduce the leakage current, thereby improving the device performance and reliability.

[0013] Further, in step 3), the thermal evaporation process is carried out under a vacuum degree of 10 -5 Pa, and the thermal evaporation current is 60.48 - 90.85 A.

[0014] Further, in step 4), the magnetron sputtering process is carried out in an Ar atmosphere of 0.6 pascal, the sputtering frequency is 70 W, and the sputtering time is 80 - 120 s; the annealing temperature is 200 °C and the annealing time is 60 - 80 min.

[0015] The beneficial effects of the present invention are as follows: 1. The oxide heterojunction synaptic transistor disclosed in the present application includes a substrate, a high-K gate dielectric, a P-type oxide semiconductor layer, an N-type oxide semiconductor layer, and a top electrode. The two types of oxide semiconductors form a P-N junction. The used P-type oxide semiconductor is a material with rich oxygen vacancies, a narrow bandgap, and high mobility. The oxygen vacancies serve as charge traps, and the channel conductance is changed by the arrangement of the oxygen vacancies; the N-type oxide semiconductor is a material with high mobility and a high on-off ratio, with few interface defects and excellent stability, and can achieve efficient electron injection; after the P-type and N-type oxides are in contact, a good built-in electric field is formed, which can inhibit the spontaneous diffusion of charges and ensure data non-volatility; 2. The synaptic transistor based on the P / N-type oxide heterojunction disclosed in the present application realizes the non-volatile synaptic function through the following mechanism: by changing the gate voltage polarity, on the one hand, the depletion layer width of the P-N region of the heterojunction is dynamically changed, and on the other hand, by changing the distribution of oxygen vacancies in the oxide semiconductor, the formation state of the channel conduction path is modulated, and finally, information writing and retention are realized through a significant change in the source-drain current; in addition, by designing different gate pulse voltage modes (such as pulse amplitude, number, width, etc.), the distribution of oxygen vacancies and the width of the P-N junction barrier can be finely regulated to realize the dynamic switching and stable retention of the long-term potentiation and depression of synaptic energy efficiency; 3. The present application realizes the construction of an oxide heterojunction transistor with non-volatile synaptic function through the specific selection of oxide semiconductor materials and the collaborative optimization of atomic-level interface engineering. Without the need for the stacking of multiple layers of materials such as tunneling layers and charge trapping layers in traditional floating gate or semi-floating gate structures, the non-volatility of the synapse is achieved only by relying on oxide interface defects (such as oxygen vacancies), significantly reducing the process complexity; moreover, the preparation technology of oxide heterojunction transistors is mature, the production process is perfect, it can be prepared in large areas and is highly compatible with existing CMOS processes, further effectively reducing the production cost and the difficulty of popularization; 4. The oxide heterojunction synaptic transistor disclosed in the present application regulates the distribution of oxygen vacancy trap charges through gate pulses, and has the characteristics of low power consumption and good CMOS compatibility, making it more adaptable to future development trends, providing new ideas for the development of neuromorphic synaptic devices, and having broad application prospects in Internet of Things (IoT) devices, intelligent chips, and the field of artificial intelligence. Description of the Drawings

[0016] Figure 1 is the flow chart for preparing a non-volatile oxide heterojunction synaptic transistor in Example 1; Figure 2 Subfigure a is the atomic force microscope (AFM) image of the TeSeO x semiconductor surface prepared in Example 1, and subfigure b is the atomic force microscope (AFM) image of the IZO semiconductor surface prepared in Example 1; Figure 3 Subfigure a is the schematic structural diagram of the non-volatile oxide heterojunction synaptic transistor prepared in Example 1, and subfigure b is the corresponding synapse schematic diagram, where 1 - synaptic vesicle, 2 - neurotransmitter, 3 - receptor, 4 - mitochondrion, 5 - presynaptic membrane, 6 - synaptic cleft, 7 - postsynaptic membrane; Figure 4 is the non-volatile memory level curve modulated after applying different pulse patterns to the gate of the oxide heterojunction synaptic transistor prepared in Example 1. Among them, subfigure a is the non-volatile memory level curve modulated by applying positive pulse voltages of different magnitudes, subfigure b is the non-volatile memory level curve modulated by changing the voltage pulse width when the pulse voltage is 3 V, and subfigure c is the non-volatile memory level curve modulated by applying different numbers of voltage pulses when the pulse voltage is 3 V; Figure 5It is the non-volatile memory level curves modulated after applying different pulse patterns to the gate of the oxide heterojunction synaptic transistor prepared in Example 1. Among them, Subfigure a is the non-volatile memory level curve modulated by applying negative pulse voltages of different magnitudes, Subfigure b is the non-volatile memory level curve modulated by changing the voltage pulse width when the pulse voltage is -0.5 V, and Subfigure c is the non-volatile memory level curve modulated by applying different numbers of voltage pulses when the pulse voltage is -0.5 V; Figure 6 In Subfigure a is the cyclic programming / erasing characteristic curve of the device, triggered by 35 consecutive enhancing positive pulses (+4V) and 35 suppressing negative pulses (-0.8 V), with a pulse width of 400 ms. Subfigure b is an enlarged view of part A in Subfigure a; Figure 7 It is the P-N junction barrier energy band diagram of the oxide heterojunction synaptic transistor prepared in Example 1. Among them, Subfigure a is the energy band diagram for writing by applying a positive gate voltage, and Subfigure b is the energy band diagram for gradually restoring the source-drain current by applying a negative gate voltage. Detailed implementation manners

[0017] To enable those of ordinary skill in the art to better understand the technical solutions of the present invention, the technical solutions of the present invention will be further described below with reference to the accompanying drawings and embodiments.

[0018] Example 1

[0019] This example discloses a preparation method of a non-volatile oxide heterojunction synaptic transistor. The preparation process refers to Figure 1 , and the specific preparation steps are as follows:

[0020] 1) Pretreatment of the substrate: Ultrasonically clean the P-type heavily doped silicon wafer in anhydrous ethanol and deionized water for 10 minutes respectively, repeat twice to ensure the surface is clean and free of impurities. After drying with a nitrogen gun, heat it at 80 °C for 5 minutes to ensure the substrate is dry, and the substrate thickness is 0.55 mm.

[0021] 2) Preparation of the gate dielectric layer: Put the pretreated substrate into an atomic layer deposition (ALD) device, introduce tetrakis(dimethylamino)hafnium (TDMAH) and H2O, and grow a 20 nm thick HfO2 gate dielectric on the substrate. Rapidly anneal at 300 °C for 5 minutes to improve the capacitance characteristics of the gate dielectric and reduce leakage current.

[0022] 3) Preparation of the P-type oxide semiconductor layer: On the surface of the gate dielectric layer, use a hard mask to perform patterning in a high-vacuum thermal evaporator to obtain a rectangular channel layer with a length of 1300 μm and a width of 750 μm; Use a mixture of 93% TeO2 and 7% Se as the P-type semiconductor material, fully mix and grind it, and then put it into a tungsten evaporation boat; At 10 -5Thermal evaporation was carried out under a vacuum of Pa, with a thermal evaporation current of 90.85 A, to prepare a 10 nm thick TeSeO x front channel layer.

[0023] Figure 2 Neutron figure a shows the AFM image of the smooth surface of the TeSeO x semiconductor.

[0024] 4) Preparation of the N-type oxide semiconductor layer: A layer of IZO (N-type semiconductor material) was deposited on the sample channel using a high-vacuum triple-target coating machine; patterning was carried out by making a hard mask with a length of 1200 μm and a width of 550 μm, so that it was completely embedded in the P-type channel; using radio frequency magnetron sputtering technology, in an Ar atmosphere of 0.6 Pascal, with a 99.99% pure IZO ceramic target as the sputtering target, the radio frequency power was adjusted to 70 W, sputtering for 80 s, with a thickness of about 15 nm, and then the sample was placed in air and annealed at 200 °C for 60 min.

[0025] Figure 2 Neutron figure b shows the AFM image of the smooth surface of the IZO semiconductor.

[0026] 5) Manufacturing source and drain electrodes using vacuum thermal evaporation technology: Metal Al particles and the device covered with the mask were placed in an evaporation instrument. Under a vacuum of 10 -5 Pa, with a thermal evaporation current of 110.8 A, a 100 nm thick Al source and drain electrode (1000 μm long and 150 μm wide) was prepared; after evaporation, the power was slowly reduced to 0, and after the cavity was completely cooled, nitrogen was flushed in and the finished product was taken out.

[0027] The edge of the device was scratched, silver paste was applied, and the bottom electrode was led out for testing.

[0028] The structural schematic diagram and the corresponding synaptic schematic diagram of the oxide heterojunction synaptic transistor prepared according to the above method are shown in Figure 3 neutron figures a and b respectively. The structure of the transistor device from bottom to top is P + -Si substrate, HfO2 high-K gate dielectric layer, P-type oxide semiconductor (TeSeO x ), front channel layer, N-type oxide semiconductor (IZO) back channel layer, and Al metal top electrode.

[0029] The Keysight B1500 was used to conduct electrical tests on the oxide heterojunction synaptic transistor prepared in this example. The test circuit was that the probe was in contact with the source, drain, and gate of the device, the source was grounded, different pulse voltages were applied to the gate, and a fixed read voltage was applied to the drain. Figure 4 and Figure 5Shows the experimental results of realizing the dynamic modulation of the memory characteristics of the device by regulating the gate voltage pulse pattern. Among them, Figure 4 The influence of positive voltage pulses on the memory level was studied: by adjusting the amplitude of the positive pulse ( Figure 4 subfigure a), changing the pulse width (from 400 ms to 5000 ms, Figure 4 subfigure b), and applying different numbers of pulses ( Figure 4 subfigure c), the device exhibited obvious long-term potentiation characteristics. Correspondingly, Figure 5 The regulation effect of negative voltage pulses was systematically explored: by adjusting the amplitude of the negative pulse ( Figure 5 subfigure a), expanding the pulse width range ( Figure 5 subfigure b), and changing the number of pulses ( Figure 5 subfigure c), the device showed significant long-term depression phenomenon. The experimental results show that by precisely regulating parameters such as the amplitude, width, and number of positive and negative pulses, the multi-state dynamic regulation of the memory level can be effectively achieved, providing an important experimental basis for realizing reconfigurable synaptic functions. This is mainly because applying different biases to the gate affects the P-N junction width and the migration of oxygen vacancies.

[0030] In addition, as can be seen from Figure 6 using 35 positive pulses of 4 V can realize the memory process in the device, while applying 35 negative pulses of -0.8 V gradually reduces the current to achieve the forgetting process. The pulse widths of the positive and negative pulses used are both 400 ms. The memory process and the forgetting process together simulate the synaptic energy efficiency process of the device, and the device shows stable and repeatable cycling performance.

[0031] For the transistor device prepared in this embodiment, the materials for forming the P-N junction are the P-type oxide semiconductor TeSeO x and the N-type oxide semiconductor IZO. TeSeO x is a material with abundant oxygen vacancies, a narrow bandgap, and high mobility. The oxygen vacancies act as charge traps, and the channel conductance is changed by the arrangement of oxygen vacancies; IZO is a material with high mobility and a high on-off ratio, with few interface defects and excellent stability, and can achieve efficient electron injection. The amorphous structure with high mobility supports fast transport, and the oxygen vacancies act as electron capture centers, having the ability to enhance non-volatility.

[0032] The energy band diagram of the P-N junction barrier of this device can be seen in Figure 7 From Figure 7From the perspective of Subfigure a, when a positive gate pulse (+4V) is applied, the P-N junction is in a forward bias state. The positive gate pulse not only weakens the potential of the built-in electric field but also changes the distribution of oxygen vacancies. Driven by the positive gate voltage, the positively charged oxygen vacancies in the P-type oxide approach the P-N junction, further weakening the potential of the built-in electric field. This drives electrons to transfer from the N-type oxide across the potential barrier to the P-type oxide, and the injected charge quantity increases with the increase in the number of pulses, pulse width, and pulse voltage. When the pulse disappears, since the oxygen vacancies slowly return to their initial positions spontaneously, it is difficult for the built-in electric field to return to its initial state. Therefore, the channel conductance increases and the current increases. When a negative gate pulse of -0.8 V is applied ( Figure 7 Subfigure b), the external electric field will accelerate the pulling away of the oxygen vacancies staying at the P-N junction, causing the oxygen vacancies to be rearranged, restoring the built-in electric field, reducing the channel conductance, and achieving the inhibition function.

[0033] The above shows and describes the basic principles, main features, and advantages of the present invention. However, the above are only specific embodiments of the present invention, and the technical features of the present invention are not limited thereto. Any other implementation manners obtained by those skilled in the art without departing from the technical solution of the present invention should be covered within the scope of the present invention.

Claims

1. A nonvolatile oxide heterojunction synaptic transistor, characterized in that: It includes a substrate, a high-K gate dielectric layer, a P-type oxide semiconductor layer, an N-type oxide semiconductor layer and a metal top electrode which are arranged in sequence; The P-type oxide semiconductor is selected from materials having abundant oxygen vacancies, high mobility and narrow band gap; The N-type oxide semiconductor is selected from materials having high mobility and high on / off ratio; After the P-type and N-type oxides come into contact, a good built-in electric field is formed at the P / N interface; By applying different pulse voltage modes to the gate, the distribution of oxygen vacancies and the width of the PN junction barrier can be regulated, which can affect the channel resistance, change the source-drain current, and achieve reversible switching and stable maintenance of synaptic weights between long-term potentiation and long-term inhibition.

2. The nonvolatile oxide heterojunction synapse transistor according to claim 1, wherein: The different pulse voltage modes include different pulse sizes, different pulse numbers and different pulse widths.

3. The nonvolatile oxide heterojunction synapse transistor according to claim 1, wherein: The high-K gate dielectric is a hafnium-based, zirconium-based, aluminum-based, tantalum-based or titanium-based material, and the thickness of the high-K gate dielectric layer is 15~25 nm.

4. The nonvolatile oxide heterojunction synapse transistor according to claim 1, wherein: The P-type oxide semiconductor is selected from TeSeO x , any one of NiO, SnO or Cu2O, and the thickness of the P-type oxide semiconductor layer is 8~15 nm.

5. The nonvolatile oxide heterojunction synapse transistor according to claim 1, wherein: The N-type oxide semiconductor is selected from any one of IZO, ZnO, In2O3 or IGZO, and the thickness of the N-type oxide semiconductor layer is 10-15 nm.

6. The nonvolatile oxide heterojunction synapse transistor according to claim 1, wherein: The substrate material is P-type heavily doped silicon, the substrate thickness is 0.55~0.75 mm, and the metal top electrode thickness is 85~100 nm.

7. The method for preparing a non-volatile oxide heterojunction synapse transistor according to any one of claims 1 to 6, characterized in that: The specific steps are as follows: 1) Pre-treat the substrate; 2) After growing the high-K gate dielectric on the substrate, thermal annealing is performed; 3) Preparing a P-type oxide semiconductor front channel layer on the gate dielectric layer by high vacuum thermal evaporation method; 4) sputtering an N-type oxide semiconductor on the front channel layer using magnetron sputtering technology to prepare an N-type back channel film, and annealing; 5) Prepare the top electrode on the channel layer by vacuum thermal evaporation.

8. The method for preparing a non-volatile oxide heterojunction synapse transistor according to claim 7, characterized in that: In step 2), the gate dielectric is grown on the substrate using atomic layer deposition technology, and after the gate dielectric is grown, it is annealed at 300° C. for 3 to 5 minutes.

9. The method for preparing a nonvolatile oxide heterojunction synapse transistor according to claim 7, characterized in that: In step 3), the thermal evaporation process is carried out at 10 -5 The process was carried out under a vacuum degree of 1.38 Pa and the thermal steaming current was 60.48~90.85 A.

10. The method for preparing a non-volatile oxide heterojunction synapse transistor according to claim 7, characterized in that: In step 4), the magnetron sputtering process is carried out in a 0.6 Pascal Ar atmosphere, the sputtering frequency is 70 W, and the sputtering time is 80-120 s; the annealing temperature is 200 ° C, and the annealing time is 60-80 min.

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