Low-dropout voltage stabilizing circuit without off-chip capacitor, chip and electronic equipment

Abstract

The invention provides a low-dropout voltage stabilizing circuit without an off-chip capacitor, a chip and electronic equipment, the circuit comprises a low-dropout voltage stabilizing circuit and a transient response enhancement circuit, the low-dropout voltage stabilizing circuit is used for generating a first bias voltage and a second bias voltage and transmitting the first bias voltage and the second bias voltage to the transient response enhancement circuit; the reference circuit is also used for transmitting the reference voltage output by the reference circuit to the transient response enhancement circuit; and the transient response enhancement circuit is used for receiving the first bias voltage, the second bias voltage and the reference voltage, and when the reference voltage changes, the variable quantity is coupled to the low-dropout voltage stabilizing circuit, so that the low-dropout voltage stabilizing circuit adjusts the reference voltage output by the low-dropout voltage stabilizing circuit based on the variable quantity. The reference voltage is detected through the transient response enhancement circuit, when the reference voltage changes, the variable quantity is coupled to the low-dropout voltage stabilizing circuit to adjust the reference voltage, and the transient response speed of the LDO without the off-chip capacitor can be increased.

Description

Technical Field

[0001] This application relates to the technical field of power management chips, and in particular to a low-dropout regulator circuit without external capacitors, a chip, and an electronic device. Background Art

[0002] A low-dropout regulator (LDO), also known as a low-dropout linear regulator or a low-drop voltage regulator, is a type of linear DC voltage regulator used to provide a stable DC voltage power supply. Compared with general linear DC voltage regulators, an LDO can operate under a smaller output-input voltage difference. With the popularization of electronic devices, the LDO, as an important circuit structure, is widely used in various hybrid integrated circuits to provide a stable and clean chip supply voltage.

[0003] With the development of complementary metal oxide semiconductor (CMOS) technology and the increasing requirements of electronic devices for low power consumption, integration, and small size, more and more peripheral circuits are integrated inside the chip. The LDO without external capacitors has been widely promoted due to its simple application circuit. Compared with traditional LDOs, in project applications, the LDO without external capacitors can achieve the level conversion from the input voltage to the output voltage without using capacitors outside the LDO chip. For traditional LDOs, especially for those with only one loop, in order to maintain stability under light load and heavy load conditions, the loop bandwidth is usually not made very large. Therefore, the response speed of the loop is slow. Without the voltage regulation effect of external capacitors, when the load current changes suddenly, the transient response of traditional LDOs is poor. For example, when the load current suddenly rises from 0 to the mA level, due to the poor transient response of the LDO and the lack of a fast response mechanism, the output voltage of the LDO will be quickly pulled down to nearly 0V.

[0004] Therefore, how to improve the transient response speed of the LDO without external capacitors is an important problem to be solved. Summary of the Invention

[0005] This application provides a low-dropout regulator circuit without external capacitors, a chip, and an electronic device to improve the transient response speed.

[0006] In a first aspect, this application provides a low-dropout regulator circuit without external capacitors. The low-dropout regulator circuit without external capacitors includes: a low-dropout regulator circuit and a transient response enhancement circuit. The low-dropout regulator circuit includes a first bias terminal, a second bias terminal, a first reference voltage output terminal, and a first output control terminal. The transient response enhancement circuit includes a third bias terminal, a fourth bias terminal, a second reference voltage output terminal, and a second output control terminal;

[0007] The first bias terminal is electrically connected to the third bias terminal, the second bias terminal is electrically connected to the fourth bias terminal, the first reference voltage output terminal is electrically connected to the second reference voltage output terminal, and the first output control terminal is electrically connected to the second output control terminal;

[0008] The low-dropout regulator circuit is configured to generate a first bias voltage and a second bias voltage, and transmit the first bias voltage to the transient response enhancement circuit based on the third bias terminal through the first bias terminal, and transmit the second bias voltage to the transient response enhancement circuit based on the fourth bias terminal through the second bias terminal; it is also configured to transmit the reference voltage output by itself to the transient response enhancement circuit based on the second reference voltage output terminal through the first reference voltage output terminal;

[0009] The transient response enhancement circuit is configured to receive the first bias voltage, the second bias voltage, and the reference voltage, and when the reference voltage changes, couple the change amount to the low-dropout regulator circuit based on the second output control terminal and the first output control terminal, so that the low-dropout regulator circuit adjusts the reference voltage output by itself based on the change amount.

[0010] In a possible design, the transient response enhancement circuit includes: a first response enhancement circuit and a second response enhancement circuit;

[0011] When the reference voltage changes, generate a first change amount and a second change amount;

[0012] The first response enhancement circuit is configured to receive the first bias voltage and couple the first change amount to the second output control terminal, so that the low-dropout regulator circuit adjusts the reference voltage output by itself based on the first change amount;

[0013] The second response enhancement circuit is configured to receive the second bias voltage and couple the second change amount to the second output control terminal, so that the low-dropout regulator circuit adjusts the reference voltage output by itself based on the second change amount.

[0014] In a possible design, the first response enhancement circuit includes: a first P-type transistor, a second P-type transistor, a first N-type transistor, a second N-type transistor, a first resistor, a first capacitor, and a second capacitor;

[0015] The source of the first P-type transistor is electrically connected to the source of the second P-type transistor for accessing an input voltage. The gate of the first P-type transistor is electrically connected to the gate of the second P-type transistor and the third bias terminal respectively. The drain of the first P-type transistor is electrically connected to the drain of the first N-type transistor and the first terminal of the first capacitor respectively;

[0016] The drain of the second P-type transistor is electrically connected to the drain of the second N-type transistor, the gate of the second N-type transistor, and the second terminal of the first resistor respectively;

[0017] The source of the first N-type transistor is electrically connected to the source of the second N-type transistor and the second reference voltage output terminal respectively. The gate of the first N-type transistor is electrically connected to the first terminal of the first resistor and the first terminal of the second capacitor respectively;

[0018] The second terminal of the first capacitor is electrically connected to the second output control terminal;

[0019] The second terminal of the second capacitor is grounded.

[0020] In a possible design, the second response enhancement circuit includes: a third P-type transistor, a fourth P-type transistor, a third N-type transistor, a fourth N-type transistor, a second resistor, a third capacitor, and a fourth capacitor;

[0021] The source of the third P-type transistor is electrically connected to the source of the fourth P-type transistor and the second reference voltage output terminal respectively. The gate of the third P-type transistor is electrically connected to the drain of the third P-type transistor, the drain of the third N-type transistor, and the first terminal of the second resistor respectively;

[0022] The gate of the fourth P-type transistor is electrically connected to the second terminal of the second resistor and the first terminal of the fourth capacitor respectively. The drain of the fourth P-type transistor is electrically connected to the drain of the fourth N-type transistor and the second terminal of the third capacitor respectively;

[0023] The source of the third N-type transistor is grounded. The gate of the third N-type transistor is electrically connected to the gate of the fourth N-type transistor and the fourth bias terminal respectively;

[0024] The source of the fourth N-type transistor is grounded. The second terminal of the fourth capacitor is grounded;

[0025] The first terminal of the third capacitor is electrically connected to the second output control terminal.

[0026] In a possible design, the low dropout regulator circuit includes: a bias circuit, an operational amplifier circuit, and an output circuit;

[0027] The bias circuit is used to generate the first bias voltage and the second bias voltage, and transmit the first bias voltage and the second bias voltage to the operational amplifier circuit;

[0028] The operational amplifier circuit is used to compare the feedback voltage with the reference voltage based on the first bias voltage and the second bias voltage to obtain a drive signal, and transmit the drive signal to the output circuit;

[0029] The output circuit is used to output the reference voltage based on the drive signal, divide the reference voltage to obtain the feedback voltage, and transmit the feedback voltage to the operational amplifier circuit.

[0030] In a possible design, the bias circuit includes: a seventh P-type transistor, an eighth P-type transistor, a fifth N-type transistor, a sixth N-type transistor, a twelfth N-type transistor, a thirteenth N-type transistor, and a fifth resistor;

[0031] The source of the seventh P-type transistor is electrically connected to the source of the eighth P-type transistor for accessing an input voltage. The gate of the seventh P-type transistor is electrically connected to the drain of the seventh P-type transistor, the drain of the thirteenth N-type transistor, the gate of the eighth P-type transistor, and the first bias terminal respectively;

[0032] The drain of the eighth P-type transistor is electrically connected to the first end of the fifth resistor and the gate of the fifth N-type transistor respectively;

[0033] The source of the fifth N-type transistor is electrically connected to the drain of the sixth N-type transistor. The drain of the fifth N-type transistor is electrically connected to the second end of the fifth resistor, the gate of the sixth N-type transistor, and the second bias terminal respectively;

[0034] The source of the sixth N-type transistor is grounded;

[0035] The drain of the twelfth N-type transistor is electrically connected to the gate of the twelfth N-type transistor and the gate of the thirteenth N-type transistor respectively for accessing a bias current;

[0036] The source of the twelfth N-type transistor and the source of the thirteenth N-type transistor are both grounded.

[0037] In a possible design, the operational amplifier circuit includes: a fifth P-type transistor, a ninth P-type transistor, a tenth P-type transistor, an eleventh P-type transistor, a twelfth P-type transistor, a thirteenth P-type transistor, a fourteenth P-type transistor, a seventh N-type transistor, an eighth N-type transistor, a ninth N-type transistor, a tenth N-type transistor, an eleventh N-type transistor, and a sixth capacitor;

[0038] The source electrodes of the ninth P-type transistor are respectively electrically connected to the source electrodes of the twelfth P-type transistor, the thirteenth P-type transistor, and the fourteenth P-type transistor for accessing the input voltage. The drain electrode of the ninth P-type transistor is respectively electrically connected to the source electrodes of the tenth P-type transistor and the eleventh P-type transistor. The gate electrodes of the ninth P-type transistor are respectively electrically connected to the gate electrodes of the fourteenth P-type transistor and the first bias terminal;

[0039] The drain electrode of the tenth P-type transistor is respectively electrically connected to the source electrode of the ninth N-type transistor, the drain electrode of the tenth N-type transistor, and the first terminal of the sixth capacitor. The gate electrode of the tenth P-type transistor is used for accessing the reference voltage;

[0040] The drain electrode of the eleventh P-type transistor is respectively electrically connected to the source electrode of the seventh N-type transistor and the drain electrode of the eighth N-type transistor. The gate electrode of the eleventh P-type transistor is electrically connected to the output circuit;

[0041] The gate electrodes of the twelfth P-type transistor are respectively electrically connected to the drain electrode of the twelfth P-type transistor, the gate electrode of the thirteenth P-type transistor, and the drain electrode of the seventh N-type transistor;

[0042] The drain electrode of the thirteenth P-type transistor is respectively electrically connected to the gate electrode of the fifth P-type transistor and the drain electrode of the ninth N-type transistor;

[0043] The drain electrode of the fourteenth P-type transistor is respectively electrically connected to the source electrode of the fifth P-type transistor and the first output control terminal;

[0044] The drain electrode of the fifth P-type transistor is electrically connected to the drain electrode of the eleventh N-type transistor;

[0045] The gate electrodes of the seventh N-type transistor are respectively electrically connected to the gate electrodes of the ninth N-type transistor and the fifth N-type transistor;

[0046] The gate electrodes of the eighth N-type transistor are respectively electrically connected to the second bias terminal, the gate electrode of the tenth N-type transistor, and the gate electrode of the eleventh N-type transistor;

[0047] The source electrodes of the eighth N-type transistor, the tenth N-type transistor, and the eleventh N-type transistor are all grounded;

[0048] The second terminal of the sixth capacitor is electrically connected to the output circuit.

[0049] In a possible design, the output circuit includes: a sixth P-type transistor, a third resistor, a fourth resistor, and a fifth capacitor;

[0050] The source of the sixth P-type transistor is used to access the input voltage. The gate of the sixth P-type transistor is electrically connected to the first output control terminal. The drain of the sixth P-type transistor is electrically connected to the second terminal of the sixth capacitor, the first terminal of the third resistor, the first terminal of the fifth capacitor, and the first reference voltage output terminal, and the first reference voltage output terminal outputs the reference voltage;

[0051] The second terminal of the third resistor is electrically connected to the first terminal of the fourth resistor and the gate of the eleventh P-type transistor;

[0052] The second terminal of the fourth resistor and the second terminal of the fifth capacitor are both grounded.

[0053] In a second aspect, the present application provides a chip, including: the low dropout regulator circuit without external capacitors as described in the first aspect.

[0054] In a third aspect, the present application provides an electronic device, including: the chip as described in the second aspect.

[0055] Advantageous effects of the embodiments of the present application:

[0056] In the embodiments of the present application, the reference voltage Vout output by the low dropout regulator circuit is detected by the transient response enhancement circuit. When the reference voltage changes, the change amount is timely coupled to the low dropout regulator circuit, so that the low dropout regulator circuit adjusts the reference voltage based on the change amount. When the load current changes suddenly, the reference voltage also changes. The transient response enhancement circuit can improve the response speed of the loop and the transient response speed of the LDO without external capacitors.

[0057] For what is provided in the above second aspect and each possible design of the second aspect, the beneficial effects can refer to the beneficial effects brought by the above first aspect and each possible implementation manner of the first aspect, and will not be elaborated here. Description of the Drawings

[0058] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, other embodiments can also be obtained according to these drawings.

[0059] Figure 1 A traditional LDO circuit diagram provided for the related art;

[0060] Figure 2 A structural schematic diagram of a low dropout regulator circuit without external capacitors provided for the embodiments of the present application;

[0061] Figure 3 The circuit structure diagram of a transient response enhancement circuit provided by an embodiment of the present application;

[0062] Figure 4 The circuit structure diagram of a low dropout regulator circuit without an external capacitor provided by an embodiment of the present application. Detailed implementation manners

[0063] In the present application, "at least one" means one or more, and "a plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone, where A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after. "At least one (item)" or its similar expression refers to any combination of these items, including any combination of single item (item) or plural items (items). For example, at least one (item) of a alone, b alone, or c alone can represent: a alone, b alone, c alone, the combination of a and b, the combination of a and c, the combination of b and c, or the combination of a, b, and c, where a, b, and c can be single or multiple. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0064] The orientation or positional relationship indicated by the terms "center", "longitudinal", "transverse", "upper", "lower", "left", "right", "front", "rear", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to the present application.

[0065] The terms "connected" and "connection" should be understood in a broad sense. For example, the "connection" or "connection" of a circuit structure can refer not only to a physical connection, but also to an electrical connection or a signal connection. For example, it can be a direct connection, that is, a physical connection, or it can be indirectly connected through at least one intermediate element, as long as the circuit is connected. It can also be the connection inside two elements; the signal connection can refer not only to the signal connection through a circuit, but also to the signal connection through a media medium. For example, radio waves. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific situations.

[0066] See Figure 1 , Figure 1 A traditional LDO circuit provided by the related art, such as Figure 1As shown, in the traditional LDO circuit, the first N-type switch QN1, the second N-type switch QN2, the first P-type switch QP1, the second P-type switch QP2, the third N-type switch QN3, and the fourth N-type switch QN4 together form a bias circuit. By mirroring the bias current ibias_1, a bias voltage and a bias current are generated to provide bias for each switch in the LDO circuit. The fifth N-type switch QN5, the sixth N-type switch QN6, the seventh N-type switch QN7, the eighth N-type switch QN8, the sixth P-type switch QP6, the seventh P-type switch QP7, the fourth P-type switch QP4, the fifth P-type switch QP5, the eighth P-type switch QP8, the ninth P-type switch QP9, and the ninth N-type switch QN9 together form a multi-stage operational amplifier. Among them, the fourth P-type switch QP4 and the fifth P-type switch QP5 are the input stage of the operational amplifier. The gate of the fourth P-type switch QP4 is the inverting input terminal of the operational amplifier, and the gate of the fifth P-type switch QP5 is the non-inverting input terminal of the operational amplifier. The fifth N-type switch QN5, the sixth N-type switch QN6, the seventh N-type switch QN7, the eighth N-type switch QN8, the sixth P-type switch QP6, and the seventh P-type switch QP7 together form the first output stage of the folded cascode telescopic operational amplifier. The eighth P-type switch QP8, the ninth P-type switch QP9, and the ninth N-type switch QN9 together form the second output stage of the operational amplifier. Through the second output stage, the output terminal of the operational amplifier can be separated from the gate of the tenth P-type switch QP10, and at the same time, the driving ability of the gate of the tenth P-type switch QP10 is enhanced, and the response time is reduced. In addition, the tenth P-type switch QP10, the first voltage-dividing resistor R1_1, and the second voltage-dividing resistor R2_1 together form the output stage of the LDO circuit. The middle node of the first voltage-dividing resistor R1_1 and the second voltage-dividing resistor R2_1 is electrically connected to the gate of the fifth P-type switch QP5 to form a negative feedback loop. The capacitor C2_1 is a compensation capacitor, and the capacitor C1_1 is an output voltage stabilizing capacitor.

[0067] Under the action of the feedback network in the traditional LDO circuit, the expression between the output voltage Vout_1 and the reference voltage VREF is:

[0068]

[0069] In the formula, r 1_1 is the resistance value of the first voltage-dividing resistor R1_1, and r 2_1 is the resistance value of the second voltage-dividing resistor R2_1.

[0070] When the current of the load changes, voltage fluctuations will occur on the output voltage Vout_1. The changes on the output voltage Vout_1 are transmitted to the gate of the fifth P-type switch QP5 through the feedback loop composed of the first voltage-dividing resistor R1_1 and the second voltage-dividing resistor R2_1, and the gate voltage of the tenth P-type switch QP10 is adjusted through the operational amplifier.

[0071] For Figure 1 the traditional LDO in [reference], especially for an LDO with only one loop, in order to maintain stability under light load and heavy load conditions, the loop bandwidth is usually not made very large. Therefore, the response speed of the loop is slow; in addition, without the voltage regulation effect of an external capacitor, when the load current changes suddenly, the transient response of the LDO is poor.

[0072] Since the LDO without an external capacitor has no external capacitor, the transient response speed of the LDO without an external capacitor is slow. In order to improve the transient response speed of the LDO without an external capacitor. Refer to Figure 2 , the embodiment of the present application provides a low-dropout voltage regulation circuit without an external capacitor. As Figure 2 shown, the low-dropout voltage regulation 1000 circuit without an external capacitor includes: a low-dropout voltage regulation circuit 100 and a transient response enhancement circuit 200. The low-dropout voltage regulation circuit 100 includes a first bias terminal P1, a second bias terminal P2, a first reference voltage output terminal OUT1, and a first output control terminal PG1. The transient response enhancement circuit includes a third bias terminal P3, a fourth bias terminal P4, a second reference voltage output terminal OUT2, and a second output control terminal PG2.

[0073] The first bias terminal P1 is electrically connected to the third bias terminal P3, the second bias terminal P2 is electrically connected to the fourth bias terminal P4, the first reference voltage output terminal OUT1 is electrically connected to the second reference voltage output terminal OUT2, and the first output control terminal PG1 is electrically connected to the second output control terminal PG2.

[0074] The low-dropout voltage regulation circuit 100 is used to generate a first bias voltage Vp1 and a second bias voltage Vn1, and transmit the first bias voltage Vp1 to the transient response enhancement circuit 200 based on the third bias terminal P3 through the first bias terminal P1, and transmit the second bias voltage Vn1 to the transient response enhancement circuit 200 based on the fourth bias terminal P4 through the second bias terminal P2; it is also used to transmit the reference voltage Vout output by itself to the transient response enhancement circuit 200 based on the second reference voltage output terminal OUT2 through the first reference voltage output terminal OUT1.

[0075] The transient response enhancement circuit 200 is configured to receive a first bias voltage Vp1, a second bias voltage Vn1, and a reference voltage Vout. When the reference voltage Vout changes, the change amount is coupled to the low dropout regulator circuit 100 based on a second output control terminal PG2 and a first output control terminal PG1, so that the low dropout regulator circuit 100 adjusts the reference voltage Vout output by itself based on the change amount.

[0076] The low dropout regulator circuit 100 can generate a first bias voltage Vp1 and a second bias voltage Vn1, and transmit the first bias voltage Vp1 to the transient response enhancement circuit 200 through a first bias terminal P1 and a third bias terminal P3, and transmit the second bias voltage Vn1 to the transient response enhancement circuit 200 through a second bias terminal P2 and a fourth bias terminal P4, so as to provide bias voltages for each module in the transient response enhancement circuit. In addition, a first reference voltage output terminal OUT1 of the low dropout regulator circuit 100 is electrically connected to a second reference voltage output terminal OUT2 of the transient response enhancement circuit 200, and the reference voltage Vout can be transmitted to the transient response enhancement circuit 200, so that the transient response enhancement circuit 200 can detect the change of the reference voltage Vout and can respond in time when the reference voltage Vout changes.

[0077] When the reference voltage Vout changes, the transient response enhancement circuit 200 can timely couple the change amount to the low dropout regulator circuit 100 based on the second output control terminal PG2 and the first output control terminal PG1, so that the low dropout regulator circuit 100 adjusts the reference voltage Vout based on the change amount.

[0078] In the embodiment of the present application, the reference voltage Vout output by the low dropout regulator circuit is detected by the transient response enhancement circuit. When the reference voltage changes, the change amount is timely coupled to the low dropout regulator circuit, so that the low dropout regulator circuit adjusts the reference voltage based on the change amount. When the load current suddenly changes, the reference voltage also changes. The transient response enhancement circuit can improve the response speed of the loop and the transient response speed of the LDO without an external capacitor.

[0079] In a possible embodiment, refer to Figure 3 , Figure 3 A transient response enhancement circuit provided by an embodiment of the present application, as Figure 3 shown, the transient response enhancement circuit 200 includes: a first response enhancement circuit 201 and a second response enhancement circuit 202.

[0080] When the reference voltage Vout changes, a first change amount and a second change amount are generated.

[0081] The first response enhancement circuit 201 is configured to receive a first bias voltage Vp1 and couple a first variation to a second output control terminal PG2, so that the low dropout regulator circuit 100 adjusts its output reference voltage Vout based on the first variation.

[0082] The second response enhancement circuit 202 is configured to receive a second bias voltage Vn1 and couple a second variation to the second output control terminal PG2, so that the low dropout regulator circuit 100 adjusts its output reference voltage Vout based on the second variation.

[0083] When the reference voltage Vout changes, it can increase or decrease. When the reference voltage Vout undergoes a downward mutation, that is, when Vout decreases, a first variation is generated; when the reference voltage Vout undergoes an upward mutation, that is, when Vout increases, a second variation is generated. The transient response enhancement circuit in the embodiments of the present application includes a first response enhancement circuit and a second response enhancement circuit, and is configured to enable the low dropout regulator circuit to adjust its output reference voltage Vout based on the first variation and the second variation in both cases of downward mutation and upward mutation of the reference voltage Vout.

[0084] In a possible embodiment, referring to Figure 3 , the first response enhancement circuit 201 includes: a first P-type transistor MP1, a second P-type transistor MP2, a first N-type transistor MN1, a second N-type transistor MN2, a first resistor R1, a first capacitor C1, and a second capacitor C2.

[0085] The source of the first P-type transistor MP1 is electrically connected to the source of the second P-type transistor MP2 for connecting to an input voltage Vdd_ldo. The gate of the first P-type transistor MP1 is electrically connected to the gate of the second P-type transistor MP2 and a third bias terminal P3 respectively. The drain of the first P-type transistor MP1 is electrically connected to the drain of the first N-type transistor MN1 and the first end of the first capacitor C1 respectively.

[0086] The drain of the second P-type transistor MP2 is electrically connected to the drain of the second N-type transistor MN2, the gate of the second N-type transistor MN2, and the second end of the first resistor R1 respectively.

[0087] The source of the first N-type transistor MN1 is electrically connected to the source of the second N-type transistor MN2 and a second reference voltage output terminal OUT2 respectively. The gate of the first N-type transistor MN1 is electrically connected to the first end of the first resistor R1 and the first end of the second capacitor C2 respectively.

[0088] The second end of the first capacitor C1 is electrically connected to the second output control terminal PG2.

[0089] The second end of the second capacitor C2 is grounded.

[0090] The third bias terminal P3 is used to access the first bias voltage Vp1. The first bias voltage Vp1 provides bias voltages for the first N-type transistor MN1 and the second N-type transistor MN2. The second reference voltage output terminal OUT2 is used to access the reference voltage Vout output by the low-dropout regulator circuit. The second output control terminal PG2 is electrically connected to the gate of the P-type transistor in the low-dropout regulator circuit, and is used to couple and transmit the second variation amount to the low-dropout regulator circuit, which will be introduced in detail in combination with the low-dropout regulator circuit later.

[0091] The first resistor R1 and the second capacitor C2 form a low-pass filter network, which is used to stabilize the voltage of the gate of the first N-type transistor MN1. The function of the second N-type transistor MN2 is to provide the bias voltage for the first N-type transistor MN1. The first P-type transistor MP1 and the second P-type transistor MP2 act as current sources and can provide bias currents for the first N-type transistor MN1 and the second N-type transistor MN2.

[0092] In the embodiments of the present application, the first P-type transistor MP1, the second P-type transistor MP2, the first N-type transistor MN1, and the second N-type transistor MN2 can be metal-oxide-semiconductor field-effect transistors or gallium nitride transistors. The embodiments of the present application do not make specific limitations on this.

[0093] In a possible embodiment, refer to Figure 3 , the second response enhancement circuit 202 includes: a third P-type transistor MP3, a fourth P-type transistor MP4, a third N-type transistor MN3, a fourth N-type transistor MN4, a second resistor R2, a third capacitor C3, and a fourth capacitor C4.

[0094] The source of the third P-type transistor MP3 is electrically connected to the source of the fourth P-type transistor MP4 and the second reference voltage output terminal OUT2 respectively. The gate of the third P-type transistor MP3 is electrically connected to the drain of the third P-type transistor MP3, the drain of the third N-type transistor MN3, and the first end of the second resistor R2 respectively.

[0095] The gate of the fourth P-type transistor MP4 is electrically connected to the second end of the second resistor R2 and the first end of the fourth capacitor C4 respectively. The drain of the fourth P-type transistor MP4 is electrically connected to the drain of the fourth N-type transistor MN4 and the second end of the third capacitor C3 respectively.

[0096] The source of the third N-type transistor MN3 is grounded. The gate of the third N-type transistor MN3 is electrically connected to the gate of the fourth N-type transistor MN4 and the fourth bias terminal P4 respectively.

[0097] The source of the fourth N-type transistor MN4 is grounded. The second end of the fourth capacitor C4 is grounded.

[0098] The first end of the third capacitor C3 is electrically connected to the second output control terminal PG2.

[0099] The third bias terminal P4 is used to access the second bias voltage Vn1. The first bias voltage Vn1 provides a bias voltage for the third P-type transistor MP3 and the fourth P-type transistor MP4. The second reference voltage output terminal OUT2 is used to access the reference voltage Vout output by the low-dropout voltage regulator circuit. The second output control terminal PG2 is electrically connected to the gate of the P-type transistor in the low-dropout voltage regulator circuit and is used to couple and transmit the second variation amount to the low-dropout voltage regulator circuit, which will be introduced in detail in combination with the low-dropout voltage regulator circuit later.

[0100] The first resistor R2 and the second capacitor C4 form a low-pass filter network for stabilizing the voltage of the gate of the fourth P-type transistor MP4. The function of the third P-type transistor MP3 is to provide a bias voltage for the fourth P-type transistor MP4. The third N-type transistor MN3 and the fourth N-type transistor MN4 act as current sources and can provide a bias current for the third P-type transistor MP3 and the fourth P-type transistor MP4.

[0101] In the embodiments of the present application, the third P-type transistor MP3, the fourth P-type transistor MP4, the third N-type transistor MN3, and the fourth N-type transistor MN4 can be metal-oxide-semiconductor field effect transistors or gallium nitride transistors, and the embodiments of the present application do not make specific limitations in this regard.

[0102] See Figure 3, the working principle of the transient response enhancement circuit in this application is as follows: When the reference voltage Vout output by the low-dropout regulator circuit remains unchanged, the current between the source and drain of the first P-type transistor MP1 and the second P-type transistor MP2 is equal to the current between the source and drain of the third N-type transistor MN3 and the fourth N-type transistor MN4, the driving signal Pmos_G output by the second output control terminal PG2 remains unchanged, and the reference voltage Vout also remains unchanged; When the reference voltage Vout output by the low-dropout regulator circuit undergoes a downward mutation, that is, when Vout becomes smaller, a first change amount is generated. Since the low-pass filter network composed of the first resistor R1 and the second capacitor C2 stabilizes the voltage of the gate of the first N-type transistor MN1, the influence of the second N-type transistor MN2 on the gate of the first N-type transistor MN1 is reduced, enabling the first N-type transistor MN1 to conduct rapidly when the reference voltage Vout undergoes a downward mutation. The first change amount is coupled to the second output control terminal PG2 through the first capacitor C1, and the driving signal Pmos_G output by the second output control terminal PG2 is transmitted to the gate of the P-type transistor in the low-dropout regulator circuit. At this time, the gate voltage of the P-type transistor undergoes a downward mutation, the on-resistance of the P-type transistor decreases, and the reference voltage Vout rises; When the reference voltage Vout output by the low-dropout regulator circuit undergoes an upward mutation, that is, when Vout becomes larger, a second change amount is generated. Since the low-pass filter network composed of the first resistor R2 and the second capacitor C4 stabilizes the voltage of the gate of the third P-type transistor MP3, the influence of the third P-type transistor MP3 on the gate of the fourth P-type transistor MP4 is reduced, enabling the fourth P-type transistor MP4 to conduct rapidly when the reference voltage Vout undergoes an upward mutation. The second change amount is coupled to the second output control terminal PG2 through the first capacitor C9, and the driving signal Pmos_G output by the second output control terminal PG2 is transmitted to the gate of the P-type transistor in the low-dropout regulator circuit. At this time, the gate voltage of the P-type transistor undergoes an upward mutation, the on-resistance of the P-type transistor increases, and the reference voltage Vout drops.

[0103] The transient response enhancement circuit in the embodiments of the present application has an extremely fast response speed, which can reach within 10 nS (nanoseconds), and can effectively improve the transient response speed of the capacitorless LDO. In addition, since the first P-type transistor MP1 and the second P-type transistor MP2 act as current sources to provide bias current for the first N-type transistor MN1 and the second N-type transistor MN2, and the third N-type transistor MN3 and the fourth N-type transistor MN4 act as current sources to provide bias current for the third P-type transistor MP3 and the fourth P-type transistor MP4, the bias current only needs to satisfy that the third P-type transistor MP3 and the first N-type transistor MN1 are forward-biased and can conduct after the reference voltage Vout changes suddenly. The bias current can be as low as the nA level. Therefore, the transient response enhancement circuit has low power consumption. When working normally, the transient response enhancement circuit has little impact on the power consumption of the low-dropout voltage regulator circuit, and enhances the transient response speed of the capacitorless LDO when the load switches between light load and heavy load.

[0104] In a possible embodiment, refer to Figure 4 , Figure 4 which is a capacitorless low-dropout voltage regulator circuit 1000 provided by the embodiments of the present application. As Figure 4 shown, wherein, the low-dropout voltage regulator circuit 100 includes: a bias circuit 101, an operational amplifier circuit 102, and an output circuit 103.

[0105] The bias circuit 101 is configured to generate a first bias voltage Vp1 and a second bias voltage Vn1, and transmit the first bias voltage Vp1 and the second bias voltage Vn1 to the operational amplifier circuit 102.

[0106] The operational amplifier circuit 102 is configured to compare the feedback voltage VFB with the reference voltage Vref based on the first bias voltage Vp1 and the second bias voltage Vn1 to obtain a drive signal Pmos_G, and transmit the control signal Pmos_G to the output circuit 103.

[0107] The output circuit 103 is configured to output a reference voltage Vout based on the drive signal Pmos_G, divide the reference voltage Vout to obtain a feedback voltage VFB, and transmit the feedback voltage VFB to the operational amplifier circuit 102.

[0108] The low-dropout voltage regulator circuit in the present application will be introduced in detail in subsequent embodiments in combination with the specific circuit connection relationships of each circuit.

[0109] In a possible embodiment, refer to Figure 4, the bias circuit 101 includes: a seventh P-type transistor MP7, an eighth P-type transistor MP8, a fifth N-type transistor MN5, a sixth N-type transistor MN6, a twelfth N-type transistor MN12, a thirteenth N-type transistor MN13, and a fifth resistor R5.

[0110] The source of the seventh P-type transistor MP7 is electrically connected to the source of the eighth P-type transistor MP8 for accessing the input voltage Vdd_ldo. The gate of the seventh P-type transistor MP7 is electrically connected to the drain of the seventh P-type transistor MP7, the drain of the thirteenth N-type transistor MN13, the gate of the eighth P-type transistor MP8, and the first bias terminal P1.

[0111] The drain of the eighth P-type transistor MP8 is electrically connected to the first end of the fifth resistor R5 and the gate of the fifth N-type transistor MN5.

[0112] The source of the fifth N-type transistor MN5 is electrically connected to the drain of the sixth N-type transistor MN6. The drain of the fifth N-type transistor MN5 is electrically connected to the second end of the fifth resistor R5, the gate of the sixth N-type transistor MN6, and the second bias terminal P2.

[0113] The source of the sixth N-type transistor MN6 is grounded.

[0114] The drain of the twelfth N-type transistor MN12 is electrically connected to the gate of the twelfth N-type transistor MN12 and the gate of the thirteenth N-type transistor MN13 for accessing the bias current ibias.

[0115] The source of the twelfth N-type transistor MN12 and the source of the thirteenth N-type transistor MN13 are both grounded.

[0116] The bias current ibias is generated by other current source circuits.

[0117] Among them, the seventh P-type transistor MP7, the eighth P-type transistor MP8, the fifth N-type transistor MN5, the sixth N-type transistor MN6, the twelfth N-type transistor MN12, and the thirteenth N-type transistor MN13 can all be metal-oxide semiconductor field effect transistors or gallium nitride transistors. The embodiments of the present application do not make specific limitations on this.

[0118] In a possible embodiment, refer to Figure 4, the operational amplifier circuit 102 includes: a fifth P-type transistor MP5, a ninth P-type transistor MP9, a tenth P-type transistor MP10, an eleventh P-type transistor MP11, a twelfth P-type transistor MP12, a thirteenth P-type transistor MP13, a fourteenth P-type transistor MP14, a seventh N-type transistor MN7, an eighth N-type transistor MN8, a ninth N-type transistor MN9, a tenth N-type transistor MN10, an eleventh N-type transistor MN11, and a sixth capacitor C6.

[0119] The source of the ninth P-type transistor MP9 is electrically connected to the sources of the twelfth P-type transistor MP12, the thirteenth P-type transistor MP13, and the fourteenth P-type transistor MP14 respectively for accessing the input voltage Vdd_ldo. The drain of the ninth P-type transistor MP9 is electrically connected to the sources of the tenth P-type transistor MP10 and the eleventh P-type transistor MP11 respectively. The gate of the ninth P-type transistor MP9 is electrically connected to the gates of the fourteenth P-type transistor MP14 and the first bias terminal P1 respectively.

[0120] The drain of the tenth P-type transistor MP10 is electrically connected to the source of the ninth N-type transistor MN9, the drain of the tenth N-type transistor MN10, and the first terminal of the sixth capacitor C6 respectively. The gate of the tenth P-type transistor MP10 is used to access the reference voltage Vref.

[0121] The drain of the eleventh P-type transistor MP11 is electrically connected to the source of the seventh N-type transistor MN7 and the drain of the eighth N-type transistor MN8 respectively. The gate of the eleventh P-type transistor MP11 is electrically connected to the output circuit 103.

[0122] The gate of the twelfth P-type transistor MP12 is electrically connected to the drain of the twelfth P-type transistor MP12, the gate of the thirteenth P-type transistor MP13, and the drain of the seventh N-type transistor MN7 respectively.

[0123] The drain of the thirteenth P-type transistor MP13 is electrically connected to the gate of the fifth P-type transistor MP5 and the drain of the ninth N-type transistor MN9 respectively.

[0124] The drain of the fourteenth P-type transistor MP14 is electrically connected to the source of the fifth P-type transistor MP5 and the first output control terminal PG1 respectively.

[0125] The drain of the fifth P-type transistor MP5 is electrically connected to the drain of the eleventh N-type transistor MN11.

[0126] The gate of the seventh N-type transistor MN7 is electrically connected to the gates of the ninth N-type transistor MN9 and the fifth N-type transistor MN5 respectively.

[0127] The gates of the eighth N-type transistor MN8 are electrically connected to the second bias terminal P2, the gate of the tenth N-type transistor MN10, and the gate of the eleventh N-type transistor MN11 respectively.

[0128] The sources of the eighth N-type transistor MN8, the tenth N-type transistor MN10, and the eleventh N-type transistor MN11 are all grounded.

[0129] The second terminal of the sixth capacitor C6 is electrically connected to the output circuit 103.

[0130] Among them, the fifth P-type transistor MP5, the ninth P-type transistor MP9, the tenth P-type transistor MP10, the eleventh P-type transistor MP11, the twelfth P-type transistor MP12, the thirteenth P-type transistor MP13, the fourteenth P-type transistor MP14, the seventh N-type transistor MN7, the eighth N-type transistor MN8, the ninth N-type transistor MN9, the tenth N-type transistor MN10, and the eleventh N-type transistor MN11 can all be metal-oxide semiconductor field effect transistors or gallium nitride transistors, and the embodiments of the present application do not make specific limitations in this regard.

[0131] In a possible embodiment, referring to Figure 4 , the output circuit 103 includes: a sixth P-type transistor MP6, a third resistor R3, a fourth resistor R4, and a fifth capacitor C5.

[0132] The source of the sixth P-type transistor MP6 is used to access the input voltage Vdd_ldo. The gate of the sixth P-type transistor MP6 is electrically connected to the first output control terminal PG1. The drain of the sixth P-type transistor MP6 is electrically connected to the second terminal of the sixth capacitor C6, the first end of the third resistor R3, the first end of the fifth capacitor C5, and the first reference voltage output terminal OUT1 respectively. The first reference voltage output terminal OUT1 outputs the reference voltage Vout.

[0133] The second end of the third resistor R3 is electrically connected to the first end of the fourth resistor R4 and the gate of the eleventh P-type transistor MP11 respectively.

[0134] The second ends of the fourth resistor R4 and the fifth capacitor C5 are both grounded.

[0135] The connection point between the second end of the third resistor R3 and the first end of the fourth resistor R4 is used as the feedback voltage terminal, and the output feedback voltage VFB is sent to the gate of the eleventh P-type transistor MP11 in the operational amplifier circuit to provide a negative feedback loop.

[0136] Among them, the sixth P-type transistor MP6 can be a metal-oxide semiconductor field effect transistor or a gallium nitride transistor, and the embodiments of the present application do not make specific limitations in this regard.

[0137] See Figure 4 In the low dropout regulator circuit of the present application, the twelfth N-type transistor MN12, the thirteenth N-type transistor MN13, the seventh P-type transistor MP7, the eighth P-type transistor MP8, the fifth N-type transistor MN5, and the sixth N-type transistor MN6 together constitute a bias circuit. By mirroring the bias current ibias, a bias voltage is generated to provide bias voltages for the various transistors in the low dropout regulator circuit. The seventh N-type transistor MN7, the eighth N-type transistor MN8, the ninth N-type transistor MN9, the tenth N-type transistor MN10, the twelfth P-type transistor MP12, the thirteenth P-type transistor MP13, the tenth P-type transistor MP10, the eleventh P-type transistor MP11, the fourteenth P-type transistor MP14, the fifth P-type transistor MP5, and the eleventh N-type transistor MN11 together constitute a multi-stage operational amplifier. Among them, the tenth P-type transistor MP10 and the eleventh P-type transistor MP11 are the input stage of the operational amplifier. The gate of the tenth P-type transistor MP10 is the inverting input terminal of the operational amplifier, and the gate of the eleventh P-type transistor MP11 is the non-inverting input terminal of the operational amplifier. The seventh N-type transistor MN7, the eighth N-type transistor MN8, the ninth N-type transistor MN9, the tenth N-type transistor MN10, the twelfth P-type transistor MP12, and the thirteenth P-type transistor MP13 together constitute the first output stage of the folded cascode telescopic operational amplifier. The fourteenth P-type transistor MP14, the fifteenth P-type transistor MP15, and the eleventh N-type transistor MN11 together constitute the second output stage of the operational amplifier. Through the second output stage, the output terminal of the operational amplifier can be separated from the gate of the sixth P-type transistor MP6, and at the same time, the driving ability of the gate of the sixth P-type transistor MP6 is enhanced, and the response time is reduced. In addition, the sixth P-type transistor MP16, the third resistor R3, and the fourth resistor R4 together constitute the output stage of the low dropout regulator circuit. The third resistor R3 and the fourth resistor R4 are voltage-dividing resistors. The middle node of the third resistor R3 and the fourth resistor R4 is electrically connected to the gate of the eleventh P-type transistor MP11 to form a negative feedback loop. The sixth capacitor C6 is a compensation capacitor, and the fifth capacitor C5 is an output voltage stabilizing capacitor.

[0138] The working principle of the low dropout regulator circuit is as follows: The reference voltage Vout is collected at the gate of the eleventh P-type transistor MP11 through the feedback resistors (i.e., the third resistor R3 and the fourth resistor R4), and compared with the reference voltage Vref. The sixth P-type transistor MP6 is controlled through the operational amplifier circuit to adjust the reference voltage Vout to form a negative feedback loop.

[0139] The low-dropout regulator circuit without external capacitors provided by the present application can introduce the transient change of the reference voltage Vout to the gate of the sixth P-type transistor MP6 quickly through the transient response enhancement circuit introduced between the gate of the sixth P-type transistor MP6 and the first reference voltage output terminal OUT, so as to adjust the reference voltage Vout and reduce the sudden change of the output voltage. Specifically, when the reference voltage Vout undergoes a downward sudden change, a first change amount is generated, and the first change amount is quickly transmitted to the gate of the sixth P-type transistor MP6 through the transient response enhancement circuit. The gate voltage of the sixth P-type transistor MP6 undergoes a downward sudden change, the on-resistance of the sixth P-type transistor MP6 decreases, and the reference voltage Vout rises; when the reference voltage Vout undergoes an upward sudden change, a second change amount is generated, and the second change amount is quickly transmitted to the gate of the sixth P-type transistor MP6 through the transient response enhancement circuit. The gate voltage of the sixth P-type transistor MP6 undergoes an upward sudden change, the on-resistance of the sixth P-type transistor MP6 increases, and the reference voltage Vout decreases. The transient response enhancement circuit in the embodiment of the present application has an extremely fast response speed, which can reach within 10 nS (nanoseconds), and can effectively improve the transient response speed of the LDO without external capacitors.

[0140] The embodiment of the present application also provides a chip, including the low-dropout regulator circuit without external capacitors as described above.

[0141] Among them, the chip can be an LDO without external capacitors, which is used to convert the input voltage into an output voltage and provide a stable DC voltage power supply. The LDO chip without external capacitors can convert the input voltage into a reference voltage. In one example, the LDO chip without external capacitors can convert 5 VDC into 3.3 VDC.

[0142] The embodiment of the present application also provides an electronic device, including the chip as described above.

[0143] In the present application, the electronic device may include, but is not limited to: adapters, chargers, tablet computers, smart home devices, vehicles, and wearable devices.

[0144] Finally, it should be noted that the above embodiments are only specific implementation manners of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present application should be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A low voltage dropout voltage stabilizing circuit without external capacitor, characterized in that: The low voltage difference voltage stabilizing circuit without off-chip capacitor comprises: a low voltage difference voltage stabilizing circuit and a transient response enhancement circuit, wherein the low voltage difference voltage stabilizing circuit comprises a first bias terminal, a second bias terminal, a first reference voltage output terminal and a first output control terminal, and the transient response enhancement circuit comprises a third bias terminal, a fourth bias terminal, a second reference voltage output terminal and a second output control terminal; The first bias terminal is electrically connected to the third bias terminal, the second bias terminal is electrically connected to the fourth bias terminal, the first reference voltage output terminal is electrically connected to the second reference voltage output terminal, and the first output control terminal is electrically connected to the second output control terminal; The low voltage difference voltage stabilizing circuit is used to generate a first bias voltage and a second bias voltage, and transmit the first bias voltage to the transient response enhancement circuit based on the third bias terminal through the first bias terminal, and transmit the second bias voltage to the transient response enhancement circuit based on the fourth bias terminal through the second bias terminal; and is also used to transmit the reference voltage output by itself to the transient response enhancement circuit based on the second reference voltage output terminal through the first reference voltage output terminal; The transient response enhancement circuit is used to receive the first bias voltage, the second bias voltage and the reference voltage, and when the reference voltage changes, the change amount is coupled to the low voltage difference voltage regulator circuit based on the second output control terminal and the first output control terminal, so that the low voltage difference voltage regulator circuit adjusts the reference voltage output by itself based on the change amount.

2. The low voltage dropout voltage stabilizing circuit without external capacitor according to claim 1, characterized in that: The transient response enhancement circuit comprises: a first response enhancement circuit and a second response enhancement circuit; When the reference voltage changes, a first change amount and a second change amount are generated; The first response enhancement circuit is used to receive the first bias voltage and couple the first variation to the second output control terminal, so that the low voltage difference voltage stabilization circuit adjusts the reference voltage outputted by itself based on the first variation; The second response enhancement circuit is used to receive the second bias voltage and couple the second variation to the second output control terminal, so that the low voltage difference voltage regulator circuit adjusts the reference voltage outputted by itself based on the second variation.

3. The low voltage dropout voltage stabilizing circuit without external capacitor according to claim 2, characterized in that: The first response enhancement circuit includes: a first P-type transistor, a second P-type transistor, a first N-type transistor, a second N-type transistor, a first resistor, a first capacitor and a second capacitor; The source of the first P-type transistor is electrically connected to the source of the second P-type transistor for receiving an input voltage, the gate of the first P-type transistor is electrically connected to the gate of the second P-type transistor and the third bias terminal, and the drain of the first P-type transistor is electrically connected to the drain of the first N-type transistor and the first terminal of the first capacitor; The drain of the second P-type transistor is electrically connected to the drain of the second N-type transistor, the gate of the second N-type transistor, and the second end of the first resistor respectively; The source of the first N-type transistor is electrically connected to the source of the second N-type transistor and the second reference voltage output terminal respectively, and the gate of the first N-type transistor is electrically connected to the first end of the first resistor and the first end of the second capacitor respectively; The second end of the first capacitor is electrically connected to the second output control end; The second terminal of the second capacitor is grounded.

4. The low voltage dropout voltage stabilizing circuit without external capacitor according to claim 2, characterized in that: The second response enhancement circuit includes: a third P-type transistor, a fourth P-type transistor, a third N-type transistor, a fourth N-type transistor, a second resistor, a third capacitor, and a fourth capacitor; The source of the third P-type transistor is electrically connected to the source of the fourth P-type transistor and the second reference voltage output terminal respectively, and the gate of the third P-type transistor is electrically connected to the drain of the third P-type transistor, the drain of the third N-type transistor, and the first end of the second resistor respectively; The gate of the fourth P-type transistor is electrically connected to the second end of the second resistor and the first end of the fourth capacitor, and the drain of the fourth P-type transistor is electrically connected to the drain of the fourth N-type transistor and the second end of the third capacitor; The source of the third N-type transistor is grounded, and the gate of the third N-type transistor is electrically connected to the gate of the fourth N-type transistor and the fourth bias terminal respectively; The source of the fourth N-type transistor is grounded, and the second end of the fourth capacitor is grounded; The first end of the third capacitor is electrically connected to the second output control end.

5. The low voltage dropout voltage stabilizing circuit without external capacitor according to claim 1, characterized in that: The low voltage difference voltage stabilizing circuit comprises: a bias circuit, an operational amplifier circuit and an output circuit; The bias circuit is used to generate the first bias voltage and the second bias voltage, and transmit the first bias voltage and the second bias voltage to the operational amplifier circuit; The operational amplifier circuit is used to compare the feedback voltage with a reference voltage based on the first bias voltage and the second bias voltage to obtain a drive signal, and transmit the drive signal to the output circuit; The output circuit is used to output the reference voltage based on the driving signal, divide the reference voltage to obtain the feedback voltage, and transmit the feedback voltage to the operational amplifier circuit.

6. The low voltage dropout voltage stabilizing circuit without external capacitor according to claim 5, characterized in that: The bias circuit includes: a seventh P-type transistor, an eighth P-type transistor, a fifth N-type transistor, a sixth N-type transistor, a twelfth N-type transistor, a thirteenth N-type transistor and a fifth resistor; The source of the seventh P-type transistor is electrically connected to the source of the eighth P-type transistor for receiving an input voltage, and the gate of the seventh P-type transistor is electrically connected to the drain of the seventh P-type transistor, the drain of the thirteenth N-type transistor, the gate of the eighth P-type transistor, and the first bias terminal respectively; The drain of the eighth P-type transistor is electrically connected to the first end of the fifth resistor and the gate of the fifth N-type transistor respectively; The source of the fifth N-type transistor is electrically connected to the drain of the sixth N-type transistor, and the drain of the fifth N-type transistor is electrically connected to the second end of the fifth resistor, the gate of the sixth N-type transistor, and the second bias end respectively; The source of the sixth N-type transistor is grounded; The drain of the twelfth N-type transistor is electrically connected to the gate of the twelfth N-type transistor and the gate of the thirteenth N-type transistor respectively, and is used to access the bias current; A source of the twelfth N-type transistor and a source of the thirteenth N-type transistor are both grounded.

7. The low voltage dropout voltage stabilizing circuit without external capacitor according to claim 6, characterized in that: The operational amplifier circuit includes: a fifth P-type transistor, a ninth P-type transistor, a tenth P-type transistor, an eleventh P-type transistor, a twelfth P-type transistor, a thirteenth P-type transistor, a fourteenth P-type transistor, a seventh N-type transistor, an eighth N-type transistor, a ninth N-type transistor, a tenth N-type transistor, an eleventh N-type transistor and a sixth capacitor; The source of the ninth P-type transistor is electrically connected to the source of the twelfth P-type transistor, the source of the thirteenth P-type transistor, and the source of the fourteenth P-type transistor, respectively, for receiving the input voltage, the drain of the ninth P-type transistor is electrically connected to the source of the tenth P-type transistor and the source of the eleventh P-type transistor, respectively, and the gate of the ninth P-type transistor is electrically connected to the gate of the fourteenth P-type transistor and the first bias terminal, respectively; The drain of the tenth P-type transistor is electrically connected to the source of the ninth N-type transistor, the drain of the tenth N-type transistor, and the first end of the sixth capacitor, respectively, and the gate of the tenth P-type transistor is used to access the reference voltage; The drain of the eleventh P-type transistor is electrically connected to the source of the seventh N-type transistor and the drain of the eighth N-type transistor respectively, and the gate of the eleventh P-type transistor is electrically connected to the output circuit; The gate of the twelfth P-type transistor is electrically connected to the drain of the twelfth P-type transistor, the gate of the thirteenth P-type transistor, and the drain of the seventh N-type transistor respectively; The drain of the thirteenth P-type transistor is electrically connected to the gate of the fifth P-type transistor and the drain of the ninth N-type transistor respectively; The drain of the fourteenth P-type transistor is electrically connected to the source of the fifth P-type transistor and the first output control terminal respectively; The drain of the fifth P-type transistor is electrically connected to the drain of the eleventh N-type transistor; The gate of the seventh N-type transistor is electrically connected to the gate of the ninth N-type transistor and the gate of the fifth N-type transistor respectively; The gate of the eighth N-type transistor is electrically connected to the second bias terminal, the gate of the tenth N-type transistor, and the gate of the eleventh N-type transistor respectively; The source of the eighth N-type transistor, the source of the tenth N-type transistor, and the source of the eleventh N-type transistor are all grounded; The second end of the sixth capacitor is electrically connected to the output circuit.

8. The low voltage dropout voltage stabilizing circuit without external capacitor according to claim 7, characterized in that: The output circuit includes: a sixth P-type transistor, a third resistor, a fourth resistor and a fifth capacitor; The source of the sixth P-type transistor is used to access the input voltage, the gate of the sixth P-type transistor is electrically connected to the first output control terminal, the drain of the sixth P-type transistor is electrically connected to the second end of the sixth capacitor, the first end of the third resistor, the first end of the fifth capacitor, and the first reference voltage output terminal, respectively, and the first reference voltage output terminal outputs the reference voltage; The second end of the third resistor is electrically connected to the first end of the fourth resistor and the gate of the eleventh P-type transistor respectively; The second end of the fourth resistor and the second end of the fifth capacitor are both grounded.

9. A chip, characterized in that: include: A low voltage dropout voltage stabilizing circuit without external capacitor as claimed in any one of claims 1 to 8.

10. An electronic device, characterized in that: include: The chip as claimed in claim 9.

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