A Combinatorial Equivalence Verification Method Based on Intelligent Engine Selection

Abstract

The present invention discloses a combined equivalence verification method based on intelligent engine selection. This method constructs a random simulation of the Miter circuit, extracts embedding vectors and splices them into an image, which is then input into the trained AlexNet network. The optimal scan engine is predicted to perform equivalence verification on candidate equivalent node pairs. After all candidate equivalent node pairs are verified and merged, the SAT solver is used for the final equivalence verification. This method can achieve efficient and adaptive optimal scan engine selection, showing significant advantages when dealing with circuits with high XOR density, with a greatly improved processing speed, and can significantly improve the verification efficiency and accuracy of the equivalence verification of two circuits. The present invention provides a new research idea for the design of combined equivalence verification tools, can significantly reduce the solving time, improve the stability and adaptability of the solution, and has important practical significance for the application in the field of logic synthesis and the development of equivalence verification tools.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a combination equivalence verification method based on intelligent engine selection. Background Art

[0002] Combinational Equivalence Checking (CEC) is a key technology for formally proving whether two designs are functionally equivalent. It is widely used in Electronic Design Automation (EDA) and digital integrated circuit (IC) design. CEC runs through the entire EDA process, from high-level design inputs such as register transfer level (RTL) to silicon wafer manufacturing. Its core purpose is to verify whether circuits at different design stages maintain functional equivalence, such as performing equivalence checks between RTL and netlist.

[0003] Currently, most combinatorial CEC algorithms create a "miter" circuit by connecting the inputs and outputs of the two circuits being compared. If the output of the miter circuit is 0, it indicates that the two designs are functionally equivalent. The miter circuit can be treated as a single entity, and its output values can be verified using a boolean satisfiability (SAT) solver or a binary decision diagram (BDD) solver. However, as the circuit size increases, the memory usage and computation time grow nonlinearly, making it difficult for the solver to handle. To address this issue, circuit scanning techniques are used to merge potentially equivalent internal nodes, thereby reducing the size of the overall circuit. First, potentially equivalent pairs of internal nodes are identified through random simulation. Then, the scanning engine checks the equivalence of each pair of nodes and merges the equivalent nodes after verification.

[0004] Typically, scan engines include BDD scan, SAT scan, and simulation. The efficiency of these engines depends on the structure of the circuit. In circuits with dense XOR chains (such as datapath circuits containing multipliers, adders, and multiplexers), SAT solvers are often challenged, while exact probability-based simulation (EPS) and BDD scans are more effective. Hybrid-CEC is one of the most advanced CEC tools, which uses SAT scans in circuits with low XOR density and EPS in small-scale, high-XOR density circuits. However, it is not suitable for medium-sized circuits with high XOR density, and there is a lack of appropriate scheduling methods for these scan engines, which needs further research and optimization. Summary of the Invention

[0005] The object of the present invention is to provide a combined equivalence verification method based on intelligent engine selection, aiming to solve the problems in the prior art such as insufficient engine selection in combined equivalence verification (CEC), limited adaptability to specific circuit structures, and low efficiency in processing medium-scale and high-XOR density circuits. The method of the present invention can realize efficient and adaptive optimal scan engine selection according to the specific characteristics of the two circuits to be verified for equivalence, showing significant advantages when dealing with high-XOR density circuits, greatly improving the processing speed, and significantly improving the verification efficiency and accuracy of the equivalence verification of the two circuits.

[0006] The technical solution adopted by the present invention to solve the above technical problems is: a combined equivalence verification method based on intelligent engine selection. First, construct the two circuits to be verified for equivalence into a Miter circuit and represent it in AIG format. Then, perform random simulation on the Miter circuit to identify potential equivalent node pairs. Next, extract the embedding vectors of the function and structure of each pair of candidate equivalent node pairs. After splicing the extracted embedding vectors into an image, input it into the trained AlexNet network. The optimal scan engine is predicted by the trained AlexNet network. Use the optimal scan engine to verify the equivalence of the candidate equivalent node pairs, and merge the candidate equivalent node pairs that are verified to be equivalent. After all candidate equivalent node pairs are verified and merged, use a SAT solver to perform the final equivalence verification on the Miter circuit.

[0007] Preferably, the combined equivalence verification method based on intelligent engine selection of the present invention specifically includes the following steps:

[0008] Step 1: Construct the two circuits to be verified for equivalence into a Miter circuit and represent it in AIG format;

[0009] Step 2: Perform random simulation on the Miter circuit, identify potential equivalent node pairs and classify them as candidate equivalent node pairs to obtain a candidate equivalent set, and enter Step 3; if a counterexample is found in the random simulation, it is determined that the two circuits are not equivalent, and the verification process is terminated;

[0010] Step 3: Input the candidate equivalent node pairs in the candidate equivalent set into a circuit characterization learning tool to extract the embedding vectors of the function and structure of each pair of candidate equivalent node pairs;

[0011] Step 4: Adjust the first layer of the existing AlexNet network from a three-channel convolutional layer to a single-channel convolutional layer, train the adjusted AlexNet network to obtain the trained AlexNet network; splice the extracted embedding vectors into an image and input it into the trained AlexNet network, and use the trained AlexNet network to predict the optimal scan engine based on the spliced embedding vectors. Verify the equivalence of the candidate equivalent node pairs through the optimal scan engine. If the candidate equivalent node pairs are verified to be equivalent, merge them;

[0012] Step 5: After all candidate equivalent node pairs are verified and merged, use a SAT solver to perform a final equivalence verification on the Miter circuit. If the verification result is SAT, it means that the two circuits are not equivalent; if the verification result is UNSAT, it means that the two circuits are equivalent.

[0013] Preferably, in the random simulation of Step 2, a set of random values is assigned to the input ports of the Miter circuit, and these random values are propagated to the output ports of the Miter circuit. Record and compare the logical behaviors of different internal nodes to identify potential equivalent node pairs.

[0014] Preferably, in Step 3, the circuit characterization learning tool is the DeepGate2 tool. DeepGate2 is a known circuit characterization learning tool based on deep learning, which is specifically used to extract the functional and structural features of nodes or sub-circuits from digital logic circuits. It analyzes the circuit through a neural network model to generate embedding vectors that can characterize the logical behavior and topological structure of the circuit. These vectors can be used for various EDA downstream tasks, such as equivalence verification, logic optimization, and fault diagnosis.

[0015] Preferably, in Step 4, the process of training the adjusted AlexNet network is as follows: Use the EPS, SAT, and BDD scan engines as candidate scan engines, represent the labels corresponding to the candidate scan engines using one-hot encoding, and test whether the two candidate equivalent nodes in each pair of candidate equivalent node pairs are equivalent through the EPS, SAT, and BDD scan engines respectively. Select the label corresponding to the scan engine with the shortest test time as the measured optimal scan engine label; splice the embedding vectors of each pair of candidate equivalent node pairs into an image, and use the spliced embedding vectors and the measured optimal scan engine label as training data. Use 80% of the training data as the training set, 10% of the training data as the validation set, and the remaining 10% of the training data as the test set to train the adjusted AlexNet network to obtain the trained AlexNet network.

[0016] The embedded vectors are concatenated into an image. This concatenation method preserves the structural and functional relationships between nodes, enabling the AlexNet network to learn meaningful representations and perform classification. To adapt to the input form of the embedded vectors, the first layer of the AlexNet network in the present invention is adjusted. The original three-channel convolutional layer is adjusted to a single-channel convolutional layer. This adjustment enables the AlexNet network to process the concatenated embedded vectors as a single-channel image and use it as a classifier. The present invention uses three scanning engines, namely EPS, SAT, and BDD, as candidate scanning engines, represents the labels corresponding to the candidate scanning engines using one-hot encoding, and tests each pair of candidate equivalent node pairs. This method can dynamically predict the optimal scanning engine based on the characteristics of each pair of candidate equivalent node pairs, thereby improving the efficiency and accuracy of equivalence verification.

[0017] Compared with the prior art, the present invention has the following advantages: The combined equivalence verification method based on intelligent engine selection in the present invention is a machine learning-based adaptive engine selection method, aiming to solve problems in the prior art such as insufficient engine selection in combined equivalence verification (CEC), limited adaptability to specific circuit structures, and low efficiency in processing medium-scale and high-XOR density circuits. The method of the present invention can achieve efficient and adaptive optimal scanning engine selection according to the specific characteristics of the two circuits to be verified for equivalence. When processing high-XOR density circuits, it shows significant advantages, with a substantial increase in processing speed, and can significantly improve the verification efficiency and accuracy of the equivalence verification of the two circuits. The present invention provides a new research idea for the design of combined equivalence verification tools, which can not only significantly reduce the solution time but also improve the stability and adaptability of the solution, and has important practical significance for the application in the field of logic synthesis and the development of equivalence verification tools. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 Schematic diagram of the Miter circuit in the embodiment;

[0019] Figure 2 Schematic diagram of an AIG;

[0020] Figure 3 Schematic diagram of the core content of steps 2 to 4 in the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0021] The present invention will be further described in detail below in conjunction with the embodiments of the drawings.

[0022] Embodiment: The method of the present invention is used to Figure 1 perform equivalence verification on the Figure 1 circuit shown. As shown in (A) of Figure 1 , there are Circuit 1 and Circuit 2, and as shown in (B) of Figure 1Among them, p is the output of Circuit 1, q is the output of Circuit 2, a and b are the inputs of Circuit 1 and Circuit 2, and z is the output of the XOR gate with p and q as inputs. For Figure 1 The method for verifying the equivalence of the shown circuit specifically includes the following steps:

[0023] Step 1: Construct the Miter circuit for the two circuits (i.e., Circuit 1 and Circuit 2) whose equivalence is to be verified. As shown in (B) of Figure 1 Connect the two circuits through an XOR gate to form a Miter circuit, and represent the Miter circuit in AIG format. AIG is a special directed acyclic graph, often used to represent digital logic circuits. In AIG, each node has two inputs, representing an AND gate, and the directed edges with inverters are used to connect these nodes, thus forming a logically complete Boolean function. Figure 2 shows a schematic diagram of an AIG, which includes three primary inputs a, b, c, two primary outputs p0, p1, and six AND gate nodes AND. The solid black lines with arrows represent the signal transmission paths, and the dashed black lines with arrows represent the edges with inverters.

[0024] Step 2: Perform random simulation on the Miter circuit. By assigning a set of random values to the input ports of the Miter circuit and propagating these random values to the output ports of the Miter circuit. During this process, record the logical behavior of each internal node, including its output value and state changes. By comparing the logical behaviors of different internal nodes, identify potential equivalent node pairs, that is, those node pairs with the same output results in multiple random simulations, and classify these potential equivalent node pairs as candidate equivalent node pairs to obtain a candidate equivalent set, and then enter Step 3; if it is found in multiple random simulations that the output results of a certain node pair are inconsistent, that is, there is a counterexample, then it is determined that the two circuits are not equivalent, and the verification process is terminated.

[0025] Step 3: Input the candidate equivalent node pairs in the candidate equivalent set into the circuit representation learning tool DeepGate2 to extract the embedding vectors of the function and structure of each pair of candidate equivalent node pairs. This embedding vector can comprehensively represent the logical behavior and circuit structure characteristics of the candidate equivalent node pairs.

[0026] Step 4: Adjust the first layer of the existing AlexNet network from a three-channel convolutional layer to a single-channel convolutional layer, and then train the adjusted AlexNet network. The process is as follows: Use three scanning engines, namely EPS, SAT (specifically Kissat in this embodiment), and BDD, as candidate scanning engines. Represent the labels corresponding to the three candidate scanning engines EPS, SAT, and BDD with one-hot encodings [1, 0, 0], [0, 0, 1], and [0, 1, 0] respectively. Test whether the two candidate equivalent nodes in each pair of candidate equivalent node pairs are equivalent through the three scanning engines EPS, SAT, and BDD respectively, and select the label corresponding to the scanning engine with the shortest test time as the measured optimal scanning engine label. For example, if the adjusted AlexNet network outputs [0, 0, 1], it indicates that for the tested candidate equivalent node pair, the SAT scanning engine is the predicted optimal scanning engine. This method enables the adjusted AlexNet network to dynamically predict the optimal scanning engine according to the characteristics of the node pair, thereby improving the efficiency and accuracy of equivalence verification; Concatenate the embedding vectors of each pair of candidate equivalent node pairs into an image, and use the concatenated embedding vector and its measured optimal scanning engine label as training data. Use 80% of the training data as the training set, 10% of the training data as the validation set, and the remaining 10% of the training data as the test set to train the adjusted AlexNet network to obtain the trained AlexNet network; Concatenate the extracted embedding vectors into an image, input the concatenated embedding vector into the trained AlexNet network, and the trained AlexNet network predicts the optimal scanning engine based on the concatenated embedding vector. The optimal scanning engine performs equivalence verification on the candidate equivalent node pair. If the candidate equivalent node pair is verified to be equivalent, merge it to reduce the redundant structure of the circuit.

[0027] The schematic diagrams of the core content of the above Steps 2 to 4 are as Figure 3 shown. Figure 3 In the figure, the solid blue circles represent candidate equivalent nodes, the hollow circles represent the nodes around the candidate equivalent nodes, "Node 1" and "Node 2" represent the two candidate equivalent nodes in a pair of candidate equivalent node pairs, the solid blue rectangle represents the concatenated embedding vector, and the numbers in the brackets represent one-hot encodings.

[0028] Step 5: After all candidate equivalent node pairs are verified and merged, use the SAT solver to perform the final equivalence verification on the Miter circuit to ensure the correctness and completeness of the verification result. If the verification result is SAT, it means that the two circuits are not equivalent; if the verification result is UNSAT, it means that the two circuits are equivalent.

[0029] We compared Auto-CEC (the abbreviation of the method of the present invention) with the &cec command in the ABC tool and Hybrid-CEC. The results are shown in Table 1. The solution time of Auto-CEC was successfully accelerated by 11.29 times compared with Hybrid-CEC, and it can solve instances that &cec cannot solve. When dealing with circuits with high XOR density, the method of the present invention significantly improves the verification efficiency and accuracy of the equivalence verification of two circuits.

[0030] All of the above experiments were conducted in a system equipped with an 11th generation Intel(R) Core(TM) i5-1155G7 CPU @ 2.50GHz and 8GB of memory, and the operating system was Ubuntu 20.04 LTS (64-bit). The benchmark test sets used in the experiments included industrial test cases and several modified combinational circuits. All circuits were represented in AIG format and consisted of Miter circuits formed by connecting two potentially equivalent circuits. Among them, the dp circuit is a typical data path circuit containing a multiply-accumulate mixed operation unit, the ec circuit is a hybrid circuit composed of the dp circuit and fewer arithmetic units, and the equ and TOP circuits are arithmetic circuits with fewer equivalent nodes.

[0031] Table 1

[0032]

[0033] In summary, the combinational equivalence verification method based on intelligent engine selection proposed in the present invention significantly improves the solution efficiency and optimizes the intelligence of engine selection. By introducing the intelligent engine selection method, the Auto-CEC method of the present invention not only makes up for the deficiencies of Hybrid-CEC in specific scenarios but also achieves a significant performance improvement in most test cases, with an acceleration ratio of up to 11.29 times. The present invention provides a new research idea for the design of combinational equivalence verification tools, which can not only significantly reduce the solution time but also improve the stability and adaptability of the solution, and has important practical significance for the application in the field of logic synthesis and the development of equivalence verification tools.

Claims

1. A combined equivalence verification method based on intelligent engine selection, characterized in that, First, construct two circuits whose equivalence is to be verified into a Miter circuit and represent it in AIG format. Then, perform random simulation on the Miter circuit to identify potential equivalent node pairs. Next, extract the embedded vectors of the function and structure of each pair of candidate equivalent node pairs. Concatenate the extracted embedded vectors into an image and input it into the trained AlexNet network. The optimal scan engine is predicted by the trained AlexNet network. Verify the equivalence of the candidate equivalent node pairs through the optimal scan engine, and merge the candidate equivalent node pairs that are verified to be equivalent. After all candidate equivalent node pairs are verified and merged, use a SAT solver to perform the final equivalence verification on the Miter circuit. The method specifically includes the following steps: Step 1: Construct two circuits whose equivalence is to be verified into a Miter circuit and represent it in AIG format; Step 2: Perform random simulation on the Miter circuit, identify potential equivalent node pairs and classify them as candidate equivalent node pairs to obtain a candidate equivalent set, and then proceed to Step 3. If a counterexample is found in the random simulation, it is determined that the two circuits are not equivalent, and the verification process is terminated; Step 3: Input the candidate equivalent node pairs in the candidate equivalent set into a circuit representation learning tool to extract the embedded vectors of the function and structure of each pair of candidate equivalent node pairs; Step 4: Adjust the first layer of the existing AlexNet network from a three-channel convolutional layer to a single-channel convolutional layer, train the adjusted AlexNet network to obtain a trained AlexNet network. Concatenate the extracted embedded vectors into an image and input it into the trained AlexNet network. The optimal scan engine is predicted by the trained AlexNet network based on the concatenated embedded vectors. Verify the equivalence of the candidate equivalent node pairs through the optimal scan engine. If a candidate equivalent node pair is verified to be equivalent, merge it; Step 5: After all candidate equivalent node pairs are verified and merged, use a SAT solver to perform the final equivalence verification on the Miter circuit. If the verification result is SAT, it indicates that the two circuits are not equivalent; if the verification result is UNSAT, it indicates that the two circuits are equivalent.

2. The combination equivalence verification method based on intelligent engine selection according to claim 1, wherein In the random simulation of Step 2, by assigning a set of random values to the input ports of the Miter circuit and propagating these random values to the output ports of the Miter circuit, record and compare the logical behaviors of different internal nodes to identify potential equivalent node pairs.

3. The combination equivalence verification method based on intelligent engine selection according to claim 1, characterized in that In Step 3, the circuit representation learning tool is the DeepGate2 tool.

4. The method for verifying combinatorial equivalence based on intelligent engine selection according to claim 1, characterized in that, In step 4, the process of training the adjusted AlexNet network is as follows: Use the three scanning engines EPS, SAT, and BDD as candidate scanning engines, represent the labels corresponding to the candidate scanning engines using one-hot encoding, and test whether the two candidate equivalent nodes in each pair of candidate equivalent node pairs are equivalent through the three scanning engines EPS, SAT, and BDD respectively. Select the label corresponding to the scanning engine with the shortest test time as the measured optimal scanning engine label; Concatenate the embedding vectors of each pair of candidate equivalent node pairs into an image, and use the concatenated embedding vectors and the measured optimal scanning engine label as training data. Use 80% of the training data as the training set, 10% of the training data as the validation set, and the remaining 10% of the training data as the test set to train the adjusted AlexNet network to obtain the trained AlexNet network.

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