Semiconductor device thermal annealing process optimization method, resistance prediction method and system thereof

Abstract

The invention discloses a semiconductor device thermal annealing process optimization method, a resistance prediction method and a system thereof. According to the method, correction indexes in the thermal budget model and reference thermal budget parameters in the activation rate model are dynamically corrected through matching deviation minimization, so that the model can adapt to different thermal annealing conditions. The thermal annealing process parameters can be directly adjusted through real-time comparison of the correction activation rate and the target value. And finally, resistance prediction is realized by fusing a physical model (a thermal budget correction model and an activation rate correction model) and a data driving method, so that the calculation complexity and the time cost of traditional pure physical simulation are remarkably reduced, and the dependence of a traditional machine learning model on a large-scale data set is overcome. The bottleneck of a traditional method in the aspects of efficiency, cost, precision and generalization is solved, and an efficient, low-cost and high-reliability process optimization and performance prediction scheme is provided for advanced semiconductor manufacturing.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor device fabrication, and particularly relates to a method for optimizing a thermal annealing process of a semiconductor device, a method for predicting resistance, and a system thereof. Background Art

[0002] In the field of semiconductor device manufacturing, the performance and reliability of silicon-based semiconductor devices largely depend on the activation degree and distribution of doped impurities. Among them, the thermal annealing process, as an important process step for doping impurity activation and lattice damage repair, plays a decisive role in the final performance of the device. Traditional thermal annealing process parameters (such as annealing temperature, time, heating and cooling rates, etc.) are usually determined based on experience or a single-variable regulation method, resulting in problems such as insufficient impurity activation, residual lattice damage, and unstable electrical performance of the device in the actual production process. In addition, due to the non-linear and multi-variable coupling characteristics of the relationship between process parameters and device electrical performance, traditional prediction methods based on empirical formulas or single physical models cannot accurately predict the resistance characteristics of the doped region, limiting the precision and efficiency of semiconductor device manufacturing.

[0003] Traditionally, the optimization of the thermal annealing process of doped semiconductors and the determination of resistance usually rely on classical semiconductor process simulations (such as TCAD simulations) or directly conduct a large number of experimental tests. Although these methods can provide results with a certain degree of accuracy, they also have obvious deficiencies: physical simulation has a large computational complexity, a long computational time, and it is difficult to simulate the real process situation, resulting in a low simulation accuracy; while the experimental measurement method, although highly reliable, is costly and time-consuming, seriously restricting the efficiency and cost-effectiveness of device process optimization.

[0004] In recent years, with the wide application of machine learning and data-driven methods in the field of semiconductor process and device modeling, people have begun to attempt to use data-driven methods to predict the relationship between process parameters and device performance. However, although the pure data-driven method can quickly give prediction results, the training of its model requires a large amount of high-quality experimental data as support, so the cost is high and the modeling cycle is long; at the same time, due to the lack of support from physical models, the generalization ability of the prediction results is poor, and it is difficult to cover the process range not covered by experimental data. Especially as the device size continues to shrink and the physical characteristics of the device become more complex, higher requirements are put forward for the robustness and generalization ability of the prediction model.

[0005] Therefore, there is an urgent need to establish an efficient, accurate and well-generalized thermal annealing process parameter optimization method that can be achieved with only a small amount of experimental data to meet the requirements of rapid development of advanced semiconductor manufacturing processes and agile optimization of process parameters. Summary of the Invention

[0006] The object of the present invention is to overcome the deficiencies of the above-mentioned prior art, and to provide a method for optimizing the thermal annealing process of semiconductor devices, a method for predicting resistance, and a system thereof.

[0007] The present invention is implemented as follows. In a first aspect, the present invention provides a method for optimizing the thermal annealing process of semiconductor devices. The semiconductor devices are based on silicon-based doped semiconductors, and the method includes: Obtaining multiple pairs of data. Each pair of data comes from two semiconductor devices under the same doping conditions and different thermal annealing conditions, and includes two sets of labeled thermal annealing process data. Each set of thermal annealing process data includes doping conditions and thermal annealing conditions, and the label is the resistance value of the semiconductor device under the current thermal annealing process. For each pair of data, input the two sets of thermal annealing process data into the thermal budget model respectively to obtain two thermal annealing thermal budget values; input the two thermal annealing thermal budget values into the activation rate model respectively to obtain two doping impurity activation rates; calculate the matching deviation between the doping impurity activation rate and the semiconductor device resistance value according to the two doping impurity activation rates and their corresponding semiconductor device resistance values; accumulate the matching deviations of each pair of data to obtain the total matching deviation. Find a correction exponent of the thermal budget model and a reference thermal budget parameter of the activation rate model to minimize the total matching deviation value. Substitute the found correction exponent and characteristic thermal budget parameter into the thermal budget model and the activation rate model respectively to obtain a corrected thermal budget model and a corrected activation rate model. Input the real-time obtained thermal annealing process data into the corrected thermal budget model to obtain a corrected thermal annealing thermal budget value; input the corrected thermal annealing thermal budget value into the corrected activation rate model to obtain a corrected doping impurity activation rate; optimize the thermal annealing process of the semiconductor device according to the comparison result between the corrected doping impurity activation rate and the target value.

[0008] Preferably, the doping condition is the activation activation energy of the doping element; the thermal annealing condition is the thermal annealing temperature curve. Preferably, the calculation function of the thermal budget model is as follows: (Equation 1) Wherein, is the equivalent annealing time at the reference temperature , that is, the thermal budget; is the activation activation energy of the doping element, m is the correction exponent, k is the Boltzmann constant, is the thermal annealing temperature varying with time .

[0009] Preferably, the calculation function of the activation rate model is as follows: (Equation 2) Wherein is the activation rate of the doped impurities, is the thermal annealing thermal budget, is the reference thermal budget, which is the thermal annealing thermal budget value when the activation rate of the doped impurities in the silicon-based doped semiconductor is 63.2%.

[0010] Preferably, the calculation of the matching deviation between the activation rate of the doped impurities and the resistance value of the semiconductor device is as follows: (Equation 3) Wherein represents the matching deviation between the activation rate of the doped impurities and the resistance value of the semiconductor device for the i-th pair of data; and respectively represent two activation rates of the doped impurities obtained after the two thermal annealing process data of the i-th pair of data pass through the thermal budget model and the activation rate model; and respectively represent the resistance values of the semiconductor devices corresponding to the two thermal annealing process data of the i-th pair of data.

[0011] In a second aspect, the present invention provides a semiconductor device thermal annealing process optimization system, including: A data acquisition module, responsible for acquiring the thermal annealing process data of the semiconductor device in real time; A first calculation module, responsible for inputting the real-time acquired thermal annealing process data into the corrected thermal budget model to obtain the corrected thermal budget value of the thermal annealing; A second calculation module, responsible for inputting the corrected thermal budget value of the thermal annealing into the corrected activation rate model to obtain the corrected activation rate of the doped impurities; An optimization module, responsible for optimizing the thermal annealing process of the semiconductor device according to the comparison result between the corrected activation rate of the doped impurities and the target value.

[0012] In a third aspect, the present invention provides a method for predicting the resistance of a semiconductor device. The semiconductor device is based on a silicon-based doped semiconductor, and the method includes: Acquiring the thermal annealing process data of the semiconductor device and the corresponding resistance of the semiconductor device; Using the corrected thermal budget model and the corrected activation rate model for the thermal annealing process data to obtain the corrected activation rate of the doped impurities; Constructing a training data set with the corrected activation rate of the doped impurities and the doping dose of the doped impurities, and using the corresponding resistance value of the semiconductor device as a label; Building a machine learning model and training it with the training data; the input of the machine learning model is the corrected activation rate of the doped impurities and the doping dose of the doped impurities, and the output is the resistance value of the semiconductor device; Using the trained machine learning model to realize the prediction of the resistance of the semiconductor device.

[0013] Preferably, it further includes standardizing data preprocessing for the correction activation rate of doped impurities and the doping dose of doped impurities.

[0014] Preferably, the machine learning model adopts an AdaBoost model with SVM as the base classifier.

[0015] Fourthly, the present invention provides a semiconductor device resistance prediction system, including: A data acquisition module, responsible for acquiring the thermal annealing process data of the semiconductor device and the doping dose of doped impurities; A resistance prediction module, responsible for inputting the thermal annealing process data of the semiconductor device and the doping dose of doped impurities into the trained machine learning model, and outputting the predicted resistance value of the semiconductor device.

[0016] The present invention constructs a corrected thermal budget model and a corrected activation rate model, and realizes resistance prediction by integrating a physical model with a data-driven method, significantly reducing the computational complexity and time cost of traditional pure physical simulation, overcoming the dependence of traditional machine learning models on large-scale data sets, and the combination of the two realizes the synergistic advantages of high precision, low data requirements, and strong generalization ability.

[0017] The present invention dynamically corrects the correction exponent m in the thermal budget model and the reference thermal budget parameter τ in the activation rate model by minimizing the matching deviation, enabling the model to adapt to different thermal annealing conditions. When the actual thermal annealing process deviates from the initial model, the system calculates the total matching deviation in real time and automatically adjusts the parameters to minimize the deviation, thereby optimizing the corresponding relationship between the doped impurity activation rate and the resistance value of the semiconductor device. This process significantly improves the dynamic response ability and process stability of process parameter optimization.

[0018] The present invention can directly adjust the thermal annealing process parameters through real-time comparison of the corrected activation rate of doped impurities with the target value, realizing closed-loop optimization.

[0019] In summary, the present invention solves the bottlenecks of traditional methods in terms of efficiency, cost, accuracy, and generalization through the deep integration of physical model correction and data driving, providing an efficient, low-cost, and highly reliable process optimization and performance prediction solution for advanced semiconductor manufacturing. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention, and those of ordinary skill in the art can also obtain other drawings based on these drawings without creative efforts.

[0021] Figure 1It is a flowchart of a method for optimizing the thermal annealing process of a semiconductor device provided by an embodiment of the present invention.

[0022] Figure 2 It is a flowchart of a method for predicting the resistance of a semiconductor device provided by an embodiment of the present invention.

[0023] Figure 3 It is a flowchart of a system for optimizing the thermal annealing process of a semiconductor device provided by an embodiment of the present invention.

[0024] Figure 4 It is a flowchart of a system for predicting the resistance of a semiconductor device provided by an embodiment of the present invention.

[0025] Figure 5 It is the comparison result between the predicted resistance value and the experimental value of the present invention provided by an embodiment of the present invention. Detailed implementation manners

[0026] To make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Apparently, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0027] The terms "including" and "having" and any variations thereof mentioned in the embodiments of the present invention are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally further includes other steps or units not listed, or optionally further includes other steps or units inherent to these processes, methods, products or devices.

[0028] The optimization of the thermal annealing process of doped semiconductors and the determination of resistance usually rely on classical semiconductor process simulations (such as TCAD simulations) or directly conduct a large number of experimental tests. For example, existing physical simulation prediction methods (such as TCAD simulations) have complex calculation processes and huge calculation amounts, resulting in long prediction time, which is not conducive to rapid process optimization, and low accuracy. Traditional pure data-driven methods (such as pure machine learning models) rely heavily on the quality and scale of the data set. For real experimental data, the process is complex, the cost is high, and the cycle is long, resulting in the inability of experimental data to meet the data scale required for data-driven modeling. And when the process parameters change beyond the coverage range of the training data, the model often fails to give accurate predictions and lacks the generalization ability for unseen scenarios.

[0029] From the above defects, it can be seen that there are technical problems in the prior art of difficult optimization of the thermal annealing process of doped semiconductors and difficult resistance prediction.

[0030] Based on this, referring to the attached Figure 1 , an embodiment of the present invention provides a method for optimizing the thermal annealing process of a semiconductor device. The semiconductor device is based on a silicon-based doped semiconductor, which is a type of semiconductor with silicon (Si) as the substrate material and its electrical properties are changed by artificially introducing doping impurities. The doping impurities can be group V elements (such as phosphorus P, arsenic As), group III elements (such as boron B, aluminum Al), and so on. For example, for a metal-oxide-semiconductor field-effect transistor (MOSFET), the preparation of a MOSFET usually starts with RCA chemical cleaning of a silicon wafer to remove organic and metal contaminants and expose an atomically flat silicon surface; subsequently, a field oxide layer several hundred nanometers thick is grown by wet or dry oxidation in the non-active region for electrical isolation; then, the well region and shallow source / drain regions (LDD) are formed by photolithography and ion implantation, and a gate oxide layer of 5-20 nm is formed by dry oxidation at 800-1000 °C; then, polysilicon or a metal gate material is deposited, patterned into a gate by photolithography and etching, and sidewall isolation layers are formed on the sides of the gate to control subsequent deep implantation regions; after the deep source / drain regions are formed by high-energy ion implantation or diffusion, thermal annealing must be performed to activate the doping impurities, repair the implantation damage, and release stress, and rapid thermal annealing (RTA, 900-1100 °C, for more than ten seconds) or furnace annealing (850-1100 °C, for several minutes to several hours) can be selected, and the atmosphere is usually N2 or Ar; after annealing, the interconnect dielectric is deposited in sequence and planarized by CMP to form vias and metallization layers, such as tungsten or copper; finally, multilayer metal interconnections (aluminum or copper) are deposited, the interconnect lines are patterned by photolithography and etching, a passivation layer is added, and wafer testing, dicing, and packaging are performed. Thermal annealing is a key step in the MOSFET manufacturing process, and its activation efficiency directly affects the threshold voltage, leakage current, carrier mobility, and device reliability.

[0031] Devices based on silicon-based doped semiconductors similar to MOSFETs also include: bipolar junction transistors (BJTs), insulated gate bipolar transistors (IGBTs), junction field-effect transistors (JFETs), Schottky diodes, thin-film transistors (TFTs), silicon solar cells, power laterally diffused MOS (LDMOS), and silicon-based photodiodes / photodetectors.

[0032] Specifically, the method includes the following steps: Step S1: Obtain multiple pairs of data; each pair of data comes from two semiconductor devices under the same doping conditions but different thermal annealing conditions, which includes two sets of labeled thermal annealing process data, and each set of thermal annealing process data includes doping conditions and thermal annealing conditions. The label is the resistance value of the semiconductor device under the current thermal annealing process. Taking MOSFET as an example, the resistance values of various key regions of MOSFET, such as the lightly doped drain region (LDD), the heavily doped source-drain region, and the polysilicon gate, have an important impact on the electrical properties of the device, such as the threshold voltage, the off-current, and the saturation current. Usually, the resistance values of these key regions are obtained through the wafer acceptance test (WAT). The specific process is to obtain them by means of an integrated TLM structure: a series of metal electrodes with a fixed width and different spacings are lithographed in the test area, the resistance values at each spacing are measured, and the resistance-spacing data is linearly fitted. The fitting slope is the sheet resistance (Ω / □), and the intercept reflects the contact resistance; the four-probe method can also be used in the same WAT test, and the sheet resistance is calculated from the resistance measured by the four probes and the probe spacing and geometric parameters. The thermal annealing process directly affects the activation rate of the doped impurities, and thus affects the resistance value. Within a certain thermal budget range, the resistance value decreases as the thermal budget of the thermal annealing increases.

[0033] As an example, the doping condition is the activation energy of the doped element; the thermal annealing condition is the thermal annealing temperature curve.

[0034] Step S2: For each pair of data, input the two sets of thermal annealing process data into the thermal budget model to obtain two thermal annealing thermal budget values; input the two thermal annealing thermal budget values into the activation rate model to obtain two doping impurity activation rates , , where i represents the i-th pair of data; according to the two doping impurity activation rates and their corresponding semiconductor device resistance values , calculate the matching deviation between the doping impurity activation rate and the semiconductor device resistance value ; accumulate the matching deviations of each pair of data to obtain the total matching deviation .

[0035] In one implementation, the calculation function of the thermal budget model is as follows: (Equation 1) where is the equivalent annealing time at the reference temperature , that is, the thermal budget; is the activation energy of the doped element, m is the correction exponent, k is the Boltzmann constant, is the function of time Variable thermal annealing temperature.

[0036] In one implementation, the calculation function of the activation rate model is as follows: (Equation 2) Where is the activation rate of the doped impurity, t eq is the thermal annealing thermal budget, τ is the reference thermal budget, such as the thermal annealing thermal budget value when the activation rate of the doped impurity in the silicon-based doped semiconductor is 63.2%.

[0037] In one implementation, the matching deviation between the activation rate of the doped impurity and the resistance value of the semiconductor device is calculated as follows: (Equation 3) Specifically, the total matching deviation is calculated as follows: (Equation 4) where n is the total number of pairs of collected sample data.

[0038] Step S3: Find a pair of correction exponents m of the thermal budget model and reference thermal budget parameter τ of the activation rate model to minimize the value.

[0039] Step S4: Substitute the found correction exponent m and characteristic thermal budget parameter τ into the thermal budget model and activation rate model respectively to obtain a corrected thermal budget model and a corrected activation rate model.

[0040] Step S5: Input the real-time obtained thermal annealing process data into the corrected thermal budget model to obtain a corrected thermal budget for thermal annealing; input the corrected thermal budget for thermal annealing into the corrected activation rate model to obtain a corrected activation rate of the doped impurity.

[0041] Step S6: Optimize the thermal annealing process of the semiconductor device according to the comparison result between the corrected activation rate of the doped impurity and the target value. For example, in the preparation of ultra-shallow junctions, it is necessary to strictly control the size of the thermal annealing thermal budget to control the diffusion of doped impurities; by increasing the peak temperature of the rapid thermal annealing process and increasing the heating rate, the diffusion of doped impurities can be suppressed; therefore, on the premise of ensuring that the activation rate meets the standard, optimize the thermal annealing process to suppress the diffusion of doped impurities and achieve the preparation of ultra-shallow junctions.

[0042] Refer to Appendix Figure 2 , this embodiment also provides a method for predicting the resistance of a semiconductor device, including: Step S1: Construct a training data set Obtain the thermal annealing process data of the semiconductor device and the corresponding resistance of the semiconductor device; By correcting the thermal budget model and the correction activation rate model for the thermal annealing process data, the corrected activation rate of the doped impurity is obtained; Construct a training data set with the corrected activation rate of the doped impurity and the doping dose of the doped impurity, and use the resistance value of the corresponding semiconductor device as the label.

[0043] Step S2: Build a machine learning model and train it using the training data; the input of the machine learning model is the corrected activation rate of the doped impurity and the doping dose of the doped impurity, and the output is the resistance value of the semiconductor device.

[0044] Step S3: Use the trained machine learning model to predict the resistance of the semiconductor device.

[0045] In one implementation, it also includes performing standardized data preprocessing on the corrected activation rate of the doped impurity and the doping dose of the doped impurity. As an example, the data preprocessing process can be as follows: convert the original data x to a new value by subtracting its sample mean μ and dividing by the standard deviation σ such that the processed data distribution is centered around 0 and has a standard deviation of 1. Data preprocessing can eliminate the differences in the magnitudes of different features and help the model converge faster.

[0046] The present invention has experimented and debugged various machine learning models, such as random forest models, support vector machine models, linear models, multi-layer perceptron models, etc. The final results show that the AdaBoost model with SVM as the base classifier has the fastest convergence speed and the highest prediction accuracy, so this model is adopted.

[0047] Figure 5 shows 31 groups of test data. For the resistance prediction values predicted by this embodiment, the average prediction time is 0.1017 s, and the error between the resistance prediction values and the experimental values is less than 1%.

[0048] The present invention only needs a small amount of experimental data (about 10 groups) to correct the thermal budget model and the activation rate model. At the same time, the corrected activation rate can be combined with the doping dose of the doped impurity to train a machine learning model, realizing the optimization of the thermal annealing process and resistance prediction of doped semiconductor devices with low cost, high speed, and high accuracy.

[0049] Therefore, the present invention constructs a hybrid physical data-driven model composed of a corrected thermal budget model, a corrected activation rate model, and a machine learning model, and uses it to realize resistance prediction, significantly reducing the computational complexity and time cost of traditional pure physical simulation, overcoming the dependence of traditional machine learning models on large-scale data sets, and the combination of the two realizes the synergistic advantages of high precision, low data requirements, and strong generalization ability.

[0050] Finally, this embodiment also provides a semiconductor device thermal annealing process optimization system and a resistance prediction system.

[0051] See the appendix Figure 3 , the semiconductor device thermal annealing process optimization system includes: A data acquisition module, responsible for obtaining the thermal annealing process data of the semiconductor device in real time; A first calculation module, responsible for inputting the real-time obtained thermal annealing process data into the corrected thermal budget model to obtain the corrected thermal budget value of thermal annealing; A second calculation module, responsible for inputting the corrected thermal budget value of thermal annealing into the corrected activation rate model to obtain the corrected activation rate of the doped impurities; An optimization module, responsible for optimizing the thermal annealing process of the semiconductor device according to the comparison result between the corrected activation rate of the doped impurities and the target value.

[0052] See the appendix Figure 4 , the semiconductor device resistance prediction system includes: A data acquisition module, responsible for obtaining the thermal annealing process data of the semiconductor device and the doping dose of the doped impurities; A resistance prediction module, responsible for inputting the thermal annealing process data of the semiconductor device and the doping dose of the doped impurities into the trained machine learning model and outputting the predicted resistance value of the semiconductor device.

[0053] The above is the preferred embodiment of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements can be made, and these improvements and refinements are also regarded as the protection scope of the present invention.

Claims

1. A method for optimizing the thermal annealing process of a semiconductor device, the semiconductor device being based on a silicon-based doped semiconductor, characterized in that, The method includes: Obtain multiple pairs of data, each pair of data coming from two semiconductor devices under the same doping condition and different thermal annealing conditions, which includes two sets of labeled thermal annealing process data. Each set of thermal annealing process data includes the doping condition and the thermal annealing condition, and the label is the resistance value of the semiconductor device under the current thermal annealing process; For each pair of data, input the two sets of thermal annealing process data into the thermal budget model respectively to obtain two thermal annealing thermal budget values; input the two thermal annealing thermal budget values into the activation rate model respectively to obtain two doping impurity activation rates; calculate the matching deviation between the doping impurity activation rate and the semiconductor device resistance value according to the two doping impurity activation rates and their corresponding semiconductor device resistance values; accumulate the matching deviations of each pair of data to obtain the total matching deviation; Find a set of correction exponents of the thermal budget model and reference thermal budget parameters of the activation rate model to minimize the total matching deviation value; Substitute the found correction exponent and characteristic thermal budget parameters into the thermal budget model and the activation rate model respectively to obtain a corrected thermal budget model and a corrected activation rate model; Input the real-time obtained thermal annealing process data into the corrected thermal budget model to obtain a corrected thermal annealing thermal budget value; input the corrected thermal annealing thermal budget value into the corrected activation rate model to obtain a corrected doping impurity activation rate; optimize the thermal annealing process of the semiconductor device according to the comparison result between the corrected doping impurity activation rate and the target value.

2. The method according to claim 1, characterized in that, The doping condition is the activation activation energy of the doping element; the thermal annealing condition is the thermal annealing temperature curve.

3. The method according to claim 2, characterized in that, The calculation function of the thermal budget model is as follows: (Formula 1) Among them, is the equivalent annealing time at the reference temperature , that is, the thermal budget; is the activation energy of the dopant element activation, m is the correction exponent, k is the Boltzmann constant, is the thermal annealing temperature that changes with time .

4. The method according to claim 3, wherein The calculation function of the activation rate model is as follows: (Formula 2) where is the activation rate of the doped impurity, t eq is the thermal annealing thermal budget, and τ is the reference thermal budget.

5. The method according to claim 1, wherein The calculation of the matching deviation between the doping impurity activation rate and the semiconductor device resistance value is as follows: (Formula 3) wherein represents the matching deviation between the doping impurity activation rate and the resistance value of the semiconductor device for the i-th pair of data; and respectively represent two doping impurity activation rates obtained from the thermal budget model and the activation rate model for the two sets of thermal annealing process data of the i-th pair of data; and respectively represent the resistance values of the semiconductor devices corresponding to the two sets of thermal annealing process data of the i-th pair of data.

6. A semiconductor device thermal annealing process optimization system for implementing the method according to any one of claims 1-5, characterized in that, Includes: A data acquisition module responsible for real-time acquiring the thermal annealing process data of the semiconductor device; A first calculation module responsible for inputting the real-time obtained thermal annealing process data into the corrected thermal budget model to obtain a corrected thermal annealing thermal budget value; A second calculation module responsible for inputting the corrected thermal annealing thermal budget value into the corrected activation rate model to obtain a corrected doping impurity activation rate; An optimization module responsible for optimizing the thermal annealing process of the semiconductor device according to the comparison result between the corrected doping impurity activation rate and the target value.

7. A method for predicting the resistance of a semiconductor device, the semiconductor device being based on a silicon-based doped semiconductor, characterized in that, The method includes: Obtain the thermal annealing process data of the semiconductor device and the corresponding semiconductor device resistance; Obtain the corrected doping impurity activation rate for the thermal annealing process data by using the method according to any one of claims 1-5; Construct a training data set with the corrected doping impurity activation rate and the doping dose of the doping impurity, and use the corresponding semiconductor device resistance value as the label; Build a machine learning model and train it with the training data; the input of the machine learning model is the corrected doping impurity activation rate and the doping dose of the doping impurity, and the output is the semiconductor device resistance value; Use the trained machine learning model to predict the semiconductor device resistance.

8. The method according to claim 7, wherein It also includes performing standardized data preprocessing on the corrected doping impurity activation rate and the doping dose of the doping impurity.

9. The method according to claim 7, characterized in that The machine learning model uses an AdaBoost model with SVM as the base classifier.

10. A semiconductor device resistance prediction system for implementing the method according to any one of claims 7-9, characterized in that, Includes: A data acquisition module, responsible for acquiring the thermal annealing process data of semiconductor devices and the doping doses of doped impurities; A resistance prediction module, responsible for inputting the thermal annealing process data of semiconductor devices and the doping doses of doped impurities into a trained machine learning model and outputting the predicted resistance values of semiconductor devices.

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