Method and device for automatically generating verilog file controlled by PAD
By automatically generating PAD-controlled verilog files, the problems of high design complexity and mismatch in traditional designs are solved, and more efficient design flow and higher consistency are achieved.
Patent Information
- Application Number
- CN202510299459.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-13
- Publication Date
- 2025-06-24
AI Technical Summary
In integrated circuit design, the design complexity of traditional PAD control circuits is high, and relying on design engineers to manually update the verilog file, which is prone to errors. The instructions for PAD control need to be updated synchronously, resulting in mismatch between the actual circuit and the instructions for use.
Provides a PAD-controlled verilog file automatic generation method and device. By pre-establishing a process-related PAD logic standard unit library, using python scripts to process excel files, and automatically generates synthesisable verilog files.
It reduces the design complexity of the PAD control circuit. It supports only the PAD logic standard unit needs to be updated when process replacement to quickly generate corresponding verilog files, ensuring a high consistency between the circuit and the instructions.
Smart Images
Figure CN120197565A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of integrated circuit design, and relates to a method and device for automatically generating a Verilog file for PAD control. Background Art
[0002] In integrated circuit design, PAD (chip pin) is the physical interface for the chip to interact with the external circuit, responsible for providing electrical characteristics such as voltage conversion, signal driving, and anti-noise. PAD control refers to the configuration of the electrical attributes of the pins. Traditional PAD control is to have a design engineer write a Verilog (a hardware description language (HDL), usually used to describe the functions of digital logic circuits) file, and then use EDA (Electronic Design Automation Tools, a class of software tools for assisting in the design of electronic systems) to generate a circuit based on this Verilog file; among them, the design engineer is also responsible for writing the usage instructions for PAD control and handing them over to the test and application engineers for circuit testing.
[0003] The number of PADs on the chip is limited, and PADs usually need to be reused. As the chip scale gets larger and larger, the complexity of the PAD control circuit is also continuously increasing. Relying on design engineers to manually update the Verilog file has a relatively high chance of errors. And integrated circuit design is a continuously updated process, the Verilog file for PAD control also needs to be continuously updated, and the usage instructions for PAD control also need to be synchronously updated accordingly. However, due to reasons such as tight chip tape-out time and limited manpower, design engineers often pay more attention to the update of the Verilog file, which easily causes the mismatch between the actual PAD control circuit and its usage instructions, making it difficult for the test and application sides to carry out work. In addition, PAD is closely related to the process it adopts, and different processes adopted by different manufacturers will result in different PADs, and changing the process requires correspondingly updating the PAD control circuit. Therefore, how to automatically generate a Verilog file for PAD control has become one of the current technical problems to be solved. Summary of the Invention
[0004] In view of the problems existing in the above traditional technologies, the present invention proposes a method for automatically generating a Verilog file for PAD control and a device for automatically generating a Verilog file for PAD control, which can automatically generate a Verilog file for PAD control.
[0005] To achieve the above object, the embodiments of the present invention adopt the following technical solutions: On the one hand, a method for automatically generating a Verilog file for PAD control is provided, including the steps: Write an Excel file according to the interface signals of the standard cells of the PAD logic based on the position where the PAD needs to be placed; the standard cells include the standard cell ICD_PAD_H and the standard cell ICD_PAD_V, and the interface signals include input / output control, input of functional mode, input enable, output enable, output, and default value. The information written in the Excel file includes the serial number of the PAD, the name of the PIN finally connected to the PAD, the default drive type of the PAD, the standard cell used when instantiating the PAD, and the interface signals. Use the top-level script of the Python script to process the written Excel file; the top-level script is used to define the Excel file to be processed, the row and column positions of the port signals of the standard cells of the PAD logic in the Excel file, and the generated Verilog file name. Use the head function sub-script of the Python script to process the written Excel file to generate the input and output ports of the Verilog file. Use the inst function sub-script of the Python script to process the written Excel file to perform the instantiation of the standard cells of the PAD logic in the Verilog file. The top-level script is also used to call the head function sub-script and the inst function sub-script to write the generated code into the Verilog file to generate the Verilog file for PAD control.
[0006] In one embodiment, when the PAD process provided by the process manufacturer is changed compared to the currently used PAD process, before the step of writing the Excel file according to the interface signals of the standard cells of the PAD logic based on the position where the PAD needs to be placed, the following steps are further included: Obtain the latest PAD process provided by the process manufacturer. Update the interface signals of the standard cells of the PAD logic according to the latest PAD process.
[0007] In one embodiment, during the process of using the head function sub-script of the Python script to process the written Excel file, if there are duplicate signals, the duplicate signals are merged.
[0008] On the other hand, a device for automatically generating a Verilog file for PAD control is also provided, including: A file writing module, configured to write an Excel file according to the interface signals of the standard cells of the PAD logic based on the position where the PAD needs to be placed; the standard cells include the standard cell ICD_PAD_H and the standard cell ICD_PAD_V, and the interface signals include input / output control, input of function mode, input enable, output enable, output, and default value. The information written in the Excel file includes the serial number of the PAD, the name of the PIN finally connected to the PAD, the default drive type of the PAD, the standard cell used when instantiating the PAD, and the interface signals. A top-level processing module, configured to process the written Excel file by using the top-level script of the Python script; the top-level script is used to define the Excel file to be processed, the positions of the port signals of the standard cells of the PAD logic in the rows and columns of the Excel file, and the generated Verilog file name. An input / output generation module, configured to process the written Excel file by using the head function sub-script of the Python script to generate the input / output ports of the Verilog file. A cell instantiation module, configured to process the written Excel file by using the inst function sub-script of the Python script to perform the instantiation of the standard cells of the PAD logic in the Verilog file; the top-level script is also used to call the head function sub-script and the inst function sub-script to write the generated code into the Verilog file to generate a Verilog file for PAD control.
[0009] In one embodiment, when the PAD process provided by the process manufacturer is replaced compared with the currently used PAD process, the file writing module is further configured to obtain the latest PAD process provided by the process manufacturer and update the interface signals of the standard cells of the PAD logic according to the latest PAD process.
[0010] In one embodiment, during the process of the input / output generation module processing the written Excel file by using the head function sub-script of the Python script, if there are duplicate signals, the duplicate signals are merged.
[0011] One of the above technical solutions has the following advantages and beneficial effects: The above-mentioned method and device for automatically generating a Verilog file for PAD control establish a standard cell library for PAD logic related to the process in advance. The standard cells in the standard cell library include standard cell ICD_PAD_H and standard cell ICD_PAD_V, which can be directly called by the top layer for instantiation of the standard cells for PAD logic. This enables writing an Excel file for PAD control according to the interface signals of the standard cells for PAD logic based on the position where the PAD needs to be placed during actual use. Then, a Python script is used to process this Excel file to automatically generate a synthesizable Verilog file. Compared with the traditional method, it supports only updating the standard cells for PAD logic when changing the process, then updating the Excel file, and quickly generating the corresponding Verilog file for PAD control using the Python script, thus greatly reducing the design complexity of the PAD control circuit, facilitating front-end optimization and maintenance as well as back-end placement and wiring, and ensuring a high degree of consistency between the final circuit and the instruction manual. Description of the Drawings
[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or in the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.
[0013] Figure 1 It is a flowchart of a method for automatically generating a Verilog file for PAD control in an embodiment; Figure 2 It is a block diagram of a device for automatically generating a Verilog file for PAD control in an embodiment. Detailed Embodiments
[0014] In order to make the objectives, technical solutions, and advantages of the present invention clearer, the following further details the present invention in conjunction with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field of the present invention. The terms used in the description of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention.
[0015] It should be noted that when "embodiment" is mentioned in this text, it means that the specific features, structures or characteristics described in combination with the embodiment can be included in at least one embodiment of the present invention. The display of this phrase at various positions in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art can understand that the embodiments described herein can be combined with other embodiments. The term "and / or" used in the specification and appended claims of the present invention refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.
[0016] The following will specifically describe the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention.
[0017] In one embodiment, as Figure 1 shown, a method for automatically generating a verilog file controlled by PAD is provided, which may include the following steps S12 to S18: S12, write an excel file according to the interface signals of the standard cells of the PAD logic according to the positions where the PADs need to be placed; the standard cells include the standard cell ICD_PAD_H (i.e., the horizontal PAD) and the standard cell ICD_PAD_V (i.e., the vertical PAD), and the interface signals include input / output control, input of function mode, input enable, output enable, output and default value. The information written in the excel file includes the serial number of the PAD, the name of the PIN finally connected to the PAD, the default drive type of the PAD, the standard cell used when instantiating the PAD, and the interface signals; S14, use the top-level script of the python script to process the written excel file; the top-level script is used to define the excel file to be processed, the positions of the port signals of the standard cells of the PAD logic in the rows and columns of the excel file, and the generated verilog file name; S16, use the head function sub-script of the python script to process the written excel file to generate the input / output ports of the verilog file; S18, use the inst function sub-script of the python script to process the written excel file to perform the instantiation of the standard cells of the PAD logic in the verilog file; the top-level script is also used to call the head function sub-script and the inst function sub-script to write the generated code into the verilog file to generate a verilog file controlled by PAD.
[0018] It can be understood that according to the positions where the PADs on the chip need to be placed, the foundry will provide PADs in the horizontal and vertical directions respectively, such as ********_IO33_H and ********_IO33_V. According to different processes, the standard cells ICD_PAD_H and ICD_PAD_V for PAD logic are made first. The standard cell ICD_PAD_H instantiates a ********_IO33_H, and the standard cell ICD_PAD_V instantiates a ********_IO33_V. If the process needs to be changed, then only the interface of the standard cell needs to be changed according to the PADs provided by the foundry to achieve adaptation.
[0019] The interfaces of the standard cells ICD_PAD_H and ICD_PAD_V for PAD logic usually can include: (1) input / output control (io_ctrl), (2) inputs (i), input enable (ie), output enable (oe), outputs (c), and default values (default) for the functional modes.
[0020] There can be three python scripts. Among them, one top-level script is icd_padc_digital.py, and the two sub-scripts are the head function sub-script head.py and the inst function sub-script inst.py. The top-level script icd_padc_digital.py defines the excel file to be processed, the row and column positions of the port signals of the standard cells for PAD logic in the excel, and the generated verilog file name (such as padc_digital.v). The top-level script icd_padc_digital.py is also used to call the two sub-scripts to write the generated code into the verilog file. The parameter descriptions in part of the code of the top-level script icd_padc_digital.py can be as follows: pin_col_num represents the column position of the Pin in the excel file; pad_col_num represents the column position of the PAD instantiation type PAD_TYPE in the excel file; io_ctrl_col_num represents the column position of the input / output control io_ctrl in the excel file; func_start_num represents the starting column position of the input I of the functional mode of FUNCTION0 in the excel file; func_port_num represents the number of FUNCTIONs in the excel file (FUNCTION0 and FUNCITON1); rtl_file represents the generated verilog file name; The excel_file represents the name of the excel file processed by the python script.
[0021] The head function sub-script head.py defines a head function in python, which is used to generate the input and output ports of the verilog file.
[0022] The inst function sub-script inst.py defines an inst function in python, which is mainly used for instantiating the standard cells of the PAD logic in the verilog file. The PAD_TYPE in the excel is read to define them respectively. For example, the interface GPIO1 in the excel file is instantiated using the standard cell ICD_PAD_V, and the interface GPIO2 is instantiated using the standard cell ICD_PAD_H. The instantiated ports are connected according to the signals in the excel file.
[0023] The above method for automatically generating the verilog file for PAD control establishes a standard cell library for the PAD logic related to the process in advance. The standard cells in the standard cell library include the standard cell ICD_PAD_H and the standard cell ICD_PAD_V, which can be directly called by the top layer for instantiating the standard cells of the PAD logic. This enables writing the excel file for PAD control according to the interface signals of the standard cells of the PAD logic based on the position where the PAD needs to be placed during actual use, and then using the python script to process this excel file to automatically generate a synthesizable verilog file. Compared with the traditional method, it only requires updating the standard cells of the PAD logic when changing the process, and then updating the excel file. The corresponding verilog file for PAD control can be quickly generated using the python script, thus greatly reducing the design complexity of the PAD control circuit, facilitating the front-end optimization and maintenance as well as the back-end placement and wiring, and ensuring a high consistency between the final circuit and the instruction manual.
[0024] Among them, one specific example of writing an Excel file can be as follows: According to the positions where the PADs need to be placed and the interfaces of the above-mentioned standard cells ICD_PAD_H and ICD_PAD_V, write the corresponding Excel file as shown in Table 1. The first column No in Table 1 refers to the serial number of the PAD, the second column Pin refers to the name of the PIN (interface of the internal logic unit of the chip) to which the PAD is finally connected (such as GPIO1 and GPIO2, etc.), PULL refers to the default drive type of the PAD (up indicates pull-up drive, down indicates pull-down drive). PAD_TYPE is the standard cell provided by the process manufacturer when instantiating the PAD (including ICD_PAD_V and ICD_PAD_H). The input / output control io_ctrl such as r_gpio1_io_ctrl and r_gpio2_io_ctrl, etc. FS Default and Default are both default values, and the remaining columns are specific function columns, such as Function0, Function1, etc. The input I (synonymous with the lowercase i) of the function mode can include existing function modes such as tcon_padc_tg_out[0], tcon_padc_tg_out[1], tcs_padc_d3[0], and tcs_padc_d3[1], etc. IE represents input enable, OE represents output enable (oe), and C represents output.
[0025] Table 1
[0026] In one embodiment, when the PAD process provided by the process manufacturer is replaced compared with the currently used PAD process, before the step of writing the Excel file according to the interface signals of the standard cells of the PAD logic based on the positions where the PADs need to be placed, the following steps are further included: Obtain the latest PAD process provided by the process manufacturer; based on this latest PAD process, information such as the positions where the PADs need to be placed and the standard cells used for instantiating the interfaces can be directly obtained; Update the interface signals of the standard cells of the PAD logic according to the latest PAD process.
[0027] It can be understood that if the process is replaced, then only the standard cells of the PAD logic need to be updated, and then the design engineer can update the Excel file and use the Python script to generate the corresponding Verilog file for PAD control, reducing the design complexity of the PAD control circuit and improving the design efficiency at the same time.
[0028] In one embodiment, during the process of using the head function sub-script of the Python script to process the written Excel file, if there are duplicate signals, the duplicate signals are merged.
[0029] It can be understood that when the head function subscript head.py has duplicate signals in the prepared excel file (such as tcon_padc_tg_out[0] and tcon_padc_tg_out[1] in Table 1), they can be merged into tcon_padc_tg_out[1:0] to accurately write the duplicate signals into the verilog file, saving the time for manual search and processing.
[0030] It should be understood that although the various steps in the above process Figure 1 are shown in sequence according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise clearly stated in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, at least a part of the steps in the above process Figure 1 can include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed alternately or in turn with at least a part of other steps or sub-steps or stages of other steps.
[0031] In one embodiment, as Figure 2As shown in the figure, a PAD control Verilog file automatic generation device 100 is provided, which includes a file writing module 11, a top-level processing module 13, an input / output generation module 15, and a unit instantiation module 17. Among them, the file writing module 11 is used to write an Excel file according to the interface signals of the standard cells of the PAD logic according to the positions where the PADs need to be placed; the standard cells include the standard cell ICD_PAD_H and the standard cell ICD_PAD_V, and the interface signals include input / output control, input of function mode, input enable, output enable, output, and default value. The information written in the Excel file includes the serial number of the PAD, the name of the PIN finally connected to the PAD, the default drive type of the PAD, the standard cell used when instantiating the PAD, and the interface signals. The top-level processing module 13 is used to process the written Excel file by using the top-level script of the Python script; the top-level script is used to define the Excel file to be processed, the positions of the port signals of the standard cells of the PAD logic in the rows and columns of the Excel file, and the generated Verilog file name. The input / output generation module 15 is used to process the written Excel file by using the head function sub-script of the Python script to generate the input / output ports of the Verilog file. The unit instantiation module 17 is used to process the written Excel file by using the inst function sub-script of the Python script to execute the instantiation of the standard cells of the PAD logic in the Verilog file; the top-level script is also used to call the head function sub-script and the inst function sub-script to write the generated code into the Verilog file to generate a PAD control Verilog file.
[0032] For the above-mentioned PAD control Verilog file automatic generation device 100, by pre-establishing a standard cell library for the PAD logic related to the process, the standard cells in the standard cell library include the standard cell ICD_PAD_H and the standard cell ICD_PAD_V, which can be directly called by the top level to perform the instantiation of the standard cells of the PAD logic, so that in the actual use process, an Excel file for PAD control can be written according to the interface signals of the standard cells of the PAD logic according to the positions where the PADs need to be placed, and then the Python script is used to process the Excel file to automatically generate a synthesizable Verilog file. Compared with the traditional method, it can support only updating the standard cells of the PAD logic when changing the process, and then updating the Excel file, and quickly generating the corresponding PAD control Verilog file by using the Python script, thus greatly reducing the design complexity of the PAD control circuit, facilitating the front-end optimization and maintenance and the back-end placement and wiring, and ensuring a high consistency between the final circuit and the instruction manual file.
[0033] In one embodiment, when the PAD process provided by the process manufacturer is replaced compared with the currently used PAD process, the file writing module 11 is further configured to obtain the latest PAD process provided by the process manufacturer and update the interface signals of the standard cells of the PAD logic according to the latest PAD process.
[0034] In one embodiment, during the process of the input / output generation module 15 processing the written excel file by using the head function sub-script of the python script, if there are duplicate signals, the duplicate signals are merged.
[0035] For the specific limitations of the verilog file automatic generation device 100 for PAD control, reference may be made to the corresponding explanations of the verilog file automatic generation method for PAD control in the foregoing text and understood in the same way, which will not be elaborated herein.
[0036] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above methods. Among them, any reference to a memory, storage, database, or other medium used in the various embodiments provided by the present invention can include non-volatile and / or volatile memories. Non-volatile memories can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memories can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), memory bus dynamic random access memory (Rambus DRAM, abbreviated as RDRAM), and interface dynamic random access memory (DRDRAM), etc.
[0037] The technical features of the above embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this specification.
[0038] The above embodiments merely illustrate several implementation manners of the present invention. The description thereof is relatively specific and detailed, but it should not be construed as a limitation on the protection scope of the invention. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and all of them fall within the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the appended claims.
Claims
1. A method for automatically generating a Verilog file controlled by a PAD, characterized in that: Includes steps: Write an excel file according to the interface signal of the standard unit of the PAD logic according to the position where the PAD needs to be placed; the standard unit includes the standard unit ICD_PAD_H and the standard unit ICD_PAD_V, the interface signal includes input and output control, input of the function mode, input enable, output enable, output and default value, and the information written in the excel file includes the serial number of the PAD, the name of the PIN to which the PAD is finally connected, the default driver type of the PAD, the standard unit used when instantiating the PAD, and the interface signal; The written Excel file is processed using a top-level script of a Python script; the top-level script is used to define the Excel file to be processed, the position of the row and column of the port signal of the standard unit of the PAD logic in the Excel file, and the generated Verilog file name; Use the head function sub-script of the Python script to process the written Excel file to generate the input and output ports of the Verilog file; The inst function sub-script of the Python script is used to process the written Excel file and execute the instantiation of the standard unit of the PAD logic in the Verilog file; the top-level script is also used to call the head function sub-script and the inst function sub-script to write the generated code into the Verilog file to generate the Verilog file controlled by the PAD.
2. The method for automatically generating a Verilog file for PAD control according to claim 1, characterized in that: When the PAD process provided by the process manufacturer is changed compared to the currently used PAD process, before the step of writing the Excel file according to the interface signal of the standard unit of the PAD logic according to the position where the PAD needs to be placed, the following steps are also included: Obtain the latest PAD technology provided by the process manufacturer; The interface signals of the standard cells of the PAD logic are updated according to the latest PAD process.
3. The method for automatically generating a Verilog file for PAD control according to claim 1 or 2, characterized in that: In the process of processing the written Excel file using the head function sub-script of the Python script, if there are repeated signals, the repeated signals are merged.
4. A PAD-controlled Verilog file automatic generation device, characterized in that: include: A file writing module is used to write an excel file according to the interface signal of the standard unit of the PAD logic according to the position where the PAD needs to be placed; the standard unit includes the standard unit ICD_PAD_H and the standard unit ICD_PAD_V, the interface signal includes input and output control, input of the function mode, input enable, output enable, output and default value, and the information written in the excel file includes the serial number of the PAD, the name of the PIN to which the PAD is finally connected, the default driver type of the PAD, the standard unit used when instantiating the PAD, and the interface signal; A top-level processing module is used to process the written Excel file using a top-level script of a Python script; the top-level script is used to define the Excel file to be processed, the position of the row and column of the port signal of the standard unit of the PAD logic in the Excel file, and the generated Verilog file name; An input and output generation module is used to process the written Excel file using the head function sub-script of the Python script to generate input and output ports of the Verilog file; The unit instantiation module is used to use the inst function sub-script of the Python script to process the written Excel file and execute the instantiation of the standard unit of the PAD logic in the Verilog file; the top-level script is also used to call the head function sub-script and the inst function sub-script to write the generated code into the Verilog file to generate the Verilog file controlled by the PAD.
5. The automatic generation device of Verilog files for PAD control according to claim 4, characterized in that: When the PAD process provided by the process manufacturer is replaced with the currently used PAD process, the file writing module is further used to obtain the latest PAD process provided by the process manufacturer, and update the interface signal of the standard unit of the PAD logic according to the latest PAD process.
6. The automatic generation device of Verilog files for PAD control according to claim 4 or 5, characterized in that: When the input-output generation module processes the written Excel file using the head function sub-script of the Python script, if there are repeated signals, the repeated signals are merged.