Driving circuit and driving method for increasing abnormal power failure voltage

Abstract

The invention discloses a driving circuit and a driving method for increasing abnormal power-down voltage, and the driving circuit is applied to a display device. The discharging unit comprises at least two discharging circuits which are connected in parallel, and the input end of the discharging unit is electrically connected with the output end of the voltage generating unit; the plurality of capacitor units comprise first capacitor units, and each path of discharging circuit comprises a first capacitor unit; wherein when the display device is abnormally powered down, the first capacitor unit of at least one discharge circuit in the discharge units is shared with the other one or more capacitor units in the drive circuit. On the premise that the capacitance value of the off-chip capacitor and the number of the off-chip capacitors are not increased, the driving capacity of the driving circuit is improved when the BOR is triggered.

Description

Technical Field

[0001] The present invention relates to the technical field of liquid crystal display, and particularly to a driving circuit and a driving method for improving the abnormal power-off voltage of a panel. Background Art

[0002] In recent years, liquid crystal display devices (LCDs) have been widely used in many fields and continue to show a rapid growth trend. With the improvement of driving technology, they have the advantages of low power consumption, thin and light weight, and low-voltage driving, and are currently widely used in video cameras, laptop computers, desktop display devices, and various projection devices.

[0003] Liquid crystal display devices in which switching transistors are formed in each pixel distributed in a matrix form on a liquid crystal panel are now widely used. A liquid crystal display device usually has a gate driving circuit, a source driving circuit, and a pixel array. The pixel array has a plurality of pixel circuits, and each pixel circuit is turned on and off according to a scanning signal provided by the gate driving circuit, and displays a data picture according to a data signal provided by the source driving circuit.

[0004] With the increasing popularity of high-resolution and full-screen handheld devices, users have put forward higher and higher requirements for energy conservation and other aspects. Compared with traditional a-Si panels, panels based on IGZO (Indium Gallium Zinc Oxide) technology have better performance in terms of low power consumption and energy saving due to the improvement of their mobility and extremely low off-state leakage.

[0005] IGZO is an amorphous oxide containing indium, gallium, and zinc. For a TFT panel (TFT: Thin Film Transistor) based on this technology, its carrier mobility is 20 to 30 times that of amorphous silicon, which can greatly improve the charge and discharge rate of the TFT to the pixel electrode and achieve a faster refresh rate. At the same time, the faster response also greatly improves the row scanning rate of the pixels, making ultra-high resolution possible in a TFT-LCD (Thin film transistor liquid crystal display). In addition, because IGZO is completely transparent and insensitive to visible light, it can greatly increase the aperture ratio of the component, improve the brightness, and reduce the power consumption. The IGZO display panel has a higher energy efficiency level and is more efficient. Therefore, in terms of the main performance parameters of the panel, the IGZO display panel has been comprehensively improved compared with the traditional TFT panel and has been more and more widely used.

[0006] During actual use, there are application scenario requirements for abnormal power off APO (Abnormal power off) such as the external power supply being cut off in the IGZO display panel. In order to better clear the charges on the IGZO display panel and prevent liquid crystal polarization, when the brown-out reset BOR (Brown-out Reset) triggered by abnormal power off occurs, voltages with different power-off slopes of driving capabilities need to be provided to meet the requirements of abnormal power off of the IGZO display panel. The traditional method is that when BOR is triggered, different driving voltages are respectively connected to resistors with different resistance values and voltage-stabilizing capacitors to form different discharge paths, and different discharge slopes are controlled through different RC constants to meet the discharge requirements of the IGZO display panel. However, in the prior art, in order to meet the peak levels that different driving voltages can reach when abnormal power off occurs, the discharge circuit corresponding to a large load usually needs to increase the capacitance value of the voltage-stabilizing capacitor or additionally connect more capacitors in parallel; but usually increasing the capacitance value or the number of capacitors will result in an increase in volume, which does not meet the application requirements of thin and light handheld devices; moreover, the cost is also higher, bringing mass production pressure to the module factory. Summary of the Invention

[0007] The object of the present invention is to provide a driving circuit and a driving method for boosting the abnormal power-off voltage, which can achieve a driving circuit and method that save costs and improve the voltage driving ability when BOR is triggered without increasing the capacitance value of the off-chip capacitor and the number of off-chip capacitors, so as to solve the problems brought by the traditional method.

[0008] In order to achieve the above object, the present invention is realized through the following technical solutions:

[0009] A driving circuit for boosting the abnormal power-off voltage, which is applied to a display device, and the driving circuit includes: a voltage generation unit;

[0010] A discharge unit, the discharge unit includes at least two discharge circuits connected in parallel, the input end of the discharge unit is electrically connected to the output end of the voltage generation unit; a plurality of capacitor units, the plurality of capacitor units include a first capacitor unit, and each discharge circuit includes the first capacitor unit; wherein, when the display device has an abnormal power off, the first capacitor unit of at least one discharge circuit in the discharge unit shares with one or more other capacitor units in the driving circuit.

[0011] Optionally, the way that the first capacitor unit of at least one discharge circuit in the discharge unit shares with other capacitor units in the driving circuit includes: in the discharge unit, the first capacitor unit of one discharge circuit shares with the first capacitor unit of the remaining one or more discharge circuits.

[0012] Optionally, the driving circuit further includes: a voltage regulation unit, an input end of the voltage regulation unit is electrically connected to an output end of the voltage generation unit, and an input end of the discharge unit is electrically connected to the output end of the voltage generation unit through the voltage regulation unit. The plurality of capacitor units further includes a second capacitor unit, one end of the second capacitor unit is coupled to the output end of the voltage generation unit, and the other end is grounded; or one end of the second capacitor unit is the input end of the voltage regulation unit, and the other end is grounded.

[0013] Optionally, the manner in which the first capacitor unit of at least one discharge circuit in the discharge unit shares with other capacitor units in the driving circuit includes: in the discharge unit, the first capacitor unit of one of the discharge circuits shares with the second capacitor unit.

[0014] Or, while the first capacitor unit of one of the discharge circuits shares with the first capacitor units of the remaining one or more discharge circuits, it also shares with the second capacitor unit.

[0015] Optionally, the driving circuit further includes: a plurality of control units, the plurality of control units includes a first control unit, and the first control unit is configured to control whether at least one of the discharge circuits in the discharge unit is connected in parallel with one or more other discharge circuits in the discharge unit.

[0016] Optionally, the first control unit includes a plurality of first sub-control units, and in the discharge unit, at least one of the discharge circuits includes the first sub-control unit.

[0017] Optionally, the plurality of control units further includes a second control unit, and the second control unit is configured to control whether the second capacitor unit shares with the first capacitor unit when an abnormal power-off occurs.

[0018] Optionally, the plurality of control units further includes a third control unit, and the third control unit is configured to control whether the discharge circuit in the discharge unit starts a discharge phase.

[0019] Optionally, the capacitance values of the first capacitor units of different discharge circuits are the same or different.

[0020] Optionally, the driving circuit further includes: an abnormal power-off determination unit, and the abnormal power-off determination unit is configured to monitor whether the abnormal power-off occurs and determine whether the display device has an abnormal power-off according to a preset determination criterion.

[0021] Optionally, each of the discharge circuits includes a resistor unit, and whether the resistor unit is used for discharging in the discharge phase is controlled by a third control unit.

[0022] Optionally, the resistance values of the resistance units in different discharge circuits are not equal.

[0023] Optionally, the first capacitor unit is disposed inside or outside the driving chip of the display device, and the resistance unit is disposed inside or outside the driving chip of the display device.

[0024] On the other hand, the present invention further provides a driving method for a driving circuit for boosting an abnormal power-off voltage according to the foregoing, including the steps of:

[0025] Step 1: Abnormal power-off determination. The abnormal power-off determination unit monitors whether the abnormal power-off occurs and outputs a determination result. If the determination result is that no abnormal power-off occurs, the process returns to normal display; if the determination result is that an abnormal power-off occurs, then enter Step 2: Abnormal power-off discharge process.

[0026] Step 2: Abnormal power-off discharge process. S1: Peak voltage level matching stage; for one or more discharge circuits, according to the timing signal, control a plurality of control units to enable the first capacitor unit of at least one discharge circuit to be shared with other capacitor units in the driving circuit, so as to match the peak voltage levels required by different driving loads corresponding to different discharge circuits. S2: Discharge stage; according to the timing signal, control a plurality of control units to ground each of the discharge circuits through the resistance unit. S3: Discharge end stage; enter the free power-off mode, and after the charge of the display device is exhausted, complete the abnormal power-off discharge process.

[0027] Optionally, in the normal display state or during abnormal power-off determination, the third control unit among the plurality of control units remains disconnected.

[0028] Optionally, in the peak voltage level matching stage, the third control unit among the plurality of control units remains disconnected, and control the conduction of the sub-control units in a suitable number of the discharge circuits and / or the conduction of the second control unit, so as to meet the peak voltage level requirements corresponding to different driving loads of different discharge circuits.

[0029] Optionally, in the discharge stage, control the third control unit among the plurality of control units to switch from disconnected to conducting, and the other control units among the plurality of control units to switch from conducting to disconnected.

[0030] The present invention has at least one of the following advantages:

[0031] When the display device experiences an abnormal power-off (BOR trigger), at least one discharge circuit in the discharge unit provided by the present invention shares the first capacitor unit with one or more other capacitor units in the driving circuit, so that different driving loads corresponding to different discharge circuits can reach the required peak voltage level. Thus, the present invention can improve the voltage driving ability of the driving circuit and save costs when the display device experiences an abnormal power-off without increasing the capacitance value of the off-chip capacitor and the number of off-chip capacitors. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 FIG. is a block diagram of a driving circuit for improving the abnormal power-off voltage provided by an embodiment of the present invention;

[0033] Figure 2 FIG. is a schematic flowchart of a driving method for a driving circuit for improving the abnormal power-off voltage provided by an embodiment of the present invention;

[0034] Figure 3 FIG. is a schematic diagram of a driving circuit for abnormal power-off of a display panel provided by the first embodiment of the present invention;

[0035] Figure 3a is Figure 3 a timing chart of the opening and closing of each switch when VGHO1 and VGHO2 are shared in the driving circuit shown;

[0036] Figure 3b is Figure 3 a timing chart of the opening and closing of each switch when VGH, VGHO1, and VGHO2 are shared in the driving circuit shown;

[0037] Figure 3c is Figure 3 a timing chart of the opening and closing of each switch when VGH and VGHO2 are shared in the driving circuit shown;

[0038] Figure 4 FIG. is a schematic diagram of a driving circuit for abnormal power-off of a display panel provided by the second embodiment of the present invention;

[0039] Figure 4a is Figure 4 a timing chart of the opening and closing of each switch when VGHO1 and VGHO2 are shared in the driving circuit shown;

[0040] Figure 4b is Figure 4 a timing chart of the opening and closing of each switch when VGH, VGHO1, and VGHO2 are shared in the driving circuit shown;

[0041] Figure 4c is Figure 4The on-off timing table of each switch when VGH and VGHO1 are shared in the shown driving circuit;

[0042] Figure 5 The structural schematic diagram of a driving circuit for abnormal power-off of a display panel provided in the third embodiment of the present invention;

[0043] Figure 5a is Figure 5 The on-off timing table of each switch when VGHO1 and VGHO2 are shared in the shown driving circuit;

[0044] Figure 5b is Figure 5 The on-off timing table of each switch when VGH, VGHO1 and VGHO2 are shared in the shown driving circuit;

[0045] Figure 5c is Figure 5 The on-off timing table of each switch when VGH and VGHO1 are shared in the shown driving circuit;

[0046] Figure 5d is Figure 5 The on-off timing table of each switch when VGH and VGHO2 are shared in the shown driving circuit;

[0047] Figure 6 The schematic diagram of the signal intensity and time curves in the power-off process of an IGZO display panel provided in an embodiment of the present invention;

[0048] Figure 7 The flow schematic diagram of a driving method for a driving circuit of abnormal power-off of a display panel provided in an embodiment of the present invention;

[0049] Figure 8 The schematic diagram of the power-off stage curves of VGHO1 and VGHO2 in the prior art;

[0050] Figure 9 The schematic diagram of the power-off stage curves of VGHO1 and VGHO2 provided in an embodiment of the present invention. Detailed implementation manners

[0051] The following further describes in detail a driving circuit and a driving method for improving abnormal power-off voltage proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are in a very simplified form and use non-precise scales, only for the purpose of facilitating and clearly assisting in explaining the embodiments of the present invention. In order to make the objectives, features, and advantages of the present invention more obvious and understandable, please refer to the accompanying drawings. It should be known that the structures, scales, sizes, etc. shown in the drawings of this specification are only used to cooperate with the content disclosed in the specification for those skilled in this technology to understand and read, and are not used to limit the limiting conditions for the implementation of the present invention. Therefore, they do not have technical essential meanings. Any modification of the structure, change of the proportional relationship, or adjustment of the size, without affecting the effects that the present invention can produce and the objectives that can be achieved, should still fall within the scope covered by the technical content disclosed by the present invention.

[0052] The display device may be a liquid crystal display device. A liquid crystal display device in which switching transistors are formed in each pixel distributed in a matrix form in a liquid crystal panel is now widely used. A gate driving circuit, a source driving circuit, and a pixel array are usually provided in the liquid crystal display device. A plurality of pixel circuits are provided in the pixel array. Each pixel circuit is turned on and off according to a scanning signal provided by the gate driving circuit (GATE driving line), and displays a data picture according to a data signal provided by the source driving circuit (Source driving line).

[0053] The pixel circuit of the liquid crystal panel is composed of a pixel electrode connected to the data signal line Data, a common electrode VCOM (VCOM electrode line), a gate signal line GATE of the switching transistor, a liquid crystal capacitor, a storage capacitor, etc. The liquid crystal molecules are controlled by the gate signal to control the rotation angle of the liquid crystal molecules through the electric field formed by applying voltages to the liquid crystal capacitor through the pixel electrode and the common electrode voltage VCOM respectively, so as to realize the display of a single liquid crystal pixel. The storage capacitor is mainly used to maintain the normal display of the previous row of images for one frame time during the progressive scanning of the gate driving signal.

[0054] Currently, the driving of the horizontal scanning lines of the liquid crystal panel is realized by an external integrated circuit. The external integrated circuit can control the progressive opening of each level of row scanning lines. By using the GOA (Gate Driver on Array) method, the row scanning driving circuit can be integrated on the display panel substrate, which can reduce the number of external ICs, thereby reducing the production cost of the display panel, and can realize the narrow bezel of the display device.

[0055] Generally, metal traces and GOA circuits are provided in the border area of the display panel. Signal lines such as CK1, CK2, VGH, and VGL are provided in the metal trace area. CK1 and CK2 are high-frequency alternating current signals, and VGH and VGL are direct current signal sources.

[0056] As Figure 1 shown, this embodiment provides a driving circuit for boosting the abnormal power-off voltage, which is applied to a display device. The driving circuit includes: a voltage generation unit 100; a discharging unit 200, where the discharging unit 200 includes at least two parallel discharging circuits (i.e., the discharging unit 200 may include n discharging circuits, where n≥2, which can be referred to the reference numerals 201-20n shown in the appendix Figure 1 ), the input end of the discharging unit 200 is electrically connected to the output end of the voltage generation unit 100; a plurality of capacitor units, the plurality of capacitor units includes a first capacitor unit (which can be referred to the reference numerals 2011-201n shown in the appendix Figure 1 ), and each discharging circuit includes the first capacitor unit; wherein, when the display device has an abnormal power-off, the first capacitor unit of at least one discharging circuit in the discharging unit 200 shares with one or more other capacitor units in the driving circuit.

[0057] When the display device has an abnormal power-off (BOR trigger), the first capacitor unit of at least one discharging circuit in the discharging unit provided in this embodiment shares with one or more other capacitor units in the driving circuit, so that different driving loads corresponding to different discharging circuits can reach the required peak voltage level. Thus, this embodiment can achieve improving the voltage driving ability of the driving circuit when the display device has an abnormal power-off without increasing the capacitance value of the off-chip capacitor and the number of off-chip capacitors, and saves costs.

[0058] In this embodiment, the display device is an IGZO display panel, but the present invention is not limited thereto.

[0059] In this embodiment, please continue to refer to Figure 1 shown, the manner in which the first capacitor unit of at least one discharging circuit in the discharging unit 200 shares with other capacitor units in the driving circuit includes: (1) in the discharging unit 200, the first capacitor unit of one discharging circuit shares with the first capacitor unit of the remaining one or more discharging circuits. For example, in the discharging unit 200, the first capacitor unit 2011 of the first discharging circuit 201 shares with the first capacitor unit (which can be referred to the reference numerals 2012-201n shown in the appendix Figure 1 ) of the remaining one or more discharging circuits (which can be referred to the reference numerals 202-20n shown in the appendix Figure 1 ).

[0060] Without increasing the capacitance value of the off-chip capacitor and increasing the number of off-chip capacitors, different driving loads corresponding to different discharge circuits can reach the required peak voltage level. This improves the voltage driving ability of the driving circuit and saves costs.

[0061] In this embodiment or some other embodiments, please continue to refer to Figure 1 As shown, the driving circuit further includes: a voltage regulating unit 300, an input end of the voltage regulating unit 300 is electrically connected to an output end of the voltage generating unit 100, and an input end of the discharging unit 200 is electrically connected to the output end of the voltage generating unit 100 through the voltage regulating unit 300.

[0062] The plurality of capacitor units further includes a second capacitor unit 210. One end of the second capacitor unit 210 is coupled to the output end of the voltage generating unit 100, and the other end is grounded; or one end of the second capacitor unit 210 is coupled to the input end of the voltage regulating unit 300, and the other end is grounded.

[0063] In this embodiment or some other embodiments, please continue to refer to Figure 1 As shown, the way that the first capacitor unit of at least one discharge circuit in the discharging unit 200 shares with other capacitor units in the driving circuit further includes:

[0064] (2) In the discharging unit 200, the first capacitor unit of one of the discharge circuits shares with the second capacitor unit 210. For example, the first capacitor unit 2011 of the first discharge circuit 201 shares with the second capacitor unit 210.

[0065] (3) The first capacitor unit of one of the discharge circuits shares with the first capacitor units of the other one or more discharge circuits and also shares with the second capacitor unit 210 at the same time.

[0066] For example, the first capacitor unit 2011 of the first discharge circuit 201 shares with the first capacitor units (which can be referred to the reference numerals 2012 to 201n shown in the appendix) of the other one or more discharge circuits (which can be referred to the reference numerals 202 to 20n shown in the appendix) and also shares with the second capacitor unit 210 at the same time. Figure 1 in the appendix Figure 1 in the appendix

[0067] Without increasing the capacitance value of the off-chip capacitor and increasing the number of off-chip capacitors, different driving loads corresponding to different discharge circuits can reach the required peak voltage level. This improves the voltage driving ability of the driving circuit and saves costs.

[0068] In this embodiment or some other embodiments, please continue to refer to Figure 1 As shown, the driving circuit further includes: a plurality of control units, the plurality of control units including a first control unit 401, and the first control unit 401 is configured to control whether at least one of the discharge circuits in the discharge unit 200 is connected in parallel with one or more other discharge circuits in the discharge unit 200, so as to realize whether the first capacitor unit of one of the discharge circuits in the discharge unit 200 shares with the first capacitor units of the other one or more discharge circuits.

[0069] In this embodiment or some other embodiments, please continue to refer to Figure 1 As shown, in the discharge unit 200, the first control unit 401 includes a plurality of first sub-control units, and at least one of the discharge circuits includes the first sub-control unit. The plurality of control units further includes a second control unit 402, and the second control unit 402 is configured to control whether the second capacitor unit 210 shares with the first capacitor unit when an abnormal power-off occurs.

[0070] In this embodiment or some other embodiments, please continue to refer to Figure 1 As shown, the plurality of control units further includes a third control unit 403, and the third control unit 403 includes a plurality of third sub-control units (which can be referred to the reference numerals 4031 to 403n shown in the appendix Figure 1 ), and each discharge circuit includes one of the third sub-control units, and the third control unit is configured to control whether the discharge circuit in the discharge unit 200 starts the discharge stage.

[0071] In this embodiment, the capacitance values of the first capacitor units of different discharge circuits are the same or different.

[0072] In this embodiment or some other embodiments, the driving circuit further includes: an abnormal power-off determination unit, and the abnormal power-off determination unit is configured to monitor whether the abnormal power-off occurs and determine whether the display device has an abnormal power-off according to a preset determination criterion.

[0073] By monitoring the power supply voltage of the external power supply of the display device (commonly, such as: AVDD / AVEE / IOVCC) through the abnormal power-off determination unit, if the power supply voltage is zero or not within the normal value range for a certain period of time, it is determined that the display device has an abnormal power-off.

[0074] In this embodiment or some other embodiments, please continue to refer to Figure 1 As shown, each discharge circuit 201 includes a resistance unit (which can be referred to the appendix Figure 1(indicated by reference numerals 2021 to 202n), and whether the resistance unit is used for discharging during the discharging stage is controlled by a third control unit.

[0075] In this embodiment or some other embodiments, the resistance values of the resistance units in different discharge circuits are not equal. Different discharge circuits thus formed can discharge at different discharge slopes.

[0076] In this embodiment or some other embodiments, the first capacitor unit is disposed inside or outside the driving chip of the display device, and the resistance unit is disposed inside or outside the driving chip of the display device, and can be appropriately adjusted according to the requirements of the chip size.

[0077] On the other hand, as Figure 2 shown, based on the driving circuit for improving the abnormal power-off voltage provided in the above embodiment, this embodiment further provides a driving method for a driving circuit, including the following steps:

[0078] Step 1: Abnormal power-off determination;

[0079] The abnormal power-off determination unit monitors whether the abnormal power-off occurs and outputs a determination result. If the determination result is that no abnormal power-off occurs, it returns to normal display.

[0080] If the determination result is that an abnormal power-off occurs, it enters Step 2: Abnormal power-off discharge process.

[0081] Step 2: Abnormal power-off discharge process;

[0082] S1: Peak voltage level matching stage; for one or more discharge circuits, several control units are controlled according to the timing signal to enable the first capacitor unit of at least one discharge circuit to be shared with other capacitor units in the driving circuit, so as to match the peak voltage levels required by different driving loads corresponding to different discharge circuits.

[0083] S2: Discharging stage; several control units are controlled according to the timing signal to ground each of the discharge circuits through the resistance unit.

[0084] S3: Discharge end stage; enter the free power-off mode, and after the charge of the display device is exhausted, the abnormal power-off discharge process is completed.

[0085] In this embodiment, by sharing multiple capacitor units provided in the driving circuit, different driving loads corresponding to different discharge circuits can reach the required peak voltage levels, improving the voltage driving ability of the driving circuit and saving costs.

[0086] In this embodiment, during normal display or abnormal power-off determination, the third control unit among the several control units remains disconnected.

[0087] In this embodiment, during the peak voltage level matching stage, the third control unit among the several control units remains disconnected, and controls the conduction of the first sub-control units in an appropriate number of the discharge circuits, and / or the conduction of the second control unit, so as to meet the peak voltage level requirements for different driving loads corresponding to different discharge circuits.

[0088] In this embodiment, during the discharge stage, the third control unit among the several control units is switched from disconnected to conducting, and the other control units among the several control units are switched from conducting to disconnected.

[0089] The following further details a driving circuit and a driving method proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer.

[0090] First Embodiment

[0091] Preferably, in order to reduce the complexity of control and improve the layout utilization rate, at least one path of the discharge circuit can be set not to include the first sub-control unit. As Figure 3 shown, the driving circuit for improving the abnormal power-off voltage provided in this embodiment is applied to a display device and includes:

[0092] A voltage generating unit, in this embodiment, the voltage generating unit is a boost circuit for generating a first voltage VGH.

[0093] A discharge unit, taking two discharge circuits connected in parallel as an example, which are called the first discharge circuit and the second discharge circuit.

[0094] The first discharge circuit includes: a first sub-control unit, a first capacitor unit, a first resistor unit, and a third sub-control unit.

[0095] In this embodiment, the first sub-control unit is the fourth switch SW4; the first capacitor unit is the first voltage stabilizing capacitor C1; the first resistor unit is the first resistor R1; the third sub-control unit is the second switch SW2.

[0096] The second discharge circuit includes: a first capacitor unit, a second resistor unit, and another third sub-control unit among the third control units;

[0097] In this embodiment, the first capacitor unit is the second voltage stabilizing capacitor C2; the second resistor unit is the second resistor R2; the another third sub-control unit is the third switch SW3.

[0098] The output terminal of the boost circuit is respectively connected to the fourth switch SW4 and the first terminal of the second voltage stabilizing capacitor C2; the second terminal of the fourth switch SW4 is connected to the first terminal of the first voltage stabilizing capacitor C1; the second terminal of the first voltage stabilizing capacitor C1 is grounded; the first terminal of the second switch SW2 is connected to the first terminal of the first voltage stabilizing capacitor C1, the second terminal of the second switch SW2 is connected to one end of the first resistor R1, and the other end of the first resistor R1 is grounded.

[0099] The second terminal of the second voltage stabilizing capacitor C2 is grounded; the first terminal of the third switch SW3 is connected to the first terminal of the second voltage stabilizing capacitor C2, the second terminal of the third switch SW3 is connected to one end of the second resistor R2, and the other end of the second resistor R2 is grounded.

[0100] Wherein, when an abnormal power failure occurs in the display device, the first voltage stabilizing capacitor C1 and the second voltage stabilizing capacitor C2 are shared. So that when an abnormal power failure occurs, different driving loads corresponding to the first and second discharge circuits can reach the required peak voltage level. Thus, in this embodiment, without increasing the capacitance value of the off-chip capacitor and the number of off-chip capacitors, when an abnormal power failure occurs in the display device, the voltage driving ability of the driving circuit is improved and the cost is saved.

[0101] Please continue to refer to Figure 3 As shown, in this embodiment, it further includes: a voltage regulation unit, which can be a low dropout linear regulator (LDO) for example. The input terminal of the low dropout linear regulator is electrically connected to the output terminal of the boost circuit, and the input terminal of the discharge unit is electrically connected to the output terminal of the boost circuit through the low dropout linear regulator.

[0102] The low dropout linear regulator is used to adjust and process the first voltage VGH and output a second voltage VGHO.

[0103] Please continue to refer to Figure 3 As shown, in this embodiment, it further includes: a second control unit, which is the first switch SW1 and is connected in parallel across the low dropout linear regulator. A second capacitor unit, which is the third voltage stabilizing capacitor C3. The first terminal of the third voltage stabilizing capacitor C3 is connected to the input terminal of the low dropout linear regulator, and the second terminal of the third voltage stabilizing capacitor C3 is grounded.

[0104] As Figure 3a As shown, when the display device is in the BOR trigger state, the power-off process of the display device is divided into stages T1 to T4.

[0105] In the T1 stage, it is the BOR trigger determination stage, and the opening and closing states of the first switch SW1 to the fourth switch SW4 are the same as those when the display device is normally displaying.

[0106] In the T2 stage, the first switch SW1, the second switch SW2, and the third switch SW3 are turned off, and the fourth switch SW4 is turned on. At this time, the first driving voltage VGHO1 output by the first voltage stabilizing capacitor C1 and the second driving voltage VGHO2 output by the second voltage stabilizing capacitor C2 are shared to match the peak voltage levels required by different driving loads corresponding to different discharge circuits.

[0107] Or, as Figure 3b shown, in the T2 stage, the second switch SW2 and the second switch SW3 are both turned off, and the first switch SW1 and the fourth switch SW4 are both turned on.

[0108] At this time, the third voltage stabilizing capacitor C3 is directly connected to the discharge unit;

[0109] The first voltage VGH output by the third voltage stabilizing capacitor C3, the first driving voltage VGHO1 output by the first voltage stabilizing capacitor C1, and the second driving voltage VGHO2 output by the second voltage stabilizing capacitor C2 are shared to match the peak voltage levels required by different driving loads corresponding to different discharge circuits.

[0110] Or, as Figure 3c shown, in the T2 stage, the second switch SW2, the second switch SW3, and the fourth switch SW4 are all turned off, and the first switch SW1 is turned on. At this time, the third voltage stabilizing capacitor C3 is directly connected to the discharge unit. The first voltage VGH output by the third voltage stabilizing capacitor C3 and the second driving voltage VGHO2 output by the second voltage stabilizing capacitor C2 are shared to match the peak voltage levels required by different driving loads corresponding to different discharge circuits.

[0111] In this embodiment, the peak voltage is greater than or equal to 10V.

[0112] In the T3 stage, the first switch SW1 and the fourth switch SW4 are both turned off, the second switch SW2 and the third switch SW3 are both turned on, the first voltage stabilizing capacitor C1 is connected to the first resistor R1 to form the first discharge circuit, and the first driving voltage VGHO1 is powered off through the first discharge circuit; the second voltage stabilizing capacitor C2 is connected to the second resistor R2 to form the second discharge circuit, and the second driving voltage VGHO1 is powered off through the second discharge circuit; the first driving voltage VGHO1 and the second driving voltage VGHO2 are powered off at different slopes.

[0113] That is, the discharge time constant of the first discharge circuit is R1C1, where R1 represents the resistance value of the first resistor and C1 represents the capacitance value of the first voltage stabilizing capacitor; and the discharge time constant of the second discharge circuit is R2C2, where R2 represents the resistance value of the second resistor and C2 represents the capacitance value of the second voltage stabilizing capacitor; different discharge time constants of the two are used to achieve different discharge slopes, so as to meet the discharge requirements of the display device.

[0114] In the T4 stage, the first switch SW1 to the fourth switch SW4 are all turned off, and the power-off of the display device is completed.

[0115] Such as Figures 3 to 3b As shown, in the T0 stage, that is, the normal display stage of the display device, the first switch SW1, the second switch SW2, and the third switch SW3 are all turned off, and the fourth switch SW4 is closed. The first driving voltage VGHO1 = the second driving voltage VGHO2 = the second voltage VGHO ≠ the first voltage VGH; thus to meet the voltage level required for the GOA signal in the display device to drive the scanning GATE driving line.

[0116] Or, as Figures 3 to 3b As shown, in the T0 stage, the first switch SW1 and the fourth switch SW4 are both closed, the second switch SW2 and the third switch SW3 are both turned off, and the first driving voltage VGHO1 = the second driving voltage VGHO2 = the second voltage VGHO = the first voltage VGH; thus to meet the voltage level required for the GOA signal in the display panel to drive the scanning GATE driving line.

[0117] Second Embodiment

[0118] Preferably, in order to reduce the complexity of control and improve the layout utilization rate, at least one path of the discharge circuit can be set not to include the first sub-control unit. Such as Figure 4 As shown, the driving circuit for improving the abnormal power-off voltage provided in this embodiment is applied to a display device and includes:

[0119] A voltage generation unit. In this embodiment, the voltage generation unit is a boost circuit for generating a first voltage VGH.

[0120] A discharge unit. The discharge unit includes two parallel discharge circuits, which are called the first discharge circuit and the second discharge circuit.

[0121] The first discharge circuit includes: a first capacitor unit, a first resistor unit, and a third sub-control unit.

[0122] In this embodiment, the first capacitor unit is the first voltage-stabilizing capacitor C1; the first resistor unit is the first resistor R1; the third sub-control unit is the second switch SW2.

[0123] The second discharge circuit includes: another third sub-control unit among the first sub-control unit, the first capacitor unit, the second resistor unit, and the third control unit.

[0124] In this embodiment, the other first sub-control unit is the fifth switch SW5; the first capacitor unit is the second voltage-stabilizing capacitor C2; the second resistor unit is the second resistor R2; the third sub-control unit is the third switch SW3.

[0125] The output terminal of the boost circuit is connected to the first terminal of the fifth switch SW5 and the first terminal of the first voltage-stabilizing capacitor C1; the second terminal of the first voltage-stabilizing capacitor C1 is grounded; the first terminal of the second switch SW2 is connected to the first terminal of the first voltage-stabilizing capacitor C1, the second terminal of the second switch SW2 is connected to one end of the first resistor R1, and the other end of the first resistor R1 is grounded.

[0126] The second terminal of the fifth switch SW5 is connected to the first terminal of the second voltage-stabilizing capacitor C2; the second terminal of the second voltage-stabilizing capacitor C2 is grounded; the first terminal of the third switch SW3 is connected to the first terminal of the second voltage-stabilizing capacitor C2, the second terminal of the third switch SW3 is connected to one end of the second resistor R2, and the other end of the second resistor R2 is grounded.

[0127] Wherein, when the display device has an abnormal power-off, the first voltage-stabilizing capacitor C1 and the second voltage-stabilizing capacitor share. So that different driving loads corresponding to different first and second discharge circuits can reach the required peak voltage level. Thus, this embodiment can achieve improving the voltage driving ability of the driving circuit and saving costs when the display device has an abnormal power-off without increasing the capacitance value of the off-chip capacitor and the number of off-chip capacitors.

[0128] Please continue to refer to Figure 4 As shown, in this embodiment, it further includes: a voltage regulation unit, the voltage regulation unit can be, for example, a low-dropout linear regulator, the input terminal of the low-dropout linear regulator is electrically connected to the output terminal of the boost circuit, and the input terminal of the discharge unit is electrically connected to the output terminal of the boost circuit through the low-dropout linear regulator.

[0129] The low-dropout linear regulator is used to adjust and process the first voltage VGH and output a second voltage VGHO.

[0130] Please continue to refer to Figure 4As shown, in this embodiment, it further includes: a second control unit, where the second control unit is a first switch SW1, which is connected in parallel across the low dropout linear regulator. A second capacitor unit, where the second capacitor unit is a third voltage stabilizing capacitor C3, and a first end of the third voltage stabilizing capacitor C3 is connected to an input end of the low dropout linear regulator, and a second end of the third voltage stabilizing capacitor C3 is grounded.

[0131] As Figure 4a shown, when the display device is in the BOR trigger state, the power-down process of the display device is divided into stages T1 to T4;

[0132] In stage T1, which is a BOR trigger determination stage, the opening and closing states of the first switch SW1 to the third switch SW3 and the fifth switch SW5 are the same as when the display device is normally displaying.

[0133] In stage T2, the first switch SW1, the second switch SW2, and the third switch SW3 are all turned off, and the fifth switch SW5 is turned on. At this time, the first driving voltage VGHO1 output by the first voltage stabilizing capacitor C1 and the second driving voltage VGHO2 output by the second voltage stabilizing capacitor C2 are shared to match the peak voltage levels required by different driving loads corresponding to different discharge circuits.

[0134] Or, as Figure 4b shown, in stage T2, the second switch SW2 and the second switch SW3 are both turned off, and the first switch SW1 and the fifth switch SW5 are both turned on.

[0135] At this time, the third voltage stabilizing capacitor C3 is directly connected in parallel with the first voltage stabilizing capacitor C1 and the second voltage stabilizing capacitor C2. The first voltage VGH output by the third voltage stabilizing capacitor C3, the first driving voltage VGHO1 output by the first voltage stabilizing capacitor C1, and the second driving voltage VGHO2 output by the second voltage stabilizing capacitor C2 are shared to match the peak voltage levels required by different driving loads corresponding to different discharge circuits.

[0136] Or, as Figure 4c shown, in stage T2, the second switch SW2, the second switch SW3, and the fifth switch SW5 are all turned off, and the first switch SW1 is turned on.

[0137] At this time, the third voltage stabilizing capacitor C3 is connected in parallel with the first voltage stabilizing capacitor C1. The first voltage VGH output by the third voltage stabilizing capacitor C3 and the first driving voltage VGHO1 output by the first voltage stabilizing capacitor C1 are shared to match the peak voltage levels required by different driving loads corresponding to different discharge circuits.

[0138] In this embodiment, the peak voltage is greater than or equal to 10V.

[0139] Combined with Figures 4 to 4b As shown, in stage T3, the first switch SW1 and the fifth switch SW5 are both turned off, the second switch SW2 and the third switch SW3 are both turned on, the first voltage stabilizing capacitor C1 is connected to the first resistor R1 to form the first discharge circuit, and the first driving voltage VGHO1 discharges through the first discharge circuit; the second voltage stabilizing capacitor C2 is connected to the second resistor R2 to form the second discharge circuit, and the second driving voltage VGHO1 discharges through the second discharge circuit; the first driving voltage VGHO1 and the second driving voltage VGHO2 drop in voltage at different slopes.

[0140] That is, the discharge time constant of the first discharge circuit is R1C1, where R1 represents the resistance value of the first resistor and C1 represents the capacitance value of the first voltage stabilizing capacitor; and the discharge time constant of the second discharge circuit is R2C2, where R2 represents the resistance value of the second resistor and C2 represents the capacitance value of the second voltage stabilizing capacitor; the different discharge time constants of the two are used to achieve different discharge slopes, so as to meet the discharge requirements of the display device.

[0141] In stage T4, the first switch SW1 to the third switch SW3 and the fifth switch SW5 are all turned off, and the power-off of the display device is completed.

[0142] Combined with Figures 4 to 4b As shown, in stage T0, that is, the normal display stage of the display device, the first switch SW1, the second switch SW2 and the third switch SW3 are all turned off, the fifth switch SW5 is turned on, and the first driving voltage VGHO1 = the second driving voltage VGHO2 = the second voltage VGHO ≠ the first voltage VGH; thus to meet the voltage level required for the GOA signal in the display device to drive the scanning GATE driving line.

[0143] Or, combined with Figures 4 to 4b As shown, in stage T0, the first switch SW1 and the fifth switch SW5 are both turned on, the second switch SW2 and the third switch SW3 are both turned off, and the first driving voltage VGHO1 = the second driving voltage VGHO2 = the second voltage VGHO = the first voltage VGH; thus to meet the voltage level required for the GOA signal in the display device to drive the scanning GATE driving line.

[0144] Third Embodiment

[0145] Preferably, each discharge circuit includes a first sub-control unit, thereby further improving the flexibility of sharing. As Figure 5As shown, the driving circuit for increasing the abnormal power-off voltage provided in this embodiment is applied to a display device and includes:

[0146] A voltage generating unit. In this embodiment, the voltage generating unit is a boost circuit for generating a first voltage VGH.

[0147] A discharging unit. The discharging unit includes two parallel discharging circuits, referred to as a first discharging circuit and a second discharging circuit.

[0148] The first discharging circuit includes: a first sub-control unit in the first control unit, a first capacitor unit, a first resistor unit, and a third sub-control unit.

[0149] In this embodiment, the first sub-control unit is a fourth switch SW4; the first capacitor unit is a first voltage-stabilizing capacitor C1; the first resistor unit is a first resistor R1; the third sub-control unit is a second switch SW2.

[0150] The second discharging circuit includes: another first sub-control unit in the first control unit, a first capacitor unit, a second resistor unit, and another third sub-control unit in the third control unit.

[0151] In this embodiment, the other first sub-control unit is a fifth switch SW5; the first capacitor unit is a second voltage-stabilizing capacitor C2; the second resistor unit is a second resistor R2; the other third sub-control unit is a third switch SW3.

[0152] The output terminal of the boost circuit is respectively connected to the first ends of the fourth switch SW4 and the fifth switch SW5.

[0153] The second end of the fourth switch SW4 is connected to the first end of the first voltage-stabilizing capacitor C1, and the second end of the first voltage-stabilizing capacitor C1 is grounded; the first end of the second switch SW2 is connected to the first end of the first voltage-stabilizing capacitor C1, the second end of the second switch SW2 is connected to one end of the first resistor R1, and the other end of the first resistor R1 is grounded.

[0154] The second end of the fifth switch SW5 is connected to the first end of the second voltage-stabilizing capacitor C2, and the second end of the second voltage-stabilizing capacitor C2 is grounded; the first end of the third switch SW3 is connected to the first end of the second voltage-stabilizing capacitor C2, the second end of the third switch SW3 is connected to one end of the second resistor R2, and the other end of the second resistor R2 is grounded.

[0155] Among them, when the display device experiences abnormal power-off, the first voltage stabilizing capacitor C1 and the second voltage stabilizing capacitor C2 are shared, enabling different driving loads corresponding to different first and second discharge circuits to reach the required peak voltage level. Thus, in this embodiment, without increasing the capacitance value of off-chip capacitors or the number of off-chip capacitors, when the display device experiences abnormal power-off, the voltage driving ability of the driving circuit is improved, and costs are saved.

[0156] Please continue to refer to Figure 5 As shown, in this embodiment, it further includes: a voltage regulation unit, which can be, for example, a low dropout linear regulator. The input end of the low dropout linear regulator is electrically connected to the output end of the boost circuit, and the input end of the discharge unit is electrically connected to the output end of the boost circuit through the low dropout linear regulator.

[0157] The low dropout linear regulator is used to adjust and process the first voltage VGH and output a second voltage VGHO.

[0158] Please continue to refer to Figure 5 As shown, in this embodiment, it further includes: a second control unit, which is a first switch SW1 and is connected in parallel across the low dropout linear regulator. A second capacitor unit, which is a third voltage stabilizing capacitor C3. The first end of the third voltage stabilizing capacitor C3 is connected to the input end of the low dropout linear regulator, and the second end of the third voltage stabilizing capacitor C3 is grounded.

[0159] Combined with Figures 5 to 5b As shown, when the display device is in the BOR trigger state, the power-off process of the display device is divided into stages T1 to T4.

[0160] In stage T1, it is the BOR trigger determination stage, and the opening and closing states of the first switch SW1 to the fifth switch SW5 are the same as when the display device is normally displaying.

[0161] As Figure 5a As shown, in stage T2, the first switch SW1 to the third switch SW3 are all turned off, and the fourth switch SW4 and the fifth switch SW5 are both turned on; at this time, the first driving voltage VGHO1 output by the first voltage stabilizing capacitor C1 and the second driving voltage VGHO2 output by the second voltage stabilizing capacitor C2 are shared to match the peak voltage levels required by different driving loads corresponding to different discharge circuits.

[0162] Or, as Figure 5bAs shown, in the T2 stage, the second switch SW2 and the third switch SW3 are both turned off, and the first switch SW1, the fourth switch SW4, and the fifth switch SW5 are all turned on. At this time, the third voltage stabilizing capacitor C3 is connected in parallel with the first voltage stabilizing capacitor C1 and the second voltage stabilizing capacitor C2. The first voltage VGH output by the third voltage stabilizing capacitor C3, the first driving voltage VGHO1 output by the first voltage stabilizing capacitor C1, and the second driving voltage VGHO2 output by the second voltage stabilizing capacitor C2 are shared to match the peak voltage levels required by different driving loads corresponding to different discharge circuits.

[0163] Or, as Figure 5c shown, in the T2 stage, the second switch SW2, the third switch SW3, and the fifth switch SW5 are all turned off, and the first switch SW1 and the fourth switch SW4 are both turned on. At this time, the third voltage stabilizing capacitor C3 is connected in parallel with the first voltage stabilizing capacitor C1. The first voltage VGH output by the third voltage stabilizing capacitor C3 and the first driving voltage VGHO1 output by the first voltage stabilizing capacitor C1 are shared to match the peak voltage levels required by different driving loads corresponding to different discharge circuits.

[0164] Or, as Figure 5d shown, in the T2 stage, the second switch SW2, the third switch SW3, and the fourth switch SW4 are all turned off, and the first switch SW1 and the fifth switch SW5 are both turned on. At this time, the third voltage stabilizing capacitor C3 is connected in parallel with the second voltage stabilizing capacitor C2. The first voltage VGH output by the third voltage stabilizing capacitor C3 and the first driving voltage VGHO2 output by the second voltage stabilizing capacitor C2 are used to match the peak voltage levels required by different driving loads corresponding to different discharge circuits.

[0165] In this embodiment, the peak voltage is greater than or equal to 10V.

[0166] Combined with Figures 5 to 5b shown, in the T3 stage, the first switch SW1, the fourth switch SW4, and the fifth switch SW5 are all turned off, and the second switch SW2 and the third switch SW3 are both turned on. The first voltage stabilizing capacitor C1 is connected to the first resistor R1 to form the first discharge circuit, and the first driving voltage VGHO1 discharges through the first discharge circuit. The second voltage stabilizing capacitor C2 is connected to the second resistor R2 to form the second discharge circuit, and the second driving voltage VGHO1 discharges through the second discharge circuit; the first driving voltage VGHO1 and the second driving voltage VGHO2 drop in voltage at different slopes.

[0167] That is, the discharge time constant of the first discharge circuit is R1C1, where R1 represents the resistance value of the first resistor and C1 represents the capacitance value of the first voltage stabilizing capacitor; and the discharge time constant of the second discharge circuit is R2C2, where R2 represents the resistance value of the second resistor and C2 represents the capacitance value of the second voltage stabilizing capacitor; different discharge slopes are achieved by the different discharge time constants of the two, so as to meet the discharge requirements of the display device.

[0168] Combined with Figures 5 to 5b As shown, in stage T4, the first switch SW1 to the fifth switch SW5 are all turned off, and the power-off of the display panel is completed.

[0169] Combined with Figures 5 to 5b As shown, in this embodiment, in stage T0, that is, during the normal display stage of the display device, the first switch SW1 to the third switch SW3 are all turned off, the fourth switch SW4 and the fifth switch SW5 are both turned on, and the first driving voltage VGHO1 = the second driving voltage VGHO2 = the second voltage VGHO ≠ the first voltage VGH; thus meeting the voltage level required for the signal to drive and scan the GATE driving line in the GOA circuit of the display device.

[0170] Or, combined with Figures 5 to 5b As shown, in this embodiment, in stage T0, the first switch SW1, the fourth switch SW4 and the fifth switch SW5 are turned on, the second switch SW2 and the third switch SW3 are turned off, and the first driving voltage VGHO1 = the second driving voltage VGHO2 = the second voltage VGHO = the first voltage VGH; thus meeting the voltage level required for the GOA signal to drive and scan the GATE driving line of the display device.

[0171] As Figure 6 shown, it is a schematic diagram of the signal intensity and time curves during the power-off process of the IGZO display panel provided by the present invention when an abnormal power-off occurs (taking the abnormal power-off in the case of forced shutdown as an example); it is described based on the first to third embodiments Figure 6 as follows:

[0172] Generally, the loads connected to the first voltage stabilizing capacitor C1 include: GATE driving lines in the liquid crystal panel, CLR * signal lines (clear signal lines), etc.

[0173] The loads connected to the second voltage stabilizing capacitor C2 include: GATE driving lines in the liquid crystal panel; GCK (CK * ) signal lines (clock signals of GATE driving signals), VGL (VSS) signal lines (ground lines of the liquid crystal panel), etc. Among them,

[0174] In the t1 stage, all voltage signals in the load connected to the first voltage stabilizing capacitor C1 and the second voltage stabilizing capacitor C2 are in a normal driving state. The Source voltage signal in the Source driving line in the liquid crystal panel, and the pixel electrode and common electrode voltage signal VCOM are also in a normal driving state.

[0175] In the t2 stage, when abnormal power-off starts, through any combination of the first voltage stabilizing capacitor C1, the second voltage stabilizing capacitor C2, and the third voltage stabilizing capacitor C3, the peak voltages of the GCK voltage signal, the VGL voltage signal, and the CLR* voltage signal are raised to more than 10V. That is, all voltage signals in the load connected to the first voltage stabilizing capacitor C1 and the second voltage stabilizing capacitor C2 still remain in a normal driving state. At this time, the Source voltage signal in the Source driving line in the liquid crystal panel, and the pixel electrode and common electrode voltage signal VCOM are both pulled to the GND level. Then, it enters the free power-off stage. After several milliseconds, the GCK voltage signal and the VGL voltage signal drop from the peak voltage to the GND level.

[0176] In the t3 stage, the charge clearing stage, due to the slower power-off rate of the CLR* voltage signal than that of the GCK voltage signal and the VGL voltage signal, it drops from the peak voltage to the GND level only in this stage. In this stage, the Source voltage signal in the Source driving line in the liquid crystal panel, and the pixel electrode and common electrode voltage signal VCOM still remain at the GND level.

[0177] As Figure 7 shown, this embodiment also provides a driving method for a driving circuit, which is implemented by using the driving circuits provided in the first to third embodiments; the driving method includes:

[0178] Step S11: By monitoring the power supply voltage of the external power supply of the display device, if abnormal power-off occurs, BOR is triggered, and after digital Debounce detection determines that after a certain threshold time, the signal triggered by BOR is sent out, and the BOR power-off process is officially entered; if the above conditions are not met, it returns to the normal display state.

[0179] Step S12: According to a predetermined timing, control the opening and closing of each switch in the driving circuit, so that in the BOR trigger stage, the first driving voltage VGHO1 output by the first voltage stabilizing capacitor C1 and the second driving voltage VGHO2 output by the second voltage stabilizing capacitor C2 share and jointly drive all GOA signals in the display device.

[0180] Alternatively, the first driving voltage VGHO1 output by the first voltage stabilizing capacitor C1 and the first voltage VGH output by the third voltage stabilizing capacitor C3 share to commonly drive all GOA signals in the display device.

[0181] Alternatively, according to a predetermined timing sequence, control the opening and closing of each switch in the driving circuit, such that during the BOR triggering stage, any one of the first driving voltage VGHO1 output by the first voltage stabilizing capacitor C1, the second driving voltage VGHO2 output by the second voltage stabilizing capacitor C2, and the first voltage VGH output by the third voltage stabilizing capacitor C3 shares to commonly drive all GOA signals in the display device.

[0182] Step S13: After all GOA signals in the display device are greater than the peak voltage, the first voltage stabilizing capacitor C1 and the second voltage stabilizing capacitor C2 are respectively connected to the ground through the first resistor R1 and the second resistor R2, so as to realize the power-off of the first driving voltage VGHO1 and the second driving voltage VGHO2 at different slopes.

[0183] Step S14: After discharging the charges on the display device, enter the free power-off stage, and all switches in the driving circuit are turned off, completing the power-off process.

[0184] The beneficial effects of the embodiments of the present disclosure are illustrated by the following examples:

[0185] As Figure 8 shown, it is a schematic diagram of the power-off stage curves of VGHO1 and VGHO2 in the prior art; among them, the loads connected to VGHO1 and VGHO2 are different, and the load of VGHO2 connected to GCK and VGL, etc., is larger. Typically, the load on the signal line of the GOA circuit of the liquid crystal panel, and the load capacitances of GCK and VGL are the largest, usually in the order of ~nF. Therefore, at the moment of BOR triggering, since the load connected to VGHO1 is lighter, it is easy to meet the requirement of the peak voltage Vpeak>10V; while the load connected to VGHO2 is larger, for the voltage level to be pulled up from the normal display VGLO (generally about -10V) to VGHO2 (required to be 10V+), which is about 20V, the amount of charge Q = C*△V needs to be provided, where △V = VGHO2 - VGL, and C represents the capacitance. However, in the existing driving circuit made, limited by requirements such as circuit size, during the process of pulling VGLO to VGHO2, the peak value of VGHO2 can only reach 7-8V; it cannot meet the design requirement of the peak voltage Vpeak>10V for all signals in the GOA circuit, and correspondingly in the appendix Figure 8 It can be seen that in the existing driving circuit, when abnormal power-off occurs, VGHO2 cannot guarantee the peak voltage level.

[0186] Figure 9 Schematic diagram of the power-down phase curves of VGHO1 and VGHO2 provided for one of the embodiments, for comparison Figure 8 and Figure 9 It can be seen that, compared with the prior art, in this embodiment, through any combination sharing of the first voltage-stabilizing capacitor C1, the second voltage-stabilizing capacitor C2, and the third voltage-stabilizing capacitor C3, the way of increasing the capacitor or replacing the original small capacitor with a large capacitor is avoided, so as to meet the design requirement that the peak voltage Vpeak of all signals in the GOA circuit is > 10V. Specifically, as Figure 9 shown, the load voltage VGHO2 connected to the second voltage-stabilizing capacitor C2 can reach the same peak voltage (greater than or equal to 10V) as the load voltage VGHO1 connected to the first voltage-stabilizing capacitor C1 at stage T2. Thus, not only the technical problem that the peak voltage cannot be guaranteed in the prior art is solved, but also the size of the driving circuit can be reduced. The advantages of the driving circuit provided by the present disclosure compared with the traditional driving circuit can be referred to as shown in Table 1. The capacitance value of the voltage-stabilizing capacitor of the driving circuit of the present disclosure is smaller than that of the prior art, which is beneficial to reducing the device size; when an abnormal power-down occurs, all loads can reach the peak voltage level through the shared capacitor. Moreover, to implement this embodiment, the modification to the existing driving circuit is small, the circuit structure is simple, which is beneficial to reducing the production cost.

[0187] Table 1 Comparison of the advantages and disadvantages between the traditional driving circuit and the driving circuit provided by this embodiment

[0188] Traditional method Method of the present invention Drive Vpeak voltage Approximately ~8V ～10V+ Capacitance value Large Small Volume (space requirement) Large Small Application cost High Low

[0189] In summary, through only the application of the added control unit and the corresponding control timing, the discharge circuit in the driving circuit of the present disclosure can share additional capacitors, realizing a higher and stronger driving-capability voltage output, so as to meet the voltage requirement for power-down screen clearing of the IGZO panel, and solve the problems of large off-chip capacitance value, large volume, and high cost brought by the traditional method.

[0190] It should be noted that, in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including a..." does not exclude the existence of additional identical elements in the process, method, article or device including the element.

[0191] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "center", "height", "thickness", "upper", "lower", "vertical", "horizontal", "top", "bottom", "inner", "outer", "axial", "radial", "circumferential", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present invention. In the description of the present invention, unless otherwise specified, the meaning of "a plurality of" is two or more than two.

[0192] In the description of the present invention, unless otherwise clearly defined and limited, the terms "mounted", "connected", "coupled", "fixed" shall be construed broadly. For example, it may be a fixed connection, a detachable connection, or integrated; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the internal communication of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0193] In the present invention, unless otherwise clearly defined and limited, the first feature being "above" or "below" the second feature may include the direct contact between the first and second features, or may include the situation where the first and second features are not in direct contact but in contact through additional features therebetween. Moreover, the first feature being "above", "over" and "on" the second feature includes that the first feature is directly above and obliquely above the second feature, or merely means that the horizontal height of the first feature is higher than that of the second feature. The first feature being "under", "beneath" and "under" the second feature includes that the first feature is directly below and obliquely below the second feature, or merely means that the horizontal height of the first feature is lower than that of the second feature.

[0194] Although the content of the present invention has been introduced in detail through the above preferred embodiments, it should be recognized that the above description should not be considered as a limitation to the present invention. After those skilled in the art have read the above content, various modifications and substitutions to the present invention will be obvious. Therefore, the protection scope of the present invention should be defined by the appended claims.

Claims

1. A driving circuit for increasing abnormal power-off voltage, applied to a display device, characterized in that: The driving circuit comprises: a voltage generating unit; A discharge unit, the discharge unit comprising at least two discharge circuits connected in parallel, the input end of the discharge unit being electrically connected to the output end of the voltage generating unit; A plurality of capacitor units, wherein the plurality of capacitor units include a first capacitor unit, and each of the discharge circuits includes the first capacitor unit; Wherein, when the display device experiences abnormal power failure, the first capacitor unit of at least one discharge circuit in the discharge unit is shared with one or more other capacitor units in the drive circuit.

2. The driving circuit according to claim 1, characterized in that: The manner in which the first capacitor unit of at least one discharge circuit in the discharge unit is shared with other capacitor units in the drive circuit includes: in the discharge unit, the first capacitor unit of one discharge circuit is shared with the first capacitor units of the remaining one or more discharge circuits.

3. The driving circuit for increasing abnormal power-off voltage according to claim 1 or 2, characterized in that: The driving circuit further includes: a voltage regulating unit, wherein an input end of the voltage regulating unit is electrically connected to an output end of the voltage generating unit, and an input end of the discharge unit is electrically connected to an output end of the voltage generating unit through the voltage regulating unit; The plurality of capacitor units further include a second capacitor unit, one end of the second capacitor unit is coupled to the output end of the voltage generating unit and the other end is grounded; or one end of the second capacitor unit is coupled to the input end of the voltage regulating unit and the other end is grounded.

4. The driving circuit for increasing abnormal power-off voltage according to claim 3, characterized in that: The manner in which the first capacitor unit of at least one discharge circuit in the discharge unit is shared with other capacitor units in the drive circuit includes: In the discharge unit, the first capacitor unit and the second capacitor unit of one discharge circuit are shared; Or, the first capacitor unit of one discharge circuit is shared with the first capacitor units of the remaining one or more discharge circuits and also shared with the second capacitor unit.

5. The driving circuit for increasing abnormal power-off voltage according to claim 1 or 3, characterized in that: The driving circuit further includes: A plurality of control units, wherein the plurality of control units include a first control unit, and the first control unit is used to control whether at least one discharge circuit in the discharge unit is connected in parallel with another one or more discharge circuits in the discharge unit.

6. The driving circuit for increasing abnormal power-off voltage according to claim 5, characterized in that: The first control unit includes a plurality of first sub-control units, and in the discharge unit, at least one discharge circuit includes the first sub-control unit.

7. The driving circuit for increasing abnormal power-off voltage according to claim 5, characterized in that: The plurality of control units further include a second control unit, and the second control unit is used to control whether the second capacitor unit is shared with the first capacitor unit when an abnormal power failure occurs.

8. The driving circuit for increasing abnormal power-off voltage according to claim 5, characterized in that: The plurality of control units further include a third control unit, and the third control unit is used to control whether the discharge circuit in the discharge unit starts a discharge phase.

9. The driving circuit for increasing abnormal power-off voltage according to claim 1, characterized in that: The capacitances of the first capacitor units in different discharge circuits are the same or different.

10. The driving circuit for increasing abnormal power-off voltage according to claim 1, characterized in that: The driving circuit further includes: an abnormal power failure determination unit, which is used to monitor whether the abnormal power failure occurs and determine whether the display device has an abnormal power failure according to a preset determination standard.

11. A driving circuit for boosting abnormal power-off voltage according to any one of the preceding claims, characterized in that: Each of the discharge circuits includes a resistor unit, and the resistor unit is controlled by the third control unit to be used for discharge in the discharge stage.

12. The driving circuit for increasing abnormal power-off voltage according to claim 11, characterized in that: The resistance values ​​of the resistance units in different discharge circuits are not equal.

13. The driving circuit for increasing abnormal power-off voltage according to claim 11, characterized in that: The first capacitor unit is disposed inside or outside the driving chip of the display device, and the resistor unit is disposed inside or outside the driving chip of the display device.

14. A driving method for a driving circuit for increasing abnormal power-off voltage according to any one of claims 1 to 13, characterized in that: Includes steps: Step 1: Abnormal power failure determination; The abnormal power failure determination unit monitors whether the abnormal power failure occurs and outputs a determination result. If the determination result is that the abnormal power failure does not occur, the normal display is restored; If the result of the determination is that an abnormal power failure has occurred, then the process proceeds to step 2: abnormal power failure discharge process; Step 2: Abnormal power-off discharge process; S1: Peak voltage level matching stage: for one or more discharge circuits, a plurality of control units are controlled according to the timing signal to achieve sharing of the first capacitor unit of at least one discharge circuit with other capacitor units in the driving circuit to match the peak voltage levels required by different driving loads corresponding to different discharge circuits; S2: Discharging stage; controlling a plurality of control units according to the timing signal to ground each of the discharge circuits through a resistor unit; S3: Discharge end stage; enter the free power-off mode, and complete the abnormal power-off discharge process after the charge of the display device is discharged.

15. The method according to claim 14, characterized in that In a normal display state or when abnormal power failure is determined, the third control unit among the plurality of control units remains disconnected.

16. The method according to claim 14, characterized in that During the peak voltage level matching stage, the third control unit among the plurality of control units remains disconnected, and controls the first control unit to select an appropriate number of first sub-control units to be turned on, and / or selects the second control unit to be turned on, so as to achieve the peak voltage level requirements required by different driving loads corresponding to different discharge circuits.

17. The method according to claim 14, characterized in that In the discharge stage, the third control unit among the plurality of control units is controlled to switch from off to on, and the other control units among the plurality of control units are controlled to switch from on to off.

Images