Goa driving circuit and method, cascaded circuit and display panel
By setting two pull-down units in the GOA drive circuit and performing two pull-down operations, the display panel's abnormal display problems caused by external environmental temperature, static electricity, or mechanical deformation are solved, thus improving display quality.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- TRULY (RENSHOU) HIGH-END DISPLAY TECH LTD
- Filing Date
- 2025-04-21
- Publication Date
- 2026-06-16
AI Technical Summary
In the prior art, when the display panel is exposed to low temperature, static electricity, external signal interference, or mechanical deformation, the GOA driving circuit outputs abnormally, resulting in display abnormalities.
Two pull-down units are set in the GOA driver circuit, and pull-down is performed twice in the two-row drive to ensure that the input level is completely pulled down.
It effectively avoids display abnormalities caused by external environmental temperature, static electricity, external signal interference, or mechanical deformation, thus improving display quality.
Smart Images
Figure CN120199199B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of display panel driving technology, and in particular to a GOA driving circuit and method, cascaded circuit and display panel. Background Technology
[0002] Gate-on-array (GOA) technology refers to integrating the gate driving circuit on the array substrate. It uses the same process as thin-film transistors to fabricate the line scanning driving circuit on the glass substrate. By directly integrating the circuitry controlling the gate onto the TFT-LCD panel, it achieves panel driving and display. This eliminates the need for traditional gate-on-array (COF) circuitry and improves module process yield.
[0003] Gate-of-Area (GOA) technology is favored by consumers because it can reduce the bezel of displays. However, since GOA technology places the gate-of-area (GOA) circuit on the display itself, it is susceptible to problems. When the display is in a low-temperature environment, the GOA circuit may not drive sufficiently, resulting in reduced transistor current and affecting the gate circuit's output (Gout). Additionally, when electrostatic discharge (ESD) occurs on the display, the gate circuit output may also become abnormal. Furthermore, external stresses, such as pressure or mechanical deformation of the display, can alter the characteristics of the TFTs in the GOA circuit, affecting the display's Gout output. Finally, external disturbances and signal interference can also affect the display's Gout output, leading to display abnormalities, impacting display quality, and reducing the user experience.
[0004] In summary, there is a need for a method that can avoid abnormal gate output (Gout) to improve display quality and enhance product competitiveness. Summary of the Invention
[0005] In existing technologies, when the display panel is affected by external environmental temperature, static electricity, external signal interference, or mechanical deformation, the GOA driving circuit outputs abnormally, which in turn leads to display abnormalities.
[0006] To address the aforementioned problems, a GOA driving circuit and method, a cascaded circuit, and a display panel are proposed. By setting two pull-down units in the GOA driving circuit and performing two pull-down operations on the current GOA driving circuit in the subsequent two rows of driving, the incomplete pull-down of the input level of the output unit of the GOA driving circuit is avoided. This solves the problem in the prior art where the display panel is affected by external environmental temperature, static electricity, external signal interference, or mechanical deformation, leading to display abnormalities. Firstly, a GOA driving circuit is provided for driving the corresponding nth row gate line, comprising:
[0007] Forward scan start unit, reverse scan start unit, first pull-down unit, second pull-down unit and output unit;
[0008] The output terminal of the forward scan start unit is connected to the output terminal of the reverse scan start unit, the first pull-down unit, the second pull-down unit, and the output unit.
[0009] The first pull-down unit is also electrically connected to the second pull-down unit, and the second pull-down unit is also electrically connected to the output unit;
[0010] The second pull-down unit is electrically connected to the output terminal of the output unit of the (n+1)th row gate line, and is used to pull down the input level of the output unit of the nth row gate line once when the (n+1)th row gate line is driven to output.
[0011] The first pull-down unit is electrically connected to the output terminal of the output unit of the (n+2)th row gate line, and is used to pull down the input terminal level of the output unit of the nth row gate line a second time when the (n+2)th row gate line is driven to output.
[0012] Where n is a natural number.
[0013] In conjunction with the GOA driving circuit described in the first aspect of the present invention, in a first possible embodiment, the forward scan startup unit and the reverse scan startup unit respectively include:
[0014] First transistor, second transistor;
[0015] The gates of the first transistor and the second transistor are electrically connected to the start signal line and the reset signal line, respectively. The drain of the first transistor is electrically connected to the forward scan signal line, and the source of the second transistor is electrically connected to the reverse scan signal line. The source of the first transistor and the drain of the second transistor are connected together.
[0016] In conjunction with the first possible embodiment of the first aspect of the present invention, in a second possible embodiment, the output unit includes:
[0017] The third transistor and the first capacitor;
[0018] The gate of the third transistor is connected to the first terminal of the first capacitor, the source of the first transistor, and the drain of the second transistor at the first common connection point.
[0019] The second terminal of the first capacitor is connected to the source of the third transistor at the second common connection point;
[0020] The drain of the third transistor is electrically connected to the clock signal line.
[0021] In conjunction with the second possible implementation of the first aspect of the present invention, in the third possible implementation, the first pull-down unit includes a fourth transistor;
[0022] The first end of the second pull-down unit and the drain of the fourth transistor are both connected to the first common connection point;
[0023] The gate of the fourth transistor is electrically connected to the output terminal of the output unit of the (n+2)th row gate line;
[0024] The source of the fourth transistor is electrically connected to the second terminal of the second pull-down unit;
[0025] The third end of the second pull-down unit is connected to the second common connection point.
[0026] In a second aspect, a cascaded circuit includes a plurality of GOA driving circuits and GOA signal line units as described in the first aspect, wherein each GOA driving circuit is electrically connected to a clock signal line, a forward scan signal line, a reverse scan signal line and a low-level signal line corresponding to the GOA signal line unit.
[0027] The gate of the forward scan startup unit transistor of the GOA driving circuit corresponding to the first row of gate lines is electrically connected to the startup signal line. The output terminal of the GOA driving circuit corresponding to the nth row of gate lines is electrically connected to the gate of the forward scan startup unit transistor of the GOA driving circuit corresponding to the (n+1)th row of gate lines. The second pull-down unit of the GOA driving circuit corresponding to the nth row of gate lines is electrically connected to the output terminal of the GOA driving circuit corresponding to the (n+1)th row of gate lines. The first pull-down unit of the GOA driving circuit corresponding to the nth row of gate lines is electrically connected to the output terminal of the GOA driving circuit corresponding to the (n+2)th row of gate lines.
[0028] Thirdly, a GOA driving method employs the cascaded circuit described in the second aspect, comprising:
[0029] Step 100: Start the nth row GOA driving circuit, output driving signal to the gate line of the nth row, and input a high-level start signal to the (n+1)th row GOA driving circuit to start the (n+1)th row GOA driving circuit.
[0030] Step 200: The (n+1)th row GOA driving circuit outputs a driving signal, inputs a high-level start signal to the (n+2)th row GOA driving circuit, and pulls down the (n)th row GOA driving circuit once.
[0031] Step 300: The (n+2)th row GOA driving circuit outputs a driving signal, inputs a high-level start signal to the (n+3)th row GOA driving circuit, and performs a second pull-down on the nth row GOA driving circuit;
[0032] Where n is a natural number.
[0033] In conjunction with the GOA-driven method described in the third aspect of the present invention, in a first possible implementation, step 100 includes:
[0034] Step 110: When the gate line of the nth row GOA driving circuit is the initial row, the gate of the positive scan start-up unit transistor of the nth row GOA driving circuit is electrically connected to the start-up signal line to obtain a high-level start-up signal;
[0035] Step 120: The output unit of the nth row GOA driving circuit outputs a high-level signal to the gate of the forward scan start unit transistor of the (n+1)th row GOA driving circuit to input a high-level start signal.
[0036] In conjunction with the first possible embodiment of the third aspect of the present invention, in the second possible embodiment, step 200 includes:
[0037] Step 210: The output unit of the (n+1)th row GOA driving circuit outputs a high-level start signal to the gate of the forward scan start unit transistor of the (n+2)th row GOA driving circuit, and simultaneously pulls down the nth row GOA driving circuit once through the second pull-down unit of the nth row GOA driving circuit.
[0038] In conjunction with the first possible embodiment of the third aspect of the present invention, in the second possible embodiment, step 300 includes:
[0039] Step 310: The output unit of the (n+2)th row GOA driving circuit outputs a high-level start signal to the gate of the forward scan start unit transistor of the (n+3)th row GOA driving circuit, and simultaneously pulls down the (n)th row GOA driving circuit a second time through the first pull-down unit of the (n)th row GOA driving circuit.
[0040] Fourthly, a display panel including the cascaded circuit described in the second aspect.
[0041] By implementing the GOA driving circuit and method, cascaded circuit and display panel described in this invention, two pull-down units are set in the GOA driving circuit, and the current GOA driving circuit is pulled down twice in the subsequent two rows of driving. This avoids the incomplete pull-down of the input level of the output unit of the GOA driving circuit, and solves the problem of display abnormality caused by the display panel being affected by external ambient temperature, static electricity, external signal interference or mechanical deformation in the prior art. Attached Figure Description
[0042] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0043] Figure 1 This is a schematic diagram of a GOA driving circuit in the prior art;
[0044] Figure 2 This is a schematic diagram of a cascaded circuit in the prior art;
[0045] Figure 3 This is a schematic diagram of the GOA driving circuit in this application;
[0046] Figure 4 This is a schematic diagram of the cascaded circuit in this application;
[0047] Figure 5 This is a schematic diagram of the driving timing of the cascaded circuit in this application;
[0048] Figure 6 This is a schematic diagram of the module connection of the GOA driving circuit in this application;
[0049] Figure 7 This is a schematic flowchart of a specific embodiment of the GOA-driven method in this application;
[0050] Figure 8 yes Figure 7 A schematic diagram of a specific embodiment of step 100. Detailed Implementation
[0051] The technical solutions of this invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this invention, and not all of them. Other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are all within the scope of protection of this invention.
[0052] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.
[0053] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.
[0054] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.
[0055] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.
[0056] In existing technologies, display panels can experience abnormal output from the GOA drive circuit when exposed to external environmental factors such as temperature fluctuations, static electricity, external signal interference, or mechanical deformation, leading to display malfunctions. Figure 1 and Figure 2 , Figure 1 This is a schematic diagram of a GOA driving circuit in the prior art. Figure 2 This is a schematic diagram of a cascaded circuit in the prior art. When the Gout output in the GOA driver circuit is abnormal, it is usually because the first common contact potential is not fully pulled down, causing the subsequent clock signal (CK signal) to pass through the third transistor T3 of the output unit. This results in an abnormal output of Gout from the output unit of the GOA driver circuit, affecting normal display. For example, when the display is in forward scan (forward scan signal line FW is high, reverse scan signal line BW is low), after the output Gout1 of the first row's GOA driver circuit outputs a high level, Gout1 simultaneously provides the start signal input to the start signal STV of the second row's GOA driver circuit GOA2. When the next CK signal is input to the drain of T3 of GOA2, Gout2 will output a high level. This high level is then connected to the RST position of GOA1, i.e. Figure 1 The gate of the second transistor T2 is low-level (BW), which passes through T2 and reaches the first common junction, pulling down the P point of GOA1. At this time, the gate of the third transistor T3 is low-level, turning off T3 and preventing subsequent CK from passing through T3, thus avoiding abnormal output of Gout1. However, when the display is under special conditions (such as low temperature, ESD, external stress, external disturbances, signal coupling, etc.), the P point potential may not be fully pulled down, or there may be abnormal output from the previous stage's Gout, which may prevent the P point potential from being pulled low, affecting the normal display of subsequent Gout.
[0057] To address the above problems, a GOA driving circuit and method, a cascaded circuit, and a display panel are proposed.
[0058] Firstly, a GOA driving circuit, such as Figure 5 and Figure 6 , Figure 5 This is a schematic diagram of the driving timing of the cascaded circuit in this application. Figure 6 This is a schematic diagram of the module connection of the GOA driving circuit in this application; it is used to drive the corresponding nth row gate line, including a forward scan start unit, a reverse scan start unit, a first pull-down unit, a second pull-down unit, and an output unit; the output terminal of the forward scan start unit is connected to the output terminal of the reverse scan start unit, the first pull-down unit, the second pull-down unit, and the output unit; the first pull-down unit is also electrically connected to the second pull-down unit, and the second pull-down unit is also electrically connected to the output unit; the second pull-down unit is electrically connected to the output terminal of the output unit of the (n+1)th row gate line, and is used to pull down the input terminal level of the output unit of the nth row gate line once when the (n+1)th row gate line is driven to output; the first pull-down unit is electrically connected to the output terminal of the output unit of the (n+2)th row gate line, and is used to pull down the input terminal level of the output unit of the nth row gate line a second time when the (n+2)th row gate line is driven to output; where n is a natural number. By setting two pull-down units in the GOA driver circuit and performing two pull-down operations on the current GOA driver circuit in the subsequent two rows of driving, the incomplete pull-down of the input level of the output unit of the GOA driver circuit is avoided. This solves the problem in the prior art where the display panel is affected by external ambient temperature, static electricity, external signal interference or mechanical deformation, leading to abnormal display.
[0059] like Figure 3 , Figure 3 This is a schematic diagram of the GOA driving circuit in this application. The forward scan startup unit and the reverse scan startup unit include a first transistor T1 and a second transistor T2, respectively. The gate of the first transistor T1 and the gate of the second transistor T2 are electrically connected to the startup signal line and the reset signal line, respectively. The drain of the first transistor T1 is electrically connected to the forward scan signal line FW, and the source of the second transistor T2 is electrically connected to the reverse scan signal line BW. The source of the first transistor T1 and the drain of the second transistor T2 are connected together.
[0060] like Figure 3 The output unit includes a third transistor T3 and a first capacitor C; the gate of the third transistor T3, the first terminal of the first capacitor C, the source of the first transistor T1, and the drain of the second transistor T2 are all connected to the first common junction P; the second terminal of the first capacitor C and the source of the third transistor T3 are all connected to the second common junction; the drain of the third transistor T3 is electrically connected to the clock signal line CK.
[0061] like Figure 3The first pull-down unit includes a fourth transistor; the first terminal of the second pull-down unit and the drain of the fourth transistor are connected to the first common connection point P; the gate of the fourth transistor is electrically connected to the output terminal of the output unit of the (n+2)th row gate line; the source of the fourth transistor is electrically connected to the second terminal of the second pull-down unit; and the third terminal of the second pull-down unit is connected to the second common connection point.
[0062] Secondly, a cascaded circuit, such as Figure 4 , Figure 4 This is a schematic diagram of the cascaded circuit in this application; it includes multiple GOA driving circuits and GOA signal line units of the first aspect. Each GOA driving circuit is electrically connected to the clock signal line CK, forward scan signal line FW, reverse scan signal line BW, and low-level signal line VGL corresponding to the GOA signal line unit, respectively. The gate of the forward scan start-up unit transistor of the GOA driving circuit GOA1 corresponding to the first row of gate lines is electrically connected to the start-up signal line. The output terminal of the GOA driving circuit GOAn corresponding to the nth row of gate lines is electrically connected to the gate of the forward scan start-up unit transistor of the GOA driving circuit GOAn+1 corresponding to the n+1th row. The second pull-down unit of the GOA driving circuit GOAn corresponding to the nth row of gate lines is electrically connected to the output terminal of the GOA driving circuit GOAn+1 corresponding to the n+1th row. The first pull-down unit of the GOA driving circuit GOAn corresponding to the nth row of gate lines is electrically connected to the output terminal of the GOA driving circuit GOAn+2 corresponding to the n+2th row.
[0063] like Figure 4 The first dropdown unit is as follows: Figure 4 RST2 in the middle, the second drop-down unit is as follows Figure 4 In the circuit, RST1, the output terminal Gout1 of the GOA drive circuit GOA1 corresponding to the first row of gate lines is electrically connected to the start terminal STV (gate of the first transistor T1) of the forward scan start unit of the GOA drive circuit GOA2 corresponding to the second row of gate lines. When Gout1 outputs a high level, the GOA drive circuit GOA2 corresponding to the second row of gate lines can be started. The output Gout2 of the GOA drive circuit GOA2 corresponding to the second row of gate lines is electrically connected to the second pull-down unit RST1 of the GOA drive circuit GOA1 corresponding to the first row of gate lines. When its output is high level, the first common contact P of the GOA drive circuit GOA1 corresponding to the first row of gate lines is pulled down once through the second pull-down unit RST1. Furthermore, the output Gout2 of the GOA drive circuit GOA3 corresponding to the third row of gate lines is electrically connected to the first pull-down unit RST2 of the GOA drive circuit GOA1 corresponding to the first row of gate lines. When its output is high level, the first common contact P of the GOA drive circuit GOA1 corresponding to the first row of gate lines is pulled down twice through the first pull-down unit RST2.
[0064] Thirdly, a GOA-driven approach, such as... Figure 7 , Figure 7 This is a schematic flowchart of a specific embodiment of the GOA driving method in this application; employing a cascaded circuit of the second aspect, including: Step 100, starting the nth row GOA driving circuit, outputting a driving signal to the gate line of the nth row, and inputting a high-level start signal to the (n+1)th row GOA driving circuit to start the (n+1)th row GOA driving circuit; Step 200, the (n+1)th row GOA driving circuit outputs a driving signal, inputs a high-level start signal to the (n+2)th row GOA driving circuit, and performs a pull-down once on the nth row GOA driving circuit; Step 300, the (n+2)th row GOA driving circuit outputs a driving signal, inputs a high-level start signal to the (n+3)th row GOA driving circuit, and performs a second pull-down on the nth row GOA driving circuit; where n is a natural number.
[0065] Preferably, such as Figure 8 , Figure 8 yes Figure 7 A schematic flowchart of a specific embodiment of step 100 is shown. Step 100 includes: Step 110, when the gate line of the nth row GOA driving circuit is the initial row, the gate of the forward scan start-up unit transistor of the nth row GOA driving circuit is electrically connected to the start-up signal line STV to obtain a high-level start-up signal; Step 120, the output unit of the nth row GOA driving circuit outputs a high-level signal to the gate of the forward scan start-up unit transistor of the (n+1)th row GOA driving circuit to input a high-level start-up signal.
[0066] Preferably, step 200 includes: step 210, the output terminal of the output unit of the (n+1)th row GOA driving circuit inputs a high-level start signal to the gate of the forward scan start unit transistor of the (n+2)th row GOA driving circuit, and at the same time pulls down the nth row GOA driving circuit once through the second pull-down unit of the nth row GOA driving circuit.
[0067] Preferably, step 300 includes: step 310, the output terminal of the output unit of the (n+2)th row GOA driving circuit inputs a high-level start signal to the gate of the positive sweep start unit transistor of the (n+3)th row GOA driving circuit, and at the same time performs a secondary pull-down on the nth row GOA driving circuit through the first pull-down unit of the nth row GOA driving circuit.
[0068] Fourthly, a display panel including the cascaded circuitry of the second aspect.
[0069] The GOA driving circuit and method, cascaded circuit and display panel of the present invention, by setting two pull-down units in the GOA driving circuit and pulling down the current GOA driving circuit twice in the subsequent two rows of driving, avoids the incomplete pull-down of the input level of the output unit of the GOA driving circuit, and solves the problem of display abnormality caused by the display panel in the prior art when it is affected by the external ambient temperature, static electricity, external signal interference or mechanical deformation.
[0070] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.
Claims
1. A GOA driving circuit for driving corresponding row gate lines, characterized in that, include: Forward scan start unit, reverse scan start unit, first pull-down unit, second pull-down unit and output unit; The output terminal of the forward scan start unit is connected to the output terminal of the reverse scan start unit, the first pull-down unit, the second pull-down unit, and the output unit. The first pull-down unit is also electrically connected to the second pull-down unit, and the second pull-down unit is also electrically connected to the output unit; The second pull-down unit is electrically connected to the output terminal of the output unit of the (n+1)th row gate line, and is used to pull down the input level of the output unit of the (n+1)th row gate line once when the (n+1)th row gate line is driven to output. The first pull-down unit is electrically connected to the output terminal of the output unit of the (n+2)th row gate line, and is used to pull down the input terminal level of the output unit of the nth row gate line a second time when the (n+2)th row gate line is driven to output. Where n is a natural number.
2. The GOA driving circuit according to claim 1, characterized in that, The forward scan start unit and the reverse scan start unit each include: First transistor, second transistor; The gates of the first transistor and the second transistor are electrically connected to the start signal line and the reset signal line, respectively. The drain of the first transistor is electrically connected to the forward scan signal line, and the source of the second transistor is electrically connected to the reverse scan signal line. The source of the first transistor and the drain of the second transistor are connected together.
3. The GOA driving circuit according to claim 2, characterized in that, The output unit includes: The third transistor and the first capacitor; The gate of the third transistor is connected to the first terminal of the first capacitor, the source of the first transistor, and the drain of the second transistor at the first common connection point. The second terminal of the first capacitor is connected to the source of the third transistor at the second common connection point; The drain of the third transistor is electrically connected to the clock signal line.
4. The GOA driving circuit according to claim 3, characterized in that, The first pull-down unit includes a fourth transistor; The first end of the second pull-down unit and the drain of the fourth transistor are both connected to the first common connection point; The gate of the fourth transistor is electrically connected to the output terminal of the output unit of the (n+2)th row gate line; The source of the fourth transistor is electrically connected to the second terminal of the second pull-down unit; The third end of the second pull-down unit is connected to the second common connection point.
5. A cascaded circuit, characterized in that, It includes multiple GOA driving circuits and GOA signal line units as described in any one of claims 1-4, wherein each GOA driving circuit is electrically connected to the clock signal line, forward scan signal line, reverse scan signal line and low-level signal line corresponding to the GOA signal line unit; The gate of the forward scan startup unit transistor of the GOA driving circuit corresponding to the first row of gate lines is electrically connected to the startup signal line. The output terminal of the GOA driving circuit corresponding to the nth row of gate lines is electrically connected to the gate of the forward scan startup unit transistor of the GOA driving circuit corresponding to the (n+1)th row of gate lines. The second pull-down unit of the GOA driving circuit corresponding to the nth row of gate lines is electrically connected to the output terminal of the GOA driving circuit corresponding to the (n+1)th row of gate lines. The first pull-down unit of the GOA driving circuit corresponding to the nth row of gate lines is electrically connected to the output terminal of the GOA driving circuit corresponding to the (n+2)th row of gate lines.
6. A GOA driving method, employing the cascaded circuit described in claim 5, characterized in that, include: Step 100: Start the nth row GOA driving circuit, output driving signal to the gate line of the nth row, and input a high-level start signal to the (n+1)th row GOA driving circuit to start the (n+1)th row GOA driving circuit. Step 200: The (n+1)th row GOA driving circuit outputs a driving signal, inputs a high-level start signal to the (n+2)th row GOA driving circuit, and pulls down the (n)th row GOA driving circuit once. Step 300: The (n+2)th row GOA driving circuit outputs a driving signal, inputs a high-level start signal to the (n+3)th row GOA driving circuit, and performs a second pull-down on the nth row GOA driving circuit; Where n is a natural number.
7. The GOA driving method according to claim 6, characterized in that, Step 100 includes: Step 110: When the gate line of the nth row GOA driving circuit is the initial row, the gate of the positive scan start-up unit transistor of the nth row GOA driving circuit is electrically connected to the start-up signal line to obtain a high-level start-up signal; Step 120: The output unit of the nth row GOA driving circuit outputs a high-level signal to the gate of the forward scan start unit transistor of the (n+1)th row GOA driving circuit to input a high-level start signal.
8. The GOA-driven method according to claim 7, characterized in that, Step 200 includes: Step 210: The output unit of the (n+1)th row GOA driving circuit outputs a high-level start signal to the gate of the forward scan start unit transistor of the (n+2)th row GOA driving circuit, and simultaneously pulls down the nth row GOA driving circuit once through the second pull-down unit of the nth row GOA driving circuit.
9. The GOA-driven method according to claim 8, characterized in that, Step 300 includes: Step 310: The output unit of the (n+2)th row GOA driving circuit outputs a high-level start signal to the gate of the forward scan start unit transistor of the (n+3)th row GOA driving circuit, and simultaneously pulls down the (n)th row GOA driving circuit a second time through the first pull-down unit of the (n)th row GOA driving circuit.
10. A display panel, characterized in that, Includes the cascaded circuit described in claim 5.