DRAM (Dynamic Random Access Memory) and end-side equipment

Abstract

The invention relates to a DRAM (Dynamic Random Access Memory) and end side equipment, and the DRAM comprises a DRAM storage circuit which is used for the DRAM to store or access data; the logic circuit is used for executing a calculation task of the DRAM; and the DRAM storage circuit control module is connected with the DRAM storage circuit and the logic circuit, can generate a refreshing signal for refreshing the DRAM storage circuit, and controls the DRAM storage circuit to preferentially respond to the refreshing signal when the refreshing signal and a data access signal of the logic circuit exist at the same time. According to the design, the data access signal of the logic circuit and the refresh signal of the DRAM storage circuit can be prevented from conflicting.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and particularly to a DRAM memory and an edge device. Background Art

[0002] With the rapid development of artificial intelligence (AI) technology, the application scenarios based on large pre-trained models have been continuously expanding, such as natural language processing, image recognition, and multi-modal interaction. Due to their excellent performance, large models have been widely applied in both cloud and edge devices. However, with the continuous growth of the model parameter scale, migrating large models from the cloud to edge devices (such as AI mobile phones and AIPCs) faces many challenges.

[0003] As Figure 1 shown, due to the limitations of power consumption, volume, and real-time response requirements, the computing resources and storage resources of edge devices are relatively limited compared to cloud servers. In particular, during the inference process of large models, frequent memory access will cause a large amount of data to be transferred between the processor and the memory. The current mainstream storage medium is DRAM, which is restricted by data transfer bandwidth and access latency, becoming an important bottleneck restricting the inference performance of large models. In addition, frequent data transfer will significantly increase the system energy consumption, having a negative impact on the battery life of mobile devices.

[0004] To solve the above problems, a common technical means is to directly integrate computing units into the memory system. For example, a processor unit or a computing engine is embedded inside the DRAM. This "near-memory computing" architecture effectively reduces the distance and frequency of data transfer and improves the data processing efficiency. The core concept of in-memory computing is to execute computing tasks in place, that is, directly complete the computing at the location where the data is stored, thereby breaking through the bottleneck of the traditional "storage-computing" separation architecture to a certain extent and significantly improving the performance and energy efficiency of edge devices running large models. The design and optimization of in-memory computing architectures for large model edge acceleration have important research value and application prospects.

[0005] As for the edge device as Figure 2 shown, the DRAM die and the computing logic achieve high-bandwidth interconnection through a three-dimensional stacking form. Compared with Device 1 that decouples the process platform of the computing logic and the DRAM storage die platform, therefore, the computing logic can use a relatively advanced CMOS logic process to achieve the integration of large-scale computing power. Under this device, in the near-memory computing architecture, due to the ability to integrate large-scale computing power, the computing pressure of the SoC is greatly reduced or the end-to-end application of large models is completed by the near-memory computing architecture. In this case, the bottleneck of the large model inference performance caused by the low data transfer bandwidth of the existing memory interface is solved.

[0006] However, DRAM needs to perform a refresh operation regularly to prevent the data in the memory cells from being lost due to charge leakage. The refresh operation will briefly lock a specific row or area, preventing other operations from accessing the refreshed memory cells. This may cause an access conflict when the computing circuit attempts to access the memory circuit that is performing the refresh operation.

[0007] Therefore, it is necessary to improve the existing DRAM memory. Summary of the Invention

[0008] In view of the above problems, the present invention provides a DRAM memory, including: a DRAM memory circuit for storing or accessing data by the DRAM memory; a logic circuit for performing the computing tasks of the DRAM memory; and a DRAM memory circuit control module connected to the DRAM memory circuit and the logic circuit, capable of generating a refresh signal for refreshing the DRAM memory circuit, and controlling the DRAM memory circuit to preferentially respond to the refresh signal when the refresh signal and the data access signal of the logic circuit exist simultaneously.

[0009] Optionally, the DRAM memory circuit control module includes: a refresh control module capable of generating a refresh control signal based on an external instruction; a refresh signal generation module connected to the refresh control module, capable of generating a refresh signal in response to the refresh control signal; and a memory access module connected to the refresh signal generation module, the logic circuit, and the DRAM memory circuit, capable of preferentially responding to the refresh signal when receiving the refresh signal and the data access signal of the logic circuit.

[0010] Optionally, the memory access module includes: an arbiter with two input terminals respectively connected to the refresh signal generation module and the logic circuit for receiving the refresh signal and the data access signal, and ruling to execute the refresh signal when receiving the refresh signal and the data access signal simultaneously; and a read / write control module connected to the output terminal of the arbiter and the DRAM memory circuit, capable of controlling the DRAM memory circuit in response to the output signal of the arbiter.

[0011] Optionally, the DRAM storage circuit control includes: a mode selection module capable of determining whether the DRAM memory operates in a computing mode or a storage mode based on an external signal; a logic refresh control module capable of generating a refresh control signal in the computing mode; a refresh control module capable of generating a refresh control signal in the storage mode; a first selector with two input terminals respectively connected to the logic refresh control module and the refresh control module, and a control terminal connected to the mode selection module; a refresh signal generation module connected to the output terminal of the first selector, capable of generating a refresh signal in response to the output signal of the first selector; and a memory access module connected to the refresh signal generation module, the logic circuit, and the DRAM storage circuit, capable of preferentially responding to the refresh signal when receiving the refresh signal and the data access signal of the logic circuit.

[0012] Optionally, the memory access module includes: a second selector with two input terminals respectively connected to the refresh signal generation module and the logic circuit for receiving the refresh signal and the data access signal, and a control terminal connected to the mode selection module and the logic circuit. The second selector is configured to: output the refresh signal in the storage mode; in the computing mode, preferentially execute the refresh signal when receiving both the refresh signal and the data access signal; and a read / write control module connected to the output terminal of the second selector and the DRAM storage circuit, capable of controlling the DRAM storage circuit in response to the output signal of the second selector.

[0013] Optionally, the DRAM storage circuit includes a plurality of memory blocks connected to the memory access module, and a shared storage unit is provided between the logic circuit and the memory access module. The shared storage unit can store data corresponding to the data access signal of the logic circuit.

[0014] Optionally, the DRAM storage circuit includes a plurality of memory blocks, and a logic circuit is provided corresponding to each memory block. The DRAM storage circuit control module includes: a refresh control module capable of generating a refresh control signal based on an external instruction; a refresh signal generation module connected to the refresh control module, capable of generating a refresh signal in response to the refresh control signal; a plurality of local storage units provided corresponding to each logic circuit and connected to the corresponding logic circuit for storing data corresponding to the data access signal of the logic circuit; and a plurality of memory access modules connected to the refresh signal generation module, the corresponding local storage units, and the corresponding memory blocks, capable of preferentially responding to the refresh signal when receiving the refresh signal and the data access signal of the logic circuit.

[0015] Optionally, the DRAM storage circuit includes a plurality of memory blocks, and a logic circuit is provided corresponding to each memory block. The DRAM storage circuit control module includes: a global refresh control module capable of generating a refresh control signal based on an external instruction; a plurality of refresh signal generation modules connected to the global refresh control module and corresponding memory access modules, capable of generating refresh signals in response to the refresh control signal; a plurality of local storage units provided corresponding to each logic circuit and connected to the corresponding logic circuit for storing data corresponding to the data access signal of the logic circuit; and a plurality of memory access modules connected to the corresponding refresh signal generation module, corresponding local storage unit, and corresponding memory block, capable of preferentially responding to the refresh signal when receiving the refresh signal and the data access signal of the logic circuit.

[0016] Optionally, it further includes: a storage controller and a logic controller. The storage controller is connected to the refresh control module, and the logic controller is connected to the refresh control module and the logic circuit. The DRAM memory is further configured with the high-speed interface for information interaction with the outside. The high-speed interface is respectively connected to the storage controller and the logic controller. In response to an external instruction, the storage controller and the logic controller can control the DRAM storage circuit control module, thereby realizing access, refresh, and completion of computing tasks for the DRAM storage circuit.

[0017] Optionally, it further includes a storage chip and a logic chip. The high-speed interface, the storage controller, the refresh control module, and the refresh signal generation module are encapsulated in the storage chip, and the logic controller and the logic circuit are encapsulated in the logic chip.

[0018] Optionally, it further includes a storage chip and a logic chip. The high-speed interface, the storage controller, the refresh control module, and the refresh signal generation module are encapsulated in the storage chip, and the memory access module, the logic controller, and the logic circuit are encapsulated in the logic chip.

[0019] To achieve the above-mentioned invention purpose, the present application also provides an edge device, which includes an SoC system and a DRAM memory connected to the SoC system.

[0020] The DRAM memory provided by the present invention can avoid conflicts between the data access signal of the logic circuit and the refresh signal of the DRAM storage circuit. Description of the Drawings

[0021] Figure 1 It is a schematic diagram of the architecture of an edge device in the prior art.

[0022] Figure 2 It is a schematic diagram of the architecture of end - side devices in the prior art.

[0023] Figure 3 It is a schematic diagram of the structure of a DRAM memory provided by an embodiment of the present invention.

[0024] Figure 4 It is a schematic diagram of the structure of a DRAM memory provided by an embodiment of the present invention.

[0025] Figure 5 It is a schematic diagram of the structure of a DRAM memory provided by an embodiment of the present invention.

[0026] Figure 6 It is a schematic diagram of the structure of a DRAM memory provided by an embodiment of the present invention.

[0027] Figure 7 It is a schematic diagram of the structure of a DRAM memory provided by an embodiment of the present invention.

[0028] Figure 8 It is a schematic diagram of the structure of a DRAM memory provided by an embodiment of the present invention.

[0029] Figure 9 It is a schematic diagram of the packaging structure of a DRAM memory provided by an embodiment of the present invention.

[0030] Figure 10 It is a schematic diagram of the packaging structure of a DRAM memory provided by an embodiment of the present invention.

[0031] Figure 11 It is a schematic diagram of the packaging structure of a DRAM memory provided by an embodiment of the present invention. Detailed implementation manners

[0032] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0033] Such as Figure 3As shown in the figure, this embodiment provides a DRAM memory, which includes a DRAM storage circuit 100, a logic circuit 200, and a DRAM storage circuit control module 300. The DRAM storage circuit 100 is used for the DRAM memory to store or access data; the logic circuit 200 is used to execute the computing tasks of the DRAM memory; the DRAM storage circuit control module 300 is connected to the DRAM storage circuit 100 and the logic circuit 200, and can generate a refresh signal for refreshing the DRAM storage circuit 100, and when the refresh signal and the data access signal of the logic circuit exist simultaneously, control the DRAM storage circuit 100 to preferentially respond to the refresh signal.

[0034] With such a design, it is possible to avoid conflicts between the data access signal of the logic circuit 200 and the refresh signal of the DRAM storage circuit 100.

[0035] The DRAM storage circuit control module 300 includes: a refresh control module 310, a refresh signal generation module 320, and a memory access module 330.

[0036] The refresh control module 310 is connected to the refresh signal generation module 320 and can drive the refresh signal generation module 320 to generate a refresh signal. The refresh signal generation module 320 is connected to the memory access module 330 and can send the refresh signal to the memory access module 330. The memory access module 330 is respectively connected to the DRAM storage circuit 100 and the logic circuit 200, and can receive the data access signal of the logic circuit 200. The memory access module 330 is configured to preferentially respond to the refresh signal to complete the refresh of the DRAM storage circuit 100 when both the refresh signal and the data access signal are received. Before the refresh of the DRAM storage circuit 100 is completed, the data access signal of the logic circuit 200 is not responded to and is postponed. In other words, after the refresh of the DRAM storage circuit 100 is completed, the data access signal of the logic circuit 200 is responded to / executed.

[0037] The DRAM memory provided by this embodiment, through the priority setting of the refresh signal and the data access signal, makes the refresh signal be preferentially responded to when the two signals are generated simultaneously, thereby avoiding conflicts between the refresh of the DRAM storage circuit 100 and the access of the logic circuit 200 to the DRAM storage circuit 100.

[0038] Specifically, as Figure 4As shown in the figure, the memory access module 330 includes: an arbiter 331 and a read / write control module 332. Two input terminals of the arbiter 331 are respectively connected to the refresh signal generation module 320 and the logic circuit 200 for receiving a refresh signal refresh and a data access signal PE. The output terminal of the arbiter 331 is connected to the read / write control module 332. Taking the arbiter 331 as a priority arbiter as an example, the arbiter 331 is configured such that the priority of the refresh signal is higher than that of the data access signal. Based on this, when the arbiter 331 receives both the refresh signal and the DRAM data access signal at the same time, it responds to the refresh signal until the refresh of the DRAM storage circuit 100 is completed through the read / write control module 332, and then responds to the data access signal.

[0039] The memory access module 330 designed based on the arbiter 331 and the read / write control module 332 has a simple structure and is easy to implement.

[0040] Optionally, as Figure 5 shown, this embodiment provides another DRAM memory, which Figure 3 and Figure 4 The difference between the provided DRAM memory and the Figure 5 provided DRAM memory is that it further includes a logic refresh control module 340 and a mode selection module 350. The logic refresh control module 340 and the refresh control module 310 are connected to the input terminals of the first selector 360. The output terminal of the first selector 360 is connected to the refresh signal generation module 320. The control terminal of the first selector 360 is connected to the mode selection module 350 and is configured to receive an electrical signal representing the working mode of the DRAM memory. The DRAM memory includes two working modes. The first is the computing mode, and the second is the storage mode. In the computing mode, the logic refresh control module 340 is selected by the first selector 360 to complete the management of signal refreshing. In the storage mode, the refresh control module 310 is selected by the first selector 360 to complete the management of signal refreshing. Figure 5 The provided DRAM memory and Figure 3 and Figure 4 The difference between the provided DRAM memory and the

[0041] The following is an explanation of its operation logic: After receiving an electrical signal representing the working mode of the DRAM memory, the first selector 360 selects the refresh operation of the module management signal corresponding to the mode. Specifically, in the computing mode, the logic refresh control module 340 manages the signal refresh operation. The logic circuit 200 determines the order of the execution data access signal and the refresh signal, and sends the corresponding signals to the control terminal of the second selector 333, so that the corresponding signals are transmitted to the read / write control module; in the storage mode, the refresh control module 310 manages the signal refresh operation, and the second selector 333 selects the refresh signal based on the electrical signal representing the storage mode and sends it to the read / write control module 332.

[0042] Optionally, the DRAM storage circuit includes a plurality of memory blocks 110. Based on the refresh control of each memory block 110, different architectures are set in this embodiment, such as Figure 6 As shown, in one embodiment, the plurality of memory blocks 110 are respectively connected to the memory access module 330, that is, the plurality of memory blocks 110 share one memory access module 330. In this architecture, the DRAM memory further includes a shared storage unit 400. The shared storage unit 400 is connected between the logic circuit 200 and the memory access module 330, and can store data corresponding to the data access signal of the logic circuit for the logic circuit to obtain.

[0043] In this architecture, high-bandwidth data transmission is achieved at a lower cost.

[0044] Such as Figure 7 As shown, in another embodiment, a separate memory access module 330, a local storage unit 500, and a logic circuit 200 are provided for each memory block 110. The local storage unit 500 is connected between the corresponding memory access module 330 and the logic circuit 200. In this architecture, each logic circuit 200 can independently access the corresponding memory block 110 through the memory access module 330, and can execute computing tasks more independently and flexibly.

[0045] Such as Figure 8 As shown, in another embodiment, on the basis of the architecture shown in Figure 7 the refresh control module 310 and the refresh signal generation module 320 are configured as: a global refresh control module 310' and a plurality of local refresh signal generation modules 320'. Specifically, the global refresh control module 310' is connected to each local refresh signal generation module 320', and each local refresh signal generation module 320' is connected to the corresponding memory access module 330. In this case, the global refresh signal control module responds to an external signal and refreshes the corresponding memory block 110 through each local refresh signal generation module 320' at different time points; therefore, the duration of each refresh signal is compared with Figure 6 andFigure 7 The architecture is shorter. Further, the probability of conflict between the refresh signal and the data access signal will be further reduced, and as the duration of the refresh signal is shortened, the access efficiency of DRAM data will be higher.

[0046] The following describes the packaging structure of the DRAM memory. As Figure 9 described, the logic circuit 200, the DRAM memory circuit 100, and the DRAM memory circuit control module 300 are all provided on the same chip. The chip is also provided with a memory controller 600 and a logic controller 700. The memory controller 600 is connected to the refresh control module 310. The refresh signal generation module 320 is connected to the refresh control module 310 and the memory access module 330. The logic controller 700 is connected to the refresh control module 310 and the logic circuit 200. The DRAM memory is further configured with a high-speed interface 800 for information interaction with the outside of the memory. The high-speed interface 800 is respectively connected to the memory controller 600 and the logic controller 700. In response to external instructions, the memory controller 600 and the logic controller 700 can control the DRAM memory circuit control module 300, thereby realizing access, refresh, and completion of computing tasks for the DRAM memory circuit 200.

[0047] In another embodiment of the present invention, the DRAM memory is packaged using a three-dimensional stacking process, including a memory chip 10 and a logic chip 20. In this case, the memory access module 330, the refresh control module 310, the refresh signal generation module 320, the high-speed interface 800, the logic controller 700, and the memory controller 600 can be selectively provided on the memory chip 10 or the logic chip 20.

[0048] Preferably, as Figure 10 shown, the high-speed interface 800, the memory controller 600, the refresh control module 310, the refresh signal generation module 320, and the memory access module 330 are provided on the memory chip, and the logic controller 700 and the logic circuit 200 are provided on the logic chip 20; Figure 11 The difference between the DRAM memory shown in Figure 10 and

[0049] is that the memory access module 330 is provided on the logic chip 20.

[0050] So far, the technical solution of the present invention has been described with reference to the accompanying drawings. However, it is easily understood by those skilled in the art that the protection scope of the present invention is obviously not limited to the above specific embodiments. Without departing from the principle of the present invention, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will all fall within the protection scope of the present invention.

Claims

1. A DRAM memory, characterized in that: include: A DRAM storage circuit, used for storing or accessing data by the DRAM memory; Logic circuits for performing computational tasks on DRAM memory; as well as The DRAM storage circuit control module is connected to the DRAM storage circuit and the logic circuit, and can generate a refresh signal for refreshing the DRAM storage circuit, and when the refresh signal and the data access signal of the logic circuit exist at the same time, control the DRAM storage circuit to preferentially respond to the refresh signal.

2. The DRAM memory according to claim 1, characterized in that: The DRAM storage circuit control module includes: A refresh control module capable of generating a refresh control signal based on an external instruction; a refresh signal generating module, connected to the refresh control module, capable of generating a refresh signal in response to the refresh control signal; and The memory access module is connected to the refresh signal generating module, the logic circuit and the DRAM storage circuit, and can respond to the refresh signal preferentially upon receiving the refresh signal and the data access signal of the logic circuit.

3. The DRAM memory according to claim 2, characterized in that: The memory access module comprises: an arbiter, two input ends of which are respectively connected to the refresh signal generating module and the logic circuit, for receiving the refresh signal and the data access signal, and determining to execute the refresh signal when the refresh signal and the data access signal are received at the same time; and The read / write control module is connected to the output end of the arbitrator and the DRAM storage circuit, and can control the DRAM storage circuit in response to the output signal of the arbitrator.

4. The DRAM memory according to claim 1, characterized in that: The DRAM storage circuit control includes: A mode selection module, capable of determining whether the DRAM memory operates in a computing mode or a storage mode based on an external signal; A logic refresh control module capable of generating a refresh control signal in the calculation mode; A refresh control module capable of generating a refresh control signal in the storage mode; A first selector, wherein two input ends thereof are respectively connected to the logic refresh control module and the refresh control module, and a control end thereof is connected to the mode selection module; a refresh signal generating module, connected to the output end of the first selector, capable of generating a refresh signal in response to the output signal of the first selector; and The memory access module is connected to the refresh signal generating module, the logic circuit and the DRAM storage circuit, and can respond to the refresh signal preferentially upon receiving the refresh signal and the data access signal of the logic circuit.

5. The DRAM memory according to claim 4, characterized in that: The memory access module comprises: a second selector, wherein two input ends are respectively connected to the refresh signal generating module and the logic circuit for receiving the refresh signal and the data access signal, and a control end is connected to the mode selection module and the logic circuit, and the second selector is configured to: output a refresh signal in the storage mode; and preferentially execute the refresh signal when the refresh signal and the data access signal are received simultaneously in the calculation mode; and A read / write control module is connected to the output end of the second selector and the DRAM storage circuit, and can control the DRAM storage circuit in response to an output signal of the second selector.

6. The DRAM memory according to claim 2, characterized in that: The DRAM storage circuit includes a plurality of memory blocks connected to the memory access module. A shared storage unit is provided between the logic circuit and the memory access module. The shared storage unit can store data corresponding to a data access signal of the logic circuit.

7. The DRAM memory according to claim 1, characterized in that: The DRAM storage circuit includes a plurality of storage blocks, and a logic circuit is provided corresponding to each of the storage blocks. The DRAM storage circuit control module includes: A refresh control module capable of generating a refresh control signal based on an external instruction; A refresh signal generating module, connected to the refresh control module, capable of generating a refresh signal in response to the refresh control signal; a plurality of local storage units, arranged corresponding to each of the logic circuits and connected to the corresponding logic circuits, for storing data corresponding to the data access signal of the logic circuit; and A plurality of memory access modules are connected to the refresh signal generating module, the corresponding local storage units and the corresponding memory blocks, and can preferentially respond to the refresh signal when receiving the refresh signal and the data access signal of the logic circuit.

8. The DRAM memory according to claim 1, characterized in that: The DRAM storage circuit includes a plurality of storage blocks, and a logic circuit is provided corresponding to each of the storage blocks. The DRAM storage circuit control module includes: A global refresh control module capable of generating a refresh control signal based on an external instruction; A plurality of refresh signal generating modules, connected to the global refresh control module and the corresponding memory access modules, capable of generating refresh signals in response to the refresh control signal; a plurality of local storage units, arranged corresponding to each of the logic circuits and connected to the corresponding logic circuits, for storing data corresponding to the data access signal of the logic circuit; and A plurality of memory access modules are connected to the corresponding refresh signal generating modules, the corresponding local storage units and the corresponding memory blocks, and can preferentially respond to the refresh signal when receiving the refresh signal and the data access signal of the logic circuit.

9. The DRAM memory according to claim 2, characterized in that: Also includes: A storage controller and a logic controller, the storage controller is connected to the refresh control module, and the logic controller is connected to the refresh control module and the logic circuit; the DRAM memory is also configured with the high-speed interface for exchanging information with the outside, the high-speed interface is connected to the storage controller and the logic controller respectively, and in response to external instructions, the storage controller and the logic controller can control the DRAM storage circuit control module, thereby realizing access to the DRAM storage circuit, refreshing and completing computing tasks.

10. The DRAM memory according to claim 9, characterized in that: It also includes a storage chip and a logic chip. The high-speed interface, the storage controller, the refresh control module, the refresh signal generating module, and the memory access module are encapsulated in the storage chip, and the logic controller and the logic circuit are encapsulated in the logic chip.

11. The DRAM memory according to claim 9, characterized in that: It also includes a storage chip and a logic chip. The high-speed interface, the storage controller, the refresh control module, the refresh signal generating module are packaged in the storage chip, and the memory access module, the logic controller and the logic circuit are packaged in the logic chip.

12. A terminal side device, characterized in that: The invention comprises the DRAM memory as described in any one of claims 1 to 11 and a SoC system connected thereto.

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