Processor chip with built-in FLASH

Abstract

The invention discloses a processor chip with a built-in FLASH, which is provided with a programming refresh algorithm circuit, the current byte address of the FLASH is read by comparing a standard threshold current with a margin threshold current, the programming refresh algorithm circuit only programs the current byte address with inconsistent reading results of the current byte address of the FLASH, and the current byte address of the FLASH is read by the programming refresh algorithm circuit. Therefore, the number of storage units involved in one-time refreshing of the FLASH is greatly reduced, the data keeping capacity of the FLASH can be guaranteed, and meanwhile the situation that the service life of the FLASH is obviously shortened due to the fact that the correctness of data stored by the FLASH is affected by excessive electron retention of a silicon dioxide insulating layer due to excessive charging and discharging times of a floating grid electrode of the storage unit is avoided.

Description

Technical Field

[0001] The present invention relates to the technology of MCU (Micro Controller Unit) chips, and particularly to a processor chip with built-in FLASH. Background Art

[0002] An MCU chip integrates a central processing unit (CPU), memory, a counter (Timer), A / D conversion, and peripheral interfaces such as UART (Universal Asynchronous Receiver / Transmitter) on a single chip, forming a chip-level computer for different combinations of control in different application scenarios. With the development of application diversity, MCUs generally use built-in FLASH (flash memory) as the storage medium for the CPU to run programs.

[0003] Therefore, the stability of storing data in the built-in FLASH is of crucial importance.

[0004] Temperature has always been one of the several important issues that various electronic components have to face. Electronic devices not only generate heat during their own operation but are also affected by the heat conduction of surrounding devices. Similarly, the data retention ability of the built-in FLASH is greatly affected by the ambient temperature. The higher the ambient temperature, the shorter the data retention time, and at the same time, it accelerates the shortening of the memory life.

[0005] The storage unit of FLASH is a three-terminal device with the same names as a field-effect transistor: source, drain, and gate. The difference is that the field-effect transistor has a single-gate structure, while FLASH has a double-gate structure with a floating gate added between the gate and the substrate. The structure is as Figure 1 shown.

[0006] There is a silicon dioxide insulating layer between the floating gate and the silicon substrate to protect the charges in the floating gate from leakage. Therefore, the data in FLASH remains after power-off.

[0007] 1) For the programming of flash memory, that is, controlling the gate to be charged and applying voltage to the gate, so that the charges stored in the floating gate increase and exceed the threshold, which represents data 0.

[0008] 2) For the erasure of flash memory, by applying voltage to the source, the floating gate is discharged. When the charge is lower than the threshold, it represents data 1.

[0009] The FLASH read operation applies a positive voltage to the control gate. If there are electrons in the floating gate, the channel conducts and there is a conduction current; otherwise, there is no conduction current. In the normal read mode, when the detected conduction current is greater than the threshold current, it is determined as data "0"; otherwise, it is data "1". Margin read is a special read mode that changes the threshold current. Generally, the threshold current of margin read is 1.5 times that of normal read.

[0010] The charging and discharging of the floating gate is actually the migration of electrons. Since the thickness of the silicon dioxide insulating layer is only 10 nanometers, each electron migration will cause wear to the insulating layer. When the silicon dioxide insulating layer is damaged, electrons may remain in the insulating layer, which continuously increases the negative charge of this layer and affects the correctness of the FLASH stored data. When the temperature rises, the electron mobility increases, increasing the data uncertainty. Summary of the Invention

[0011] The technical problem to be solved by the present invention is to provide a processor chip with built-in FLASH, which can ensure the data retention ability of the FLASH while avoiding the obvious shortening of the FLASH service life due to excessive charge and discharge times of the floating gate of the storage unit, resulting in excessive electron retention in the silicon dioxide insulating layer and affecting the correctness of the FLASH stored data.

[0012] To solve the above technical problem, the processor chip with built-in FLASH provided by the present invention includes a central processor, a FLASH module, and a programming and refreshing algorithm circuit;

[0013] The programming and refreshing algorithm circuit is used to output a refreshing programming instruction to the FLASH module;

[0014] The working process of the programming and refreshing algorithm circuit is as follows:

[0015] S1. Start, and use the default byte address as the current byte address of the FLASH;

[0016] S2. Read the data at the current byte address of the FLASH with the standard threshold current as the standard data;

[0017] S3. Read the data at the current section address of the FLASH with the margin threshold current as the margin data, and the margin threshold current is greater than the standard threshold current;

[0018] S4. If the standard data and the margin data at the current byte address of the FLASH are different, go to step S5; otherwise, go to step S7;

[0019] S5. Output the programming instruction to the FLASH module, refresh the bits where the standard data and the margin data at the current byte address of the FLASH are different, and refresh the corresponding bits at the current byte address of the FLASH module to the status of the corresponding bits of the standard data;

[0020] S6. Perform step S3;

[0021] S7. Use the next byte address as the current byte address of the FLASH;

[0022] S8. If the current byte address of the FLASH exceeds the byte address range of the FLASH module, perform step S9; otherwise, perform step S2;

[0023] S9. End a FLASH refresh.

[0024] Preferably, in step S5, only the bits where the standard data and the margin data at the current byte address of the FLASH are different are refreshed, and the bits where the standard data and the margin data at the current byte address of the FLASH are the same are not refreshed.

[0025] Preferably, the processor chip with built-in FLASH further includes a FLASH action arbitration circuit;

[0026] When the programming refresh algorithm circuit performs step S1, it outputs a programming refresh occupancy FLASH control request to the FLASH action arbitration circuit;

[0027] When the CPU issues a FLASH read / write instruction, it outputs a CPU occupancy FLASH control request to the FLASH action arbitration circuit;

[0028] The FLASH action arbitration circuit outputs a control right selection signal according to the programming refresh occupancy FLASH control request output by the programming refresh algorithm circuit and the CPU occupancy FLASH control request output by the CPU, and controls to select the CPU to access the FLASH and prohibit the programming refresh algorithm circuit from programming and refreshing the FLASH, or controls to select the programming refresh algorithm circuit to program and refresh the FLASH and prohibit the CPU from accessing the FLASH.

[0029] Preferably, when both the programming refresh occupancy FLASH control request and the CPU occupancy FLASH control request are received, it controls to select the CPU to access the FLASH and prohibits the programming refresh algorithm circuit from programming and refreshing the FLASH.

[0030] Preferably, in step S9, after ending a FLASH refresh, perform step S1 to start the next FLASH refresh.

[0031] Preferably, the programming refresh algorithm circuit first performs step S1 after being powered on.

[0032] Preferably, the processor chip is an MCU chip.

[0033] Preferably, the byte address is 7-bit, 8-bit, 15-bit, 16-bit, 32-bit, 64-bit or 128-bit.

[0034] Preferably, the margin threshold current is 1.4 to 1.6 times the standard threshold current.

[0035] For the processor chip with built-in FLASH of the present invention, a programming refresh algorithm circuit (program refresh algorithm) is provided. By comparing the standard threshold current and the margin threshold current to read the current byte address of the FLASH respectively, the programming refresh algorithm circuit only programs the current byte address with inconsistent read results of the current byte address of the FLASH, thereby greatly reducing the number of memory cells involved in one refresh of the FLASH. While ensuring the data retention ability of the FLASH, it can avoid the obvious shortening of the service life of the FLASH caused by excessive charge and discharge times of the floating gate of the memory cell, which leads to excessive electron retention in the silicon dioxide insulating layer and affects the correctness of the data stored in the FLASH. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions of the present invention, the following briefly introduces the drawings required for the present invention. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0037] Figure 1 is a schematic diagram of the FLASH memory cell structure;

[0038] Figure 2 Schematic diagram of the structure of an embodiment of the processor with built-in FLASH of the present invention;

[0039] Figure 3 is the working process of the programming refresh algorithm circuit of an embodiment of the processor with built-in FLASH of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0040] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts belong to the scope of protection of the present invention.

[0041] The terms "first", "second" and similar terms used in this application do not denote any order, quantity or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the elements or objects appearing before this term cover the elements or objects listed after this term and their equivalents, without excluding other elements or objects. Terms such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Terms such as "upper", "lower", "left" and "right" are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0042] It should be noted that, without conflict, the embodiments in the present invention and the features in the embodiments may be combined with each other.

[0043] Embodiment 1

[0044] A processor chip with built-in FLASH, as Figure 2 shown, includes a central processing unit (CPU), a FLASH (flash memory) module, and a programming refresh algorithm circuit (program refresh algorithm);

[0045] The programming refresh algorithm circuit is used to output a refresh control instruction refflashctl to the FLASH (flash memory) module;

[0046] As Figure 3 shown, the working process of the programming refresh algorithm circuit is as follows:

[0047] S1. Start, using the default byte address as the current byte address of the FLASH;

[0048] S2. Read the data at the current byte address of the FLASH with the standard threshold current as the standard data;

[0049] S3. Read the data at the current section address of the FLASH with the margin threshold current as the margin data, and the margin threshold current is greater than the standard threshold current;

[0050] S4. If the standard data at the current byte address of the FLASH read in step S2 is different from the margin data, then go to step S5, otherwise go to step S7;

[0051] S5. Output the refresh programming instruction refflashctl to the FLASH (flash memory) module, and only refresh the bits where the standard data and the margin data of the current byte address of the FLASH are different, and refresh the corresponding bits of the current byte address of the FLASH (flash memory) module to the state of the corresponding bits of the standard data; for example, if the standard data of the current byte address of the FLASH is 11010011 and the margin data of the current byte address of the FLASH is 11010111, then refresh the second bit of the current byte address of the FLASH to "0";

[0052] S6. Perform step S3;

[0053] S7. Use the next byte address as the current byte address of the FLASH;

[0054] S8. If the current byte address of the FLASH exceeds the byte address range of the FLASH module, then perform step S9, otherwise perform step S2;

[0055] S9. End a FLASH refresh.

[0056] For the processor chip with built-in FLASH in Embodiment 1, it is provided with a programming refresh algorithm circuit (programrefresh algorithm), reads the current byte address of the FLASH by comparing the standard threshold current and the margin threshold current respectively, and the programming refresh algorithm circuit only programs the current byte address with inconsistent read results of the current byte address of the FLASH, so that the number of storage units involved in a FLASH refresh is greatly reduced. While ensuring the data retention ability of the FLASH, it can avoid the shortening of the service life of the FLASH caused by the excessive charge and discharge times of the floating gates of the storage units, which leads to too much electron retention in the silicon dioxide insulating layer and affects the correctness of the FLASH stored data.

[0057] The processor chip with built-in FLASH in Embodiment 1 can enhance the FLASH data stability at high temperatures and is particularly suitable for application scenarios where it is difficult to reduce the operating temperature.

[0058] Embodiment 2

[0059] Based on the processor chip with built-in FLASH in Embodiment 1, in step S5, only the bits where the standard data and the margin data of the current byte address of the FLASH are different are refreshed, and the bits where the standard data and the margin data of the current byte address of the FLASH are the same are not refreshed. For example, if the standard data of the current byte address of the FLASH is 11010011 and the margin data of the current byte address of the FLASH is 11010111, then only the second bit of the current byte address of the FLASH is refreshed to "0", and the bits 0-1 and 3-7 of the current byte address of the FLASH are not refreshed.

[0060] The processor chip with built-in FLASH in Embodiment 2, when refreshing the FLASH, only refreshes the inconsistent data bits at the byte addresses with inconsistent read results, further reducing the number of memory cells involved in one FLASH refresh.

[0061] Embodiment 3

[0062] Based on Embodiment 1 or 2, the processor chip with built-in FLASH further includes a FLASH action arbitrator;

[0063] When the programming refresh algorithm circuit performs step S1, it outputs a FLASH control request for programming refresh, refactreq, to the FLASH action arbitrator;

[0064] When the CPU issues a FLASH read / write instruction, it outputs a CPU FLASH control request, cpuactreq, to the FLASH action arbitrator;

[0065] The FLASH action arbitrator, based on the FLASH control request for programming refresh, refactreq, output by the programming refresh algorithm circuit and the CPU FLASH control request, cpuactreq, output by the CPU, outputs a control right selection signal, actslect, to control and select CPU access (read / write) to the FLASH and prohibit the programming refresh algorithm circuit from programming and refreshing the FLASH, or control and select the programming refresh algorithm circuit to program and refresh the FLASH and prohibit CPU access (read / write) to the FLASH.

[0066] Preferably, when both the FLASH control request for programming refresh, refactreq, and the CPU FLASH control request, cpuactreq, are received simultaneously, it controls and selects CPU access to the FLASH and prohibits the programming refresh algorithm circuit from programming and refreshing the FLASH. During the period when the CPU does not access the FLASH (FLASH idle state), self-checking and refreshing of the FLASH are achieved through its own programming refresh algorithm. During the period when the CPU accesses the FLASH, the refresh operation is suspended without affecting the CPU execution.

[0067] For the processor chip with built-in FLASH in Embodiment 3, the programming and refreshing algorithm circuit outputs the FLASH control request refactreq for programming and refreshing to the FLASH action arbitration circuit according to its own algorithm. The FLASH action arbitration circuit returns the refreshing enable signal refactack to the programming and refreshing algorithm circuit based on whether the CPU simultaneously issues the FLASH control request cpuactreq. When the state of the refreshing enable signal refactack is 1, the programming and refreshing algorithm circuit can output the programming and refreshing action.

[0068] Embodiment 4

[0069] Based on the processor chip with built-in FLASH in Embodiment 1 or 2, in step S9, after finishing one FLASH refresh, step S1 is performed to start the next FLASH refresh.

[0070] Preferably, the programming and refreshing algorithm circuit first performs step S1 after being powered on.

[0071] Preferably, the processor chip is an MCU (Micro Controller Unit) chip.

[0072] Preferably, the byte address is 7 bits, 8 bits, 15 bits, 16 bits, 32 bits, 64 bits or 128 bits, etc.

[0073] Preferably, the margin threshold current is 1.4 to 1.6 times (e.g., 1.5 times) of the standard threshold current.

[0074] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the scope of protection of the present invention.

Claims

1. A processor chip with built-in FLASH, characterized in that, It includes a central processing unit, a FLASH module, and a programming and refreshing algorithm circuit; The programming and refreshing algorithm circuit is used to output a refreshing programming instruction to the FLASH module; The working process of the programming and refreshing algorithm circuit is as follows: S1. Start, and use the default byte address as the current byte address of the FLASH; S2. Read the data at the current byte address of the FLASH with the standard threshold current as the standard data; S3. Read the data at the current section address of the FLASH with the margin threshold current as the margin data, and the margin threshold current is greater than the standard threshold current; S4. If the standard data and the margin data at the current byte address of the FLASH are different, go to step S5, otherwise go to step S7; S5. Output a refreshing programming instruction to the FLASH module to refresh the bits where the standard data and the margin data at the current byte address of the FLASH are different, and refresh the corresponding bits at the current byte address of the FLASH module to the state of the corresponding bits of the standard data; S6. Go to step S3; S7. Use the next byte address as the current byte address of the FLASH; S8. If the current byte address of the FLASH exceeds the byte address range of the FLASH module, go to step S9, otherwise go to step S2; S9. End a FLASH refresh.

2. The processor chip with built-in FLASH according to claim 1, wherein In step S5, only the bits where the standard data and the margin data at the current byte address of the FLASH are different are refreshed, and the bits where the standard data and the margin data at the current byte address of the FLASH are the same are not refreshed.

3. The processor chip with built-in FLASH according to claim 1 or 2, wherein The processor chip with built-in FLASH further includes a FLASH operation arbitration circuit; When the programming and refreshing algorithm circuit performs step S1, it outputs a programming and refreshing occupation FLASH control request to the FLASH operation arbitration circuit; When the CPU issues a FLASH read / write instruction, it outputs a CPU occupation FLASH control request to the FLASH operation arbitration circuit; The FLASH operation arbitration circuit outputs a control right selection signal according to the programming and refreshing occupation FLASH control request output by the programming and refreshing algorithm circuit and the CPU occupation FLASH control request output by the CPU, and controls to select the CPU to access the FLASH and prohibit the programming and refreshing algorithm circuit from programming and refreshing the FLASH, or controls to select the programming and refreshing algorithm circuit to program and refresh the FLASH and prohibit the CPU from accessing the FLASH.

4. The processor chip with built-in FLASH according to claim 3, wherein When receiving the programming and refreshing occupation FLASH control request and the CPU occupation FLASH control request at the same time, it controls to select the CPU to access the FLASH and prohibits the programming and refreshing algorithm circuit from programming and refreshing the FLASH.

5. The processor chip with built-in FLASH according to claim 1, wherein In step S9, after one FLASH refresh is completed, step S1 is carried out to start the next FLASH refresh.

6. The processor chip with built-in FLASH according to claim 1, characterized in that after the programming refresh algorithm circuit is powered on, step S1 is first carried out.

7. The processor chip with built-in FLASH according to claim 1, characterized in that the processor chip is an MCU chip.

8. The processor chip with built-in FLASH according to claim 1, characterized in that the byte address is 7 bits, 8 bits, 15 bits, 16 bits, 32 bits, 64 bits or 128 bits.

9. The processor chip with built-in FLASH according to claim 1, characterized in that the margin threshold current is 1.4 to 1.6 times the standard threshold current.

Images