Chip wafer level multi-chip simultaneous test circuit, system and method
By designing a chip wafer-level multi-chip test circuit in memory chip testing, and using the collaborative work of the main chip and slave chip, the problem of chip test number restriction caused by limited bidirectional I/O pin resources in the existing technology is solved, and efficient testing and reducing testing costs are achieved.
Patent Information
- Application Number
- CN202510335624.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-20
- Publication Date
- 2025-06-24
AI Technical Summary
In the existing memory chip testing technology, due to the limited bidirectional I/O pin resources, the chip's test number is limited, and it is impossible to reduce the test time and test cost by increasing the test number.
A chip wafer-level multi-chip test circuit is designed. Through the coordinated work of the main chip and multiple slave chips, multiplexers and off-chip wiring are used to realize multiplexed test signals and serial transmission of results, thereby improving the test efficiency.
Through this technology, testing efficiency can be improved, testing costs can be reduced, and synchronous testing of multiple chips can be supported without increasing the chip area.
Smart Images
Figure CN120199308A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of memory chip testing, and particularly relates to a circuit, a system and a method for testing multiple memory chips on a wafer level simultaneously. Background Art
[0002] The testing duration of memory chips is part of the chip cost. Besides being determined by the length of the test program, the testing duration can also save the cost in terms of testing duration by increasing the number of chips tested simultaneously.
[0003] The existing testing technology is that the machine tests the chips on the wafer one-to-many through a probe card. During the test, the read return value of each chip is collected and analyzed. When the machine tests, the test program is output to the receiver (i.e., Pad) of the chip under test through the probes (i.e., pins) on the probe card. At the same time, the output value of the chip under test can also be sampled back to the machine through the pins for test analysis. Since the number of pins for machine testing is limited, the number of pins of the test machine limits the number of chips that can be tested simultaneously by one machine.
[0004] The bidirectional I / O pins (I refers to input, O refers to output, and bidirectional means that a pin has both input and output functions) of the memory chip testing machine are limited in resources. Therefore, the number of I / O pins (i.e., the bidirectional pins of the chip under test, which are input pins when receiving commands and output pins during read operations) of the chips under test that the machine can connect limits the number of chips that can be tested simultaneously by this machine. Thus, it is impossible to reduce the test time and test cost by increasing the number of chips tested simultaneously. Summary of the Invention
[0005] In order to improve the testing efficiency of memory chips at the wafer level, in the first aspect of the present invention, a circuit for testing multiple memory chips on a wafer level simultaneously is provided, including: a main chip, configured to respond to a first signal and perform a detection operation through a multiplexer and an internal bus; and respond to a second signal, and transmit the second signal to each slave chip in sequence through off-chip wiring or a first multiplexer, and receive the test results of one or more slave chips, and integrate and serially transmit the test results to a test bench; a plurality of slave chips, serially connected through off-chip wiring, configured to respond to the second signal, synchronously perform a detection operation within a preset period, and integrate and return the detection results to the main chip step by step through a second multiplexer and off-chip traces.
[0006] In some embodiments of the present invention, the first input terminal and the second input terminal of the first multiplexer are respectively connected to the off-chip wiring and the receiving module of the main chip, and the output terminal of the first multiplexer is connected to the input terminal of the internal bus of the main chip.
[0007] Further, the output ends of the internal bus are respectively connected to an execution module inside the main chip and a first input end of an AND gate, and a second input end of the AND gate receives a second signal through off-chip wiring.
[0008] Preferably, the output end of the AND gate is connected to at least one slave chip through off-chip wiring.
[0009] In some embodiments of the present invention, a first input end and a second input end of the second multiplexer are respectively connected to off-chip wiring and a receiving module of a slave chip, and an output end of the second multiplexer is connected to an input end of an internal bus of the slave chip.
[0010] In the above embodiments, each slave chip further includes: a selection circuit, configured to perform a storage detection or a monitoring test operation and forward a test result in response to the second signal and a plurality of preset enable signals.
[0011] Further, the selection circuit includes: a third multiplexer, configured to determine the validity of the second signal and a plurality of enable signals, and select to perform a storage detection operation, a monitoring test, or forward a test result of the slave chip according to the determination result: if the second signal and a test enable signal of a storage unit are both valid, perform a storage detection operation, and integrate and serially transmit the test result to a test bench for sampling.
[0012] Preferably, input ends of the third multiplexer respectively receive the second signal and enable signals in different modes, and an output end of the third multiplexer is connected to the main chip or the slave chip.
[0013] In a second aspect of the present invention, there is provided a system for co-testing multiple chips at the wafer level of a chip, including: a test bench, configured to send a first signal to the main chip, the main chip being configured to respond to the first signal and perform a detection operation on a storage unit through a multiplexer and an internal bus; and respond to a second signal, and sequentially transmit the second signal to each slave chip through off-chip wiring or a first multiplexer, and receive test results of one or more slave chips, and integrate and serially transmit the test results to the test bench for sampling; a plurality of slave chips, serially connected through off-chip wiring, being configured to respond to the second signal and synchronously perform a detection operation on a storage unit within a preset period, and integrate and return the detection results to the main chip step by step through a second multiplexer and off-chip traces.
[0014] In a third aspect of the present invention, there is provided a test method for a system for co-testing multiple chips at the wafer level of a chip according to the second aspect of the present invention.
[0015] The beneficial effects of the present invention are:
[0016] Through off-chip metal connections and a small amount of on-chip logic overhead, with a clever design concept, the AA (i.e., the device design of the chip) of each Die is made consistent, and only the metal option (i.e., metal connection) is slightly different. While saving the test cost, the impact on the chip area is almost zero, and there is no impact on the number of chips on a wafer. Description of the Drawings
[0017] Figure 1 Schematic diagram of the basic structure of the circuit for multi-chip co-testing at the chip wafer level in some embodiments of the present invention;
[0018] Figure 2 One of the schematic diagrams of the specific structure of the circuit for multi-chip co-testing at the chip wafer level in some embodiments of the present invention;
[0019] Figure 3 Another schematic diagram of the specific structure of the circuit for multi-chip co-testing at the chip wafer level in some embodiments of the present invention;
[0020] Figure 4 Schematic diagram of the wafer structure for co-testing on four chips in some embodiments of the present invention;
[0021] Figure 5 Schematic diagram of the logic of the co-test enable signal of the main chip in some embodiments of the present invention;
[0022] Figure 6 Schematic diagram of the flow of the 4die_en signal or the logic of the co-test enable signal of the slave chip in some embodiments of the present invention;
[0023] Figure 7 Schematic diagram of the structure of the multiplexer when the main chip receives the machine platform command and processes the command in some embodiments of the present invention;
[0024] Figure 8 Schematic diagram of the connection of co-test signals on four chips in some embodiments of the present invention;
[0025] Figure 9 Schematic diagram of the waveform of the main chip when four chips are tested simultaneously in some embodiments of the present invention;
[0026] Figure 10 Schematic diagram of the structure for supporting the monitoring test of a single chip when four chips are co-tested in some embodiments of the present invention;
[0027] Figure 11 Schematic diagram of the waveforms of the input and output of the main chip and the internal enable signals of each co-test chip when four chips are co-tested in some embodiments of the present invention;
[0028] Figure 12Schematic flowchart of the method for co-testing multiple chips at the wafer level of the present invention;
[0029] Reference numerals
[0030] 10. Main chip, 101. First multiplexer;
[0031] 20. Slave chip, 201. Second multiplexer; 202. Third multiplexer;
[0032] 30. Test bench. Detailed implementation manners
[0033] The principles and features of the present invention will be described below with reference to the accompanying drawings. The examples given are only for explaining the present invention and are not intended to limit the scope of the present invention.
[0034] Refer to Figures 1 to 4 , in the first aspect of the present invention, a circuit for co-testing multiple chips at the wafer level is provided, including: a main chip 10, configured to respond to a first signal, perform a storage detection operation through a multiplexer and an internal bus; and output a second signal, and sequentially transmit the second signal to each slave chip 20 through off-chip wiring, and receive test results of one or more slave chips 20, and transmit the test results to a test bench 30 for sampling; a plurality of slave chips 20, serially connected through off-chip wiring, configured to respond to the second signal, synchronously perform corresponding detections within a preset period, and return the detection results to the main chip 10 through a second multiplexer 201.
[0035] It can be understood that for the convenience of description, the above first signal and second signal do not cause changes in the function or flow direction of the signal due to the change of the names "first" and "second" in practice; without loss of generality, the first signal represents a test signal sent by the test bench to the main chip, and the second signal represents a co-test signal or a synchronization signal sent by the main chip to the slave chips. The test operations include, but are not limited to, performance tests, security tests, aging tests, logic device tests, etc. of the chips based on read and write operations, as well as other tests including logic devices or wafer chips.
[0036] In some embodiments of the present invention, the first input terminal and the second input terminal of the first multiplexer 101 in the main chip are respectively connected to the off-chip wiring and the receiving module of the main chip 10, and the output terminal of the first multiplexer 101 is connected to the input terminal of the internal bus of the main chip 10.
[0037] Specifically, refer to Figure 5 and Figure 6, on the Master Die0 (i.e., the main chip, and only the Pads of the main chip (i.e., the inputs of the receivers) are connected to the pick-up stage through the pin card), the 4die_en signal (the enable signal for simultaneous testing of four chips, the second signal) comes from the value in the MR register. After initialization, this enable signal is in an invalid state, and its value can be set to valid through the operation of MRW (i.e., register write operation). When the 4die_en signal is valid, the mode of simultaneous testing of four chips is enabled.
[0038] Set the 4die_en value on the Master Die0 to be valid. When the 4die_en signal on the Master Die0 is valid, this signal will be sent to the three Slave Dies step by step through the off-chip metal traces as shown in Figure 8 . At this time, the function of simultaneous testing of four chips has been enabled.
[0039] After the 4die test function is enabled, at the RCV (i.e., the input signal receiving module of the chip), the internal CMD bus signal of the Master Die0 (i.e., the command signal, the 'CLK', 'CE_n' and 'DQ[7:0]' shown in Figure 7 are command signals) is defaultly input from the RCV bus, that is, only the main chip will receive the commands from the pick-up stage. After the main chip receives the commands from the pick-up stage, on the one hand, it is input into the main chip for internal execution and corresponding command operations are completed, and on the other hand, the main chip will transmit the received commands (i.e., the 'CMD_o' in Figure 8 ) to the next-level slave chips through off-chip traces. Figure 7
[0040] Furthermore, the output ends of the internal bus are respectively connected to the execution module inside the main chip 10 and the first input end of the AND gate, and the second input end of the AND gate receives the second signal through off-chip wiring.
[0041] Preferably, the output end of the AND gate is connected to at least one slave chip 20 through off-chip wiring.
[0042] Figure 7 Refer to Figure 8 and , in some embodiments of the present invention, the first input end and the second input end of the second multiplexer 201 of the slave chip are respectively connected to the off-chip wiring and the receiving module of the slave chip 20, and the output end of the second multiplexer 201 is connected to the input end of the internal bus of the slave chip 20.
[0043] Specifically, the 4die_en signal on the Slave Die (i.e., the slave chip) comes from Master Die0 and is connected level by level through off-chip metal wiring. Only the power Pad of the slave chip (i.e., the receiver of the chip) is connected to the machine tool, and the machine tool only provides power to the slave chip; while all control test commands are sent from the master chip to the slave chip level by level through off-chip traces; the measured data of the slave chip is also transmitted back to the master chip level by level through off-chip traces, and the machine tool then samples the data Pad of the master chip to monitor the test return values of all chips under test.
[0044] When the 4die test function is enabled, at the RCV (i.e., the input signal receiving module of the chip), through the design shown in Figure 7 The internal test control signal of Master Die0 is defaultly input through the RCV bus, that is, only the master chip will receive the machine tool commands (i.e., test control signals). After the master chip receives the commands from the machine tool, on the one hand, it is input into the master chip for internal execution and corresponding command operations are completed, on the other hand, the master chip will transmit the received commands to the next-level slave chip through off-chip traces.
[0045] The test control signals of the Slave die are all input through off-chip traces, that is, the slave chip can only receive the machine tool commands (i.e., test control signals) received by the master chip, and transmit this command to the next slave chip through off-chip traces.
[0046] Next, as shown in Figure 8 Master Die0 receives the machine tool test control command, and transmits the test command (the first signal) to Slave Die1, Die2, and Die3 level by level through the off-chip metal wiring of CLK, CE_n, and DQ (i.e., the test control signals of the chip, command control lines) in the following figure. Slave Die1, the first-level slave chip, can receive the machine tool commands received by the master chip, and transmit this command to Slave Die2 (i.e., the second-level slave chip) through off-chip traces. Similarly, Slave Die2 can receive the command of Die1 and transmit this command to Slave Die3 (i.e., the third-level slave chip).
[0047] After Slave Die3 receives the read command, it transmits the verification result to Die2 through the off-chip trace of Die3_RD (i.e., the test return value of the chip, which needs to be sampled by the machine tool to determine whether the chip function is normal). Die2 integrates the results of Die3 and its own results and transmits them to Die1 together through the off-chip trace of Die2_RD. Die1 serially transmits the test return results of Die1 / 2 / 3 to Master Die0 through the off-chip trace of Die1_RD.
[0048] Finally, on Master Die0, the results of Die0 / 1 / 2 / 3 are serially output together through DQ0 (i.e., bidirectional Pad), and sampled by the machine.
[0049] Reference Figure 9 , which shows a schematic waveform diagram of four chips being tested simultaneously. This diagram is the waveform diagram of the main chip. CLK and CMD are the test control commands received on the machine. When this command is a read command, the main chip starts to output the read detection return value after a fixed number of cycles (RL + 3, RL is read latency, which can be configured by MR). Two clock cycles form a loop unit. In the first half of the first clock cycle, the read detection return value of Master Die0 is output, and in the second half of the first clock cycle, the read detection return value of Slave Die1 is output; in the first half of the second clock cycle, the read detection return value of Slave Die2 is output, and in the second half of the second clock cycle, the read detection return value of Slave Die3 is output; thus, the first complete data output unit ends. When outputting the second set of data, the order of die0->die1->die2->die3 is still maintained, but the read detection return values of different addresses are output (i.e., the 45 marked in the figure represents different read addresses, and the read address in the first unit is 01).
[0050] Reference Figure 3 、 Figure 10 And Figure 11 , in the above embodiments, each of the chips 10 and 20 further includes:
[0051] A selection circuit for responding to the second signal and a preset plurality of enable signals, performing a storage detection or a monitoring test operation, and forwarding the test result.
[0052] Further, the selection circuit includes: a third multiplexer 301 for judging the validity of the second signal and a plurality of enable signals, and selecting to perform a storage detection operation, a monitoring test, or forwarding the test result of the slave chip 20 according to the judgment result: if the second signal and the test enable signal of the storage unit are both valid, perform a storage detection operation, and integrate and serially transmit the test result to the test bench 30 for sampling.
[0053] If the second signal and the monitoring test enable signal are valid, perform the monitoring test operation of the enabled (only one chip can be enabled) chip, and transmit the test result; if the monitoring test enable signal is invalid, only forward the test results from other slave chips 20.
[0054] Specifically, the co-testing circuit also supports outputting the test results of a selected chip on Master Die0. For example, for the function of digital signal monitor (i.e., internal signal monitoring of the chip), it is necessary to transfer the test results of the selected chip to Master Die0 and output them on the basis of co-testing. Through the write operation of MRW, a certain chip among the 4 chips is selected, and then only the selected Die will execute the corresponding test command. As Figure 10 and Figure 11 , only the TM_DP_MON_sel of the selected chip (i.e., a test mode signal that can enable the mathematical signal monitor function of the chip) will be set to 1 and be valid. Therefore, only the selected chip will connect the monitor signal (i.e., test result) of this chip to Die_mon_o (i.e., the output port corresponding to the test) for output. The remaining chips are in the unselected mode and will only directly output the Die_mon_o signal from the previous chip to the Die_mon_o of this chip. That is, only the selected chip can transmit its test result signal level by level to the main chip and output it, and finally be sampled by the machine.
[0055] The Slave die can transmit the test results back to Master Die0 through the off-chip connection of Die_mon_o (i.e., the output port of the monitored digital signal of the slave chip), but only the results of the selected Die will be output on DQ0 (the bidirectional Pad port on the main chip) of Master Die0. As Figure 11 the waveform schematic diagram shows that Die1 is selected and only the 'emrs_en' test enable signal of Die1 is 1.
[0056] It should be noted that although the above takes 1 main chip and 3 slave chips as an example, it does not affect the extension of the above method to more than 4 co-testing chips on the wafer. And except for the different external wirings between the main chip and the slave chips, their internal structures are the same.
[0057] Embodiment 2
[0058] Continue to refer to Figures 1 to 3, in the second aspect of the present invention, a system for multi-chip co-testing at the chip wafer level is provided, including: a test bench 30 for sending a first signal to the main chip; a main chip 10 configured to respond to the first signal and perform a detection operation on the storage unit through a multiplexer and an internal bus; and in response to a second signal, sequentially transmit the second signal to each slave chip 20 through off-chip wiring or a first multiplexer 101, receive the test results of one or more slave chips 20, and integrate and serially transmit the test results to the test bench 30 for sampling; a plurality of slave chips 20 serially connected through off-chip wiring, configured to respond to the second signal, synchronously perform a detection operation on the storage unit within a preset period, and integrate and return the detection results to the main chip 10 through a second multiplexer 201 and off-chip traces step by step.
[0059] Embodiment 3
[0060] Reference Figure 12 , in the third aspect of the present invention, a testing method for a system for multi-chip co-testing at the chip wafer level based on the second aspect of the present invention is provided, including a test bench, a main chip, and a plurality of slave chips. S100. The test bench sends a first signal to the main chip; S200. The main chip responds to the first signal and performs a storage detection operation through a multiplexer and an internal bus; and in response to a second signal, sequentially transmit the second signal to each slave chip through off-chip wiring or a first multiplexer, and receive the test results of one or more slave chips, and transmit the test results to the test bench for sampling; S300. A plurality of slave chips, serially connected through off-chip wiring, are configured to respond to the second signal, synchronously perform storage detection within a preset period, and return the detection results to the main chip through a second multiplexer.
[0061] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagram may represent a module, a program segment, or a part of code that includes one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than that marked in the accompanying drawings. For example, two consecutive blocks shown may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. It should be noted that each block in the block diagram and / or flowchart, and the combination of blocks in the block diagram and / or flowchart, can be implemented by a dedicated hardware-based system for performing the specified functions or operations, or can be implemented by a combination of dedicated hardware and computer instructions.
[0062] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.
Claims
1. A circuit for simultaneous testing of multiple chips at wafer level, characterized in that: include: A master chip is configured to perform a detection operation through a multiplexer and an internal bus in response to a first signal; and in response to the second signal, transmitting the second signal to each slave chip in sequence through off-chip wiring or a first multiplexer, receiving test results of one or more slave chips, and integrating and serially transmitting the test results to the test station; Multiple slave chips are serially connected via off-chip wiring, and are configured to respond to a second signal, synchronously perform detection operations within a preset period, and integrate the detection results step by step through a second multiplexer and off-chip wiring and return them to the master chip.
2. The circuit for simultaneously testing multiple chips at the wafer level according to claim 1, characterized in that: The first input terminal and the second input terminal of the first multiplexer are respectively connected to the off-chip wiring and the receiving module of the main chip, and the output terminal of the first multiplexer is connected to the input terminal of the internal bus of the main chip.
3. The circuit for simultaneously testing multiple chips at the wafer level according to claim 2, characterized in that: The output end of the internal bus is connected to the execution module inside the main chip and the first input end of the AND gate respectively, and the second input end of the AND gate receives the second signal through off-chip wiring.
4. The circuit for simultaneously testing multiple chips at the wafer level according to claim 3, characterized in that: The output end of the AND gate is connected to at least one slave chip through off-chip wiring.
5. The circuit for simultaneously testing multiple chips at the wafer level according to claim 1, characterized in that: The first input terminal and the second input terminal of the second multiplexer are respectively connected to the off-chip wiring and the receiving module of the slave chip, and the output terminal of the second multiplexer is connected to the input terminal of the internal bus of the slave chip.
6. The circuit for simultaneously testing multiple chips at the wafer level according to claim 1, characterized in that: Each slave chip also includes: The selection circuit is used for executing a storage detection or monitoring test operation and forwarding a test result in response to a second signal and a plurality of preset enable signals.
7. The circuit for simultaneously testing multiple chips at the wafer level according to claim 6, characterized in that: The selection circuit comprises: The third multiplexer is used to judge the validity of the second signal and the multiple enable signals, and select to perform a storage detection operation, a monitoring test or forward the test result of the slave chip according to the judgment result: If the second signal and the test enable signal of the storage unit are both valid, a storage detection operation is performed, and the test results are integrated and transmitted serially to the test bench for sampling.
8. The circuit for simultaneously testing multiple chips at the wafer level according to claim 7, characterized in that: The input end of the third multiplexer receives the second signal and the preset monitoring signal respectively, and the output end of the third multiplexer is connected to the master chip or the slave chip.
9. A system for simultaneously testing multiple chips at the wafer level, comprising: A test bench, used for sending a first signal to the main chip; A main chip is configured to respond to the first signal and perform a detection operation of the storage unit through the multiplexer and the internal bus; and in response to the second signal, transmitting the second signal to each slave chip in sequence through off-chip wiring or a first multiplexer, receiving test results of one or more slave chips, and integrating and transmitting the test results in series to a test bench for sampling; Multiple slave chips are connected in series through off-chip wiring, and are configured to respond to the second signal, synchronously perform detection operations on the storage units within a preset period, and integrate the detection results step by step through the second multiplexer and off-chip wiring and return them to the master chip.
10. A method for simultaneously testing multiple chips at the wafer level, comprising a test bench, a master chip and a plurality of slave chips, characterized in that: include: The test bench sends a first signal to the main chip; The main chip responds to the first signal and performs a detection operation of the storage unit through the multiplexer and the internal bus; and in response to the second signal, transmitting the second signal to each slave chip in sequence through off-chip wiring or a first multiplexer, receiving test results of one or more slave chips, and integrating and transmitting the test results in series to a test bench for sampling; The plurality of slave chips respond to the second signal and are connected in series via off-chip wiring; And in response to the second signal, the detection operation of the storage unit is synchronously performed within a preset period, and the detection result is integrated step by step through the second multiplexer and the off-chip wiring and returned to the main chip.