Semiconductor memory

Abstract

The invention provides a semiconductor memory which comprises a built-in self-test module, an internal control module and an address repair module, the built-in self-test module is used for receiving a mode register write instruction sent by an external control module and generating a parallel test instruction according to the mode register write instruction, and the internal control module is used for receiving the parallel test instruction and repairing the parallel test instruction according to the parallel test instruction. And simultaneously testing the plurality of storage libraries according to the parallel test instruction to obtain a fault address. The repair address module is used for decoding the fault address to determine the address of the fault storage area, sending the address of the fault storage area to the internal control module, receiving repair resource information sent by the internal control module, generating a repair identifier according to the repair resource information, and sending the repair identifier to the internal control module; the repair resource information is determined by the internal control module according to the address of the fault storage area, so that the fault storage area can be replaced based on the repair identifier, and the yield of the semiconductor memory is improved.

Description

Technical Field

[0001] This application relates to, but is not limited to, a semiconductor memory. Background Art

[0002] With the popularization of electronic devices such as mobile phones, tablets, and personal computers, semiconductor memory technology has also developed rapidly.

[0003] Semiconductor memories provide a Memory Build-In-Self Test (MBIST) function. The MBIST function means that the test vectors of the semiconductor memory are automatically generated by a built-in test module. Compared with testing a semiconductor memory using an external test machine, in an MBIST test, only by transmitting test instructions through the machine, the test results can be obtained from the interface.

[0004] The design of the built-in self-test function has also been one of the improvement directions of semiconductor memories. Summary of the Invention

[0005] This application provides a semiconductor memory, including:

[0006] A built-in self-test module, configured to receive a mode register write instruction sent by an external control module, and generate a parallel test instruction according to the mode register write instruction;

[0007] An internal control module, configured to receive the parallel test instruction, and simultaneously test multiple memory banks according to the parallel test instruction to obtain a fault address;

[0008] A repair address module, configured to decode the fault address to determine the address of the faulty storage area, send the address of the faulty storage area to the internal control module, and receive the repair resource information sent by the internal control module, and generate a repair flag according to the repair resource information; wherein, the repair resource information is determined by the internal control module according to the address of the faulty storage area.

[0009] In some embodiments, the built-in self-test module is further configured to generate and send a prompt signal to the external control module, so that the external control module generates a mode register read instruction;

[0010] The repair address module receives the mode register read instruction, and sends the repair flag to the external control module, so that the external control module controls the startup mode of the semiconductor memory according to the repair flag.

[0011] In some embodiments, the built-in self-test module includes:

[0012] A read / write mode circuit, configured to output a read / write mode signal;

[0013] An instruction circuit that receives a read / write mode signal and periodically outputs read / write instructions and a counting clock signal based on the read / write mode signal;

[0014] An address counter that receives the read / write mode signal and the counting clock signal, counts the read / write address using the counting clock signal based on the read / write mode signal, and outputs a built-in self-test end signal when the count value reaches a target value.

[0015] In some embodiments, the repair address module also receives the count value output by the address counter and decodes the faulty address to determine the address of the faulty storage area when the count value reaches the target value.

[0016] In some embodiments, the instruction circuit is configured to periodically output write instructions and a write counting clock signal according to the read / write mode signal; after receiving the read / write switching signal output by the address counter, it periodically outputs read instructions and a read counting clock signal according to the read / write switching signal;

[0017] The address counter is used to count the write address under the control of the read / write mode signal and the write counting clock signal, and output a read / write switching signal when the write count value reaches a preset quantity threshold; it is also used to count the read address under the control of the read / write mode signal and the read counting clock signal, and output a built-in self-test end signal when the read count value reaches the preset quantity threshold.

[0018] In some embodiments, when the read / write mode signal represents the fast column mode, the instruction circuit periodically outputs write instructions and a write column counting clock signal according to the read / write mode signal; correspondingly, the address counter includes:

[0019] A column counter that receives the write column counting clock signal, counts the write column address under the control of the write column counting clock signal, outputs a write column counter end signal when the write column count value meets the column counting target value, and clears the count value of the column counter; it outputs a write column counter termination signal when receiving the write row counter termination signal;

[0020] A row counter that receives the write column counter end signal, counts the write row address under the control of the write column counter end signal, and outputs a write row counter termination signal when the write row count value meets the row counting target value.

[0021] In some embodiments, when the read / write mode signal represents the fast row mode, the instruction circuit periodically outputs write instructions and a write row counting clock signal according to the read / write mode signal; correspondingly, the address counter includes:

[0022] A row counter that receives a write row count clock signal, counts the write row address under the control of the write row count clock signal, outputs a write row counter end signal when the write row count value meets the row count target value, clears the count value of the row counter, and is also used to output a write row counter termination signal when receiving a write column counter termination signal;

[0023] A column counter that receives the write row counter end signal, counts the write column address under the control of the write row counter end signal, and outputs a write column counter termination signal when the write column count value meets the column count target value.

[0024] In some embodiments, when the read / write mode signal represents the fast column mode, the instruction circuit periodically outputs a read instruction and a read column count clock signal according to the read / write mode signal; correspondingly, the address counter includes:

[0025] A column counter that receives the read column count clock signal, counts the read column address under the control of the read column count clock signal, outputs a read column counter end signal when the column count value meets the column count target value, and clears the count value of the column counter; outputs a read column counter termination signal when receiving a read row counter termination signal;

[0026] A row counter that receives the read column counter end signal, counts the read row address under the control of the read column counter end signal, and outputs a read row counter termination signal when the read row count value meets the row count target value.

[0027] In some embodiments, when the read / write mode signal represents the fast row mode, the instruction circuit periodically outputs a read instruction and a read row count clock signal according to the read / write mode signal; correspondingly, the address counter includes:

[0028] A row counter that receives the read row count clock signal, counts the read row address under the control of the read row count clock signal, outputs a read row counter end signal when the read row count value meets the row count target value, clears the count value of the row counter, and is also used to output a read row counter termination signal when receiving a read column counter termination signal;

[0029] A column counter that receives the read column counter end signal, counts the read column address under the control of the read column counter end signal, and outputs a read column counter termination signal when the column count value meets the column count target value.

[0030] In some embodiments, the built-in self-test module includes:

[0031] A first mode register, which is configured to receive a mode register write instruction, generate a first enable signal according to the mode register write instruction, further receive a built-in self-test end signal output by an address counter, and generate a second enable signal according to the built-in self-test end signal;

[0032] A clock unit, which receives the first enable signal, generates a test clock signal according to the first enable signal, and makes a prompt signal at a first level; stops outputting the test clock signal according to the second enable signal, and makes the prompt signal at a second level;

[0033] Wherein, the test clock signal controls the operation of a read-write mode circuit, an instruction circuit, an address counter, and a repair address module.

[0034] In some embodiments, the repair address module includes:

[0035] A decoding circuit, which is configured to decode a fault address to determine the address of a fault storage area, and send the address of the fault storage area to an internal control module;

[0036] A second mode register, which receives repair resource information sent by the internal control module, and generates and stores a repair identifier according to the repair resource information.

[0037] The semiconductor memory provided by this application includes a built-in self-test module, an internal control module, and a repair address module. When the built-in self-test module receives a mode register write instruction sent by an external control module outside the semiconductor memory, it generates and sends a parallel test instruction to the internal control module, enabling the internal control module to test multiple memory banks simultaneously, thereby improving the test efficiency. After obtaining the fault address, the fault address is decoded to obtain the address of the fault storage area, so as to determine whether there are repairable faults, determine the repair resource information, and then generate a repair identifier based on the repair resource information, and further replace the fault storage area based on the repair identifier, improving the yield of the semiconductor memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The drawings herein are incorporated into the specification and constitute a part of this specification, showing embodiments consistent with this application, and are used together with the specification to explain the principles of this application.

[0039] Figure 1 It is a schematic structural diagram of a semiconductor memory provided by some embodiments of this application;

[0040] Figure 2 It is a schematic structural diagram of a semiconductor memory provided by other embodiments of this application;

[0041] Figure 3 It is a schematic structural diagram of a semiconductor memory provided by yet other embodiments of this application;

[0042] Figure 4 A structural schematic diagram of a semiconductor memory provided for some other embodiments of the present application;

[0043] Figure 5 A structural schematic diagram of a semiconductor memory provided for some other embodiments of the present application.

[0044] Reference numerals:

[0045] 100, Built-in self-test module; 110, First mode register; 120, Clock unit; 130, Read / write mode circuit; 140, Address counting circuit; 150, Instruction circuit; 200, Repair address module; 210, Decoding circuit; 220, Second mode register; 141, Column counter; 142, Row counter; 300, External control module; 400, Internal control module.

[0046] Through the above-mentioned drawings, specific embodiments of the present application have been shown, and there will be more detailed descriptions hereinafter. These drawings and textual descriptions are not intended to limit the scope of the concept of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. Detailed description of specific embodiments

[0047] Here, exemplary embodiments will be described in detail, and examples are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0048] It should be noted that the so-called high level and low level mentioned below are relative concepts (that is, the voltage value of the high level is higher than the voltage value of the corresponding low level), without limiting the specific voltage value of the high level, nor the specific voltage value of the low level. And it does not limit that the high levels applied on different signal lines in this specific embodiment are equal. For example, the high level on the bit line and the high level on the word line can be different voltages, nor does it limit that the high levels of a specific signal line are equal at different stages. For example, the high levels applied on the bit line during the write 1 operation and the read operation can be different voltage values. Those skilled in the art should understand that the corresponding high level and low level values can be set by themselves according to process nodes, speed requirements, reliability requirements, etc.

[0049] As Figure 1 shown, some embodiments of the present application provide a semiconductor memory, and the semiconductor memory includes a built-in self-test module 100, an internal control module 400, and a repair address module 200.

[0050] The built-in self-test module 100 is used to receive a mode register write instruction (abbreviated as MRW: Mode Register Write) sent by the external control module 300, and generate parallel test instructions according to the mode register write instruction.

[0051] The internal control module 400 is used to receive the parallel test instructions, and simultaneously test multiple memory banks according to the parallel test instructions to obtain the fault address.

[0052] The repair address module 200 is used to decode the fault address to determine the address of the faulty memory area, send the address of the faulty memory area to the internal control module 400, and receive the repair resource information sent by the internal control module 400, and generate a repair flag according to the repair resource information. Among them, the repair resource information is determined by the internal control module 400 according to the address of the faulty memory area.

[0053] Among them, the semiconductor memory includes multiple bank groups, each bank group includes multiple memory banks, each memory bank includes multiple memory areas, and each memory area includes at least one memory cell. The external control module 300 outside the semiconductor memory sends a mode register write instruction MRW to the built-in self-test module 100, and the built-in self-test module 100 generates parallel test instructions according to the mode register write instruction MRW. The internal control module 400 simultaneously tests multiple memory banks based on the parallel test instructions to obtain the fault address. Then, the repair address module 200 decodes the fault address to determine the address of the faulty memory area, and the repair address module 200 sends the address of the faulty memory area to the internal control module 400. The internal control module 400 determines the repair resource information according to the address of the faulty memory area, and generates a repair flag based on the repair resource information.

[0054] In the semiconductor memory, the memory area occupies a large chip area of the semiconductor memory, which has an important impact on the yield of the semiconductor memory. In order to reduce the impact of the memory area on the chip yield, redundant memory areas are usually added to replace the faulty area obtained by the built-in self-test in a timely manner.

[0055] The failure address is a parallel address. By decoding the failure address, the memory bank address where the failed storage area is located, the memory repository address where the failed storage area is located, and the row address of the failed storage area are obtained. Then, based on the memory bank address where the failed storage area is located, the memory repository address where the failed storage area is located, and the row address of the failed storage area, it is determined whether there are repair resources for the failed storage area, and repair resource information is generated according to the determination result. If it is determined that there are repair resources for the failed storage area, the generated repair resource information indicates the existence of repair resources. If it is determined that there are no repair resources for the failed storage area, the generated repair resource information indicates the non-existence of repair resources.

[0056] In the above technical solution, the semiconductor memory includes a built-in self-test module 100, an internal control module 400, and a repair address module 200. When the built-in self-test module 100 receives a mode register write instruction MRW sent by an external control module 300, it generates and sends a parallel test instruction to the internal control module 400, enabling the internal control module 400 to test multiple memory repositories simultaneously, thereby improving the test efficiency. After obtaining the failure address, the failure address is decoded to obtain the address of the failed storage area, so that it is possible to determine whether there are repairable failures, determine the repair resource information, and then generate a repair identifier based on the repair resource information. Furthermore, based on the repair identifier, the failed storage area can be replaced, improving the yield of the semiconductor memory.

[0057] In some embodiments, the built-in self-test module 100 is further configured to generate a prompt signal ALERT_n when it determines that the testing of multiple memory repositories is completed, and send the prompt signal ALERT_n to the external control module 300, enabling the external control module 300 to generate a mode register read instruction (Mode Register Read, abbreviated as: MRR). The repair address module 200 receives the mode register read instruction MRR sent by the external control module 300 and sends a repair identifier to the external control module 300, enabling the external control module 300 to control the startup mode of the semiconductor memory according to the repair identifier.

[0058] Among them, the prompt signal ALERT_n is used to prompt the external control module 300 that the current built-in self-test is completed. When the external control module 300 receives the prompt signal ALERT_n, it generates a mode register read instruction MRR. The identification information is stored in the mode register of the repair address module. The mode register read instruction MRR is used to read the information in the mode register. In this way, the external control module 300 reads the repair identifier, and after reading the repair identifier, it controls the startup mode of the semiconductor memory according to the repair identifier.

[0059] In some embodiments, when the built-in self-test module 100 determines that the internal control module 400 has completed testing multiple repositories, it generates a built-in self-test end signal MBIST_END, then generates a prompt signal ALERT_n according to the built-in self-test end signal MBIST_END, and sends the prompt signal ALERT_n to the external control module 300. The prompt signal ALERT_n is used to prompt the end of the built-in self-test.

[0060] In the above technical solution, when the external control module 300 sends a mode register write instruction MRW to trigger the built-in self-test of the semiconductor memory, after the built-in self-test is completed, the built-in self-test module 100 generates and sends a prompt signal ALERT_n to the external control module 300, so that the external control module 300 can generate a mode register read instruction to read the repair flag in the repair address module and control the startup mode of the semiconductor memory to start again based on the repair flag.

[0061] In some embodiments, the repair address module 200 includes a decoding circuit 210 and a second mode register 220. The decoding circuit 210 is used to decode the faulty address to determine the address of the faulty storage area and send the address of the faulty storage area to the internal control module 400. The second mode register 220 receives the repair resource information sent by the internal control module 400 and generates and stores a repair flag according to the repair resource information. Thus, after the built-in self-test is completed, the external control module 300 can generate a mode register read instruction to read the repair flag stored in the second mode register 220 and control the startup mode of the semiconductor memory according to the repair flag.

[0062] In some embodiments, the repair flag is used to indicate that the semiconductor memory has no faults, the semiconductor memory has repairable faults, the semiconductor memory has irreparable faults, and the built-in self-test continues.

[0063] When the repair flag indicates that the semiconductor memory has repairable faults, the external control module 300 controls the semiconductor memory to repair the faults and updates the repair flag so that the updated repair flag indicates that the built-in self-test continues. When the repair flag indicates that the semiconductor memory has irreparable faults or no faults, the external control module 300 is used to control the semiconductor memory to start normally.

[0064] More specifically, the external control module 300 reads the repair flag. When the repair flag indicates that there is a repairable fault in the semiconductor memory, the external control module 300 controls the semiconductor memory to perform fault repair and updates the repair flag. After the fault repair is completed, the external control module 300 reads the repair flag. When the repair flag indicates to continue the built-in self-test, the external control module 300 controls the built-in self-test module to generate parallel test instructions, tests multiple memory banks according to the parallel test instructions, and updates the repair flag according to the test results. When the repair flag continues to indicate that there is a repairable fault in the semiconductor memory, the external control module 300 continues to control the semiconductor memory to perform fault repair and updates the repair flag. This cycle continues until the repair flag indicates that there is an irreparable fault or no fault in the semiconductor memory, and then the external control module 300 controls the semiconductor memory to start normally.

[0065] In the above technical solution, when the repair flag indicates that there is a repairable fault in the semiconductor memory, the external control module 300 controls the semiconductor memory to perform fault repair and updates the repair flag, so that the updated repair flag indicates to continue the built-in self-test. After the next built-in self-test is completed, the repair flag is updated, and it is determined whether to perform repair based on the repair flag. After multiple such cycles, the repair of the faulty storage area in the semiconductor memory can be completed, improving the yield of the semiconductor memory.

[0066] In some embodiments, the built-in self-test module 100 includes a read / write mode circuit 130, an instruction circuit 150, and an address counter 140.

[0067] The read / write mode circuit 130 is used to output a read / write mode signal. The instruction circuit 150 receives the read / write mode signal and periodically outputs read / write instructions and a count clock signal CNT_CLK based on the read / write mode signal. The address counter 140 counts the read / write addresses under the control of the read / write mode signal and the count clock signal CNT_CLK, and outputs a built-in self-test end signal MBIST_END when the count value reaches a target value.

[0068] Since there are multiple storage areas in each memory bank, it takes multiple write operations to complete the data writing of all storage units in a memory bank. Correspondingly, it takes multiple read operations to complete the data reading of all storage units in a memory bank.

[0069] To perform a complete MBIST operation on a semiconductor memory, access to rows and columns in all banks of all memory banks is required. It is only necessary to count the rows and columns read and written during the MBIST operation to determine whether the MBIST operation is completed. More specifically, each time a read / write instruction is output, a count clock signal CNT_CLK is also generated, causing the address counter 140 to count the read / write addresses under the control of the read / write mode signal and the count clock signal CNT_CLK.

[0070] The read / write mode signal includes a fast column mode and a fast row mode. The fast column mode includes a first fast column mode and a second fast column mode. The fast row mode is marked as XFAST, the first fast column mode is marked as YFAST, and the second fast column mode is marked as YPFAST. Different read / write mode signals correspond to different address counting methods. The address counter 140 counts the read / write addresses under the control of the read / write mode signal and the count clock signal CNT_CLK to adapt to different read / write modes, and outputs a built-in self-test end signal MBIST_END when the count value reaches the target value. The target value is determined based on the number of rows and columns of the memory cells in the semiconductor memory. When the count value reaches the target value, it indicates that the test of all memory cells in the semiconductor memory has been completed.

[0071] Among them, the read / write instruction includes a read instruction and a write instruction. The read instruction includes one or more combinations of a built-in self-test activation signal MBIST_ACT, a built-in self-test read signal MBIST_RD, a built-in self-test precharge signal MBIST_PRE, and a built-in self-test refresh signal MBIST_REF. The write instruction includes one or more combinations of a built-in self-test activation signal MBIST_ACT, a built-in self-test write signal MBIST_WR, a built-in self-test precharge signal MBIST_PRE, and a built-in self-test refresh signal MBIST_REF.

[0072] In the above technical solution, the built-in self-test module 100 includes a read / write mode circuit 130, an instruction circuit 150, and an address counter 140. The read / write mode circuit 130 is used to output a read / write mode signal, causing the instruction circuit 150 to generate a read / write instruction and a count clock signal CNT_CLK based on the read / write mode signal. The read / write instruction is used to read or write data to the memory cells. The address counter 140 counts the read / write addresses under the control of the read / write mode signal and the count clock signal CNT_CLK, and determines whether the built-in self-test is completed based on the count value.

[0073] In some embodiments, the repair address module 200 also receives the count value output by the address counter 140, and decodes the fault address when the count value is the target value to determine the address of the faulty storage area. When the count value is the target value, it indicates that the test of all storage units in the semiconductor memory has been completed. The repair address module 200 receives the fault address output by the internal control module 400 and decodes the fault address to determine the address of the faulty storage area, so as to ensure that the repair address module 200 can accurately decode the address of the faulty storage area.

[0074] In some embodiments, the instruction circuit 150 is configured to periodically output write instructions and write count clock signals according to the read / write mode signal. After receiving the read / write switching signal WR2RD output by the address counter 140, the instruction circuit 150 periodically outputs read instructions and read count clock signals according to the read / write switching signal WR2RD.

[0075] The address counter 140 counts the write address under the control of the read / write mode signal and the write count clock signal, and outputs the read / write switching signal WR2RD when the write count value reaches the preset quantity threshold. The address counter 140 also counts the read address under the control of the read / write mode signal and the read count clock signal, and outputs the built-in self-test end signal MBIST_END when the read count value reaches the preset quantity threshold.

[0076] Among them, the read / write instructions include write instructions and read instructions. The instruction circuit 150 is configured to periodically output write instructions and write count clock signals according to the read / write mode signal. The instruction circuit 150 is configured to send the write instructions to the internal control module 400, and the internal control module 400 writes data into multiple memory banks under the control of the write instructions. The instruction circuit 150 is also configured to output the write count clock signal to the address counter 140. The address counter 140 also receives the read / write mode signal. The address counter 140 counts the write address under the control of the read / write mode signal and the write count clock signal, and outputs the read / write switching signal WR2RD when the write count value reaches the preset quantity threshold. The preset quantity threshold is determined according to the total number of storage units in the semiconductor memory. When the write count value reaches the preset quantity threshold, it is determined that the data writing of all storage units in the semiconductor memory is completed, and then the read / write switching signal WR2RD is output.

[0077] After receiving the read / write switching signal WR2RD output by the address counter 140, the instruction circuit 150 periodically outputs a read instruction and a read count clock signal according to the read / write switching signal WR2RD. The instruction circuit 150 is used to send the read instruction to the internal control module 400, and the internal control module 400 reads data from multiple memory banks under the control of the read instruction. The address counter 140 is further used to count the read address under the control of the read / write mode signal and the read count clock signal, and output a built-in self-test end signal MBIST_END when the read count value reaches a preset quantity threshold. When the read count value reaches the preset quantity threshold, it is determined that the data reading of all memory cells in the semiconductor memory is completed. The internal control module 400 determines whether there is a fault in each memory bank based on the written data in each memory cell and the read data from each memory cell. When the read count value reaches the preset quantity threshold, it is determined that the data reading of all memory cells in the semiconductor memory is completed, and the instruction circuit 150 outputs a built-in self-test end signal MBIST_END.

[0078] In the above technical solution, the instruction circuit 150 periodically outputs a write instruction and a write count clock signal according to the read / write mode signal. The address counter 140 counts the write address under the control of the read / write mode signal and the write count clock signal, and outputs a read / write switching signal WR2RD when the write count value reaches a preset quantity threshold. After receiving the read / write switching signal WR2RD output by the address counter 140, the instruction circuit 150 periodically outputs a read instruction and a read count clock signal according to the read / write switching signal WR2RD. The address counter 140 also counts the read address under the control of the read / write mode signal and the read count clock signal, and outputs a built-in self-test end signal MBIST_END when the read count value reaches a preset quantity threshold. By using the write count clock signal and the read count clock signal to count the write address and the read address respectively, it is determined whether the test of all memory cells in the semiconductor memory is completed.

[0079] In some embodiments, such as Figure 2As shown, when the read / write mode signal represents the fast column mode, the instruction circuit 150 periodically outputs a write instruction and a write column count clock signal WCOL_CNT_CLK according to the read / write mode signal. The address counter 140 includes a column counter 141 and a row counter 142. The column counter 141 counts the column address under the control of the read / write mode signal and the write column count clock signal WCOL_CNT_CLK, outputs a write column counter end signal WCOL_ADD_END when the write column count value meets the column count target value, and clears the count value of the column counter 141. The row counter 142 counts the row address under the control of the write column counter end signal WCOL_ADD_END, outputs a write row counter termination signal WROW_CNT_ALL when the write row count value WROWCNT meets the row count target value, and the column counter 141 outputs a write column counter termination signal WCOL_CNT_ALL when it receives the write row counter termination signal WROW_CNT_ALL.

[0080] When the read / write mode signal represents the fast column mode, the instruction circuit 150 periodically outputs a write instruction and a write column count clock signal WCOL_CNT_CLK according to the read / write mode signal. The write instruction includes one or a combination of a built-in self-test activation signal MBIST_ACT, a built-in self-test write signal MBIST_WR, a built-in self-test precharge signal MBIST_PRE, and a built-in self-test refresh signal MBIST_REF.

[0081] The instruction circuit 150 outputs the write column count clock signal WCOL_CNT_CLK to the column counter 141. The column counter 141 counts the write column address under the control of the write column count clock signal WCOL_CNT_CLK, outputs a write column counter end signal WCOL_ADD_END when the write column count value meets the column count target value, and clears the count value of the column counter 141. The column counter 141 continues to receive the write column count clock signal WCOL_CNT_CLK sent by the instruction circuit 150, continues to count the write column address under the control of the write column count clock signal WCOL_CNT_CLK, outputs a write column counter end signal WCOL_ADD_END when the write column count value meets the column count target value, and clears the count value of the column counter 141. Such counting is repeated until the instruction circuit 150 stops outputting the write instruction and the write column count clock signal WCOL_CNT_CLK.

[0082] When the column counter 141 generates the write column counter end signal WCOL_ADD_END, it sends the write column counter end signal WCOL_ADD_END to the row counter 142. The row counter 142 counts the write row address under the control of the write column counter end signal WCOL_ADD_END, and outputs the write row counter termination signal WROW_CNT_ALL when the write row count value WROWCNT meets the row count target value. The row counter 142 sends the write row counter termination signal WROW_CNT_ALL to the column counter 141. The column counter 141 outputs the write column counter termination signal WCOL_CNT_ALL when it receives the write row counter termination signal WROW_CNT_ALL. When the row counter 142 outputs the write row counter termination signal WROW_CNT_ALL and the column counter 141 outputs the write column counter termination signal WCOL_CNT_ALL, the instruction circuit 150 stops outputting the write instruction and the write column count clock signal WCOL_CNT_CLK. The row counter also sends the write row count value WROWCNT to the decoding circuit, so that the decoding circuit decodes the fault address when it receives the write row count value WROWCNT and outputs the address of the fault storage area.

[0083] In the above counting scheme, the column counter 141 counts the write column address under the control of the read / write mode signal and the write column count clock signal WCOL_CNT_CLK, outputs the write column counter end signal WCOL_ADD_END when the write column count value meets the column count target value, and clears the count value of the column counter 141. The row counter 142 counts the write row address under the control of the write column counter end signal WCOL_ADD_END, and outputs the write row counter termination signal WROW_CNT_ALL when the write row count value WROWCNT meets the row count target value. The column counter 141 outputs the write column counter termination signal WCOL_CNT_ALL when it receives the write row counter termination signal WROW_CNT_ALL, so as to determine whether the test of all memory cells in the semiconductor memory is completed.

[0084] In some embodiments, such as Figure 3As shown, when the read / write mode signal characterizes the fast row mode XFAST, the instruction circuit 150 periodically outputs a write instruction and a write row count clock signal WROW_CNT_CLK according to the read / write mode signal. The address counter 140 includes a row counter 142 and a column counter 141. The row counter 142 counts the write row address under the control of the write row count clock signal WROW_CNT_CLK, outputs a write row counter end signal WROW_ADD_END when the write row count value meets the row count target value, and clears the count value of the row counter 142. The column counter 141 counts the write column address under the control of the write row counter end signal WROW_ADD_END, and outputs a write column counter termination signal WCOL_CNT_ALL when the write column count value WCOLCNT meets the column count target value. The row counter 142 is further configured to output a write row counter termination signal WROW_CNT_ALL when receiving the write column counter termination signal WCOL_CNT_ALL.

[0085] The instruction circuit 150 outputs the write row count clock signal WROW_CNT_CLK to the row counter 142. The row counter 142 counts the write row address under the control of the write row count clock signal WROW_CNT_CLK, outputs a write row counter end signal WROW_ADD_END when the write row count value meets the row count target value, and clears the count value of the row counter 142. The row counter 142 continues to receive the write row count clock signal WROW_CNT_CLK sent by the instruction circuit 150. The row counter 142 continues to count the write row address under the control of the write row count clock signal WROW_CNT_CLK, outputs a row write counter end signal WROW_ADD_END when the write row count value meets the row count target value, and clears the count value of the row counter 142. Such cyclic counting is repeated until the instruction circuit 150 stops outputting the write instruction and the write row count clock signal WROW_CNT_CLK.

[0086] When the row counter 142 generates the row write counter end signal WROW_ADD_END, it sends the row write counter end signal WROW_ADD_END to the column counter 141. The column counter 141 counts the write column address under the control of the row write counter end signal WROW_ADD_END, and outputs the write column counter termination signal WCOL_CNT_ALL when the write column count value WCOLCNT meets the column count target value. The column counter 141 sends the write column counter termination signal WCOL_CNT_ALL to the row counter 142. The row counter 142 outputs the write row counter termination signal WROW_CNT_ALL when it receives the write column counter termination signal WCOL_CNT_ALL. When the row counter 142 outputs the write row counter termination signal WROW_CNT_ALL and the column counter 141 outputs the write column counter termination signal WCOL_CNT_ALL, the instruction circuit 150 stops outputting the write instruction and the write row count clock signal WROW_CNT_CLK, and makes the column counter 141 output the write column count value WCOLCNT to the decoding circuit.

[0087] In the above counting scheme, the row counter 142 counts the write row address according to the read / write mode signal and the write row count clock signal WROW_CNT_CLK, outputs the row write counter end signal WROW_ADD_END when the write row count value meets the row count target value, and clears the count value of the row counter 142. The column counter 141 counts the write column address under the control of the row write counter end signal WROW_ADD_END, and outputs the write column counter termination signal WCOL_CNT_ALL when the write column count value WCOLCNT meets the column count target value. The row counter 142 outputs the write row counter termination signal WROW_CNT_ALL when it receives the write column counter termination signal WCOL_CNT_ALL, so as to determine whether the test of all memory cells in the semiconductor memory is completed.

[0088] In some embodiments, as Figure 4 shown, when the read / write mode signal characterizes the fast column mode, the instruction circuit 150 periodically outputs the read instruction and the read column count clock signal RCOL_CNT_CLK according to the read / write mode signal; the address counter 140 includes a column counter 141 and a row counter 142.

[0089] The column counter 141 counts the read column address based on the read / write mode signal and the read column count clock signal RCOL_CNT_CLK. When the read column count value meets the column count target value, it outputs the read column counter end signal RCOL_ADD_END and clears the count value of the column counter 141. The row counter 142 counts the read row address under the control of the read column counter end signal RCOL_ADD_END. When the read row count value RROWCNT meets the row count target value, it outputs the read row counter termination signal RROW_CNT_ALL. The column counter 141 outputs the read column counter termination signal RCOL_CNT_ALL when it receives the read row counter termination signal RROW_CNT_ALL.

[0090] When the read mode signal indicates the fast column mode, the instruction circuit 150 periodically outputs a read instruction and the read column count clock signal RCOL_CNT_CLK according to the read mode signal. The read instruction includes one or more combinations of the built-in self-test activation signal MBIST_ACT, the built-in self-test read signal MBIST_RD, the built-in self-test precharge signal MBIST_PRE, and the built-in self-test refresh signal MBIST_REF.

[0091] The instruction circuit 150 outputs the read column count clock signal RCOL_CNT_CLK to the column counter 141. The column counter 141 counts the read column address under the control of the read column count clock signal RCOL_CNT_CLK. When the read column count value meets the column count target value, it outputs the read column counter end signal RCOL_ADD_END and clears the count value of the column counter 141. The column counter 141 continues to receive the read column count clock signal RCOL_CNT_CLK sent by the instruction circuit 150. The column counter 141 continues to count the read column address under the control of the read column count clock signal RCOL_CNT_CLK. When the read column count value meets the column count target value, it outputs the read column counter end signal RCOL_ADD_END and clears the count value of the column counter 141. This counting process repeats until the instruction circuit 150 stops outputting the read instruction and the read column count clock signal RCOL_CNT_CLK.

[0092] When the column counter 141 generates the read column counter end signal RCOL_ADD_END, it sends the read column counter end signal RCOL_ADD_END to the row counter 142. The row counter 142 counts the read row address under the control of the read column counter end signal RCOL_ADD_END. When the read row count value RROWCNT meets the row count target value, it outputs the read row counter termination signal RROW_CNT_ALL. The row counter 142 sends the read row counter termination signal RROW_CNT_ALL to the column counter 141. When the column counter 141 receives the read row counter termination signal RROW_CNT_ALL, it outputs the read column counter termination signal RCOL_CNT_ALL. When the row counter 142 outputs the read row counter termination signal RROW_CNT_ALL and the column counter 141 outputs the read column counter termination signal RCOL_CNT_ALL, the instruction circuit 150 stops outputting the read instruction and the read column count clock signal RCOL_CNT_CLK. The row counter also sends the read row count value WROWCNT to the decoding circuit, enabling the decoding circuit to decode the fault address and output the address of the fault storage area when it receives the read row count value RROWCNT.

[0093] In the above counting scheme, the column counter 141 counts the read column address under the control of the read mode signal and the read column count clock signal RCOL_CNT_CLK. When the read column count value meets the column count target value, it outputs the read column counter end signal RCOL_ADD_END and clears the count value of the column counter 141. The row counter 142 counts the read row address under the control of the read column counter end signal RCOL_ADD_END. When the read row count value RROWCNT meets the row count target value, it outputs the read row counter termination signal RROW_CNT_ALL. When the column counter 141 receives the read row counter termination signal RROW_CNT_ALL, it outputs the read column counter termination signal RCOL_CNT_ALL, thus determining whether the test of all storage units in the semiconductor memory is completed.

[0094] In some embodiments, as Figure 5 shown, when the read / write mode signal represents the fast row mode XFAST, the instruction circuit 150 periodically outputs the read instruction and the read row count clock signal RROW_CNT_CLK according to the read / write mode signal; the address counter 140 includes a row counter 142 and a column counter 141.

[0095] The row counter 142 counts the read row address under the control of the read row count clock signal RROW_CNT_CLK. When the read row count value meets the row count target value, it outputs the row read counter end signal RROW_ADD_END and clears the count value of the row counter 142. The column counter 141 counts the read column address under the control of the row read counter end signal RROW_ADD_END. When the read column count value RCOLCNT meets the column count target value, it outputs the read column counter termination signal RCOL_CNT_ALL. The row counter 142 is also used to output the read row counter termination signal RROW_CNT_ALL when receiving the read column counter termination signal RCOL_CNT_ALL.

[0096] The instruction circuit 150 outputs the read row count clock signal RROW_CNT_CLK to the row counter 142. The row counter 142 counts the read row address under the control of the read row count clock signal RROW_CNT_CLK. When the read row count value meets the row count target value, it outputs the row read counter end signal RROW_ADD_END and clears the count value of the row counter 142. The row counter 142 continues to receive the read row count clock signal RROW_CNT_CLK sent by the instruction circuit 150. The row counter 142 continues to count the read row address under the control of the read row count clock signal RROW_CNT_CLK. When the read row count value RROWCNT meets the row count target value, it outputs the row read counter end signal RROW_ADD_END and clears the count value of the row counter 142. Such cyclic counting is repeated until the instruction circuit 150 stops outputting the read instruction and the read row count clock signal RROW_CNT_CLK.

[0097] When the row counter 142 generates the row read counter end signal RROW_ADD_END, it sends the row read counter end signal RROW_ADD_END to the column counter 141. The column counter 141 counts the read column addresses under the control of the row read counter end signal RROW_ADD_END. When the read column count value RCOWCNT meets the column count target value, it outputs the read column counter termination signal RCOL_CNT_ALL. The column counter 141 sends the read column counter termination signal RCOL_CNT_ALL to the row counter 142. When the row counter 142 receives the read column counter termination signal RCOL_CNT_ALL, it outputs the read row counter termination signal RROW_CNT_ALL. When the row counter 142 outputs the read row counter termination signal RROW_CNT_ALL and the column counter 141 outputs the read column counter termination signal RCOL_CNT_ALL, the instruction circuit 150 stops outputting the read instruction and the read row count clock signal RROW_CNT_CLK, and makes the column counter 141 output the read column count value RCOLCNT to the decoding circuit.

[0098] In the above counting scheme, the row counter 142 counts the read row addresses under the control of the read mode signal and the read row count clock signal RROW_CNT_CLK. When the read row count value meets the row count target value, it outputs the row read counter end signal RROW_ADD_END and clears the count value of the row counter 142. The column counter 141 counts the read column addresses under the control of the row read counter end signal RROW_ADD_END. When the read column count value RCOLCNT meets the column count target value, it outputs the read column counter termination signal RCOL_CNT_ALL. When the row counter 142 receives the read column counter termination signal RCOL_CNT_ALL, it outputs the read row counter termination signal RROW_CNT_ALL, thus determining whether the test of all memory cells in the semiconductor memory is completed.

[0099] In some embodiments, the built-in self-test module 100 includes a first mode register 110 and a clock unit 120. The first mode register 110 is configured to receive a mode register write instruction MRW, generate a first enable signal MBIST_EN1 according to the mode register write instruction MRW, further receive a built-in self-test end signal MBIST_END output by the instruction module, and generate a second enable signal MBIST_EN2 according to the built-in self-test end signal MBIST_END. The clock unit 120 generates a test clock signal MBIST_CLK according to the first enable signal MBIST_EN1 and sets the alert signal ALERT_n to a first level; the clock unit 120 stops outputting the test clock signal MBIST_CLK according to the second enable signal MBIST_EN2 and sets the alert signal ALERT_n to a second level.

[0100] The test clock signal MBIST_CLK controls the read / write mode circuit 130, the instruction circuit 150, the address counter 140, and the repair address module to operate. More specifically, the read / write mode circuit 130 outputs a read / write mode signal under the control of the test clock signal MBIST_CLK. The instruction circuit 150 periodically outputs read / write instructions and a count clock signal CNT_CLK under the control of the test clock signal MBIST_CLK and the read / write mode signal. The address counter 140 counts the read / write addresses under the control of the read / write mode signal, the test clock signal MBIST_CLK, and the count clock signal CNT_CLK, and outputs a built-in self-test end signal MBIST_END when the counted value reaches a target value. The repair address module 200 decodes the faulty address under the control of the test clock signal MBIST_CLK to determine the address of the faulty storage area, sends the address of the faulty storage area to the internal control module 400, and receives the repair resource information sent by the internal control module 400, and generates a repair identifier according to the repair resource information.

[0101] Here, taking the first level as the low level and the second level as the high level as an example, the first mode register 110 includes mode register MR23 and mode register M24. When the semiconductor memory is initialized, the external control module 300 will execute a mode register write command to set OP[4] of mode register MR23 to 1, which will generate the MBIST_EN_PRE signal. Then, the guard key input to mode register MR24 enters the MBIST, and at this time, the first enable signal MBIST_EN1 will be generated. When the semiconductor memory enters the MBIST, it will drive the prompt signal ALERT_n to the low level. At the same time, under the first enable signal MBIST_EN1, the clock unit 120 generates the test clock signal MBIST_CLK required for the MBIST. The period of the test clock signal MBIST_CLK can be internally adjusted according to different requirements.

[0102] After the test clock signal MBIST_CLK is generated, the internal test module will generate some commands for completing the MBIST test. When a MBIST is completed, the built-in self-test module 100 will generate the built-in self-test end signal MBIST_END, and the mode register will generate the second enable signal MBIST_EN2. The semiconductor memory will temporarily exit the MBIST operation. When the semiconductor memory exits the MBIST operation, it will drive the prompt signal ALERT_n to the high level.

[0103] The clock unit generates the test clock signal MBIST_CLK required for the MBIST when the semiconductor memory enters the MBIST. Since the MBIST is used to detect the health status of the memory cells, under the control of the test clock signal MBIST_CLK, the instruction circuit 150 needs to generate parallel test instructions and generate read / write instructions for accessing the memory cells according to the parallel test instructions. The test clock signal MBIST_CLK also controls the read / write mode circuit 130 and the address counter 140 to work to complete the MBIST operation. The test clock signal MBIST_CLK also controls the repair address module to work to complete the decoding of the faulty address and the generation of the repair flag.

[0104] In some embodiments, the repair address module 200 includes a decoding circuit 210 and a second mode register 220. The decoding circuit 210 is used to decode the faulty address to determine the address of the faulty memory area and send the address of the faulty memory area to the internal control module 400. The second mode register 220 receives the repair resource information sent by the internal control module 400 and generates and stores the repair flag according to the repair resource information.

[0105] When the semiconductor memory completes a full MBIST, the internal control module 400 compares the data written into the memory cells with the data read from the memory cells. When the data is inconsistent, the fault address is determined. The decoding circuit 210 decodes the fault address to output the address of the faulty memory area, and sends the address of the faulty memory area to the internal control module 400, and generates repair resource information based on the address of the faulty memory area. The repair resource information is used to determine whether there is an address that can repair the error. When there is a corresponding address for repairing the error, the repair flag is set to 001 and stored in the mode register MR22<2:0>. Read the mode register MR22<2:0>. If the data in the mode register MR22<2:0> is 001, it means that the post-package repair mode of the built-in self-test (MBIST Post Package Repair, abbreviated as mPPR) can be used for repair. When the MBIST ends, it will enter the mPPR operation mode. When there is no corresponding address for repairing the error, the repair flag is set to 010 and stored in the mode register MR22<2:0>. Read the mode register MR22<2:0>. If the data in the mode register MR22<2:0> is 010, after a MBIST is executed, the MBIST operation mode will be exited and the normal operation mode will be entered.

[0106] When a MBIST ends, the external control module 300 will execute a mode register read command to read the information of the mode register MR22<2:0>. The external control module 300 determines the operation of the semiconductor memory based on the information of MR22<2:0>. When MR22<2:0> is 001, it will enter the mPPR for repair, and at the same time set the information of MR22<2:0> to 011. When the mPPR repair operation ends, it will enter the MBIST again until the information of MR22<2:0> becomes 010, and then exit the MBIST.

[0107] In some embodiments, the external control module 300 needs to execute a mode register read command to enter the MBIST operation. Setting OP[4] of the mode register MR23 to 1 will generate the MBIST_EN_PRE signal. Then, the guard key of the mode register MR24 is input to enter the MBIST. When entering the MBIST, the first enable signal MBIST_EN1 will be generated at this time, and the alert signal ALERT_n is set to a low level. When the MBIST operation is enabled, an internal self-generated clock signal will be generated, and the ACT, WR, RD, and PRE commands will be self-generated. The MBIST operation will write the value of the data register into the memory cells of the semiconductor memory, and then read the written data to judge data errors through the parallel test mode, so as to obtain the error address information. After the semiconductor memory completes one MBIST operation, the alert signal ALERT_n is set to a high level.

[0108] After the MBIST is executed, the external control module 300 will read the value of the mode register MR22 to determine the next operation of the semiconductor memory. The external control module 300 will send a mode register read command to read the repair flag stored in the mode register MR22 to judge the next dynamics of the semiconductor memory. When the repair flags are 000 and 010 respectively, the semiconductor memory enters the normal startup mode. When the repair flag is 001, the semiconductor memory enters the post-packaging repair mode of the built-in self-test.

[0109] It should be noted here that this application is not limited to the framework of the relevant circuits for performing the memory built-in self-test function in the semiconductor memory, but is not limited to this range. Other internally generated commands for memory detection can adopt this design.

[0110] Those skilled in the art will readily conceive of other embodiments of the present application after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present application, which follow the general principles of the present application and include the common general knowledge or conventional technical means in the technical field not disclosed in the present application. The specification and embodiments are only regarded as exemplary, and the true scope and spirit of the present application are pointed out by the following claims.

[0111] It should be understood that the present application is not limited to the exact structure already described and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present application is only limited by the appended claims.

Claims

1. A semiconductor memory, characterized in that, Including: A built-in self-test module, configured to receive a mode register write instruction sent by an external control module, and generate a parallel test instruction according to the mode register write instruction; An internal control module, configured to receive the parallel test instruction, and simultaneously test a plurality of repositories according to the parallel test instruction to obtain a fault address; A repair address module, configured to decode the fault address to determine the address of a faulty storage area, send the address of the faulty storage area to the internal control module, and receive repair resource information sent by the internal control module, and generate a repair identifier according to the repair resource information; wherein, the repair resource information is determined by the internal control module according to the address of the faulty storage area.

2. The semiconductor memory according to claim 1, wherein, The built-in self-test module is further configured to generate and send a prompt signal to the external control module, so that the external control module generates a mode register read instruction; The repair address module receives the mode register read instruction, and sends the repair identifier to the external control module, so that the external control module controls the startup mode of the semiconductor memory according to the repair identifier.

3. The semiconductor memory according to claim 2, wherein The built-in self-test module includes: A read-write mode circuit, configured to output a read-write mode signal; An instruction circuit, receiving the read-write mode signal; periodically outputting read-write instructions and a counting clock signal based on the read-write mode signal; An address counter, receiving the read-write mode signal and the counting clock signal, counting a read-write address using the counting clock signal based on the read-write mode signal, and outputting a built-in self-test end signal when a count value reaches a target value.

4. The semiconductor memory according to claim 3, wherein, The repair address module further receives the count value output by the address counter, and decodes the fault address to determine the address of the faulty storage area when the count value reaches the target value.

5. The semiconductor memory according to claim 3, wherein, The instruction circuit is configured to periodically output a write instruction and a write counting clock signal according to the read-write mode signal; and periodically output a read instruction and a read counting clock signal according to the read-write switching signal after receiving the read-write switching signal output by the address counter; The address counter is configured to count a write address under the control of the read-write mode signal and the write counting clock signal, and output a read-write switching signal when a write count value reaches a preset quantity threshold; and is further configured to count a read address under the control of the read-write mode signal and the read counting clock signal, and output the built-in self-test end signal when a read count value reaches the preset quantity threshold.

6. The semiconductor memory according to claim 3, wherein When the read-write mode signal represents a fast column mode, the instruction circuit periodically outputs a write instruction and a write column counting clock signal according to the read-write mode signal; correspondingly, the address counter includes: A column counter, receiving the write column counting clock signal, counting a write column address under the control of the write column counting clock signal, outputting a write column counter end signal when a write column count value meets a column count target value, and clearing the count value of the column counter; and outputting a write column counter termination signal when receiving a write row counter termination signal; A row counter that receives the write column counter end signal, counts the write row address under the control of the write column counter end signal, and outputs the write row counter termination signal when the write row count value meets the row count target value.

7. The semiconductor memory according to claim 3, wherein When the read / write mode signal indicates the fast row mode, the instruction circuit periodically outputs a write instruction and a write row count clock signal according to the read / write mode signal; Correspondingly, the address counter includes: A row counter that receives the write row count clock signal, counts the write row address under the control of the write row count clock signal, outputs a write row counter end signal when the write row count value meets the row count target value, clears the count value of the row counter, and is also used to output a write row counter termination signal when receiving the write column counter termination signal; A column counter that receives the write row counter end signal, counts the write column address under the control of the write row counter end signal, and outputs the write column counter termination signal when the write column count value meets the column count target value.

8. The semiconductor memory according to claim 3, wherein When the read / write mode signal indicates the fast column mode, the instruction circuit periodically outputs a read instruction and a read column count clock signal according to the read / write mode signal; Correspondingly, the address counter includes: A column counter that receives the read column count clock signal, counts the read column address under the control of the read column count clock signal, outputs a read column counter end signal when the column count value meets the column count target value, and clears the count value of the column counter; outputs a read column counter termination signal when receiving the read row counter termination signal; A row counter that receives the read column counter end signal, counts the read row address under the control of the read column counter end signal, and outputs the read row counter termination signal when the read row count value meets the row count target value.

9. The semiconductor memory according to claim 3, wherein, When the read / write mode signal indicates the fast row mode, the instruction circuit periodically outputs a read instruction and a read row count clock signal according to the read / write mode signal; Correspondingly, the address counter includes: A row counter that receives the read row count clock signal, counts the read row address under the control of the read row count clock signal, outputs a read row counter end signal when the read row count value meets the row count target value, clears the count value of the row counter, and is also used to output a read row counter termination signal when receiving the read column counter termination signal; A column counter that receives the read column counter end signal, counts the read column address under the control of the read column counter end signal, and outputs the read column counter termination signal when the column count value meets the column count target value.

10. The semiconductor memory according to claim 3, characterized in that, The built-in self-test module includes: A first mode register that is used to receive the mode register write instruction, generates a first enable signal according to the mode register write instruction, also receives the built-in self-test end signal output by the address counter, and generates a second enable signal according to the built-in self-test end signal; A clock unit receives the first enabling signal, generates a test clock signal according to the first enabling signal, and makes the prompt signal at a first level; stops outputting the test clock signal according to the second enabling signal, and makes the prompt signal at a second level; Wherein, the test clock signal controls the read-write mode circuit, the instruction circuit, the address counter, and the repair address module to work.

11. The semiconductor memory according to claim 1, characterized in that, The repair address module includes: A decoding circuit for decoding the faulty address to determine the address of the faulty storage area and sending the address of the faulty storage area to the internal control module; A second mode register receives the repair resource information sent by the internal control module and generates and stores the repair identifier according to the repair resource information.

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