Image sensor
By separating the holding capacitor from the photodiode in the image sensor and introducing a peak holding transistor, the image distortion caused by the rolling shutter and the pseudo-sensitivity problems in the global shutter are solved, and a clearer image sensing effect is achieved.
Patent Information
- Application Number
- CN202411601810.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-12-21
- Filing Date
- 2024-11-11
- Publication Date
- 2025-06-24
AI Technical Summary
In the image sensor, rolling the shutter causes image distortion when shooting moving objects, and the global shutter is prone to pseudo-sensitivity problems due to the holding capacitance and photodiode sharing the substrate, resulting in increased image noise.
The holding capacitor is arranged on a different substrate than the photodiode, electrically coupled through pixel contact, preventing incident light from leaking into the holding capacitor, and introducing a peak holding transistor into the pixel circuit to reduce noise.
It effectively reduces image noise, prevents the occurrence of pseudo-sensitivity, and improves the image quality of the image sensor when shooting moving objects.
Smart Images
Figure CN120201328A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure generally relates to an image sensor in which pixel circuits are respectively provided on a plurality of substrates. Background Art
[0002] An image sensor includes a plurality of pixels arranged in a matrix, and each pixel acquires a signal corresponding to the amount of incident light.
[0003] Each pixel outputs a signal corresponding to the amount of incident light during an integration period of one frame. As an electronic shutter that defines the integration period timing, a rolling shutter or a global shutter is used.
[0004] In the case of a rolling shutter, during the shutter opening period (integration period), it moves sequentially for each row (each line). In other words, by moving the shutter opening period by one horizontal period, the signals of each line are output sequentially. In contrast, in the case of a global shutter, the shutter opening period is the same, the signal is temporarily held in the pixel, and then output line by line.
[0005] One problem with a rolling shutter is that when photographing a moving object, due to the different shutter opening periods (integration periods) between each line, the copied image will be distorted. It is best to use a global shutter for in-vehicle cameras.
[0006] To implement a global shutter, a holding capacitor that accumulates and holds a signal for a predetermined period needs to be provided in the same pixel. However, when the holding capacitor is provided on the substrate provided with a photodiode, pseudo-sensitivity may occur because part of the light entering the photodiode leaks into the holding capacitor. The pseudo-sensitivity is similar to the copied image of a rolling shutter. Therefore, in this case, the images of the global shutter and the rolling shutter are regarded as superimposed on each other.
[0007] To solve this problem, an example discloses a structure in which a holding capacitor is provided on a second substrate different from the first substrate provided with a photodiode to prevent incident light from leaking into the holding capacitor. The above two substrates are electrically coupled through pixel contacts.
[0008] Any of the above image sensors needs to reduce noise. Summary of the Invention
[0009] The image sensor according to the present disclosure includes a sensor substrate and a circuit substrate.
[0010] The sensor substrate includes a plurality of sensor substrate side pixels. Each of the sensor substrate side pixels includes a photodiode configured to operate in a photovoltaic mode, a reset transistor configured to reset the photodiode, and a pixel source follower transistor connected to the output of the photodiode.
[0011] The circuit substrate includes circuit-substrate-side pixels corresponding to respective sensor-substrate-side pixels of the sensor substrate. Each of the circuit-substrate-side pixels includes a peak-holding circuit configured to hold a peak of an output of a pixel source follower transistor by receiving the output of the pixel source follower transistor, and a readout source follower transistor configured to read out a voltage held in a holding capacitor.
[0012] The peak-holding circuit includes a peak-holding transistor configured to allow a current corresponding to the output of the pixel source follower transistor to flow therethrough, a switching transistor configured to turn on / off the output of the peak-holding transistor, and a holding capacitor configured to hold the output of the switching transistor.
[0013] The sensor-substrate-side pixels and the respective corresponding circuit-substrate-side pixels are connected to each other.
[0014] In the image sensor according to the present disclosure, the peak-holding transistor is provided in the pixel circuit, which may prevent the occurrence of flicker. In addition, the peak-holding transistor is provided on a substrate different from the substrate on which the photodiode is provided, which may reduce noise. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] Embodiments of the present disclosure will be described based on the following diagrams, where:
[0016] Figure 1 is a diagram illustrating a circuit configuration as a premise of an embodiment;
[0017] Figure 2 is Figure 1 a cross-sectional view of a sensor substrate of a part of a pixel in
[0018] Figure 3 is a diagram illustrating a circuit configuration according to an embodiment;
[0019] Figure 4 is Figure 3 a cross-sectional view of a sensor substrate of a part of a pixel in
[0020] Figure 5 is an illustration of Figure 3 a timing diagram of a circuit operation in
[0021] Figure 6 is a diagram explaining noise generation;
[0022] Figure 7 is a diagram illustrating the relationship between the current Id determined by SPICE simulation and the noise caused by dark current;
[0023] Figure 8 is a diagram illustrating a configuration in which the gate of a load transistor Load is driven by a pulse;
[0024] Figure 9 is a diagram illustrating the input / output characteristics of the pixel source follower transistor SFd;
[0025] Figure 10 is a diagram illustrating the image sensor 200 with a two-dimensional pixel arrangement according to this embodiment;
[0026] Figure 11 is illustrative of Figure 10 the timing diagram of the operation of the image sensor in;
[0027] Figure 12 is a diagram illustrating the circuit configuration according to Modification 1;
[0028] Figure 13 is Figure 12 the timing diagram of the circuit in;
[0029] Figure 14 is illustrative of the pixel circuit configuration configured to Figure 12 perform a global integration operation with the circuit in as a basis; and
[0030] Figure 15 is illustrative of Figure 14 the timing diagram of the operation of the circuit in.
[0031] Explanation of the reference numerals in the drawings
[0032] 10: Photodiode
[0033] 40, 40-2: Output line
[0034] 200: Image sensor
[0035] 210: Pixel array
[0036] 212: Vertical scanning circuit
[0037] 214: Analog-to-digital converter
[0038] 216: Horizontal scanning circuit
[0039] BL-R, BL-S: p+ barrier layer
[0040] CON: Pixel contact
[0041] CON1: Sensor substrate side contact
[0042] CON2: Circuit substrate side contact
[0043] Csigt, Crstt: Capacitor
[0044] Crst, Csig: Holding capacitor
[0045] Cs: Parasitic capacitance
[0046] FTI: Isolation
[0047] H: Level
[0048] Id: Current
[0049] Ideq: Equivalent Noise
[0050] Idrk: Dark Current
[0051] injection: Injection Power Supply
[0052] Isig: Signal Current
[0053] Load: Load Transistor
[0054] M1: Metal Wire
[0055] NWL: n-well Layer
[0056] P: Pixel
[0057] PD: Photodiode
[0058] PH: Peak Hold Transistor
[0059] PHGRST: Gate Reset Transistor
[0060] PHGRST, RST, RSTLs, RSTLr: Reset Transistor
[0061] PWL: p-well Layer
[0062] RST: Reset Transistor
[0063] SB1: Sensor Substrate
[0064] SB2: Circuit Substrate
[0065] SELrst, SELsig: Row Selection Crystal
[0066] SEL, SEL2: Selection Transistor
[0067] SF, SF2: Source Follower Transistor
[0068] SFd: Pixel Source Follower Transistor
[0069] SWrst, SWsig, SWsigt, SWrstt: Switch Transistor
[0070] Vpd: Output Voltage Specific Embodiment
[0071] An embodiment of the present disclosure will be described below with reference to the accompanying drawings. The following embodiments do not limit the present disclosure, and configurations obtained by selectively combining a plurality of descriptions are also included in the present disclosure.
[0072] Premise configuration
[0073] Figure 1 is a diagram illustrating a circuit configuration as a premise of the embodiment, Figure 2 is Figure 1 a cross-sectional view of a sensor substrate of a part of the pixels of the circuit configuration.
[0074] The photodiode PD accumulates charges (electrons in this example) based on incident light. The cathode of the photodiode PD serves as the output terminal, and the anode is connected to a power supply (e.g., ground). Therefore, the output voltage Vpd of the photodiode PD is the output signal.
[0075] The photodiode PD operates in a logarithmic region (under high illuminance), where the photodiode PD operates in a forward bias, and a linear region (under low illuminance), where the photodiode PD operates in a reverse bias and a partial forward bias. The operation mode in the logarithmic region is called the photovoltaic mode, and the operation mode in the linear region is called the linear mode.
[0076] One end (drain) of the reset transistor RST is connected to the output terminal of the photodiode PD, and the other end (source) of the reset transistor RST is connected to a power supply (e.g., ground) through the reset power supply B. In this example, the reset transistor RST is an n-channel transistor.
[0077] The cathode of the photodiode PD is connected to the gate of the peak hold transistor PH. The peak hold transistor PH is a p-channel transistor. The source of the peak hold transistor PH is connected to the injection power supply injection. The peak hold circuit includes the peak hold transistor PH, the hold capacitor Csig, and the switch transistor SWsig.
[0078] The source of the switch transistor SWsig is connected to the drain of the peak hold transistor PH. One end of the hold capacitor Csig is connected to the drain of the switch transistor SWsig. The other end of the hold capacitor Csig is connected to a power supply (e.g., ground). The switch transistor SWsig is a p-channel transistor.
[0079] The drain of the switch transistor SWsig is connected to the gate of the readout source follower transistor SF. The drain of the readout source follower transistor SF is connected to a power supply, and the source is connected to the drain of the selection transistor SEL. The source of the selection transistor SEL is connected to the output line 40.
[0080] A row selection signal is supplied to the gate of the selection transistor SEL. When the row selection signal becomes the H level, a signal corresponding to the gate voltage of the readout source follower transistor SF is output to the output line 40.
[0081] After the reset transistor RST is turned on to reset the photodiode PD, the injection power supply injection briefly becomes the H level when the switching transistor SWsig is turned on, so as to inject charge (holes) into the holding capacitor Csig through the peak holding transistor PH and discharge the excess charge. As a result, the holding capacitor Csig is placed in the reset state.
[0082] In another state, within one frame period, the signal supplied from the peak holding transistor PH through the switching transistor SWsig accumulates in the holding capacitor Csig. As described above, the output voltage corresponding to the accumulated charge of the photodiode PD is supplied to the gate of the peak holding transistor PH. Therefore, the charge corresponding to the incident light amount of the photodiode PD within one frame period accumulates in the holding capacitor Csig.
[0083] In addition, when the switching transistor SWsig is turned off and the selection transistor SEL is turned on, the voltage signal corresponding to the charge accumulated in the holding capacitor Csig is read out to the output line 40.
[0084] Note that in this embodiment, the transistor uses a Metal Oxide Semiconductor Field Effect Transistor (MOSFET).
[0085] As described above, in this embodiment, the peak holding circuit including the peak holding transistor PH, the switching transistor SWsig, and the holding capacitor Csig is included in the pixel. In addition, the readout source follower transistor SF and the selection transistor SEL for reading out the signal to the outside of the pixel are also necessary in the pixel.
[0086] When the photodiode PD operates in the logarithmic region, the photodiode PD has logarithmic characteristics; however, a signal with linear characteristics leaks into the holding capacitor Csig.
[0087] Therefore, in this embodiment, as Figure 1 shown, the photodiode PD, the reset transistor RST, and the peak holding transistor PH are provided on the sensor substrate SB1, and the switching transistor SWsig, the holding capacitor Csig, the readout source follower transistor SF, and the selection transistor SEL are provided on a circuit substrate SB2 different from the sensor substrate SB1.
[0088] In addition, the sensor substrate side line of the drain of the peak hold transistor PH on the sensor substrate SB1 and the circuit substrate side line of the source of the switch transistor SWsig on the circuit substrate SB2 are connected through the pixel contact CON provided on the two substrates. The pixel contact CON includes a sensor substrate side contact CON1 and a circuit substrate side contact CON2 that are connected to each other. In Figure 2 the output terminal of the photodiode PD and the gate of the peak hold transistor PH are connected by a wire M1.
[0089] At this time, when the peak hold transistor PH is provided on the sensor substrate SB1, there is a problem that the detection capacitance of the photodiode PD increases significantly and the sensitivity decreases significantly.
[0090] As Figure 2 shown, the n-type region on the output terminal side of the photodiode PD is shared with the source of the reset transistor RST. To prevent the signal charge (electrons) generated by the incident light in the p-substrate from leaking to the drain of the reset transistor RST, a p+ blocking layer BL-R is provided under the drain of the reset transistor RST.
[0091] Since the peak hold transistor PH is a p-channel transistor, the peak hold transistor PH is provided in the n-well layer NWL. To prevent signal charge from leaking into the n-well layer NWL, a p-well layer PWL is provided. The impurity concentration of the p-well layer PWL is preferably equivalent to the impurity concentration of the p+ blocking layer BL-R. An isolation FTI is provided around the pixel.
[0092] As described above, when the n-type photodiode PD and the p-type transistor (peak hold transistor PH) are provided in the sensor substrate SB1 which is a p-substrate, the pixel structure becomes complicated. This makes it difficult to miniaturize the pixel size. In addition, when the two substrates are coupled, a parasitic capacitance Cs is generated in the coupling part, and noise increases when the switch transistor SWsig is turned on / off, which is a problem.
[0093] On the other hand, in order to mount an image sensor using the photovoltaic mode on a vehicle, a peak hold circuit is necessary because it is necessary to suppress the LED flicker that occurs in the logarithmic region of the image sensor. In other words, in the logarithmic region, when the shutter is closed, a signal corresponding to the incident light amount is output; however, since the LED is turned on and off repeatedly at a predetermined frequency, flicker is generated due to the mixing of the signal when the LED is on and the signal when the LED is off.
[0094] Configuration according to an embodiment
[0095] Figure 3 is a diagram illustrating the circuit configuration according to an embodiment, Figure 4 is a cross-sectional view of the sensor substrate.
[0096] As Figure 3 shown, in this embodiment, the peak-holding transistor PH is not provided on the sensor substrate SB1, but on the circuit substrate SB2. In addition, the pixel source-follower transistor SFd and the load transistor Load are provided on the sensor substrate SB1. In other words, the pixel is divided into a sensor-substrate-side pixel and a circuit-substrate-side pixel, and the peak-holding circuit is not included in the sensor-substrate-side pixel but in the circuit-substrate-side pixel.
[0097] More specifically, the output terminal of the photodiode PD is connected to the gate of the pixel source-follower transistor SFd. The drain of the pixel source-follower transistor SFd is connected to a power supply, and the source is connected to the drain of the load transistor Load. The source of the load transistor Load is connected to a power supply, such as ground. When the gate voltage of the load transistor Load is set to a predetermined value, the pixel source-follower transistor SFd performs a source-follower operation, and a signal corresponding to the output of the photodiode PD is supplied to the gate of the peak-holding transistor PH.
[0098] The reset transistor RST, the pixel source-follower transistor SFd, and the load transistor Load provided on the sensor substrate SB1 are all n-channel transistors.
[0099] The source of the pixel source-follower transistor SFd is connected to the sensor-substrate-side contact CON1 of the pixel contact CON. The sensor-substrate-side contact CON1 is connected to the circuit-substrate-side contact CON2. In addition, the circuit-substrate-side contact CON2 is connected to the gate of the peak-holding transistor PH.
[0100] The peak-holding transistor PH is provided on the circuit substrate SB2 together with the switch transistor SWsig, the holding capacitor Csig, the readout source-follower transistor SF, and the selection transistor SEL. These transistors are all p-channel transistors. The operation of the circuit provided on the circuit substrate SB2 is basically similar to Figure 1 the operation of the circuit in. Since the transistors are p-channel transistors, the polarities of the control signals of the transistors other than the peak-holding transistor PH are inverted. As described above, the provided transistors are unified as p-channel, which makes it possible to simplify the structure, just like the sensor substrate SB1.
[0101] The gate reset transistor PHGRST is provided on the circuit substrate SB2. The gate reset transistor PHGRST resets the gate of the peak-holding transistor PH. The gate reset transistor PHGRST is a p-channel transistor, the source of which is connected to a power supply, and the drain is connected to the gate of the peak-holding transistor PH.
[0102] In a state where the circuit substrate SB2 is not connected to the sensor substrate SB1, the gate of the peak-holding transistor PH is in an electrically floating state. Therefore, the gate of the peak-holding transistor PH may be damaged by electrostatic discharge. When the gate reset transistor PHGRST is connected to the gate of the peak-holding transistor PH, the gate reset transistor PHGRST functions as an ESD (Electrostatic Discharge) protection transistor. In this case, the gate reset transistor PHGRST can be used in the off state.
[0103] In addition, in this example, the load transistor Load is provided on the sensor substrate SB1; however, the load transistor Load can be provided on the circuit substrate SB2. In this example, a p-channel transistor is preferably used as the load transistor Load.
[0104] As Figure 4 shown, the photodiode PD shares the source of the reset transistor RST. To prevent signal charges (electrons) generated by incident light in the p-substrate from leaking to the drain of the reset transistor RST, a p+ blocking layer BL-R is provided below the drain of the reset transistor RST. A p+ blocking layer BL-S is provided below the pixel source follower transistor SFd, which prevents signal charges from flowing into the source / drain of the pixel source follower transistor SFd.
[0105] As described above, the pixel structure can be simplified compared to the structure in Figure 2 . This enables the pixel size to be reduced. In addition, the parasitic capacitance of the gate of the switch transistor SWsig can be decreased. Therefore, when the switch transistor SWsig is turned on / off, the noise does not increase.
[0106] Figure 5 is a timing diagram illustrating the circuit operation in Figure 3 . The reset transistor RST is turned on to reset the photodiode PD. Next, when the switch transistor SWsig is turned on, holes from the injection power supply are injected into the holding capacitor Csig through the peak-holding transistor PH.
[0107] In this state, the output of the photodiode PD is accumulated in the holding capacitor Csig through the pixel source follower transistor SFd, the peak-holding transistor PH, and the switch transistor SWsig.
[0108] After the integration period of one frame ends, the switch transistor SWsig is turned off to end the signal accumulation, and the signal is held in the holding capacitor Csig. In addition, the selection transistor SEL is turned on to read out the signal accumulated in the holding capacitor Csig to the output line 40 from the readout source follower transistor SF.
[0109] Noise reduction
[0110] As Figure 6 shown, the gate reset transistor PHGRST is connected to the connection point of the source of the pixel source follower transistor SFd and the drain of the load transistor Load. Therefore, the dark current generated at the source of the gate reset transistor PHGRST becomes noise in the signal supplied to the peak hold transistor PH.
[0111] The noise caused by the dark current depends on the current Id flowing through the pixel source follower transistor SFd.
[0112] Figure 7 is a graph showing the relationship between the current Id determined by SPICE simulation and the noise caused by the dark current. Figure 7 Illustrates the noise calculated at the output of the photodiode PD when the fixed pattern noise (FPN) caused by the dark current is assumed to be 1500 ele (= electrons) / s (= seconds). The target equivalent noise Ideq is 1 ele / s.
[0113] As shown in the figure, in order to reduce the equivalent noise Ideq to 1 ele / s or lower, the current Id of the pixel source follower transistor SFd is set to 0.2 pA or higher.
[0114] When the gain of the pixel source follower transistor SFd is assumed to be 1, the approximation holds: Ideq = Idrk 2 / Id (Id: drain current of the pixel source follower transistor SFd).
[0115] At this time, when assuming Idrk = 1500 ele*q / s (q: number of elementary charges) and Ideq = 1 ele*q / s (noise caused by the target dark current of 1 ele / s), Id = 0.225 pA is obtained.
[0116] This value is basically consistent with the above simulation results.
[0117] As described above, when the drain current Id of the pixel source follower transistor SFd is set to 0.2 pA or higher, the noise caused by the above-mentioned dark current in the drain of the pixel source follower transistor SFd can be reduced to 1 electron / second or lower, and the S / N can be increased.
[0118] Note that the increase in thermal noise caused by the positive feedback of the pixel source follower transistor SFd has been studied separately. In this study, when the pixel source follower transistor SFd operates in a state where the number of carrier charges (electrons) in its channel is one or zero, the increase in thermal noise caused by positive feedback is eliminated. In the case of a transistor with a gate length of about 0.1 μm to about 0.01 μm, the current is about 1 nA.
[0119] The current of the pixel source follower transistor
[0120] Flowing the above DC current Id through the pixel source follower transistor SFd can improve the S / N. However, the flow of the DC current increases the power consumption.
[0121] In Figure 8 In the configuration shown, the power consumption is reduced by pulsing the current flowing through the pixel source follower transistor SFd. In other words, the gate of the load transistor Load is pulse-driven to limit the period during which the above DC current flows through the load transistor Load.
[0122] Figure 9 is a graph showing the input / output characteristics of the pixel source follower transistor SFd. As shown, there is almost no difference between the output when the pixel source follower transistor SFd is driven by DC (direct current) and the output when the pixel source follower transistor SFd is pulse-driven. Therefore, performing pulse driving can reduce it with almost no impact on the operation.
[0123] SPICE simulation was performed when the pixel source follower transistor SFd was pulse-driven. The pulse driving period of the load transistor Load was set to 100 μs, and the on-period was set to 5.1 μs. When the incident light is weak, the output voltage of the photodiode PD changes linearly almost within the integration period in the linear region. When the incident light becomes stronger, the change in the output voltage stops halfway, and the operation becomes an operation in the logarithmic region. In the output of the pixel source follower transistor SFd, changes caused by pulse driving appear, while in the output of the peak hold circuit, the jump waveform (hybrid wave) of the pulse disappears. This is because the peak hold circuit acts as a low-pass filter.
[0124] Configuration of the image sensor
[0125] Figure 10 is a graph showing the image sensor 200 with a two-dimensional arrangement of pixels according to the present embodiment. In this example, the pixel circuits of the pixel array 210 are provided on both the sensor substrate SB1 and the circuit substrate SB2, the vertical scanning circuit 212 and the horizontal scanning circuit 216 are provided only on the circuit substrate SB2, and the analog-to-digital converter ADC 214 can be provided on either or both of the sensor substrate SB1 and the circuit substrate SB2.
[0126] The pixel array 210 includes the pixels P as described above, arranged in m columns * n rows (m * n), that is, including m pixels in the horizontal direction and n pixels in the vertical direction. The vertical scanning circuit V-Scan 212 sequentially selects the rows of pixels in the vertical direction. The pixels in each column are connected to the analog-to-digital converter ADC 214 through the readout lines in the vertical direction. The horizontal scanning circuit H-Scan 216 is connected to the analog-to-digital converter ADC 214, and the image signals of the respective pixels are sequentially input from the horizontal scanning circuit H-Scan 216.
[0127] Figure 11 is a timing diagram Figure 10 illustrating the operation of the image sensor. Only the pixel drive pulses of the reset transistor RST and the selection transistor SEL are shown. In Figure 11 it, the Figure 5 hole injection and the pulse of the transistor SWsig in
[0128] In the (k - 1)th row, the reset transistor RST is turned on to reset the photodiode PD. The reset is performed in each vertical period (= 1 frame period). In addition, the exposure starts after one reset. Also, the signal is read out shortly before the next reset. As described above, the selection transistor SEL is turned on, and the signal accumulated in the holding capacitor Csig is read out to the output line 40. This control is performed in response to the signal from the vertical scanning circuit V-Scan 212. The read signal is an analog signal, and this analog signal is supplied to the analog-to-digital converter (ADC) 214 and converted into a digital signal. This operation is performed simultaneously on the m pixels on one horizontal line. After that, the horizontal scanning circuit (H-scan) 216 sequentially outputs the digital signals of the m pixels.
[0129] Next, by shifting the horizontal period by 1H, the same operation is performed in the kth row. By repeating this operation n times, the signals of all m * n pixels can be read out.
[0130] Modification 1
[0131] Figure 12 is a diagram illustrating the circuit configuration according to Modification 1. In this example, the source of the switch transistor SWsig and the source of the switch transistor SWrst are connected in parallel to the drain of the peak-peak holding transistor PH. The drain of the switch transistor SWrst is connected to a predetermined power supply through the holding capacitor Crst. The connection point of the switch transistor SWrst and the holding capacitor Crst is connected to the gate of the source follower transistor SF2, and the source of the source follower transistor SF2 is connected to the output line 40-2 through the selection transistor SEL2.
[0132] Therefore, the output of the peak-peak hold transistor PH can be held in and output from the hold capacitor Csig, or held in and output from the hold capacitor Crst.
[0133] Figure 13 Yes Figure 12 is the timing diagram of the circuit in. In the state where the switch transistors SWsig and SWrst are turned on, the reset transistor RST and the injection power supply are sequentially turned on for a short time to reset the photodiode PD 10 and inject holes into the hold capacitors Csig and Crst. After that, the switch transistor SWrst is turned off to keep the noise at the time of reset in the hold capacitor Crst. After the integration period ends, the switch transistor SWsig is turned off to keep the signal in the hold capacitor Csig.
[0134] After that, the row selection transistors SEL2 and SEL are turned on to output the noise and signal held in the hold capacitors Crst and Csig to the output lines 40-2 and 40, respectively. The output of the signal is performed sequentially row by row in the readout period after the integration period.
[0135] The signal and noise read out to the two output lines 40 and 40-2 are calculated in an external circuit, and the noise is removed by subtraction.
[0136] Modification 2
[0137] Figure 14 is to illustrate a pixel circuit configuration configured to Figure 12 perform a global integration operation based on the circuit in.
[0138] As shown in the figure, compared with the circuit in Figure 12 , the switch transistors SWsigt and SWrstt, the capacitors Csigt and Crstt, and the reset transistors RSTLs and RSTLr are added.
[0139] Therefore, the signal and noise held in the hold capacitors Csig and Crst can be transferred to the capacitors Csigt and Crstt and then output. Correspondingly, all pixels can hold the noise and signal in the same timing and output them row by row.
[0140] Figure 15 is to illustrate Figure 14 the circuit operation in. The photodiode PD is reset, and holes are injected into the hold capacitors Crst and Csig through the injection power supply. After immediately holding the noise in the hold capacitor Crst after reset, the held noise is transferred to the capacitor Crstt. In addition, the signal is accumulated in the hold capacitor Csig, and after the signal integration period ends, the accumulated signal is transferred to the capacitor Csigt.
[0141] Thereafter, in the next frame, the row selection transistors SELrst and SELsig are sequentially turned on, and the signals and noises accumulated in the capacitances Csigt and Crstt of the pixels are sequentially output in the row direction.
Claims
1. An image sensor, comprising: Sensor substrate; as well as Circuit board, wherein The sensor substrate includes a plurality of sensor substrate-side pixels, Each of the sensor substrate-side pixels includes a photodiode configured to operate in a photoelectric mode, a reset transistor configured to reset the photodiode, and a pixel source follower transistor connected to an output of the photodiode, The circuit substrate includes circuit substrate side pixels corresponding to the respective sensor substrate side pixels of the sensor substrate, Each of the circuit substrate side pixels includes a peak hold circuit configured to hold a peak value of an output of the pixel source follower transistor by receiving an output of the pixel source follower transistor, and a readout source follower transistor configured to read out a voltage held in a holding capacitor, The peak hold circuit includes a peak hold transistor configured to allow a current corresponding to an output of the pixel source follower transistor to flow, a switch transistor configured to turn on / off the output of the peak hold transistor, and a hold capacitor configured to hold the output of the switch transistor, and The sensor substrate side pixels and the respective corresponding circuit substrate side pixels are connected to each other. 2 . The image sensor according to claim 1 , wherein one line of sources of the pixel source follower transistor on the sensor substrate side is connected to a gate of the peak hold transistor on the circuit substrate side through a pixel contact. 3 . The image sensor according to claim 2 , wherein a protection transistor is connected to a line connecting the pixel contact on the circuit substrate and a gate of the peak hold transistor.
4. The image sensor according to claim 1, wherein The pixel source follower transistor performs a source follower operation in a state where the number of carrier charges on the channel of the pixel source follower transistor is one or zero, and The current in the source follower operation is greater than Idrk 2 / Ideq, where Idrk is the dark current in the pixel source follower transistor and Ideq is the equivalent dark current converted at the output end of the photodiode.
5. The image sensor according to claim 1, further comprising: a vertical scanning circuit configured to drive the sensor substrate side pixels on the sensor substrate and the circuit substrate side pixels on the circuit substrate; an analog-to-digital converter configured to convert an analog signal output from each of the sensor substrate-side pixels into a digital signal; and The horizontal scanning circuit is configured to serially output the digital signal obtained by the analog-to-digital converter.
6. The image sensor according to claim 1, further comprising: a vertical scanning circuit configured to drive the sensor substrate side pixels on the sensor substrate and the circuit substrate side pixels on the circuit substrate; an analog-to-digital converter configured to convert an analog signal output from each of the circuit substrate-side pixels into a digital signal; and The horizontal scanning circuit is configured to serially output the digital signal obtained by the analog-to-digital converter.
7. The image sensor according to claim 1, wherein The sensor substrate side pixels are arranged in a matrix on the sensor substrate, The circuit substrate side pixels are arranged in a matrix on the circuit substrate, and The outputs of the readout source follower transistors of each column of pixels on the circuit substrate side are connected to an output line extending in the vertical direction.