Memory, preparation method thereof and electronic equipment

Abstract

The invention discloses a memory and a preparation method thereof, and an electronic device, and relates to the technical field of semiconductors, the method comprises the steps of providing a substrate, and forming a laminated structure comprising semiconductor layers and sacrificial layers which are alternately laminated on the substrate; a first isolation structure is formed in the laminated structure, the first isolation structure comprises a vertical part and a protruding part which are integrally connected, in the row direction, the two opposite sides of the vertical part are adjacently connected with a word line preset area and a capacitor connecting area respectively, one side of the protruding part is adjacently connected with a capacitor preset area, and in the column direction, the capacitor preset area is adjacently connected with the capacitor connecting area; forming a second isolation structure and a word line structure penetrating through the laminated structure in the word line preset area; replacing the semiconductor layer in the capacitor preset area with a first electrode; and replacing the sacrificial layer of the capacitor preset area with a capacitor dielectric layer and a second electrode located on the surface of the capacitor dielectric layer. The preparation process flow of the memory is simplified, and the performance of the memory is improved.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductor technologies, and in particular, to a memory, a method for manufacturing the same, and an electronic device. Background Art

[0002] A 3D memory includes a plurality of memory cells stacked longitudinally. Adjacent memory cells in the longitudinal direction are isolated by a support layer. The lower electrodes of the storage capacitors in each memory cell need to be isolated. Typically, during the process of manufacturing the lower electrodes of the 3D memory, the lower electrode material covers the frame sacrificial layer at the same time. Subsequently, the frame sacrificial layer and the lower electrode material located on the frame sacrificial layer are removed to obtain the longitudinally isolated lower electrodes formed by the lower electrode material. The process flow is complex, and the lower electrodes formed by the lower electrode material will occupy the interlayer space between adjacent support layers, which is not conducive to the subsequent formation of the dielectric layer and the upper electrode of the storage capacitor. Summary of the Invention

[0003] Embodiments of the present disclosure provide a memory, a method for manufacturing the same, and an electronic device, which can optimize the manufacturing process of the memory and simplify the process flow.

[0004] The present disclosure provides a method for manufacturing a memory, including:

[0005] Providing a substrate, on which a stacked structure is formed, the stacked structure including semiconductor layers and sacrificial layers alternately stacked from bottom to top;

[0006] Forming a first isolation structure in the stacked structure, the first isolation structure including a vertical portion and a protruding portion integrally connected. In the longitudinal direction, the vertical portion penetrates the stacked structure, and the protruding portion is located between adjacent semiconductor layers; in the column direction, the protruding portion and the vertical portion are alternately arranged. Among them, in the row direction, the opposite sides of the vertical portion are respectively adjacent to a word line preset area and a capacitor connection area, and one side of the protruding portion is adjacent to a capacitor preset area. In the column direction, the capacitor preset area is adjacent to the capacitor connection area;

[0007] Forming a second isolation structure and a word line structure penetrating the stacked structure in the word line preset area, the second isolation structure and the word line structure extending to the first isolation structure in the row direction. In the column direction, the word line structure is located on one side of the second isolation structure;

[0008] Replacing the semiconductor layer in the capacitor preset area with a first electrode;

[0009] Replacing the sacrificial layer in the capacitor preset area with a capacitor dielectric layer and a second electrode located on the surface of the capacitor dielectric layer.

[0010] In one embodiment, forming a first isolation structure in the stacked structure includes:

[0011] Forming a first through hole penetrating the stacked structure in the stacked structure;

[0012] Laterally etch the sacrificial layer in the column direction based on the first through hole to form a first filling groove;

[0013] Fill the first filling groove and the first through hole to form a first isolation structure.

[0014] In one embodiment, a second isolation structure and a word line structure penetrating the stacked structure are formed in the word line preset area, including:

[0015] Form a word line through hole penetrating the stacked structure in the word line preset area. In the row direction, the side wall of the word line through hole exposes the first isolation structure;

[0016] Fill the word line through hole to form a second isolation structure. The second isolation structure extends along the row direction onto the first isolation structure;

[0017] In the column direction, fill the word line through hole to form a word line structure in contact with the second isolation structure.

[0018] In one embodiment, in the column direction, the second isolation structure is located in the middle area of the word line through hole. Fill the word line through hole to form a word line structure in contact with the second isolation structure, including:

[0019] Form word line structures in the word line through holes on both sides of the second isolation structure. The word line structures extend along the row direction and cover the first isolation structure on one side of the second isolation structure.

[0020] In one embodiment, on one side of the protruding portion facing away from the capacitor preset area, there is a transistor preset area adjacent thereto. In the column direction, the transistor preset area is adjacent to the word line preset area. Form word line structures in the word line through holes on both sides of the second isolation structure, including:

[0021] Form word line structures in the word line through holes on both sides of the second isolation structure that extend in the column direction to the transistor preset area adjacent to the word line through hole.

[0022] In one embodiment, on one side of the word line preset area facing away from the vertical portion, there is a bit line preset area spaced from the word line preset area and extending in the column direction. There is a transistor preset area adjacent to the word line preset area, the bit line preset area, and the protruding portion. The method for manufacturing a memory further includes:

[0023] Replace the semiconductor layer in the bit line preset area with a bit line structure, and the bit line structure is electrically connected to the semiconductor layer in the transistor preset area.

[0024] In one embodiment, replacing the semiconductor layer in the bit line preset area with a bit line structure includes:

[0025] A bit line trench extending in the column direction is formed in the bit line preset area, and the bit line trench extends from the top surface of the stacked structure at least to the top surface of the semiconductor layer located at the bottom of the stacked structure;

[0026] A bit line structure electrically connected to the semiconductor layer in the transistor preset area is formed based on the bit line trench. The bit line structures are stacked longitudinally and are arranged at intervals from the word line structure.

[0027] In one embodiment, the semiconductor layer includes a silicon material layer. Forming a bit line structure electrically connected to the semiconductor layer based on the bit line trench includes:

[0028] Forming a metal material layer in the bit line trench;

[0029] Using an annealing process to react the metal material layer with the silicon material layer to generate a bit line structure;

[0030] Removing the remaining metal material layer;

[0031] Forming a bit line lead-out structure in the bit line trench.

[0032] In one embodiment, replacing the semiconductor layer in the capacitor preset area with a first electrode includes:

[0033] Forming at least a first capacitor through hole penetrating the bottom semiconductor layer of the stacked structure in the capacitor connection area;

[0034] Laterally etching and removing each layer of the semiconductor layer in the capacitor preset area based on the first capacitor through hole to form a second filling groove;

[0035] Filling and forming a first electrode in the second filling groove.

[0036] In one embodiment, replacing the sacrificial layer in the capacitor preset area with a capacitor dielectric layer and a second electrode on the surface of the capacitor dielectric layer includes:

[0037] Forming a second capacitor through hole penetrating the stacked structure in the capacitor connection area;

[0038] Laterally etching and removing each layer of the sacrificial layer in the capacitor preset area based on the second capacitor through hole to form a third filling groove;

[0039] Sequentially forming a capacitor dielectric layer and a second electrode on the inner wall of the third filling groove.

[0040] In one embodiment, sequentially forming a capacitor dielectric layer and a second electrode on the inner wall of the third filling groove includes:

[0041] Forming a capacitor dielectric layer on the inner wall of the third filling groove, and the capacitor dielectric layer extends along the side wall of the third filling groove to cover the inner wall of the second capacitor through hole;

[0042] Forming a second electrode on the capacitor dielectric layer.

[0043] In one embodiment, the second electrode fills the third filling groove, and the method for manufacturing the memory further includes:

[0044] A reference signal line is formed by filling in the second capacitor through hole. The reference signal line is electrically connected to the second electrode and isolated from the first electrode.

[0045] In one embodiment, the side wall of the second capacitor through hole exposes the first electrode. Forming the capacitor dielectric layer on the inner wall of the third filling groove includes: forming the capacitor dielectric layer on the inner wall of the third filling groove, and the capacitor dielectric layer extends along the side wall of the third filling groove and covers the inner wall of the second capacitor through hole.

[0046] In one embodiment, an annular groove surrounds the periphery of the stacked structure, and the bottom of the annular groove is lower than or flush with the bottom of the stacked structure. The method for manufacturing the memory further includes:

[0047] Etching the sacrificial layer laterally based on the annular groove to form a fourth filling groove;

[0048] A first isolation layer is formed by filling in the fourth filling groove;

[0049] Replacing the sacrificial layer in the capacitor preset area with a capacitor dielectric layer and a second electrode on the surface of the capacitor dielectric layer includes:

[0050] Replacing the first isolation layer in the capacitor preset area with a capacitor dielectric layer and a second electrode on the surface of the capacitor dielectric layer.

[0051] In the above method for manufacturing the memory, replacing the semiconductor layer in the capacitor preset area with the first electrode eliminates the process step of forming mutually isolated lower electrodes in the interlayer space between adjacent support layers, simplifies the manufacturing process flow of the memory. The first electrode simultaneously serves as the support layer and the lower electrode of the storage capacitor, and there is no need to additionally grow the lower electrode of the storage capacitor in the interlayer space between the support layers, indirectly increasing the interlayer space for forming the capacitor dielectric layer and the upper electrode, which is beneficial to filling and forming the grounding end in contact with the upper electrode, achieving the purpose of reducing the heat dissipated inside the storage capacitor during the operation of the memory and improving the performance of the memory. Moreover, the increase in the interlayer space for forming the capacitor dielectric layer and the upper electrode is beneficial to increasing the capacitance of the storage capacitor and reducing the production cost.

[0052] The present disclosure also provides a memory, including:

[0053] A multi-layer memory cell stacked longitudinally perpendicular to a substrate; the memory cell includes a memory transistor and a memory capacitor spaced apart in a plane parallel to the substrate; the memory transistor includes a semiconductor layer, the semiconductor layer includes a source contact region, a channel region, and a drain contact region arranged in sequence in a row direction, the memory capacitor includes a first electrode, a capacitor dielectric layer, and a second electrode, in the row direction, the first electrode is located on a side of the source contact region facing away from the channel region and is electrically connected to the source contact region, in the longitudinal direction, opposite surfaces of the first electrode are flush with opposite surfaces of the semiconductor layer, the capacitor dielectric layer covers parallel surfaces of the first electrode parallel to the substrate, and the second electrode covers a surface of the capacitor dielectric layer facing away from the first electrode;

[0054] A word line structure runs longitudinally through a plurality of stacked memory cells, and the memory transistors in each memory cell share the word line structure. The semiconductor layer contacts the sidewall of the word line structure, and the semiconductor layers in different layers of memory cells are spaced apart longitudinally. In the column direction, the word line structure is located on one side of the channel region;

[0055] A bit line structure extends in the column direction. In the row direction, it is located on one side of the drain contact region and is connected to the drain contact region. The bit line structures are spaced apart longitudinally.

[0056] In one embodiment, the capacitor dielectric layer extends along the parallel surface of the first electrode and covers the sidewall of the first electrode.

[0057] In one embodiment, the memory further includes: a reference signal line that runs longitudinally through a plurality of stacked memory cells. In the row direction, it is located on a side of the word line structure facing away from the bit line structure and is isolated from the word line structure and the first electrode; in the column direction, it is located between adjacent memory capacitors and is electrically connected to the second electrodes of adjacent memory capacitors.

[0058] In one embodiment, the second electrode is a rectangular structure, and in the longitudinal direction, the capacitor dielectric layer, the second electrode, the capacitor dielectric layer, and the first electrode are alternately arranged in sequence.

[0059] In one embodiment, the word line structure includes an integrally connected through portion and a connection portion. The through portion runs longitudinally through a plurality of the stacked memory cells, and the connection portion is located on the memory transistor facing away from the substrate and is connected to the through portions adjacent in the column direction.

[0060] An electronic device includes a memory as described above.

[0061] In the above-mentioned memory, longitudinally, the relative surface of the first electrode serving as the lower electrode of the storage capacitor is flush with the relative surface of the semiconductor layer. The first electrode simultaneously serves as the support layer and the lower electrode of the storage capacitor, increasing the interlayer space for forming the capacitor dielectric layer and the upper electrode, which is conducive to filling and forming the grounding terminal in contact with the upper electrode, achieving the purpose of reducing the heat generated inside the storage capacitor during the operation of the memory and improving the performance of the memory. Moreover, the increase in the interlayer space for forming the capacitor dielectric layer and the upper electrode is conducive to increasing the capacitance of the storage capacitor and reducing the production cost. Brief Description of the Drawings

[0062] To more clearly illustrate the technical solutions in the embodiments of the present disclosure or related technologies, the following will briefly introduce the drawings required for use in the description of the embodiments or related technologies. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0063] Figure 1 It is a schematic flowchart of a method for manufacturing a memory in an embodiment;

[0064] Figure 2 It is a top view schematic diagram of the memory after forming the first isolation structure in an embodiment;

[0065] Figure 3 It is Figure 2 A cross-sectional schematic diagram of the corresponding memory in the AA direction;

[0066] Figure 4 It is Figure 2 A cross-sectional schematic diagram of the corresponding memory in the BB direction;

[0067] Figure 5 It is Figure 2 A cross-sectional schematic diagram of the corresponding memory in the CC direction;

[0068] Figure 6 It is Figure 2 A cross-sectional schematic diagram of the corresponding memory in the DD direction;

[0069] Figure 7 It is Figure 2 A cross-sectional schematic diagram of the corresponding memory in the EE direction;

[0070] Figure 8 It is Figure 2 A cross-sectional schematic diagram of the corresponding memory in the FF direction;

[0071] Figure 9 It is Figure 2 A cross-sectional schematic diagram of the corresponding memory in the GG direction;

[0072] Figure 10 A top view schematic diagram of a memory after forming a word line filling groove in an embodiment;

[0073] Figure 11 For Figure 10 A cross-sectional schematic diagram of the corresponding memory in the AA direction;

[0074] Figure 12 For Figure 10 A cross-sectional schematic diagram of the corresponding memory in the BB direction;

[0075] Figure 13 For Figure 10 A cross-sectional schematic diagram of the corresponding memory in the CC direction;

[0076] Figure 14 For Figure 10 A cross-sectional schematic diagram of the corresponding memory in the DD direction;

[0077] Figure 15 For Figure 10 A cross-sectional schematic diagram of the corresponding memory in the EE direction;

[0078] Figure 16 For Figure 10 A cross-sectional schematic diagram of the corresponding memory in the FF direction;

[0079] Figure 17 For Figure 10 A cross-sectional schematic diagram of the corresponding memory in the GG direction;

[0080] Figure 18 A top view schematic diagram of a memory after forming a word line structure in an embodiment;

[0081] Figure 19 For Figure 18 A cross-sectional schematic diagram of the corresponding memory in the AA direction;

[0082] Figure 20 For Figure 18 A cross-sectional schematic diagram of the corresponding memory in the BB direction;

[0083] Figure 21 For Figure 18 A cross-sectional schematic diagram of the corresponding memory in the CC direction;

[0084] Figure 22 For Figure 18 A cross-sectional schematic diagram of the corresponding memory in the DD direction;

[0085] Figure 23 For Figure 18 A cross-sectional schematic diagram of the corresponding memory in the EE direction;

[0086] Figure 24 ForFigure 18 Schematic cross-sectional view of the corresponding memory in the FF direction;

[0087] Figure 25 For Figure 18 Schematic cross-sectional view of the corresponding memory in the GG direction;

[0088] Figure 26 Top view of the memory after forming the bit line structure in an embodiment;

[0089] Figure 27 For Figure 26 Schematic cross-sectional view of the corresponding memory in the AA direction;

[0090] Figure 28 For Figure 26 Schematic cross-sectional view of the corresponding memory in the BB direction;

[0091] Figure 29 For Figure 26 Schematic cross-sectional view of the corresponding memory in the CC direction;

[0092] Figure 30 For Figure 26 Schematic cross-sectional view of the corresponding memory in the DD direction;

[0093] Figure 31 For Figure 26 Schematic cross-sectional view of the corresponding memory in the EE direction;

[0094] Figure 32 For Figure 26 Schematic cross-sectional view of the corresponding memory in the FF direction;

[0095] Figure 33 For Figure 26 Schematic cross-sectional view of the corresponding memory in the GG direction;

[0096] Figure 34 Top view of the memory after forming the second filling groove in an embodiment;

[0097] Figure 35 For Figure 34 Schematic cross-sectional view of the corresponding memory in the AA direction;

[0098] Figure 36 For Figure 34 Schematic cross-sectional view of the corresponding memory in the BB direction;

[0099] Figure 37 For Figure 34 Schematic cross-sectional view of the corresponding memory in the CC direction;

[0100] Figure 38 For Figure 34Schematic cross-sectional view of the corresponding memory in the DD direction;

[0101] Figure 39 is Figure 34 Schematic cross-sectional view of the corresponding memory in the EE direction;

[0102] Figure 40 is Figure 34 Schematic cross-sectional view of the corresponding memory in the FF direction;

[0103] Figure 41 is Figure 34 Schematic cross-sectional view of the corresponding memory in the GG direction;

[0104] Figure 42 is a top view of the memory after forming the first electrode in an embodiment;

[0105] Figure 43 is Figure 42 Schematic cross-sectional view of the corresponding memory in the AA direction;

[0106] Figure 44 is Figure 42 Schematic cross-sectional view of the corresponding memory in the BB direction;

[0107] Figure 45 is Figure 42 Schematic cross-sectional view of the corresponding memory in the CC direction;

[0108] Figure 46 is Figure 42 Schematic cross-sectional view of the corresponding memory in the DD direction;

[0109] Figure 47 is Figure 42 Schematic cross-sectional view of the corresponding memory in the EE direction;

[0110] Figure 48 is Figure 42 Schematic cross-sectional view of the corresponding memory in the FF direction;

[0111] Figure 49 is Figure 42 Schematic cross-sectional view of the corresponding memory in the GG direction;

[0112] Figure 50 is a top view of the memory after forming the second electrode in an embodiment;

[0113] Figure 51 is Figure 50 Schematic cross-sectional view of the corresponding memory in the AA direction;

[0114] Figure 52 is Figure 50 Schematic cross-sectional view of the corresponding memory in the BB direction;

[0115] Figure 53 is Figure 50 Schematic cross-sectional view of the corresponding memory in the CC direction;

[0116] Figure 54 is Figure 50 Schematic cross-sectional view of the corresponding memory in the DD direction;

[0117] Figure 55 is Figure 50 Schematic cross-sectional view of the corresponding memory in the EE direction;

[0118] Figure 56 is Figure 50 Schematic cross-sectional view of the corresponding memory in the FF direction;

[0119] Figure 57 is Figure 50 Schematic cross-sectional view of the corresponding memory in the GG direction.

[0120] Description of reference numerals:

[0121] 102, substrate; 104, stacked structure; 106, first isolation structure; 108, first support layer; 110, second support layer; 112, first isolation layer; 114, first filling layer; 116, second isolation structure; 118, word line structure; 120, bit line structure; 122, first protective layer; 124, second filling layer; 126, first electrode; 128, capacitive dielectric layer; 130, second electrode; 202, sacrificial layer; 204, semiconductor layer; 302, first sacrificial structure; 304, word line preset groove; 306, first capacitive via; 308, second filling groove; 310, second capacitive via. Detailed implementation manners

[0122] To facilitate the understanding of the embodiments of the present disclosure, the embodiments of the present disclosure will be described more comprehensively below with reference to the relevant drawings. The preferred embodiments of the embodiments of the present disclosure are given in the drawings. However, the embodiments of the present disclosure can be implemented in many different forms and are not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the embodiments of the present disclosure more thorough and comprehensive.

[0123] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the embodiments of the present disclosure belong. The terms used in the description of the embodiments of the present disclosure herein are only for the purpose of describing specific embodiments and are not intended to limit the embodiments of the present disclosure. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0124] In the description of the embodiments of the present disclosure, it should be understood that the orientation or positional relationships indicated by the terms "upper", "lower", "vertical", "horizontal", "inner", "outer", etc. are based on the orientation or positional relationships shown in the drawings. These are only for the convenience of describing the embodiments of the present disclosure and for simplification, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, it should not be construed as a limitation to the embodiments of the present disclosure.

[0125] It can be understood that the terms "first", "second", etc. used in the present disclosure may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the present disclosure, the first isolation structure may be referred to as the second isolation structure, and similarly, the second isolation structure may be referred to as the first isolation structure. Both the first isolation structure and the second isolation structure are isolation structures, but they are not the same isolation structure.

[0126] In addition, the terms "first", "second" are only used for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first", "second" may explicitly or implicitly include at least one of such features. In the description of the present disclosure, "a plurality" means at least two, such as two, three, etc., unless otherwise specifically defined. In the description of the present disclosure, "several" means at least one, such as one, two, etc., unless otherwise specifically defined.

[0127] As used herein, the terms "substrate", "base" mean and include the base material or structure of the material of the transistors introduced in the present disclosure. The substrate may be a semiconductor substrate, a base semiconductor layer on a support structure, a metal electrode, or a semiconductor substrate having one or more layers, structures, or regions formed thereon. The substrate may be a conventional silicon substrate or other bulk substrate including a semiconductor material layer.

[0128] In the present disclosure, the upper surface of the substrate is the surface on which the stacked structure is formed, and the lower surface of the substrate is the surface opposite to the upper surface. For the upper and lower surfaces of other structures or layers, with respect to the upper surface of the substrate, for the structures or layers located in the substrate, among the two surfaces parallel to the substrate surface, the one closer to the upper surface of the substrate is the upper surface / top surface / top / top face, and the one away from the upper surface of the substrate is the lower surface / bottom surface / bottom / bottom face. For the structures or layers located on the substrate, on the contrary, among the two surfaces, the one closer to the upper surface of the substrate is the lower surface / bottom surface / bottom / bottom face, and the one away from the upper surface of the substrate is the upper surface / top surface / top / top face. For the structures, trenches, holes or layers formed in the semiconductor structure in the direction away from the substrate surface, the surface in the longitudinal direction is the sidewall of the structure, trench, hole or layer, and the position where the trench or hole penetrates and stops is the bottom of the trench or hole.

[0129] Figure 1 is a schematic flow chart of a method for manufacturing a memory in an embodiment, as Figure 1 shown. In this embodiment, a method for manufacturing a memory is provided, including:

[0130] S102, providing a substrate on which a stacked structure including alternately stacked semiconductor layers and sacrificial layers is formed.

[0131] A substrate is provided, and a stacked structure is formed on the substrate. The stacked structure includes alternately stacked semiconductor layers and sacrificial layers from bottom to top. From bottom to top means from the upper surface of the substrate on which the stacked structure is formed in the direction away from the substrate. In some embodiments, the constituent materials of the substrate include, but are not limited to, undoped single-crystalline silicon, doped single-crystalline silicon, silicon-on-insulator (SOI), stacked silicon-on-insulator (SSOI), stacked silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), or any combination thereof. As an example, in this embodiment, the constituent material of the substrate is selected as single-crystalline silicon. The substrate has a certain thickness and can serve as a structural support for the device structures (such as the stacked structure) formed thereon. As an option, the substrate can be removed in some subsequent process steps.

[0132] S104, forming a first isolation structure in the stacked structure. The first isolation structure includes a vertical portion and a protruding portion integrally connected.

[0133] A first isolation structure is formed in the stacked structure. The first isolation structure includes a vertically extending portion and a protruding portion that are integrally connected. In the longitudinal direction, the vertically extending portion penetrates the stacked structure, and the protruding portion is located between adjacent semiconductor layers. In the column direction, the protruding portions and the vertically extending portions are alternately arranged. Among them, in the row direction, on opposite sides of the vertically extending portion, there are respectively a word line preset region and a capacitor connection region adjacent thereto, and on one side of the protruding portion, there is a capacitor preset region adjacent thereto. In the column direction, the capacitor preset region is adjacent to the capacitor connection region. That is, overall, the first isolation structure is in the column direction in a plane parallel to the substrate. When the bottom of the stacked structure close to the substrate is a semiconductor layer, in the longitudinal direction, the protruding portion is located between semiconductor layers. When the bottom of the stacked structure close to the substrate is a sacrificial layer, in the longitudinal direction, the protruding portion close to the substrate is located between the substrate and the semiconductor layer, and the protruding portion away from the substrate is located between adjacent semiconductor layers.

[0134] It can be understood that the row direction and the column direction are in a plane parallel to the substrate, the longitudinal direction is perpendicular to the plane parallel to the substrate, and adjacent means in contact with each other.

[0135] S106, form a second isolation structure and a word line structure that penetrate the stacked structure in the word line preset region.

[0136] In the word line preset region, a second isolation structure and a word line structure are formed that penetrate the stacked structure. In the column direction, the word line structure is located on one side of the second isolation structure and is in contact with the second isolation structure. In the row direction, the second isolation structure and the word line structure extend onto the first isolation structure. In the column direction, adjacent word line structures are isolated from each other.

[0137] S108, replace the semiconductor layer in the capacitor preset region with a first electrode.

[0138] Replace the semiconductor layer in the capacitor preset region with a first electrode. The first electrodes are stacked in the longitudinal direction. In the longitudinal direction, the opposite surfaces of the first electrode are flush with the opposite surfaces of the semiconductor layer, that is, the top surface of the first electrode is flush with the top surface of the same-layer semiconductor layer, and the bottom surface of the first electrode is flush with the bottom surface of the same-layer semiconductor layer. In the row direction, the first electrode is electrically connected to the adjacent semiconductor layer.

[0139] S110, replace the sacrificial layer in the capacitor preset region with a capacitor dielectric layer and a second electrode on the surface of the capacitor dielectric layer.

[0140] Replace the sacrificial layer in the capacitor preset region with a capacitor dielectric layer in contact with the first electrode and a second electrode on the surface of the capacitor dielectric layer. The second electrode is in contact with the surface of the capacitor dielectric layer facing away from the first electrode. The first electrode and the second electrode are isolated from each other by the capacitor dielectric layer. Among them, the storage capacitor includes the first electrode, the capacitor dielectric layer, and the second electrode.

[0141] In the method for manufacturing the above-mentioned memory, the semiconductor layer in the capacitor preset region is replaced with a first electrode, eliminating the process step of forming mutually isolated lower electrodes in the interlayer space between adjacent support layers, thus simplifying the manufacturing process flow of the memory. The first electrode simultaneously serves as the support layer and the lower electrode of the storage capacitor, eliminating the need to separately grow the lower electrode of the storage capacitor in the interlayer space between the support layers. Indirectly, this increases the interlayer space for forming the capacitor dielectric layer and the upper electrode, facilitating the filling of the grounding terminal in contact with the upper electrode, thereby achieving the purpose of reducing the heat dissipated inside the storage capacitor during the operation of the memory and improving the performance of the memory. Moreover, the increased interlayer space for forming the capacitor dielectric layer and the upper electrode is conducive to increasing the capacitance of the storage capacitor and reducing production costs.

[0142] Figure 2 FIG. is a top view schematic diagram of the memory after forming the first isolation structure in an embodiment. Figure 3 is Figure 2 a schematic cross-sectional view of the corresponding memory in the AA direction. Figure 4 is Figure 2 a schematic cross-sectional view of the corresponding memory in the BB direction. Figure 5 is Figure 2 a schematic cross-sectional view of the corresponding memory in the CC direction. Figure 6 is Figure 2 a schematic cross-sectional view of the corresponding memory in the DD direction. Figure 7 is Figure 2 a schematic cross-sectional view of the corresponding memory in the EE direction. Figure 8 is Figure 2 a schematic cross-sectional view of the corresponding memory in the FF direction. Figure 9 is Figure 2 a schematic cross-sectional view of the corresponding memory in the GG direction. Exemplarily, the X direction can be Figure 2 the row direction in the plane parallel to the substrate 102 shown, and the Y direction can be Figure 2 the column direction in the plane parallel to the substrate 102 shown, and the Z direction can be Figure 2 the longitudinal direction from the top surface to the bottom surface of the substrate 102, as Figure 2 - Figure 9 shown. Provide the substrate 102, and a stacked structure 104 is formed on the substrate 102. The stacked structure 104 includes sacrificial layers 202 and semiconductor layers 204 that are alternately stacked in the longitudinal Z direction perpendicular to the substrate 102. The number of semiconductor layers 204 can be set according to the number of storage units stacked in the longitudinal Z direction of the memory, and the number of longitudinally stacked storage units is the same as the number of semiconductor layers 204. Optionally, the top of the stacked structure 104 can be a sacrificial layer 202 or a semiconductor layer 204; similarly, the bottom of the stacked structure 104 can be a sacrificial layer 202 or a semiconductor layer 204.

[0143] Optionally, the sacrificial layer 202 is made of one or more materials including but not limited to silicon oxides (such as silicon dioxide), silicon nitrides (silicon oxynitrides), nitrides (such as silicon nitride), carbides (silicon carbide), silicides (germanium silicide). Exemplarily, the sacrificial layer 202 is made of germanium silicide.

[0144] Optionally, the semiconductor layer 204 is made of one or more materials including but not limited to polysilicon, amorphous silicon, IGZO, IZO, ITO, zinc oxide. Exemplarily, the semiconductor layer 204 is made of polysilicon or amorphous silicon.

[0145] In one embodiment, the bottom of the stacked structure 104 is the semiconductor layer 204, and an isolation material layer is formed on the surface of the substrate 102. By providing the isolation layer, the memory cells close to the substrate 102 are isolated from the device structures in the substrate 102. Here, the isolation material layer can be regarded as a sacrificial layer made of different materials located at the bottom of the stacked structure 104. Exemplarily, the isolation material layer is made of one or more materials including but not limited to undoped polysilicon, silicon oxides (such as silicon dioxide), silicon nitrides (silicon oxynitrides), nitrides (such as silicon nitride), carbides (silicon carbide).

[0146] In one embodiment, the top of the stacked structure 104 is the semiconductor layer 204. Before forming the first isolation structure 106 in the stacked structure 104, it further includes:

[0147] A first support layer 108 is formed on the top of the stacked structure 104. The bit line structure at the top of the memory is located between the first support layer 108 and the sacrificial layer 202. The surface of the first electrode at the top of the memory facing away from the substrate 102 is flush with the bottom surface of the first support layer 108. By providing the first support layer 108, the subsequent formed second filling grooves are all located between adjacent two film layers, and the first electrodes formed in the second filling grooves subsequently have the same structure. Hereinafter, taking the top of the stacked structure 104 as the semiconductor layer 204 and the bottom of the stacked structure 104 as the sacrificial layer 202 as an example for illustration. In some embodiments, the first support layer 108 is made of one or more materials including but not limited to silicon oxides (such as silicon dioxide), silicon nitrides (silicon oxynitrides), nitrides (such as silicon nitride), carbides (silicon carbide). Exemplarily, the first support layer 108 is made of silicon dioxide.

[0148] In one embodiment, after forming the first support layer 108 on the top of the stacked structure 104 and before forming the first isolation structure 106 in the stacked structure 104, it further includes:

[0149] A second support layer 110 is formed on the top surface of the first support layer 108, and the etching rate of the second support layer 110 is less than that of the first support layer 108. By providing the second support layer 110, all the subsequently formed third filling grooves are located between two adjacent film layers, and the capacitor dielectric layer and the second electrode formed in the third filling grooves subsequently have a repetitive structure. In some embodiments, the constituent material of the second support layer 110 includes, but is not limited to, one or more of silicon oxide (such as silicon dioxide), silicon nitride (silicon oxynitride), nitride (such as silicon nitride), and carbide (silicon carbide). Exemplarily, the constituent material of the second support layer 110 is silicon nitride.

[0150] As Figure 2 - Figure 9 shown, in one embodiment, a first isolation structure 106 is formed in the stacked structure 104, including steps S202 - S206.

[0151] Step S202, forming a first through hole penetrating the stacked structure 104 in the stacked structure 104.

[0152] Specifically, through a photolithography and etching process, a first preset trench penetrating the stacked structure 104 is formed in the stacked structure 104. The first preset trench extends along the row direction X and is arranged at intervals in the Y direction. The positions of the storage transistors and storage capacitors of each storage unit in each layer of the memory are defined in the first preset trench. A first sacrificial structure 302 is filled in the first preset trench, and the first sacrificial structure 302 fills the first preset trench completely. A first through hole penetrating the first sacrificial structure 302 is formed in the first sacrificial structure 302. The first through holes are arranged at intervals in the column direction Y; in the column direction Y, the size of the first through hole is the same as that of the first preset trench, both being L1; in the row direction X, the side walls of the first through holes expose adjacent first sacrificial structures 302, that is, in the row direction X, there is a first sacrificial structure 302 between the side walls of the first through holes and the side walls of the first preset trench. The first sacrificial structures 302 on the opposite sides of the first through hole respectively define the positions of the storage capacitor and the word line structure, that is, in the row direction X, the first sacrificial structures 302 on the opposite sides of the first through hole define the positions of the capacitor connection area and the word line preset area. In the column direction, the position where the capacitor connection area is located is between the first electrodes of the storage capacitors formed subsequently, that is, the position where the first capacitor hole or the second capacitor hole is formed subsequently, and the position where the word line preset area is located is the position where the word line through hole (word line structure) is formed subsequently. In some embodiments, the constituent material of the first sacrificial structure 302 includes, but is not limited to, one or more of undoped polysilicon, silicon oxide (such as silicon dioxide), silicon nitride (silicon oxynitride), nitride (such as silicon nitride), and carbide (silicon carbide). Exemplarily, the constituent material of the first sacrificial structure 302 is silicon dioxide.

[0153] It can be understood that in practical applications, the first through hole, the word line through hole, and the first capacitor hole can be formed separately, or the first preset trench can be formed first, and then the first through hole, the word line through hole, and the first capacitor hole are formed by etching the first sacrificial structure 302 in the first preset trench. The present disclosure does not limit this. By etching the first sacrificial structure 302 in the first preset trench to form the first through hole, the word line through hole, and the first capacitor hole, alignment of the memory transistor and the memory capacitor in the column direction can be achieved.

[0154] In some embodiments, the bottom of the first preset trench is flush with the bottom surface of the stacked structure 104. In other embodiments, in the longitudinal direction Z, the first preset trench extends into the substrate 102 (isolation material layer), and by this setting, the influence of process deviation on the longitudinal isolation of adjacent memory cells by the first isolation structure is eliminated.

[0155] S204, laterally etch the sacrificial layer in the column direction based on the first through hole to form a first filling groove.

[0156] Laterally etch the sacrificial layer 202 in the column direction Y based on the first through hole to form a first filling groove. In the longitudinal direction Z, the size of the first filling groove is equal to the thickness of the sacrificial layer 202. In some embodiments, in the column direction Y, the sacrificial layer 202 between adjacent first through holes is removed by lateral etching through the first through hole. When there are no adjacent first through holes in the column direction Y for the first through hole, the sacrificial layer 202 exposed on the sidewall of the first through hole is removed by lateral etching. The first filling groove communicates with adjacent first through holes in the column direction Y, thereby increasing the capacitance of the memory capacitor in the memory.

[0157] S206, fill the first filling groove and the first through hole to form a first isolation structure.

[0158] Adopt a chemical deposition process (such as atomic layer deposition process) to fill the first filling groove and the first through hole to form a first isolation structure 106. The first isolation structure 106 at least fills the first filling groove. The isolation between the word line structure and the capacitor structure is achieved through the first isolation structure 106. The first isolation structure 106 includes a vertical portion in the first through hole and a protruding portion in the first filling groove. In the row direction X, one side of the protruding portion is adjacent to a capacitor preset area. In the column direction Y, the capacitor preset area is adjacent to a capacitor connection area. In some embodiments, the constituent material of the first isolation structure 106 includes but is not limited to one or more of silicon oxide (such as silicon dioxide), silicon nitride (silicon oxynitride), nitride (such as silicon nitride), carbide (such as silicon carbide). Exemplarily, the constituent material of the first isolation structure 106 is silicon nitride.

[0159] Figure 10 A top view schematic diagram of the memory after forming the word line filling groove in an embodiment; Figure 11 ForFigure 10 Schematic cross-sectional view of the corresponding memory in the AA direction, Figure 12 is Figure 10 Schematic cross-sectional view of the corresponding memory in the BB direction, Figure 13 is Figure 10 Schematic cross-sectional view of the corresponding memory in the CC direction, Figure 14 is Figure 10 Schematic cross-sectional view of the corresponding memory in the DD direction, Figure 15 is Figure 10 Schematic cross-sectional view of the corresponding memory in the EE direction, Figure 16 is Figure 10 Schematic cross-sectional view of the corresponding memory in the FF direction, Figure 17 is Figure 10 Schematic cross-sectional view of the corresponding memory in the GG direction. As Figure 10 - Figure 17 shown, in one embodiment, the stacked structure 104 is surrounded by an annular groove, and the bottom of the annular groove is lower than or flush with the bottom of the stacked structure 104. The method for manufacturing the memory further includes: laterally etching the sacrificial layer 202 based on the annular groove to form a fourth filling groove; filling the fourth filling groove to form a first isolation layer 112. Specifically, the sacrificial layer 202 in the stacked structure 104 is laterally etched using an etching process to form a fourth filling groove; a chemical vapor deposition process (such as an atomic layer deposition process) is used to fill the fourth filling groove to form a first isolation layer 112, and the first isolation layer 112 fills the fourth filling groove. Among them, the sacrificial layer 202 can be replaced with the first isolation layer 112 before forming the word line structure, or the sacrificial layer 202 can be directly used to form the bit line structure, storage capacitor, etc. in the memory, which is not limited herein.

[0160] Figure 18 is a top view schematic of the memory after forming the word line structure in one embodiment, Figure 19 is Figure 18 Schematic cross-sectional view of the corresponding memory in the AA direction, Figure 20 is Figure 18 Schematic cross-sectional view of the corresponding memory in the BB direction, Figure 21 is Figure 18 Schematic cross-sectional view of the corresponding memory in the CC direction, Figure 22 is Figure 18 Schematic cross-sectional view of the corresponding memory in the DD direction, Figure 23 is Figure 18 Schematic cross-sectional view of the corresponding memory in the EE direction, Figure 24 is Figure 18 Schematic cross-sectional view of the corresponding memory in the FF direction, Figure 25 is Figure 18 Schematic cross-sectional view of the corresponding memory in the GG direction. As Figure 10 - Figure 25As shown, in one embodiment, a second isolation structure 116 and a word line structure 118 that penetrate the stacked structure 104 are formed in the word line preset area, including steps S302 to S306.

[0161] S302, a word line through hole that penetrates the stacked structure 104 is formed in the word line preset area in the row direction X, and the side wall of the word line through hole exposes the first isolation structure 106.

[0162] Specifically, in the row direction X, a first preset trench of the first sacrificial structure 302 filled on one side of the first isolation structure 106 is the word line through hole, and the area where the word line through hole is located is the word line preset area. It can be understood that when there is no first preset trench, a word line through hole that penetrates the stacked structure 104 can be directly formed in the word line preset area in the row direction X by using photolithography and etching processes, and the side wall of the word line through hole close to the first isolation structure 106 exposes the side wall of the first isolation structure 106 (vertical part). The following takes the first preset trench of the first sacrificial structure 302 filled on one side of the first isolation structure 106 as the word line through hole for exemplary illustration.

[0163] S304, the second isolation structure 116 is filled and formed in the word line through hole, and the second isolation structure 116 extends to the first isolation structure.

[0164] Specifically, a first filling layer 114 is formed on the substrate 102. The constituent materials of the first filling layer 114 include, but are not limited to, one or more of silicon oxides (such as silicon dioxide), silicon nitrides (silicon oxynitride), nitrides (such as silicon nitride), and carbides (silicon carbide). Exemplarily, the constituent material of the first filling layer 114 is silicon dioxide. Secondly, a first isolation filling groove that penetrates both the first filling layer 114 and the first sacrificial structure 302 in the longitudinal Z direction and the row direction X is formed in the word line through hole (the first preset groove on one side of the first isolation structure 106 in the row direction, i.e., the word line preset area). That is, in the row direction X, the opposite side walls of the first isolation filling groove respectively expose the side walls of the first isolation structure 106 and the side walls of the first preset groove. The first isolation filling groove extends along the row direction X onto the first isolation structure 106, penetrates the first filling layer 114 on the first isolation structure 106 in the longitudinal Z direction, and the bottom of the first isolation filling groove exposes the second support layer 110 on the first isolation structure 106. The first filling layer 114 and the first isolation filling groove are both arranged at intervals in the column direction Y. In some embodiments, the bottom of the first isolation filling groove on the first isolation structure 106 exposes the first isolation structure 106 filled in the first through hole. Then, a chemical deposition process and a chemical mechanical polishing process are used to fill and form a second isolation structure 116 in the first isolation filling groove. The top surface of the second isolation structure 116 is flush with the top surface of the first filling layer 114. Optionally, the second isolation structure 116 fills the first isolation filling groove. The constituent materials of the second isolation structure 116 include, but are not limited to, one or more of silicon oxides (such as silicon dioxide), silicon nitrides (silicon oxynitride), nitrides (such as silicon nitride), and carbides (silicon carbide). Exemplarily, the constituent material of the second isolation structure 116 is silicon nitride.

[0165] S306, in the column direction, a word line structure in contact with the second isolation structure is filled and formed in the word line through hole.

[0166] Remove the first sacrificial structure 302 in the word line via hole (word line preset area), the first filling layer 114 on the first sacrificial structure 302, and the first filling layer 114 on the first isolation structure 106 (vertical part) in the column direction Y to form a word line preset groove 304. The projection of the word line preset groove 304 on the substrate 102 is aligned with the projection of the second isolation structure 116 on the substrate 102 in the column direction Y. Then, a chemical vapor deposition process (atomic layer deposition process) and a chemical mechanical polishing process are used to fill and form a word line structure 118 in the word line preset groove 304, and the top surface of the word line structure 118 is flush with the top surface of the first filling layer 114. In some embodiments, the first filling layer 114 on the stacked structure 104 on one side of the word line via hole (between adjacent second isolation structures 116 or on one side of the second isolation structure 116) in the column direction Y is removed simultaneously, and the subsequent word line structure 118 extends to the stacked structure 104 on one side of the word line via hole in the column direction Y.

[0167] In some embodiments, the constituent materials of the word line structure 118 include, but are not limited to, one or more of conductive polysilicon, metal, conductive metal nitride, conductive metal oxide, and metal silicide. Exemplarily, the metal can be tungsten (W), nickel (Ni), copper (Cu), aluminum (Al), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN); the conductive metal oxide includes iridium oxide (IrO2); the metal silicide includes tungsten silicide (WSi). Exemplarily, the constituent materials of the word line structure 118 are a stack of titanium, titanium nitride, and tungsten.

[0168] In one of the embodiments, before filling and forming the word line structure 118 in the word line preset groove 304, it further includes: forming a gate dielectric layer on the semiconductor layer 204 exposed on the sidewall of the word line preset groove 304. The constituent materials of the gate dielectric layer include, but are not limited to, silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicide, high-K material, ferroelectric material, antiferroelectric material, or a combination thereof. For example, the gate dielectric layer can include SiO2, Si3N4, HfO2, Al2O3, ZrO2, AlON, HfON, HfSiO, and HfSiON, etc. Exemplarily, the semiconductor layer 204 is a silicon material layer. Before filling and forming the word line structure 118 in the word line preset groove 304, the silicon material layer exposed on the sidewall of the word line preset groove 304 is oxidized by a thermal oxidation process to form silicon dioxide as the gate dielectric layer.

[0169] In one of the embodiments, in the column direction Y, the second isolation structure 116 is located in the middle area of the word line via hole. Filling and forming a word line structure 118 in contact with the second isolation structure 116 in the word line via hole includes:

[0170] A word line structure 118 is formed in word line vias on both sides of the second isolation structure 116. In the row direction X, the word line structure 118 extends and covers the first isolation structure 106 (vertical part) on one side of the second isolation structure 116. In the column direction Y, the word line structures 118 are isolated by the second isolation structure 116, and the projections of the word line structures 118 on the substrate 102 are aligned with the projection of the second isolation structure 116 on the substrate 102 in the column direction Y. In some embodiments, on one side of the protruding part away from the capacitor preset area, there is a transistor preset area adjacent thereto. In the column direction Y, the transistor preset area is adjacent to the word line preset area. Forming the word line structure 118 in the word line vias on both sides of the second isolation structure 116 includes: forming a word line structure 118 in the word line vias on both sides of the second isolation structure 116 that extends in the column direction Y to the transistor preset area adjacent to the word line via. Specifically, in the column direction Y, the word line structure 118 extends to the stacked structure 104 on one side of the word line via (between adjacent second isolation structures 116, on one side of the second isolation structure 116).

[0171] Figure 26 FIG. is a top view schematic diagram of a memory after forming a bit line structure in an embodiment; Figure 27 is Figure 26 a corresponding cross-sectional schematic diagram of the memory in the AA direction, Figure 28 is Figure 26 a corresponding cross-sectional schematic diagram of the memory in the BB direction, Figure 29 is Figure 26 a corresponding cross-sectional schematic diagram of the memory in the CC direction, Figure 30 is Figure 26 a corresponding cross-sectional schematic diagram of the memory in the DD direction, Figure 31 is Figure 26 a corresponding cross-sectional schematic diagram of the memory in the EE direction, Figure 32 is Figure 26 a corresponding cross-sectional schematic diagram of the memory in the FF direction, Figure 33 is Figure 26 a corresponding cross-sectional schematic diagram of the memory in the GG direction, as Figure 26 - Figure 33 shown. In one embodiment, on one side of the word line preset area away from the vertical part, there is a bit line preset area that is spaced from the word line preset area and extends in the column direction. Between the bit line preset area and the protruding part, there is a transistor preset area that is adjacent to the word line preset area, the bit line preset area, and the protruding part at the same time. The method for manufacturing the memory further includes: replacing the semiconductor layer 204 in the bit line preset area with a bit line structure 120. The bit line structure 120 extends in the column direction Y and is stacked in the longitudinal Z direction. The bit line structure 120 is electrically connected to the semiconductor layer 204 in the transistor preset area.

[0172] as Figure 26 - Figure 33As shown, in one embodiment, replacing the semiconductor layer 204 in the bit line preset area with the bit line structure 120 includes steps S402 to S404.

[0173] S402, forming a bit line trench extending along the column direction Y in the bit line preset area, the bit line trench extending from the top surface of the stacked structure 104 at least to the top surface of the semiconductor layer 204 located at the bottom of the stacked structure 104.

[0174] In some embodiments, before forming a bit line trench extending along the column direction Y in the stacked structure 104 in the bit line preset area, it further includes: forming a first protective layer 122 on the substrate 102, by forming the first protective layer 122, avoiding damaging the word line structure 118 and the first filling layer 114 when etching to form the bit line trench, thereby affecting the structural repetition of the storage capacitor in the subsequent memory in the longitudinal Z direction (the repeatability of the capacitor dielectric layer and the second electrode).

[0175] In some embodiments, the constituent material of the first protective layer 122 includes but is not limited to one or more of undoped polysilicon, silicon oxide (such as silicon dioxide), silicon nitride (silicon oxynitride), nitride (such as silicon nitride), carbide (silicon carbide). Exemplarily, the constituent material of the first protective layer 122 is silicon nitride.

[0176] Forming a bit line trench extending along the column direction Y on the side of the second isolation structure 116 facing away from the first isolation structure 106 (bit line preset area), in the row direction X, the bit line trench and the word line structure 118 are spaced apart (there is a stacked structure 104 between the bit line trench and the word line structure 118), and the bottom of the bit line trench at least exposes the top surface of the semiconductor layer 204 in the stacked structure 104 close to the substrate 102.

[0177] S404, forming a bit line structure 120 electrically connected to the semiconductor layer 204 in the transistor preset area based on the bit line trench, the bit line structure 120 being stacked in the longitudinal Z direction and spaced apart from the word line structure 118. In one embodiment, after step S404, it further includes: filling the bit line trench to form a second filling layer 124, the top surface of the second filling layer 124 being flush with the top surface of the first protective layer 122. The constituent material of the second filling layer 124 includes but is not limited to one or more of silicon oxide (such as silicon dioxide), silicon nitride (silicon oxynitride), nitride (such as silicon nitride), carbide (silicon carbide). Exemplarily, the constituent material of the second filling layer 124 is silicon nitride.

[0178] In one embodiment, the semiconductor layer 204 includes a silicon material layer, forming a bit line structure 120 connected to the semiconductor layer 204 based on the bit line trench includes steps S502 to S506.

[0179] S502. Form a metal material layer in the bit line trench.

[0180] S504. Use an annealing process to react the metal material layer with the silicon material layer to form a bit line structure.

[0181] S506. Remove the remaining metal material layer.

[0182] Specifically, a chemical vapor deposition process (such as atomic layer deposition process) and a chemical mechanical polishing process are used to fill and form a metal material layer in the bit line trench. The metal material layer at least covers the inner wall of the silicon material layer exposed in the bit line trench; an annealing process is used to react the metal material layer with the silicon material layer to form a metal silicide layer as the bit line structure 120; a wet process is used to remove the metal material layer that has not reacted with the silicon material layer.

[0183] In some embodiments, the constituent materials of the metal material layer include, but are not limited to, titanium nitride, tungsten metal, molybdenum metal, cobalt metal, aluminum metal, etc. The metal material layer reacts with the silicon material layer to form a metal silicide. The present disclosure does not limit the constituent materials of the metal material layer.

[0184] In one embodiment, after forming the bit line structure 120 electrically connected to the semiconductor layer 204 based on the bit line trench, it further includes: forming a bit line lead-out structure in the bit line trench. The bit line lead-out structure is in contact with the bit line structure 120 and is used to lead out the bit line structure 120 stacked longitudinally in the Z direction to the same plane parallel to the substrate 102.

[0185] Figure 34 A top view schematic diagram of the memory after forming the second filling groove in an embodiment; Figure 35 For Figure 34 A cross-sectional schematic diagram of the corresponding memory in the AA direction, Figure 36 For Figure 34 A cross-sectional schematic diagram of the corresponding memory in the BB direction, Figure 37 For Figure 34 A cross-sectional schematic diagram of the corresponding memory in the CC direction, Figure 38 For Figure 34 A cross-sectional schematic diagram of the corresponding memory in the DD direction, Figure 39 For Figure 34 A cross-sectional schematic diagram of the corresponding memory in the EE direction, Figure 40 For Figure 34 A cross-sectional schematic diagram of the corresponding memory in the FF direction, Figure 41 For Figure 34 A cross-sectional schematic diagram of the corresponding memory in the GG direction, Figure 42 A top view schematic diagram of the memory after forming the first electrode in an embodiment; Figure 43 For Figure 42 A cross-sectional schematic diagram of the corresponding memory in the AA direction, Figure 44For Figure 42 Schematic cross-sectional view of the corresponding memory in the BB direction Figure 45 For Figure 42 Schematic cross-sectional view of the corresponding memory in the CC direction Figure 46 For Figure 42 Schematic cross-sectional view of the corresponding memory in the DD direction Figure 47 For Figure 42 Schematic cross-sectional view of the corresponding memory in the EE direction Figure 48 For Figure 42 Schematic cross-sectional view of the corresponding memory in the FF direction Figure 49 For Figure 42 Schematic cross-sectional view of the corresponding memory in the GG direction. As Figure 34 - Figure 49 shown, in one embodiment, the semiconductor layer 204 of the capacitor preset region is replaced with the first electrode 126, including step S602-step S606.

[0186] S602, form a first capacitor via hole 306 that at least penetrates the bottom of the stacked structure 104 and the semiconductor layer 204 in the capacitor connection region.

[0187] Specifically, in the row direction X, the first preset trench filled with the first sacrificial structure 302 on the other side of the first isolation structure 106 is the first capacitor via hole 306 (capacitor connection region). In the row direction X, the first capacitor via hole 306 (capacitor connection region) and the word line via hole (word line preset region) are located on opposite sides of the first isolation structure 106 (vertical portion); it can be understood that when there is no first preset trench, lithography and etching processes can be used to directly form the first capacitor via hole 306 that penetrates the stacked structure 104 on the opposite side (capacitor connection region) of the word line via hole (word line preset region) formed on the first isolation structure 106 (vertical portion) in the row direction X. The side wall of the first capacitor via hole 306 close to the first isolation structure 106 exposes the vertical portion of the first isolation structure 106. The following takes the first preset trench filled with the first sacrificial structure 302 on the other side of the first isolation structure 106 as the first capacitor via hole 306 for exemplary illustration.

[0188] Etch and remove the first protective layer 122 on the first sacrificial structure 302 in the capacitor connection region (the side of the first isolation structure 106 away from the word line structure 118); etch the exposed first sacrificial structure 302 to form a first capacitor via hole 306 whose bottom is lower than or flush with the bottom surface of the semiconductor layer 204 of the stacked structure 104 close to the substrate 102. At this time, the first capacitor via hole 306 at least penetrates the semiconductor layer 204 at the bottom of the stacked structure 104; in the column direction Y, the size of the first capacitor via hole 306 is equal to the size of the word line via hole (or the first sacrificial structure 302). The first capacitor via hole 306 extends in the row direction X and is arranged at intervals along the column direction Y.

[0189] S604, laterally etch the semiconductor layers 204 of each layer in the capacitor preset area based on the first capacitor through-hole 306 to form a second filling groove 308.

[0190] Laterally etch the semiconductor layer 204 exposed on the sidewall of the first capacitor through-hole 306 to remove the semiconductor layers 204 of each layer in the stacked structure 104 of the capacitor preset area, so as to form a second filling groove 308. The second filling groove 308 is located between adjacent sacrificial layers 202 and between the substrate 102 and adjacent sacrificial layers 202, and the bottom of the second filling groove 308 exposes the semiconductor layer 204. When the sacrificial layer 202 is replaced with the first isolation layer 112, the second filling groove 308 is located between adjacent first isolation layers 112 and between the substrate 102 and adjacent first isolation layers 112. When the bottom of the first capacitor through-hole 306 exposes the first isolation layer 112, the second filling groove 308 is located between adjacent first isolation layers 112. When the top of the stacked structure 104 is the semiconductor layer 204, the second filling groove 308 facing away from the substrate 102 is located between the first support layer 108 and adjacent first isolation layers 112 (or sacrificial layers 202). In the longitudinal direction Z, the size of the second filling groove 308 is equal to the thickness of the semiconductor layer 204. In some embodiments, in the column direction Y, laterally etch and remove the semiconductor layer 204 between adjacent first capacitor through-holes 306 through the first capacitor through-hole 306. When there is no adjacent first capacitor through-hole 306 in the first capacitor through-hole 306 in the column direction Y, laterally etch and remove the semiconductor layer 204 exposed on the sidewall of the first capacitor through-hole 306. The second filling groove 308 communicates with adjacent first capacitor through-holes 306 in the column direction Y, thereby increasing the length of the first electrode in the column direction Y in the memory.

[0191] S606, fill the second filling groove 308 to form a first electrode 126.

[0192] A first electrode material layer is formed by filling in the second filling groove 308 by using a deposition process (e.g., physical vapor deposition process, chemical vapor deposition process, atomic layer deposition process) and a chemical mechanical polishing process. The first electrode material layer extends to fill in the first capacitor hole 306, and the first electrode material layer extends along the side wall of the first capacitor hole 306 to cover the substrate 102. The top surface of the first electrode material layer is flush with the top surface of the first protective layer 122. Among them, the first electrode material layer at least fills the second filling groove 308. Then, the first electrode material layer filled in the first capacitor hole 306 and the first electrode material layer on the substrate 102 are etched away to obtain a first electrode 126 composed of the remaining first electrode material layer in the second filling groove 308. Among them, the first electrode 126 is in contact with the semiconductor layer 204. The projection of the side wall of the first electrode 126 in contact with the semiconductor layer 204 on the substrate 102 coincides with the projection of the side wall of the first isolation structure 106 close to the first electrode 126 on the substrate 102. The part of the semiconductor layer 204 in contact with the bit line structure 120 is the drain contact area of the memory transistor, the part of the semiconductor layer 204 in contact with the first electrode 126 is the source contact area of the memory transistor, and the semiconductor layer 204 in contact with the word line structure between the drain contact area and the source contact area serves as the channel area of the memory transistor.

[0193] It can be understood that when the semiconductor layer 204 is a silicon material layer and the first electrode is a material containing metal atoms (e.g., TIN, W), a metal silicide layer is formed by the reaction of a part of the semiconductor layer 204 and the first electrode 126.

[0194] In some embodiments, the constituent materials of the first electrode material layer include, but are not limited to, one or more of conductive polysilicon, metal, conductive metal nitride, conductive metal oxide, and metal silicide. Exemplarily, the metal can be tungsten (W), nickel (Ni), copper (Cu), aluminum (Al), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN); the conductive metal oxide includes iridium oxide (IrO2); the metal silicide includes tungsten silicide (WSi). Exemplarily, the constituent materials of the first electrode material layer are a stack of titanium, titanium nitride, and tungsten.

[0195] Figure 50 It is a top view schematic diagram of the memory after the second electrode is formed in an embodiment; Figure 51 It is Figure 50 The corresponding cross-sectional schematic diagram of the memory in the AA direction, Figure 52 It is Figure 50 The corresponding cross-sectional schematic diagram of the memory in the BB direction, Figure 53 It is Figure 50 The corresponding cross-sectional schematic diagram of the memory in the CC direction, Figure 54 It is Figure 50Schematic cross-sectional view of the corresponding memory in the DD direction, Figure 55 is Figure 50 Schematic cross-sectional view of the corresponding memory in the EE direction, Figure 56 is Figure 50 Schematic cross-sectional view of the corresponding memory in the FF direction, Figure 57 is Figure 50 Schematic cross-sectional view of the corresponding memory in the GG direction, as Figure 42 - Figure 57 shown. In one embodiment, the sacrificial layer 202 in the capacitor preset area is replaced with a capacitor dielectric layer 128 and a second electrode 130 on the surface of the capacitor dielectric layer 128, including steps S702 - S706.

[0196] S702, form a second capacitor through hole 310 penetrating the stacked structure 104 in the capacitor preset area.

[0197] Specifically, at least etch away the stacked structure 104 (sacrificial layer 202 or first isolation layer 112) at the bottom of the first capacitor through hole 306 to obtain second capacitor through holes 310 extending along the row direction X and arranged at intervals along the column direction Y.

[0198] S704, laterally etch away each layer of the sacrificial layer 202 in the capacitor preset area based on the second capacitor through hole 310 to form a third filling groove.

[0199] Laterally etch the sacrificial layer 302 (or first isolation layer 112) exposed on the side wall of the second capacitor through hole 310 to remove each layer of the sacrificial layer 202 in the stacked structure 104 of the capacitor preset area. When the top of the stacked structure 104 is a semiconductor layer 204, laterally etch the first support layer 108 exposed on the side wall of the second capacitor through hole 310. In some embodiments, during the process of laterally etching to form the third filling groove, laterally etch the first filling layer 114 on the first electrode 126 to increase the opening size of the second capacitor through hole 310. In some embodiments, in the row direction X, there is a second filling layer 114 between the side wall of the second capacitor through hole 310 and the word line structure 118. In other embodiments, the side wall of the second capacitor through hole 310 exposes the word line structure 118, and subsequently, the word line structure 118 and the second electrode 130 are isolated by the capacitor dielectric layer 128. Through this setting, the electrode area of the storage capacitor can be increased, and thus the capacity of the storage capacitor can be increased.

[0200] In some embodiments, in the column direction Y, the sacrificial layer 302 (or the first isolation layer 112) between adjacent second capacitor vias 310 is removed by lateral etching through the second capacitor vias 310. When there is no adjacent second capacitor via 310 in the column direction Y for the second capacitor via 310, the sacrificial layer 202 exposed on the sidewall of the second capacitor via 310 is removed by lateral etching. The third filling groove communicates with the adjacent second capacitor vias 310 in the column direction Y, thereby increasing the capacitance of the storage capacitor in the memory.

[0201] S706, a capacitor dielectric layer 128 and a second electrode 130 are sequentially formed on the inner wall of the third filling groove.

[0202] By using a deposition process, a capacitor dielectric layer 128 and a second electrode 130 are sequentially formed on the inner wall of the third filling groove. Among them, the capacitor dielectric layer 128 is at least in contact with the parallel surface of the first electrode parallel to the substrate 102.

[0203] In some embodiments, the constituent material of the second electrode 130 includes, but is not limited to, one or more of conductive polysilicon, metal, conductive metal nitride, conductive metal oxide, and metal silicide. Exemplarily, the metal can be tungsten (W), nickel (Ni), copper (Cu), aluminum (Al), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN); the conductive metal oxide includes iridium oxide (IrO2); the metal silicide includes tungsten silicide (WSi) and germanium silicide (SiGe). Exemplarily, the constituent material of the second electrode 130 is a stack of titanium, titanium nitride, and tungsten. The constituent material of the second electrode 130 is the same as or different from that of the first electrode 126.

[0204] In some embodiments, the constituent material of the capacitor dielectric layer 128 includes, but is not limited to, silicon oxide (such as silicon dioxide), silicon nitride (silicon oxynitride), nitride (such as silicon nitride), metal oxide (such as Al2O3), metal oxynitride (such as AlON), metal silicide, high-K dielectric material (dielectric constant greater than 3.9), low-k dielectric material (dielectric constant greater than or equal to 2.5 and less than 3.9), ultra-low-k dielectric material (dielectric constant less than 2.5), ferroelectric material, antiferroelectric material, carbide (silicon carbide), or a combination thereof. Exemplarily, the high-K material can include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanate (SrTiO3). Exemplarily, the constituent material of the capacitor dielectric layer 128 is a high-K dielectric material. Selecting a capacitor dielectric layer 128 made of a high-K dielectric material can increase the capacitance of the storage capacitor.

[0205] In one embodiment, a capacitive dielectric layer 128 and a second electrode 130 are sequentially formed on the inner wall of the third filling groove, including step S802-step S804.

[0206] S802, forming a capacitive dielectric layer 128 on the inner wall of the third filling groove, and the capacitive dielectric layer 128 extends along the side wall of the third filling groove to cover the inner wall of the second capacitive through hole 310.

[0207] S804, forming a second electrode 130 on the capacitive dielectric layer 128.

[0208] In one embodiment, the second electrode 130 fills the third filling groove, and the method for manufacturing the memory further includes: filling and forming a reference signal line in the second capacitive through hole 310, the reference signal line is electrically connected to the second electrode 130 and isolated from the first electrode 126. Wherein, the top surface of the reference signal line is flush with the top surface of the first protective layer 122. In the column direction Y, adjacent storage capacitors and storage capacitors stacked in the longitudinal direction Z share the reference signal line. Through the reference signal line, the second electrodes of the storage capacitors can be set to a reference potential, such as zero potential, reducing the heat dissipated by the storage capacitors during the operation of the memory and improving the performance of the memory. Optionally, the constituent material of the reference signal line can be the same as or different from the constituent materials of the first electrode 126 and the second electrode 130.

[0209] In some embodiments, the second electrode 130 fills the second capacitive through hole 310, the second electrode 130 includes a reference signal line, and adjacent storage capacitors in the column direction Y and storage capacitors stacked in the longitudinal direction Z share the second electrode 130, increasing the electrode area of the storage capacitor, thereby increasing the capacitance of the storage capacitor and improving the reliability of the memory.

[0210] In one embodiment, the side wall of the second capacitive through hole 310 exposes the first electrode 126, and forming the capacitive dielectric layer 128 on the inner wall of the third filling groove includes: forming a capacitive dielectric layer 128 on the inner wall of the third filling groove, and the capacitive dielectric layer 128 extends along the side wall of the third filling groove to cover the inner wall of the second capacitive through hole 126.

[0211] It should be understood that although Figure 1 the steps in the flowchart Figure 1At least a portion of the steps may include multiple sub-steps or multiple stages, and these sub-steps or stages do not necessarily need to be executed and completed at the same moment, but can be executed at different moments. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed alternately or in rotation with at least a portion of other steps or sub-steps or stages of other steps.

[0212] As Figure 50 - Figure 57 shown, the present disclosure also provides a memory, including:

[0213] A multi-layer memory cell stacked in the longitudinal direction Z perpendicular to the substrate 102; the memory cell includes a memory transistor and a memory capacitor arranged at intervals in a plane parallel to the substrate 102; the memory transistor includes a semiconductor layer 204, and the semiconductor layer 204 includes a source contact region, a channel region, and a drain contact region arranged in sequence in the row direction X. The memory capacitor includes a first electrode 126, a capacitive dielectric layer 128, and a second electrode 130. In the row direction X, the first electrode 126 is located on a side of the source contact region away from the channel region and is connected to the source contact region. In the longitudinal direction Z, the opposite surface of the first electrode 126 is flush with the opposite surface of the semiconductor layer 204. The capacitive dielectric layer 128 covers the parallel surface of the first electrode 126 parallel to the substrate 102, and the second electrode 130 covers the surface of the capacitive dielectric layer 128 away from the first electrode 126; a word line structure 118 penetrates through the stacked multiple memory cells along the longitudinal direction Z. The memory transistors in each memory cell share the word line structure 118, and the semiconductor layer 204 is in contact with the side wall of the word line structure 118. The semiconductor layers 118 in different layers of memory cells are arranged at intervals in the longitudinal direction Z. In the column direction Y, the word line structure 118 is located on one side of the channel region; a bit line structure 120 extends along the column direction Y, is located on one side of the drain contact region in the row direction X, and is electrically connected to the drain contact region. The bit line structures 120 are arranged at intervals in the longitudinal direction Z.

[0214] In the above memory, in the longitudinal direction Z, the opposite surface of the first electrode 126 serving as the lower plate of the memory capacitor is flush with the opposite surface of the semiconductor layer 204. The first electrode 126 simultaneously serves as a support layer and the lower plate of the memory capacitor, increasing the interlayer space for forming the capacitive dielectric layer 128 and the upper plate (second electrode 130), which is beneficial to filling and forming a ground terminal (reference signal line) in contact with the upper plate, achieving the purpose of reducing the heat generated inside the memory capacitor during the operation of the memory and improving the performance of the memory. Moreover, the increase in the interlayer space for forming the capacitive dielectric layer and the upper plate is beneficial to increasing the capacitance of the memory capacitor and reducing the production cost.

[0215] In one embodiment, the capacitive dielectric layer 128 extends along a parallel surface of the first electrode 126 parallel to the substrate 102 to cover the sidewall of the first electrode 126, thereby isolating the first electrode 126 from the second electrode 130 or the reference signal line.

[0216] In one embodiment, the memory further includes: a reference signal line that, in the longitudinal Z direction, penetrates through the stacked multiple layers of memory cells, and in the row direction X, is located on a side of the word line structure 118 away from the bit line structure 120 and is isolated from the word line structure 118 and the first electrode 126; in the column direction Y, it is located between adjacent storage capacitors and is electrically connected to the second electrodes 130 of adjacent storage capacitors. The storage capacitors in adjacent memory cells share the reference signal line. By means of the reference signal line, the second electrodes 130 of the storage capacitors can be set to a reference potential, such as zero potential, thereby reducing the heat dissipated by the storage capacitors during the operation of the memory and improving the performance of the memory.

[0217] In some embodiments, the second electrode 130 fills the space between adjacent first electrodes 126. The second electrode 130 includes a reference signal line. The storage capacitors adjacent in the column direction Y and the storage capacitors stacked in the longitudinal Z direction share the second electrode 130, increasing the electrode area of the storage capacitor, and thus increasing the capacitance of the storage capacitor and improving the reliability of the memory.

[0218] In one embodiment, the second electrode 130 has a rectangular structure. In the longitudinal Z direction, the capacitive dielectric layer 128, the second electrode 130, the capacitive dielectric layer 128, and the first electrode 126 are alternately arranged in sequence, that is, the second electrodes 130 in each storage capacitor are stacked in the longitudinal Z direction perpendicular to the substrate 102, and the first electrode 126 and the capacitive dielectric layer 128 located on the parallel surface of the first electrode 126 are provided between adjacent second electrodes 130 and between the substrate 102 and the adjacent second electrodes 130.

[0219] In one embodiment, the word line structure 118 includes an integrally connected through portion and a connection portion. The through portion penetrates through the stacked multiple memory cells along the longitudinal Z direction, and the connection portion is located on the memory transistor away from the substrate 102 and is connected to the through portions adjacent in the column direction Y, thereby leading out the word line structure 118 in contact with the channel region of the same memory transistor to the surface of the memory.

[0220] The present disclosure also provides an electronic device including the memory as described above. The electronic device may include a smart phone, a computer, a tablet computer, artificial intelligence, a wearable device, or a smart mobile terminal. The embodiments of the present application do not impose special limitations on the specific form of the above-mentioned electronic device.

[0221] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as within the scope described in this specification.

[0222] The above-described embodiments merely represent several implementation manners of the embodiments of the present disclosure. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the embodiments of the present disclosure, several modifications and improvements can still be made, and these all belong to the protection scope of the embodiments of the present disclosure.

Claims

1. A method for preparing a memory, characterized in that, include: Providing a substrate, on which a stacked structure is formed, the stacked structure comprising semiconductor layers and sacrificial layers alternately stacked from bottom to top; A first isolation structure is formed in the stacked structure, wherein the first isolation structure includes a vertical portion and a protruding portion connected in an integral manner, wherein in the longitudinal direction, the vertical portion penetrates the stacked structure, and the protruding portion is located between adjacent semiconductor layers; in the column direction, the protruding portion and the vertical portion are alternately arranged, wherein in the row direction, opposite sides of the vertical portion are adjacent to a word line preset region and a capacitor connection region, respectively, and one side of the protruding portion is adjacent to a capacitor preset region, and in the column direction, the capacitor preset region is adjacent to the capacitor connection region; A second isolation structure and a word line structure penetrating the stacked structure are formed in the word line preset region, wherein the second isolation structure and the word line structure extend to the first isolation structure in the row direction, and the word line structure is located on one side of the second isolation structure in the column direction; Replacing the semiconductor layer in the preset capacitor area with a first electrode; The sacrificial layer in the capacitor preset area is replaced by a capacitor dielectric layer and a second electrode located on the surface of the capacitor dielectric layer.

2. The preparation method according to claim 1, wherein The step of forming a first isolation structure in the stacked structure comprises: forming a first through hole in the stacked structure that penetrates the stacked structure; Laterally etching the sacrificial layer in the column direction based on the first through hole to form a first filling groove; The first isolation structure is formed by filling the first filling groove and the first through hole.

3. The preparation method according to claim 1, wherein The second isolation structure and the word line structure formed in the word line preset area and penetrating the stacked structure include: forming a word line through hole penetrating the stacked structure in the word line preset region, wherein the side wall of the word line through hole in the row direction exposes the first isolation structure; Filling the word line through hole to form a second isolation structure, wherein the second isolation structure extends along the row direction to the first isolation structure; In the column direction, a word line structure contacting the second isolation structure is formed by filling the word line through hole.

4. The preparation method according to claim 3, characterized in that, In the column direction, the second isolation structure is located in the middle area of ​​the word line through hole, and the word line structure formed by filling the word line through hole and contacting the second isolation structure includes: The word line structure is formed in the word line through holes on both sides of the second isolation structure, and the word line structure extends along the row direction to cover the first isolation structure on one side of the second isolation structure.

5. The preparation method according to claim 4, characterized in that, A side of the protrusion facing away from the capacitor preset area is adjacent to a transistor preset area, and in the column direction, the transistor preset area is adjacent to the word line preset area, and the word line structure is formed in the word line through holes on both sides of the second isolation structure, including: The word line structure extending along the column direction to the transistor preset area adjacent to the word line through hole is formed in the word line through hole on both sides of the second isolation structure.

6. The preparation method according to claim 1, characterized in that, On a side of the word line preset region facing away from the vertical portion, there is a bit line preset region that is spaced apart from the word line preset region and extends along the column direction. Between the bit line preset region and the protruding portion, there is a transistor preset region adjacent to the word line preset region, the bit line preset region, and the protruding portion. The manufacturing method further includes: Replacing the semiconductor layer of the bit line preset region with a bit line structure, and the bit line structure is electrically connected to the semiconductor layer of the transistor preset region.

7. The preparation method according to claim 6, characterized in that The replacing the semiconductor layer of the bit line preset region with a bit line structure includes: Forming a bit line trench extending along the column direction in the bit line preset region, and the bit line trench extends from the top surface of the stacked structure to at least the top surface of the semiconductor layer at the bottom of the stacked structure; Forming a bit line structure electrically connected to the semiconductor layer of the transistor preset region based on the bit line trench. The bit line structures are stacked in the longitudinal direction and are spaced apart from the word line structures.

8. The preparation method according to claim 6, characterized in that, The semiconductor layer includes a silicon material layer. The forming a bit line structure electrically connected to the semiconductor layer based on the bit line trench includes: Forming a metal material layer in the bit line trench; Using an annealing process to react the metal material layer with the silicon material layer to generate the bit line structure; Removing the remaining metal material layer; Forming a bit line lead-out structure in the bit line trench.

9. The preparation method according to claim 1, characterized in that, The replacing the semiconductor layer of the capacitor preset region with a first electrode includes: Forming a first capacitor through hole in the capacitor connection region that at least penetrates the semiconductor layer at the bottom of the stacked structure; Laterally etching and removing each layer of the semiconductor layer in the capacitor preset region based on the first capacitor through hole to form a second filling groove; Filling and forming the first electrode in the second filling groove.

10. The preparation method according to claim 1, characterized in that, The replacing the sacrificial layer of the capacitor preset region with a capacitor dielectric layer and a second electrode on the surface of the capacitor dielectric layer includes: Forming a second capacitor through hole in the capacitor connection region that penetrates the stacked structure; Laterally etching and removing each layer of the sacrificial layer in the capacitor preset region based on the second capacitor through hole to form a third filling groove; Sequentially forming the capacitor dielectric layer and the second electrode on the inner wall of the third filling groove.

11. The preparation method according to claim 10, characterized in that, The sequentially forming the capacitor dielectric layer and the second electrode on the inner wall of the third filling groove includes: Forming the capacitor dielectric layer on the inner wall of the third filling groove, and the capacitor dielectric layer extends along the side wall of the third filling groove to cover the inner wall of the second capacitor through hole; Forming the second electrode on the capacitor dielectric layer.

12. The preparation method according to claim 11, characterized in that, The second electrode fills the third filling groove. The manufacturing method further includes: Filling and forming a reference signal line in the second capacitor through hole, and the reference signal line is electrically connected to the second electrode and isolated from the first electrode.

13. The preparation method according to claim 11, wherein, The side wall of the second capacitor through hole exposes the first electrode. The forming the capacitor dielectric layer on the inner wall of the third filling groove includes: Forming the capacitor dielectric layer on the inner wall of the third filling groove, and the capacitor dielectric layer extends along the side wall of the third filling groove to cover the inner wall of the second capacitor through hole.

14. The preparation method according to claim 1, wherein The periphery of the stacked structure is surrounded by an annular groove, and the bottom of the annular groove is lower than or flush with the bottom of the stacked structure. The manufacturing method further includes: Laterally etching the sacrificial layer based on the annular groove to form a fourth filling groove; Filling the fourth filling groove to form a first isolation layer; Replacing the sacrificial layer in the capacitor preset area with a capacitor dielectric layer and a second electrode on the surface of the capacitor dielectric layer includes: Replacing the first isolation layer in the capacitor preset area with a capacitor dielectric layer and a second electrode on the surface of the capacitor dielectric layer.

15. A memory, characterized in that, Includes: Multiple layers of memory cells stacked longitudinally perpendicular to the substrate; the memory cells include memory transistors and memory capacitors arranged at intervals in a plane parallel to the substrate; the memory transistors include a semiconductor layer, and the semiconductor layer includes a source contact area, a channel area, and a drain contact area arranged in sequence in the row direction. The memory capacitor includes a first electrode, a capacitor dielectric layer, and a second electrode. In the row direction, the first electrode is located on the side of the source contact area facing away from the channel area and is electrically connected to the source contact area. In the longitudinal direction, the opposite surface of the first electrode is flush with the opposite surface of the semiconductor layer. The capacitor dielectric layer covers the parallel surface of the first electrode parallel to the substrate, and the second electrode covers the surface of the capacitor dielectric layer facing away from the first electrode; A word line structure that longitudinally penetrates through multiple stacked memory cells. The memory transistors in each memory cell share the word line structure. The semiconductor layer contacts the sidewall of the word line structure. The semiconductor layers in different layers of memory cells are arranged at intervals in the longitudinal direction. In the column direction, the word line structure is located on one side of the channel area; A bit line structure that extends in the column direction and is located on one side of the drain contact area and connected to the drain contact area in the row direction. The bit line structures are arranged at intervals in the longitudinal direction.

16. The memory according to claim 15, characterized in that, The capacitor dielectric layer extends along the parallel surface of the first electrode and covers the sidewall of the first electrode.

17. The memory according to claim 15, wherein Further includes: A reference signal line that longitudinally penetrates through multiple stacked memory cells. In the row direction, it is located on the side of the word line structure facing away from the bit line structure and is isolated from the word line structure and the first electrode; in the column direction, it is located between adjacent memory capacitors and is electrically connected to the second electrodes of adjacent memory capacitors.

18. The memory according to claim 15, wherein The second electrode is a rectangular structure. In the longitudinal direction, the capacitor dielectric layer, the second electrode, the capacitor dielectric layer, and the first electrode are alternately arranged in sequence.

19. The memory according to claim 15, characterized in that, The word line structure includes an integrated through portion and a connecting portion. The through portion longitudinally penetrates through multiple stacked memory cells, and the connecting portion is located on the memory transistor facing away from the substrate and is connected to the adjacent through portions in the column direction.

20. An electronic device, characterized in that, Includes the memory according to any one of claims 15-19.

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