Variable-doping planar gate silicon carbide VDMOS device and preparation process

Abstract

The invention relates to the technical field of MOS semiconductors, and discloses a variably doped planar gate silicon carbide VDMOS device and a preparation process thereof, the variably doped planar gate silicon carbide VDMOS device comprises a plurality of MOS cells which are parallel to each other, and each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode; the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer, and a lightly doped N layer is arranged in the middle of the N drift layer of a single MOS cell; lateral symmetric P-layers are arranged in the single MOS cell and located on the left side and the right side of the N drift layer, and the section contours of the corresponding sides of the lateral symmetric P-layers on the two sides are in an arc shape. By arranging the lightly doped N layer in the middle of the N drift layer and introducing the arc-shaped laterally-symmetrical P-layers to the two sides, the electric field distribution of the device is optimized, the local electric field concentration is reduced, the breakdown voltage is remarkably improved, and the charge balance capability is enhanced and the leakage current is reduced through the contact between the laterally-symmetrical P-layers and the N substrate layer.

Description

Technical Field

[0001] The present invention relates to the field of MOS semiconductor technology, and particularly to a variably doped planar gate silicon carbide VDMOS device and a manufacturing process thereof. Background Art

[0002] Silicon carbide (SiC) VDMOS devices have attracted much attention in the field of power electronics due to their high breakdown voltage, low on-resistance, and excellent high-temperature performance.

[0003] A prior patent discloses a variably doped highly reliable planar gate silicon carbide VDMOS and its manufacturing method (publication number CN119300419A). A drain metal layer is deposited on the lower side of a silicon carbide substrate to form a drain metal layer; epitaxial growth is performed on the upper side of the silicon carbide substrate to form a drift layer; a blocking layer is formed, etched, and ion-implanted to form a first N-type region, a second N-type region, and a P-type well region. In the technology disclosed in this patent, its planar gate structure is prone to cause local electric field concentration, reducing the breakdown voltage and leading to reliability problems; moreover, the doping concentration in the drift region needs to be balanced between the on-resistance and the breakdown voltage, and it is difficult for the prior art to take both into account; high-concentration N-type doping is prone to cause parasitic bipolar conduction, resulting in a latch-up effect and restricting the reliability of the device. Summary of the Invention

[0004] The present invention provides a variably doped planar gate silicon carbide VDMOS device and a manufacturing process thereof to solve the existing technical problems and address the problems in the above background art.

[0005] To solve the above technical problems, according to one aspect of the present invention, more specifically, a variably doped planar gate silicon carbide VDMOS device is provided, which is composed of a plurality of mutually juxtaposed MOS cells. A single MOS cell includes a drain, a semiconductor epitaxial layer, a source, and a gate; the semiconductor epitaxial layer includes an N substrate layer, an N drift layer, a P+ layer, an N well layer, and a P well layer. A lightly doped N layer is provided in the middle of the N drift layer of a single MOS cell. On both sides of the N drift layer inside a single MOS cell, laterally symmetric P- layers are provided, and the cross-sectional profiles of the corresponding sides of the two laterally symmetric P- layers are arc-shaped; the bottom ends of the laterally symmetric P- layers are in contact with the N substrate layer.

[0006] Furthermore, a heavily doped N layer is formed by ion implantation at the inner bottom end of the lightly doped N layer, and the bottom end of the heavily doped N layer is in contact with the N substrate layer.

[0007] Furthermore, a rectangular P- layer is formed by ion implantation in the middle region inside the heavily doped N layer, and the bottom end of the rectangular P- layer is in contact with the N substrate layer.

[0008] Further, a heavily doped N-type half layer is formed at the inner bottom end of the lightly doped N layer by ion implantation, and the bottom end of the heavily doped N-type half layer is in contact with the N substrate layer; the cross-sectional profile of the heavily doped N-type half layer is semi-elliptical.

[0009] Further, a lightly doped N-type half layer is formed in the middle region inside the heavily doped N-type half layer by ion implantation, and the bottom end of the lightly doped N-type half layer is in contact with the N substrate layer.

[0010] Further, a semi-circular P-layer is formed in the middle region inside the heavily doped N-type half layer by ion implantation, and the bottom end of the semi-circular P-layer is in contact with the N substrate layer.

[0011] A preparation process of a variable-doped planar-gate silicon carbide VDMOS device includes: S1. Epitaxially grow an N substrate layer, an N drift layer, a P+ layer, an N well layer, and a P well layer on a semiconductor epitaxial layer in sequence by chemical vapor deposition; S2. Form a lightly doped N layer by low-dose nitrogen ion implantation in the middle region of the N drift layer, and then perform high-temperature annealing to activate the doped ions; S3. Define arc-shaped mask windows on both sides of the N drift layer by photolithography, and form laterally symmetric P-layers by boron ion implantation to ensure that their bottom ends are in contact with the N substrate layer, and perform an annealing process after ion implantation to repair lattice damage; S4. In the bottom region of the lightly doped N layer, form a heavily doped N layer by high-dose nitrogen ion implantation, and perform high-temperature annealing after ion implantation to achieve impurity activation; S5. In the middle region of the heavily doped N layer, perform boron ion implantation using a rectangular mask window to form a rectangular P-layer, and perform annealing treatment; S6. Through a semi-elliptical mask design, perform high-concentration nitrogen ion implantation at the bottom end of the lightly doped N layer to form a heavily doped N-type half layer with a semi-elliptical cross section; S7. In the middle region inside the heavily doped N-type half layer, perform low-dose nitrogen ion implantation to form a lightly doped N-type half layer, and perform annealing treatment; S8. Use a semi-circular mask to perform boron ion implantation in the middle region of the heavily doped N-type half layer to form a semi-circular P-layer, and ensure its contact with the N substrate layer after annealing; S9. Deposit and pattern a metal layer in sequence by photolithography or sputtering processes to form ohmic contacts and Schottky contacts of the drain, source, and gate.

[0012] The preparation process of a variable-doped planar-gate silicon carbide VDMOS device provided by the present invention, compared with the prior art, the effects achieved by this method are: 1. The present invention optimizes the electric field distribution of the device by arranging a lightly doped N layer in the middle of the N drift layer and introducing arc-shaped laterally symmetric P- layers on both sides, reduces the local electric field concentration, significantly improves the breakdown voltage, and the contact between the laterally symmetric P- layer and the N substrate layer enhances the charge balance ability and reduces the leakage current.

[0013] 2. The present invention further reduces the on-resistance by introducing a heavily doped N layer at the bottom of the lightly doped N layer, and at the same time improves the carrier injection efficiency through high-concentration doping, thereby improving the switching performance of the device.

[0014] 3. The present invention implants a rectangular P- layer in the heavily doped N layer to achieve local charge compensation, suppress the parasitic bipolar effect, enhance the anti-latch-up ability of the device, and at the same time maintain a low on-resistance.

[0015] 4. The present invention optimizes the lateral distribution of carriers by adopting a heavily doped N-type half layer with a semi-elliptical cross-section, reduces the edge electric field spikes, and improves the dynamic response speed and reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a schematic structural diagram of Embodiment 1 of the present invention; Figure 2 is a schematic structural diagram of Embodiment 2 of the present invention; Figure 3 is a schematic structural diagram of Embodiment 3 of the present invention; Figure 4 is a schematic structural diagram of Embodiment 4 of the present invention; Figure 5 is a schematic structural diagram of Embodiment 5 of the present invention; Figure 6 is a schematic structural diagram of Embodiment 6 of the present invention.

[0017] In the figure: 1. Drain; 2. N substrate layer; 3. N drift layer; 4. Source; 5. Gate; 6. Lightly doped N layer; 7. Laterally symmetric P- layer; 8. P+ layer; 9. N well layer; 10. P well layer; 11. Heavily doped N layer; 12. Rectangular P- layer; 13. Heavily doped N-type half layer; 14. Lightly doped N-type half layer; 15. Semi-circular P- layer; 91. Heavily doped N well layer; 92. Lightly doped N well layer. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0018] To make the technical solutions of the present invention clearer, the following further describes the present invention in detail with reference to the accompanying drawings and specific embodiments.

[0019] As Figure 1-6 shown, according to one aspect of the present invention, a preparation process of a variable-doped planar gate silicon carbide VDMOS device includes: Step 1: Sequentially epitaxially grow an N substrate layer 2, an N drift layer 3, a P+ layer 8, an N well layer 9, and a P well layer 10 on the semiconductor epitaxial layer by chemical vapor deposition; sequentially epitaxially grow an N substrate layer 2, an N drift layer 3, a P+ layer 8, an N well layer 9, and a P well layer 10 by chemical vapor deposition to construct the basic epitaxial structure of the device, ensuring that the thickness and doping concentration of each functional layer are controllable.

[0020] Step 2: Form a lightly doped N layer 6 in the middle region of the N drift layer 3 by low-dose nitrogen ion implantation (energy range: 50 - 200 keV, dose: ), and then perform high-temperature annealing (1600 - 1800 °C, inert gas environment) to activate the doped ions; form a lightly doped N layer 6 (low-dose nitrogen ion implantation + high-temperature annealing) in the middle region of the N drift layer 3 to reduce the drift region resistance and optimize the on-state characteristics.

[0021] Step 3: Define arc-shaped mask windows on both sides of the N drift layer 3 using photolithography, and form laterally symmetric P- layers 7 by boron ion implantation (energy: 100 - 300 keV, dose: ), ensuring that its bottom end contacts the N substrate layer, and perform an annealing process (1500 - 1700 °C) after ion implantation to repair lattice damage; inject boron ions through the arc-shaped mask windows on both sides of the N drift layer 3 to form laterally symmetric P- layers 7, evenly disperse the electric field, avoid local electric field concentration, and at the same time contact with the N substrate layer to enhance the charge balance ability.

[0022] Step 4: In the bottom region of the lightly doped N layer 6, form a heavily doped N layer 11 by high-dose nitrogen ion implantation (energy: 200 - 400 keV, dose: ), and perform high-temperature annealing (1700 - 1900 °C) after ion implantation to achieve impurity activation; inject high-dose nitrogen ions at the bottom of the lightly doped N layer 6 to form a heavily doped N layer 11, increase the carrier concentration, reduce the on-state resistance, and activate the impurities by high-temperature annealing.

[0023] Step 5: In the middle region of the heavily doped N layer 11, perform boron ion implantation (energy: 50 - 150 keV, dose: ) using a rectangular mask window to form a rectangular P- layer 12, and perform annealing treatment (1600 - 1800 °C); inject a rectangular P- layer 12 in the middle of the heavily doped N layer 11 to neutralize excess electrons, suppress the parasitic bipolar effect, and improve the latch-up resistance.

[0024] Step 6: Through a semi-elliptical mask design, perform high-concentration nitrogen ion implantation (energy: 300 - 500 keV, dose: ), a heavily doped N-type half-layer 13 with a semi-elliptical cross-section is formed; a semi-elliptical mask design is used to form the heavily doped N-type half-layer 13 at the bottom of the lightly doped N-layer 6, optimizing the lateral electric field distribution, reducing carrier scattering, and improving the dynamic response.

[0025] Step 7: In the middle region inside the heavily doped N-type half-layer 13, low-dose nitrogen ion implantation is carried out (energy: 100 - 250 keV, dose: ), a lightly doped N-type half-layer 14 is formed, and annealing treatment is performed; the lightly doped N-type half-layer 14 is implanted inside the heavily doped N-type half-layer 13 to form a concentration gradient, optimizing the carrier migration path and reducing the on-state loss.

[0026] Step 8: Using a semi-circular mask, boron ion implantation is carried out in the middle region of the heavily doped N-type half-layer 13 (energy: 80 - 180 keV, dose: , a semi-circular P-layer 15 is formed, and after annealing, it is ensured to be in contact with the N substrate layer 2; the semi-circular P-layer 15 is implanted in the middle of the heavily doped N-type half-layer 13 to enhance the charge compensation effect and balance the trade-off relationship between the breakdown voltage and the on-resistance.

[0027] Step 9: Through photolithography or sputtering process, metal layers are deposited and patterned in sequence to form ohmic contacts and Schottky contacts for the drain 1, source 4, and gate 5.

[0028] Example 1 As Figure 1 shown, a variable-doped planar gate silicon carbide VDMOS device includes a plurality of MOS cells arranged in parallel. A single MOS cell includes a drain 1, a semiconductor epitaxial layer, a source 4, and a gate 5; the semiconductor epitaxial layer includes an N substrate layer 2, an N drift layer 3, a P+ layer 8, an N well layer 9, and a P well layer 10, and is characterized in that: a lightly doped N layer 6 is provided in the middle of the N drift layer 3 of a single MOS cell; on both sides of the N drift layer 3 inside a single MOS cell, there are side-symmetric P-layers 7, and the corresponding side cross-sectional profiles of the two side-symmetric P-layers 7 are arc-shaped; the bottom end of the side-symmetric P-layer 7 is in contact with the N substrate layer 2. The lightly doped N layer 6 is formed by low-dose nitrogen ion implantation to reduce the drift region resistance; the arc-shaped P-layer 7 is formed by boron ion implantation through a mask window defined by photolithography, and its symmetric structure evenly disperses the electric field. Combined with high-temperature annealing to repair lattice defects, it ensures the effective activation of doping ions.

[0029] By setting a lightly doped N layer 6 in the middle of the N drift layer and introducing arc-shaped side-symmetric P-layers 7 on both sides, the electric field distribution of the device is optimized, the local electric field concentration is reduced, and the breakdown voltage is significantly improved. At the same time, the contact between the side-symmetric P-layer 7 and the N substrate layer 2 enhances the charge balance ability and reduces the leakage current.

[0030] Example 2 As Figure 2 shown, a heavily doped N layer 11 is formed by ion implantation at the inner bottom end of the lightly doped N layer 6, and the bottom end of the heavily doped N layer 11 is in contact with the N substrate layer 2. A high-dose nitrogen ion implantation is used to form the heavily doped N layer 11 at the bottom of the lightly doped N layer. The high-dose implantation increases the carrier concentration, and high-temperature annealing (1700 - 1900 °C) fully activates the impurities to form a low-resistance channel and reduce the conduction loss.

[0031] Introducing the heavily doped N layer 11 at the bottom end of the lightly doped N layer 6 further reduces the on-resistance. At the same time, the carrier injection efficiency is improved by high-concentration doping, and the switching performance of the device is improved.

[0032] Example 3 As Figure 3 shown, a heavily doped N layer 11 is formed by ion implantation at the inner bottom end of the lightly doped N layer 6, the bottom end of the heavily doped N layer 11 is in contact with the N substrate layer 2, and a rectangular P-layer 12 is formed by ion implantation in the middle region inside the heavily doped N layer 11, and the bottom end of the rectangular P-layer 12 is in contact with the N substrate layer 2. Boron ion implantation is carried out through a rectangular mask window to form the rectangular P-layer 12 in the middle of the heavily doped N layer. This structure neutralizes the high-concentration electrons through hole injection to balance the charge distribution, and the annealing process ensures the stability of the doped region.

[0033] Implanting the rectangular P-layer 12 in the heavily doped N layer 11 realizes local charge compensation, suppresses the parasitic bipolar effect, enhances the anti-latch-up ability of the device, and at the same time maintains a low on-resistance.

[0034] Example 4 As Figure 4 shown, a heavily doped N-type half-layer 13 is formed by ion implantation at the inner bottom end of the lightly doped N layer 6, and the bottom end of the heavily doped N-type half-layer 13 is in contact with the N substrate layer 2; the cross-sectional profile of the heavily doped N-type half-layer 13 is semi-elliptical. High-concentration nitrogen ion implantation is carried out through a semi-elliptical mask design. The semi-elliptical doped layer fits better with the electric field distribution law. After annealing, a smooth doping gradient is formed to reduce the carrier scattering at the interface.

[0035] Adopting the heavily doped N-type half-layer 13 with a semi-elliptical cross-section optimizes the lateral distribution of carriers, reduces the edge electric field spikes, and improves the dynamic response speed and reliability of the device.

[0036] Example 5 As Figure 5As shown, a heavily doped N-type half-layer 13 is formed by ion implantation at the inner bottom of the lightly doped N-layer 6. A lightly doped N-type half-layer 14 is formed by ion implantation in the inner middle region of the heavily doped N-type half-layer 13. The bottom end of the lightly doped N-type half-layer 14 is in contact with the N substrate layer 2. A lightly doped N-type half-layer 14 is formed at the center of the heavily doped region by using low-dose nitrogen ion implantation, forming a concentration gradient from high to low, optimizing the carrier migration path, and reducing the energy loss during conduction.

[0037] A lightly doped N-type half-layer 14 is formed inside the heavily doped N-type half-layer 13, further reducing the trade-off between the on-resistance and the switching loss through gradient doping design, and improving the efficiency under high-frequency applications.

[0038] Embodiment 6 As Figure 6 shown, a heavily doped N-type half-layer 13 is formed by ion implantation at the inner bottom of the lightly doped N-layer 6. A semicircular P-layer 15 is formed by ion implantation in the inner middle region of the heavily doped N-type half-layer 13. The bottom end of the semicircular P-layer 15 is in contact with the N substrate layer 2. The semicircular P-layer 15 is formed by boron ion implantation through a semicircular mask, and its geometric structure matches the electric field distribution, effectively neutralizing the excess electrons in the heavily doped N-type half-layer, ensuring ohmic contact with the substrate after annealing, and reducing the leakage risk.

[0039] Introducing the semicircular P-layer 15 into the heavily doped N-type half-layer 13 enhances the charge compensation effect, and at the same time improves the trade-off relationship between the breakdown voltage and the on-resistance, which is suitable for high-voltage and high-power scenarios.

[0040] The above-described embodiments merely represent several implementation manners of the present invention. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention should be subject to the appended claims.

Claims

1. A variable-doped planar-gate silicon carbide VDMOS device, which is composed of a plurality of mutually parallel MOS cells. A single MOS cell includes a drain (1), a semiconductor epitaxial layer, a source (4), and a gate (5); the semiconductor epitaxial layer includes an N substrate layer (2), an N drift layer (3), a P+ layer (8), an N well layer (9), and a P well layer (10), and is characterized in that: A lightly doped N layer (6) is provided in the middle of the N drift layer (3) of a single MOS cell; On both the left and right sides of the N drift layer (3) inside a single MOS cell, there are provided laterally symmetric P- layers (7), and the cross-sectional profiles of the corresponding sides of the two laterally symmetric P- layers (7) are arc-shaped; the bottom end of the laterally symmetric P- layer (7) is in contact with the N substrate layer (2).

2. The variable-doped planar gate silicon carbide VDMOS device according to claim 1, wherein: A heavily doped N layer (11) is formed by ion implantation at the inner bottom end of the lightly doped N layer (6), and the bottom end of the heavily doped N layer (11) is in contact with the N substrate layer (2).

3. The variably doped planar gate silicon carbide VDMOS device according to claim 2, characterized in that: A rectangular P- layer (12) is formed by ion implantation in the middle region inside the heavily doped N layer (11), and the bottom end of the rectangular P- layer (12) is in contact with the N substrate layer (2).

4. The variably doped planar gate silicon carbide VDMOS device according to claim 1, characterized in that: A heavily doped N-type half layer (13) is formed by ion implantation at the inner bottom end of the lightly doped N layer (6), and the bottom end of the heavily doped N-type half layer (13) is in contact with the N substrate layer (2); the cross-sectional profile of the heavily doped N-type half layer (13) is semi-elliptical.

5. The variably doped planar gate silicon carbide VDMOS device according to claim 4, characterized in that: A lightly doped N-type half layer (14) is formed by ion implantation in the middle region inside the heavily doped N-type half layer (13), and the bottom end of the lightly doped N-type half layer (14) is in contact with the N substrate layer (2).

6. The variable-doped planar-gate silicon carbide VDMOS device according to claim 4, wherein: A semi-circular P- layer (15) is formed by ion implantation in the middle region inside the heavily doped N-type half layer (13), and the bottom end of the semi-circular P- layer (15) is in contact with the N substrate layer (2).

7. A preparation process for a variable-doped planar-gate silicon carbide VDMOS device, characterized in that, Applied to the VDMOS device according to any one of claims 1-6, the preparation process includes: S1. Sequentially epitaxially grow an N substrate layer (2), an N drift layer (3), a P+ layer (8), an N well layer (9), and a P well layer (10) on a semiconductor epitaxial layer by chemical vapor deposition; S2. Form a lightly doped N layer (6) by low-dose nitrogen ion implantation in the middle region of the N drift layer (3), and then perform high-temperature annealing to activate the doped ions; S3. Define arc-shaped mask windows on both sides of the N drift layer (3) by photolithography, and form laterally symmetric P- layers (7) by boron ion implantation to ensure that their bottom ends are in contact with the N substrate layer, and perform an annealing process after ion implantation to repair lattice damage; S4. In the bottom region of the lightly doped N layer (6), form a heavily doped N layer (11) by high-dose nitrogen ion implantation, and perform high-temperature annealing after ion implantation to achieve impurity activation; S5. In the middle region of the heavily doped N layer (11), perform boron ion implantation using a rectangular mask window to form a rectangular P- layer (12), and perform annealing treatment; S6. Through a semi-elliptical mask design, perform high-concentration nitrogen ion implantation at the bottom end of the lightly doped N layer (6) to form a heavily doped N-type half layer (13) with a semi-elliptical cross-section; S7. In the middle region inside the heavily doped N-type half layer (13), perform low-dose nitrogen ion implantation to form a lightly doped N-type half layer (14), and perform annealing treatment; S8. Use a semi-circular mask to perform boron ion implantation in the middle region of the heavily doped N-type half layer (13) to form a semi-circular P- layer (15), and after annealing, ensure that it is in contact with the N substrate layer (2); S9. Through a photolithography or sputtering process, deposit and pattern a metal layer successively to form ohmic contacts and Schottky contacts for the drain (1), source (4), and gate (5).

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