Transistor structure

Abstract

A transistor structure is disclosed. The transistor structure includes a gate, a spacer layer, a channel region, a first recess, and a first conductive region. The gate is located above a silicon surface. The spacer layer is located above the silicon surface and covers at least a sidewall of the gate. The channel region is located below the silicon surface. The first conductive region is at least partially formed within the first recess, wherein a conductive region of a neighboring transistor structure adjacent to the transistor structure is at least partially formed within the first recess. Compared to fin-type structure transistors disclosed in the prior art, the transistor structure disclosed herein can reduce leakage current.

Description

TECHNICAL FIELD

[0001] The present invention relates to a transistor structure, and more particularly, to a transistor structure with low off current. BACKGROUND

[0002] In the prior art, one of the most commonly used transistors is a metal-oxide-semiconductor field-effect transistor (MOSFET) formed in a planar silicon wafer, where the transistor has a gate formed on a silicon surface, and the gate and the silicon surface are separated by a dielectric material. In addition, the drain and source of the transistor are formed in a substrate under the silicon surface. As the size of the transistor is scaled down, the transistor can be implemented using a fin-type structure transistor (e.g., a fin field effect transistor (FinFET), a tri-gate FET, or a double-gate transistor, etc.) so that the size of the transistor can be scaled down from 22 nanometers to 7 nanometers, or to a size smaller than 7 nanometers. However, most of the fin-type structure transistors emphasize the current driving capability of the transistor to exhibit high performance of the transistor by generating high ON current, rather than emphasizing the ability of the transistor to have low off current to exhibit low OFF current of the transistor. But for deep nanometer silicon technology, the importance of using the fin-type structure transistor as a low off current and low power component is increasing, especially when the fin-type structure transistor is applied as a switching element in a memory circuit (e.g., static random access memories (SRAMs), dynamic random access memories (DRAMs), portable integrated circuits (ICs), or wearable integrated circuits, etc.).

[0003] For example, a memory cell commonly used in dynamic random access memory (DRAM) has an access transistor and a storage capacitor. When the prior art uses a planar transistor or the finFET transistor as the access transistor, the access transistor suffers from a high off-state current problem (e.g., more than 1 pico-Ampere per memory cell) which is unacceptable because the high off-state current problem causes the stored signal in the DRAM to leak quickly, resulting in the DRAM needing a very short refresh time to recover the stored signal (otherwise the stored signal is lost). In addition, there are many known sources of off-state current in the access transistor, such as (a) gate-to-channel leakage, (b) gate-induced drain leakage (GIDL), (c) drain-induced barrier lowering (DIBL) leakage, (d) sub-threshold channel leakage, (e) source / drain sidewall or region leakage due to p-n junction in silicon, etc. In order to have an off-state current of each element close to the level of femto-Ampere, the transistor size parameters in the element must be relaxed to an unacceptable level, which violates the transistor scaling theory that requires scaling down the transistor size to reduce the memory cell size in order to achieve Moore’s Law for economics. In an exaggerated example, for a 10-nanometer technology, the gate length needs to be more than 100 nanometers to reduce the off-state current to meet the requirement of 1 femto-Ampere per memory cell, which is not practical. Therefore, how to provide a transistor with low off-state current is an important issue for the DRAM designer. SUMMARY

[0004] One embodiment of the present disclosure discloses a transistor structure. The transistor structure includes a gate, a spacer, a channel region, a first recess, and a first conductive region. The gate is located above a silicon surface. The spacer is located above the silicon surface and covers at least a sidewall of the gate. The channel region is located below the silicon surface. The first conductive region is at least partially formed in the first recess, wherein the conductive region of a neighboring transistor structure next to the transistor structure is at least partially formed in the first recess.

[0005] In another embodiment of the present invention, the transistor structure further comprises a second recess and a second conductive region. The second conductive region is formed at least partially within the second recess. The first conductive region has a first dopant concentration profile along a first extension direction, and the second conductive region has a second dopant concentration profile along a second extension direction, wherein the first extension direction and the second extension direction are parallel to a normal direction of the silicon surface, and the first dopant concentration profile and the second dopant concentration profile are not symmetric.

[0006] In another embodiment of the present invention, the transistor structure further comprises a first insulating layer, wherein the first insulating layer is formed within the first recess and is located below the first conductive region. The first conductive region comprises a first upper portion, a second upper portion, and a lower portion, the first upper portion and the second upper portion contact the spacer layer, and the lower portion contacts the channel region and is located above the first insulating layer. In addition, the transistor structure further comprises a second insulating layer. The second insulating layer covers the first conductive region. In addition, the transistor structure further comprises a contact region. The contact region is formed at least partially within the first recess, wherein the second upper portion of the first conductive region contacts the contact region, and the second insulating layer separates the first upper portion and the lower portion of the first conductive region from the contact region.

[0007] In another embodiment of the present invention, the conductive region of the adjacent transistor structure is electrically isolated from the first conductive region. In addition, in another embodiment of the present invention, at least a portion of the channel region is located below the gate and the spacer layer, and a length of the channel region is not less than a sum of a length of the gate and a length of the spacer layer. In addition, in another embodiment of the present invention, a high-stress dielectric layer is formed above the first conductive region, the spacer layer, and the gate.

[0008] Another embodiment of the present invention discloses a transistor structure. The transistor structure comprises a gate, a spacer layer, a channel region, and a first conductive region. The gate is located above a silicon surface. The spacer layer covers a sidewall of the gate. At least a portion of the channel region is located below the gate and the spacer layer. The first conductive region is formed between the spacer layer and a side insulating layer, wherein a portion of a sidewall of the first conductive region is covered by the side insulating layer

[0009] In another embodiment of the present invention, the first conductive region is partially formed in a first recess, and the side insulating layer is partially formed in the first recess. A bottom insulating layer is formed in the first recess, and the first conductive region is on the bottom insulating layer. The first conductive region includes a first upper portion, a second upper portion, and a lower portion, the first and second upper portions contact the spacer layer, and the lower portion contacts the channel region and is on the bottom insulating layer. In addition, the transistor structure further includes a contact region. The contact region is at least partially formed in the first recess, wherein the second upper portion of the first conductive region contacts the contact region, and the side insulating layer separates the first upper portion and the lower portion of the first conductive region from the contact region. In addition, in another embodiment of the present invention, the first conductive region includes silicon, silicon carbide, or silicon germanium.

[0010] In another embodiment of the present invention, the transistor structure further includes a second conductive region, another side insulating layer, and another contact region. The second conductive region is partially formed in a second recess. The another side insulating layer is partially formed in the second recess. The another contact region is partially formed in the second recess, wherein the second conductive region includes a first upper portion, a second upper portion, and a lower portion, the lower portion of the second conductive region contacts the channel region, the second upper portion of the second conductive region contacts the another contact region, and the another side insulating layer separates the first upper portion and the lower portion of the second conductive region from the another contact region.

[0011] In another embodiment of the present invention, the transistor structure further includes another spacer layer. The another spacer layer covers another sidewall of the gate, wherein a length of the channel region is not less than a sum of a length of the gate, a length of the spacer layer, and a length of the another spacer layer. In addition, the spacer layer and the another spacer layer are regrown spacer layers. In addition, in another embodiment of the present invention, the transistor structure further includes a lightly doped drain region under the spacer layer.

[0012] Another embodiment of the present invention discloses a transistor structure. The transistor structure includes a gate, a spacer layer, a channel region, a first conductive region, and a second conductive region. The gate is on a silicon surface. The spacer layer is on the silicon surface and covers a sidewall of the gate. At least a portion of the channel region is under the gate and the spacer layer. The transistor structure is an asymmetric transistor structure.

[0013] In another embodiment of the present invention, a first dopant concentration profile along a first extension direction of the first conductive region is different from a second dopant concentration profile along a second extension direction of the second conductive region. A structure between the gate and the first conductive region is different from a structure between the gate and the second conductive region. A lightly doped drain region is formed between the gate and the first conductive region. In another embodiment of the present invention, the first conductive region includes a first underlying portion below the silicon surface, the second conductive region includes a second underlying portion below the silicon surface, and a thickness of the first underlying portion is different from a thickness of the second underlying portion. A width of the channel region adjacent to one end of the first conductive region is different from a width of the channel region adjacent to another end of the second conductive region. A material of the first conductive region is different from a material of the second conductive region.

[0014] Another embodiment of the present invention discloses a transistor structure. The transistor structure includes a gate, a spacer layer, a channel region, a first conductive region, and a second conductive region. The gate is located above a silicon surface. The spacer layer is located above the silicon surface and covers a sidewall of the gate. At least a portion of the channel region is located below the gate and the spacer layer. The first conductive region is electrically coupled to one end of the channel region and the second conductive region is electrically coupled to another end of the channel region. An on-current of the transistor structure is dependent on at least one of a parameter of the first conductive region, a parameter of the channel region, an asymmetric parameter of the transistor structure, and a presence of a second insulating layer covering a sidewall of the first conductive region.

[0015] In another embodiment of the present invention, an off-current of the transistor structure is dependent on at least one of a parameter of the first conductive region, a parameter of the channel region, an asymmetric parameter of the transistor structure, and a presence of a first insulating layer below the first conductive region.

[0016] A transistor structure is disclosed. The transistor structure includes a gate, a spacer layer, a channel region, a first conductive region, and a second conductive region, wherein the spacer layer separates the first conductive region and the second conductive region from the gate, and the gate is also separated from the first conductive region and the second conductive region by the spacer layer. In addition, the first conductive region is formed on a sidewall of a first recess, and the second conductive region is formed on a sidewall of a second recess, wherein a portion of the sidewall of each of the first conductive region and the second conductive region is covered by an insulating layer, and an additional insulating layer can be selectively formed on a bottom surface of the first recess and on a bottom surface of the second recess. Therefore, compared to a fin structure transistor disclosed in the prior art, the transistor structure disclosed in the present invention can reduce leakage current and adjust on / off current of the transistor by parameters of the transistor. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1A is a schematic diagram of a transistor structure disclosed in a first embodiment of the present invention.

[0018] Figure 1B is a schematic diagram of a transistor structure disclosed in another embodiment of the present invention.

[0019] Figure 2 is a flowchart of a manufacturing method of a transistor structure disclosed in a second embodiment of the present invention.

[0020] Figure 3 is a schematic diagram illustrating formation of a first dielectric layer, a polysilicon layer, a first oxide layer, and a first nitride layer on a silicon surface.

[0021] Figure 4 is a schematic diagram illustrating formation of a dielectric layer, a gate, and a covering structure.

[0022] Figure 5 is a schematic diagram illustrating formation of a spacer layer beside the dielectric layer, the gate, and the covering structure.

[0023] Figure 6A is a schematic diagram illustrating formation of a first recess and a second recess using the spacer layer as a mask for an anisotropic etching technique.

[0024] Figure 6B is a schematic diagram illustrating etching back of the spacer layer to expose a portion of the silicon surface according to another embodiment of the present invention.

[0025] Figure 7 is a schematic diagram illustrating formation of a first insulating layer in the first recess and the second recess.

[0026] Figure 8 is a schematic diagram illustrating etching back of the first insulating layer.

[0027] Figure 9 FIG. 1 is a schematic diagram illustrating forming first and second conductive regions over a first insulating layer.

[0028] Figure 10A FIG. 2 is a schematic diagram illustrating removing the spacer layer according to another embodiment of the present application.

[0029] Figure 10B FIG. 3 is a schematic diagram illustrating forming a second dielectric layer over the spacer layer, the cap structure, the first conductive region, and the second conductive region according to another embodiment of the present application.

[0030] Figure 11 FIG. 4 is a schematic diagram illustrating forming and etching back a second insulating layer.

[0031] Figure 12A FIG. 5 is a schematic diagram illustrating a final structure of the transistor structure.

[0032] Figure 12B FIG. 6 is a schematic diagram illustrating a final structure of the transistor structure according to another embodiment of the present application. Figure 6B

[0033] Figure 13 FIG. 7 is a schematic diagram illustrating the first and second conductive regions are formed completely in the first and second recesses, respectively, according to another embodiment of the present application.

[0034] Figure 14 FIG. 8 is a schematic diagram illustrating removing the second oxide layer of the spacer layer according to another embodiment of the present application.

[0035] Figure 15 FIG. 9 is a schematic diagram illustrating regenerating the third oxide layer according to another embodiment of the present application.

[0036] Figure 16 FIG. 10 is a schematic diagram illustrating four embodiments of the transistor structure according to another embodiment of the present application.

[0037] Figure 17 FIG. 11 is a schematic diagram of a transistor structure disclosed by another embodiment of the present application.

[0038] In the drawings, the following reference numerals are used:

[0039] 100, 1600, 1601, 1602, 1603 transistor structure

[0040] 101 gate

[0041] 103 spacer layer

[0042] 1031 first portion

[0043] 1032 second portion ​

[0044] 105 channel region

[0045] 107 first conductive region

[0046] 1071, 1091 lower portion

[0047] 1072, 1092 first upper portion

[0048] 1073, 1093 second upper portion

[0049] 109 second conductive region

[0050] 110 shallow trench isolation structure

[0051] 111 dielectric layer

[0052] 112 substrate

[0053] 113 silicon surface

[0054] 115 cap structure

[0055] 117 first recess

[0056] 119, 127 first insulating layer

[0057] 121, 129 second insulating layer

[0058] 123, 131 contact region

[0059] 125 second recess

[0060] 133 conductive region

[0061] 135 lightly doped drain region

[0062] 1231, 1311 isolation material

[0063] 200-218 steps

[0064] 301 first dielectric layer

[0065] 303 polysilicon layer

[0066] 305 first oxide layer

[0067] 307 first nitride layer

[0068] 401 thin oxide layer

[0069] 403 second nitride layer

[0070] 405 second oxide layer

[0071] 501 portion

[0072] 1003 second dielectric layer

[0073] 1303 gap

[0074] 1304 insulating layer

[0075] G gate structure

[0076] S0-S3 source

[0077] D0-D3 drain DETAILED DESCRIPTION

[0078] Reference is made to Figure 1A . Figure 1A is a schematic diagram of a transistor structure 100 according to a first embodiment of the present application. As shown in Figure 1AAs shown, the transistor structure 100 includes a gate 101, a spacer layer 103, a channel region 105, a first conductive region 107, and a second conductive region 109. In addition, a shallow trench isolation (STI) structure 110 is formed beside the transistor structure 100, where the structure of the STI structure 110 is well known to those skilled in the art and is not described here. The gate 101 is formed on a dielectric layer 111, where the dielectric layer 111 is formed on a silicon surface 113 of a substrate 112. In addition, a cap structure 115 can be formed on the gate 101. The spacer layer 103 is formed on the silicon surface 113 and includes a first portion 1031 and a second portion 1032, where the first portion 1031 covers a left sidewall of the gate 101 and the second portion 1032 covers a right sidewall of the gate 101. In addition, in an embodiment of the present application, the spacer layer 103 has a three-layer structure, where the three-layer structure is a thin oxide layer, a nitride layer, and an oxide layer, respectively. However, the present application is not limited to the three-layer structure of the spacer layer 103. That is, the spacer layer 103 can be a single-layer or a multi-layer dielectric layer, and the multi-layer dielectric layer can include nitride, oxide, oxynitride, or other dielectric materials. The channel region 105 is formed under the gate 101 and the spacer layer 103, and the channel region 105 is aligned with the spacer layer 103. Because of the spacer layer 103, the length of the channel region 105 is greater than the length of the gate 101. However, in another embodiment of the present application, the channel region 105 is not completely under the gate 101 and the spacer layer 103. That is, at least a portion of the channel region 105 is under the gate 101 and the spacer layer 103. In addition, the length of the channel region 105 can be adjusted according to the length of the spacer layer 103 and the length of the gate 101. In addition, a doping can be formed in the channel region 105. In addition, in another embodiment of the present application, a lightly doped region can be formed between the gate 101 and the first conductive region 107 and / or between the gate 101 and the second conductive region 109.

[0079] The first conductive region 107 is formed and contacts sidewalls of a first recess 117, and the first conductive region 107 includes a lower portion 1071 and an upper portion (including a first upper portion 1072 and a second upper portion 1073), where the lower portion 1071 is coupled to the channel region 105 and the first upper portion 1072 and the second upper portion 1073 are coupled to the first portion 1031 of the spacer layer 103. In addition, the top surface of the second upper portion 1073 can be higher or lower than the top surface of the gate 101, and as Figure 1AAs shown, the thickness of the lower portion 1071 (e.g., the distance from the top of the lower portion 1071 to the bottom of the lower portion 1071, where the top of the lower portion 1071 is aligned with the silicon surface 113) is greater than the thickness of the channel region 105 (e.g., the distance from the top of the channel region 105 to the bottom of the channel region 105). In addition, in another embodiment of the present application, the height of the first conductive region 107 is greater than the length of the gate 101 along the silicon surface 113, or greater than the sum of the length of the gate 101 along the silicon surface 113 and the length of the spacer layer 103 along the silicon surface 113. In addition, the first conductive region 107 can comprise a material with silicon, such as silicon (Si), silicon carbide (SiC), or silicon germanium (SiGe).

[0080] A first insulating layer 119 is formed within the first recess 117 and covers the bottom surface of the first recess 117, where the first insulating layer 119 is formed below the lower portion 1071. A second insulating layer 121 is formed beside the first conductive region 107 and covers the sidewall of the lower portion 1071 and the sidewall of the first upper portion 1072. In addition, the material of the first insulating layer 119 and / or the material of the second insulating layer 121 can be oxide, nitride, or other insulating material. In one embodiment of the present application, the first insulating layer 119 and / or the second insulating layer 121 can be formed by thermal oxidation. In another embodiment of the present application, the first insulating layer 119 and the second insulating layer 121 are formed by atomic layer deposition (ALD) or chemical vapor deposition (CVD).

[0081] In addition, a conductive region 133 is also partially formed within the first recess 117, where the conductive region 133 is contained within an adjacent transistor structure beside the transistor structure 100, and the conductive region 133 can be separated or electrically isolated from the first conductive region 107 by the second insulating layer 121 or other separation methods. In another embodiment of the present application, the conductive region 133 and the first conductive region 107 are formed and connected together, so as to form a "collar" shaped conductive region within the first recess 117, and the adjacent transistor structure beside the transistor structure 100 can be a dummy structure or other transistor.

[0082] In addition, the first conductive region 107 is coupled to a contact region 123 through a second upper portion 1073, wherein the contact region 123 is for future interconnection of the transistor structure 100. Due to the second insulating layer 121, the second insulating layer 121 separates the lower portion 1071 and the first upper portion 1072 of the first conductive region 107 from the contact region 123. In addition, the contact region 123 can comprise heavily doped polysilicon or a metal-containing material. In this case, the conductive region 133 is physically separated from the first conductive region 107, and the conductive region 133 is electrically coupled to the first conductive region 107 through the contact region 123.

[0083] The first conductive region 107 has a first doping concentration profile along a first extension direction of the first conductive region 107, wherein the first extension direction is from the lower portion 1071 upwardly to the second upper portion 1073. That is, the first extension direction is parallel (or substantially parallel) to the normal direction of the silicon surface 113. In particular, the first doping concentration profile comprises a doping concentration of the lower portion 1071, a doping concentration of the first upper portion 1072, and a doping concentration of the second upper portion 1073. In an embodiment of the present application, the doping concentration of the first upper portion 1072 and / or the doping concentration of the second upper portion 1073 is higher than the doping concentration of the lower portion 1071. However, the present application is not limited to the doping concentration of the first upper portion 1072 and / or the doping concentration of the second upper portion 1073 being higher than the doping concentration of the lower portion 1071, that is, the first doping concentration profile can be other doping concentration profiles, such as any combination of lightly doped, normally doped, and heavily doped in any order.

[0084] In addition, the resistance of the first conductive region 107 can be controlled by adjusting the first doping concentration profile of the first conductive region 107. That is, for example, when an on-current of the transistor structure 100 flows from the first conductive region 107 to the channel region 105, the value of the on-current also depends on the first doping concentration profile of the first conductive region 107. In addition, the voltage drop of the first conductive region 107 can be reduced or varied by controlling the resistance of the first conductive region 107. In addition, as shown, the length of the channel region 105 is greater than the length of the gate 101, and the first insulating layer 119 also reduces the contact area between the first conductive region 107 and the substrate 112. Based on the above reasons, the leakage current of the transistor structure 100 can be reduced. In addition, in another embodiment of the present application, the resistance of the first conductive region 107 can be additionally controlled by the height, width, or length of the first conductive region 107. In addition, in another embodiment of the present application, when the leakage current of the transistor structure 100 is not a key factor for the operation of the transistor structure 100, the first insulating layer 119 can be omitted. Figure 1A As shown, the length of the channel region 105 is greater than the length of the gate 101, and the first insulating layer 119 also reduces the contact area between the first conductive region 107 and the substrate 112. Based on the above reasons, the leakage current of the transistor structure 100 can be reduced. In addition, in another embodiment of the present application, the resistance of the first conductive region 107 can be additionally controlled by the height, width, or length of the first conductive region 107. In addition, in another embodiment of the present application, when the leakage current of the transistor structure 100 is not a key factor for the operation of the transistor structure 100, the first insulating layer 119 can be omitted.

[0085] Similar to the first conductive region 107, the second conductive region 109 of the transistor structure 100 is formed to contact the sidewall of a second recess 125, and the second conductive region 109 includes a lower portion 1091 and an upper portion (including a first upper portion 1092 and a second upper portion 1093), wherein the second conductive region 109 has a second doping concentration profile along a second extension direction of the second conductive region 109, and the second extension direction is from the lower portion 1091 upwardly to the second upper portion 1093. In addition, the first doping concentration profile of the first conductive region 107 and the second doping concentration profile of the second conductive region 109 are symmetrical. However, in another embodiment of the present application, the first doping concentration profile and the second doping concentration profile can be intentionally made to be non-symmetrical.

[0086] In addition, a first insulating layer 127 is formed under the second conductive region 109, a second insulating layer 129 is formed beside the second conductive region 109, and the second conductive region 109 is coupled to a contact region 131. The structure and features of the second conductive region 109, the first insulating layer 127, the second insulating layer 129, and the contact region 131 can refer to the above description of the structure and features of the first conductive region 107, the first insulating layer 119, the second insulating layer 121, and the contact region 123, and will not be repeated here.

[0087] Please refer to Figure 1B . Figure 1B The embodiment of the present application is similar to the embodiment of Figure 1A , but Figure 1B The difference between the embodiment of the present application and the embodiment of Figure 1A is that the conductive region 133 of the adjacent transistor structure is physically and electrically isolated from the first conductive region 107 by the second insulating layer 121 and an isolation material 1231. In addition, the top of the first conductive region 107 and the top of the conductive region 133 can be aligned with the top of the spacer layer 103, so that the first conductive region 107 (or the conductive region 133) can be independently electrically coupled to other conductive lines. Similarly, the other conductive region of the other adjacent transistor structure is also physically and electrically isolated from the second conductive region 109 by the second insulating layer 129 and another isolation material 1311, so that the second conductive region 109 can also be independently electrically coupled to another conductive line.

[0088] Please refer to Figures 2-11 . Figure 2 is a flowchart of a method for manufacturing a transistor structure 100 according to a second embodiment of the present application. Figure 2 The manufacturing method of the present application will be described by referring to Figures 3-11 , wherein Figures 3-11 also shows the adjacent transistor structure (or adjacent dummy structure) beside the transistor structure 100, but for simplicity Figures 3-11The structure is not shown Figures 3-11 The detailed steps of the manufacturing method are as follows:

[0089] Step 200: Start;

[0090] Step 201: Form a first dielectric layer 301, a polysilicon layer 303, a first oxide layer 305, and a first nitride layer 307 on the silicon surface 113;

[0091] Step 202: Etch the area outside the gate pattern to form the dielectric layer 111, the gate 101, and the covering structure 115;

[0092] Step 204: Form the spacer layer 103 beside the dielectric layer 111, the gate 101, and the covering structure 115;

[0093] Step 206: Use the spacer layer 103 as a mask for anisotropic etching technique to form the first recess 117 and the second recess 125;

[0094] Step 208: Form the first insulating layer 119, 127 in the first recess 117 and the second recess 125, respectively;

[0095] Step 210: Etch back the first insulating layer 119, 127;

[0096] Step 212: Form the first conductive region 107 and the second conductive region 109 on the first insulating layer 119, 127, respectively;

[0097] Step 214: Form and etch back the second insulating layer 121, 129;

[0098] Step 216: Fill the first recess 117 and the second recess 125 to form the contact region 123, 131, respectively;

[0099] Step 218: End.

[0100] First, using known process steps, a shallow trench isolation structure 110 (as shown in Figure 1A ) can be formed in the substrate 112, wherein the top of the shallow trench isolation structure 110 is about 25 to 30 nanometers lower than the silicon surface 113, and the bottom surface of the shallow trench isolation structure 110 can be about 300 to 1000 nanometers deep into the substrate 112. In addition, as shown in Figure 3As shown, in step 201, a first dielectric layer 301 is formed on the silicon surface 113, wherein the first dielectric layer 301 may be a thermally grown oxide, an oxide and composite insulating material, or other high-k material. Next, a polysilicon layer 303 (including doped polysilicon, polysilicon plus silicide material, metal, or other gate material) is deposited on the first dielectric layer 301, and a first oxide layer 305 and a first nitride layer 307 are sequentially deposited on the polysilicon layer 303.

[0101] In step 202, as Figure 4 As shown, the gate pattern corresponding to the dielectric layer 111, gate 101, and cover structure 115 is defined by a lithography masking step, and the area outside the gate pattern is etched using the anisotropic etching technique. The dielectric layer 111 includes a first dielectric layer 301, the gate 101 includes a polysilicon layer 303, and the cover structure 115 includes a first oxide layer 305 and a first nitride layer 307.

[0102] In step 204, a thin oxide layer 401, a second nitride layer 403, and a second oxide layer 405 are formed sequentially. The thin oxide layer 401 is coupled to the dielectric layer 111, the gate 101, and the capping structure 115. The second nitride layer 403 is coupled to the thin oxide layer 401, and the second oxide layer 405 is coupled to the second nitride layer 403. Next, as... Figure 5 As shown, the spacer layer 103 (including a first portion 1031 and a second portion 1032) is formed using the anisotropic etching technique. Furthermore, the spacer layer 103 is not limited to a three-layer structure; that is, the spacer layer 103 can include a two-layer structure or other multi-layer structures.

[0103] In step 206, as Figure 6A As shown, a first groove 117 and a second groove 125 are formed using an etching technique (such as the anisotropic etching technique described above) with spacer layer 103 as a photomask, and the sidewalls of the first groove 117 and the second groove 125 are aligned with spacer layer 103. The depth of each groove in the first groove 117 and the second groove 125 can be 10 nanometers, or between 10 nanometers and 30 nanometers. Additionally, in another embodiment of the invention, a portion of the second oxide layer 405 and the second nitride layer 403 can be etched again to expose a portion 501 of the silicon surface 113 (e.g., ...). Figure 6B As shown), portion 501 is located on top of the sidewalls of the first groove 117 and the second groove 125, causing the sidewalls of the first groove 117 and the second groove 125 to not align with the spacer layer 103. In subsequent steps of the manufacturing method, Figures 7-9 10A, 10B, 11, and 12A are based on Figure 6AExplained by the structure, and Figure 12B Based on Figure 6B Structural explanation.

[0104] In step 208, as Figure 7 As shown, a first insulating layer 119 is formed in a first groove 117 and covers the sidewalls and bottom of the first groove 117. Similarly, a first insulating layer 127 is formed in a second groove 125 and covers the sidewalls and bottom of the second groove 125. In addition, the first insulating layers 119 and 127 can be thermally grown oxides, deposited oxides, deposited composite insulating materials, or other materials with high dielectric constants.

[0105] In step 210, as Figure 8 As shown, portions of the first insulating layers 119 and 127 are etched back so that the tops of the first insulating layers 119 and 127 are below the silicon surface 113, thus exposing the sidewalls of the channel region 105.

[0106] In step 212, as Figure 9 As shown, a first conductive region 107 is formed and contacts the sidewall of the first groove 117, and is disposed on the first insulating layer 119. Similarly, a second conductive region 109 is formed and contacts the sidewall of the second groove 125, and is disposed on the first insulating layer 127. In one embodiment of the invention, the first conductive region 107 and the second conductive region 109 are formed by a deposition method (e.g., atomic layer deposition or chemical vapor deposition). However, in another embodiment of the invention, the first conductive region 107 and the second conductive region 109 are grown by a selective-epitaxy-growth (SEG) method. Specifically, the selective epitaxial growth method can use the left sidewall of the channel region 105 as a silicon growth seed to grow a single-crystalline silicon layer on a portion of the sidewall of the first groove 117 as the lower portion 1071 of the first conductive region 107. Then, based on the lower portion 1071, the remaining first conductive region 107 (e.g., the first upper portion 1072 and the second upper portion 1073) can be grown using the selective epitaxial growth method. During the selective epitaxial growth method, the first doping concentration distribution of the first conductive region 107 can be controlled. Similarly, the selective epitaxial growth method can use the right sidewall of the channel region 105 as the silicon growth seed to grow the single-crystalline silicon layer on a portion of the sidewall of the second groove 125 as the second conductive region 109.

[0107] Furthermore, each of the lower portion 1071, the first upper portion 1072, and the second upper portion 1073 can be deposited (or grown) through different mechanisms (e.g., using different doping concentrations or using other non-silicon materials such as mixtures of germanium or carbon atoms) to give the first conductive region 107 the first doping concentration distribution. Similarly, each of the lower portion 1091, the first upper portion 1092, and the second upper portion 1093 can also be deposited (or grown) through the aforementioned different mechanisms to give the second conductive region 109 the second doping concentration distribution. Additionally, in another embodiment of the invention, laser-annealing (or rapid thermal annealing or other annealing techniques) can be used to treat the first conductive region 107 and the second conductive region 109 to increase the quality and stability of the first conductive region 107 and the second conductive region 109. Furthermore, the design of the shape of the first conductive region 107 and the shape of the second conductive region 109 depends on the desired resistance and voltage / electric field distribution of the first conductive region 107 and the second conductive region 109. The shape / resistance of the first conductive region 107 or the shape / resistance of the second conductive region 109 can effectively control the turn-on / turn-off current of the transistor structure 100.

[0108] In another embodiment of the invention, the first conductive region 107 and the second conductive region 109 may comprise a silicon-containing material (e.g., silicon, silicon carbide, or silicon germanide) to generate stress and improve the mobility of the channel region 105. Additionally, as... Figure 10A As shown, when the first conductive region 107 and the second conductive region 109 contain silicon carbide, the spacer layer 103 can be removed to improve the stress. However, in another embodiment of the invention, as... Figure 10B As shown, a second dielectric layer 1003 (e.g., silicon nitride) can be formed on the spacer layer 103, the cover structure 115, and / or the first conductive region 107 and the second conductive region 109.

[0109] In step 214, as Figure 11 As shown, second insulating layers 121 and 129 are formed and etched back to make the second insulating layer 121 cover the lower portion 1071 and the first upper portion 1072 of the first conductive region 107, and to make the second insulating layer 129 cover the lower portion 1091 and the first upper portion 1092 of the second conductive region 109. Furthermore, the second insulating layers 121 and 129 can be thermally grown oxides, oxide and composite insulating materials, or other materials with high dielectric constants. Figure 11 As shown, the second upper portion 1073 of the first conductive region 107 is not covered by the second insulating layer 121, and the second upper portion 1093 of the second conductive region 109 is not covered by the second insulating layer 129.

[0110] In step 216, the first recess 117 and the second recess 125 are filled with n+ polysilicon material, p+ polysilicon material, metal, or other conductive material to form the contact regions 123, 131, respectively, wherein in one embodiment of the present application, the top of the contact regions 123, 131 is aligned with the top of the cover structure 115. Thus, Figure 12A The final structure of the transistor structure 100 is shown. However, in another embodiment of the present application, the top of the contact regions 123, 131 can be higher than the top of the cover structure 115. In addition, Figure 12B The final structure of the transistor structure 100 in an embodiment corresponding Figure 6B to that shown in FIG. 1A is shown. As Figure 12B shown, because the spacer layer 103 is etched back to expose portions 501 of the silicon surface 113, the portions 501 of the silicon surface 113 can also be used as the silicon growth seed to vertically grow the first and second conductive regions 107, 109 over the portions 501 of the silicon surface 113.

[0111] In another embodiment of the present application, the formation of the first insulating layers 119, 127 is not necessary, that is, step 208 can be omitted. In addition, as Figure 13 shown, in another embodiment of the present application, the portions of the first conductive region 107 below the silicon surface 113 can be formed entirely within the first recess 117, and the portions of the second conductive region 109 below the silicon surface 113 can be formed entirely within the second recess 125. That is, the second insulating layers 121, 129 can be omitted. In addition, the first and second doping concentration profiles of the first and second conductive regions 107, 109 can be controlled in the manner described above.

[0112] In addition, as Figure 14 shown, in another embodiment of the present application, the second oxide layer 405 of the spacer layer 103 can be removed to expose a gap 1303, and a third oxide or insulating layer 1304 (as Figure 15 shown) can be formed or reformed in the gap 1303 to increase the interface quality between the first conductive region 107 and the spacer layer 103 and the interface quality between the second conductive region 109 and the spacer layer 103. In addition, Figure 14 , 15 The reforming of the spacer layer is not limited to the structure of the embodiment shown in FIG. 1A, and the reforming can also be used in Figure 13 the embodiments shown in FIGS. 1B, 1C, and 1D. In addition, Figure 12Aor 12B. In addition, in another embodiment of the present application, the polysilicon layer 303 (corresponding to the gate 101) for performing a gate-first process can be replaced by other materials or p+ doped polysilicon for performing a gate-last process and having an appropriate work function (from 4.0 eV to 5.2 eV).

[0113] In addition, in another embodiment of the present application, the first doping concentration profile of the first conductive region 107 and the second doping concentration profile of the second conductive region 109 can be intentionally made asymmetric to increase the on-current of the transistor structure 100. For example, please refer to Figure 16 wherein Figure 16 The transistor structures 1600, 1601, 1602, 1603 show four embodiments, and the transistor structures 1600, 1601, 1602, 1603 correspond to a reference embodiment, an embodiment 1, an embodiment 2 and an embodiment 3 respectively. In addition, each of the transistor structures 1600, 1601, 1602, 1603 includes a gate structure G, the transistor structure 1600 includes a source S0 and a drain D0, the transistor structure 1601 includes a source S1 and a drain D1, the transistor structure 1602 includes a source S2 and a drain D2, and the transistor structure 1603 includes a source S3 and a drain D3, wherein the sources S0-S3 are the first conductive regions of the transistor structures 1600, 1601, 1602, 1603 respectively, and the drains D0-D3 are the second conductive regions of the transistor structures 1600, 1601, 1602, 1603 respectively. For simplicity of illustration, Figure 16Only the gate structures G, the source S0-S3, and the drain D0-D3 of the transistor structures 1600, 1601, 1602, 1603 are shown. In addition, the source S0-S3 and the drain D0-D3 are shown with different labels to represent different doping concentrations, which are designed depending on the trade-off between the on-current and / or the off-current requirements (or applications). In particular, as shown in the reference embodiment and embodiments 1-3, the doping concentration profile of the source S0 is the same as that of the drain D0, and the doping concentration profile of the source S3 is the same as that of the drain D3. However, the doping concentration profile of the source S0 (drain D0) is different from that of the source S3 (drain D3). For example, the doping concentration profile of the source S0 includes lightly doped, normally doped, and heavily doped from bottom to top; while the doping concentration profile of the source S3 includes only heavily doped. On the other hand, the doping concentration profile of the source S1 (e.g., including lightly doped, normally doped, and heavily doped from bottom to top) is not the same as that of the drain D1 (e.g., including only heavily doped from bottom to top), and the doping concentration profile of the source S2 (e.g., including only heavily doped from bottom to top) is not the same as that of the drain D2 (e.g., including lightly doped, normally doped, and heavily doped from bottom to top). The on-currents of embodiments 1, 2 can be higher than that of the reference embodiment. In general, embodiments with asymmetric doping concentration profiles (i.e., embodiments 1, 2) can have higher on-currents than the reference embodiment. In addition, while the asymmetric doping concentration profiles can result in a slight increase in the off-current in some cases, the desired asymmetric doping concentration profile can be selected to produce the desired on-current and an acceptable corresponding off-current.

[0114] As mentioned before, since the first conductive region 107 and / or the second conductive region 109 can include silicon, silicon carbide, or silicon germanium, the material of the first conductive region 107 can be different from the material of the second conductive region 109. Thus, a transistor having a first conductive region 107 with a material different from the material of the second conductive region 109 is an asymmetric transistor.

[0115] In addition, in another embodiment of the present application, as Figure 17As shown, before completing the spacer layer 103, a lightly-doped drain (LDD) region 135 can be formed below the silicon surface 113 and between the first conductive region 107 (e.g., the drain) and the gate 101 using some diffusion sources (without the hazards of ion implantation) or implants (which need to be removed subsequently by thermal annealing or laser annealing to remove the hazards of ion implantation). Figure 17 As shown, the lightly doped drain region 135 is formed below the silicon surface 113 of the substrate 112 or below a fin structure, and below the gate 101 and / or the spacer layer 103. In this case, no lightly doped drain is formed between the gate 101 and the second conductive region 109 (e.g., the source). Alternatively, in another embodiment of the invention, a lightly doped drain region is formed between the gate 101 and the source, rather than between the gate 101 and the drain. Therefore, the structure between the gate 101 and the source is different from the structure between the gate 101 and the drain; that is, a transistor structure containing the feature that the structure between the gate 101 and the source is different from the structure between the gate 101 and the drain is an asymmetric transistor structure.

[0116] Furthermore, the thickness of the lower portion 1071 of the first conductive region 107 (that is, the distance from the silicon surface 113 to the bottom of the lower portion 1071) may be different from the thickness of the lower portion 1091 of the second conductive region 109. Therefore, the width of one end of the channel region 105 may be different from the width of the other end of the channel region 105. In other words, a transistor structure that includes the characteristics that the thickness of the lower portion 1071 of the first conductive region 107 is different from the thickness of the lower portion 1091 of the second conductive region 109 and the width of one end of the channel region 105 is different from the width of the other end of the channel region 105 is also an asymmetric transistor structure.

[0117] Please refer to this again. Figure 1AThe channel region 105, the first conductive region 107 and the second conductive region 109 are formed by using a self-alignment technique. Therefore, the transistor structure 100 can be more accurately controlled, have a smaller form-factor, and occupy less area on a wafer plane. In addition, because the steps of the manufacturing method of the transistor structure 100 can avoid using an ion-implantation technique to form a p-n junction between the first conductive region 107 (or the second conductive region 109) and the substrate 112, damage caused by the ion-implantation technique in the p-n junction can be reduced. In addition, the position of the p-n junction, the thickness of the lower portion 1071 of the first conductive region 107 (or the thickness of the lower portion 1091 of the second conductive region 109), and the first doping concentration distribution and the second doping concentration distribution are all better controlled.

[0118] In addition, the disclosed transistor structure has an on / off current that depends on parameters of the first conductive region 107 (such as the first doping concentration distribution, the material, the thickness of the lower portion 1071 of the first conductive region 107, and the thickness of the second upper portion 1073 of the first conductive region 107), parameters of the second conductive region 109, parameters of the channel region 105 (such as the length of the channel region 105), an asymmetric parameter of the transistor structure (such as the asymmetric structure described above), and / or the presence of the first insulating layer / second insulating layer, etc. Therefore, the on / off current of the transistor structure can be adjusted by at least one of the above-mentioned parameters.

[0119] In summary, the disclosed transistor structure includes the gate, the spacer layer, the channel region, the first conductive region, and the second conductive region, wherein the first conductive region and the gate are separated by the spacer layer, and the second conductive region and the gate are also separated by the spacer layer. In addition, the first conductive region is formed to contact the sidewall of the first recess, and the second conductive region is formed to contact the sidewall of the second recess, wherein a portion of the sidewall of each of the first conductive region and the second conductive region is covered by an insulating layer, and another insulating layer can be formed on the bottom surface of the first recess and the bottom surface of the second recess. Therefore, compared to the fin-type structure transistor disclosed in the prior art, the disclosed transistor structure can reduce the leakage current and adjust the on / off current of the transistor by parameters of the transistor.

[0120] The above merely provides the preferred embodiments of the present application, and is not used to limit the present application. For those skilled in the art, the present application can have various modifications and changes. Any modifications, equivalent replacements, improvements, etc. made within the principles and technical scope of the present application shall fall into the scope of the present application.

Claims

1. A transistor structure, characterized by A transistor structure, comprising: a silicon substrate, comprising a silicon surface; a gate electrode, located above the silicon surface; a spacer layer, located above the silicon surface, wherein the spacer layer covers at least a sidewall of the gate electrode; a channel region, located below the silicon surface; a first recess, wherein a bottom surface of the first recess is lower than the silicon surface, a first insulating layer is formed in the first recess and covers the bottom surface of the first recess, and a top surface of the first insulating layer is lower than the silicon surface; a side insulating layer; a first conductive region, at least partially formed in the first recess and covering the first insulating layer, a bottom surface of the first conductive region contacts a top surface of the first insulating layer, the top surface of the first insulating layer insulates the bottom surface of the first conductive region from the silicon substrate, wherein a top surface and a portion of a side surface of the first conductive region contact a contact region, a top surface and a portion of a side surface of a conductive region of an adjacent transistor structure located beside the transistor structure contact the contact region, the contact region contacts a side surface of the side insulating layer, and the contact region comprises a metallic material; a second recess; and a second conductive region, at least partially formed in the second recess.

2. The transistor structure of claim 1, wherein: a second insulating layer is formed in the second recess and covers a bottom surface of the second recess; the second conductive region covers the second insulating layer.

3. The transistor structure of claim 2, wherein: the first conductive region has a first dopant concentration profile along a first extension direction, and the second conductive region has a second dopant concentration profile along a second extension direction, wherein the first extension direction and the second extension direction are parallel to a normal direction of the silicon surface, and the first dopant concentration profile and the second dopant concentration profile are not symmetric.

4. The transistor structure of claim 1, wherein: the first conductive region comprises a first upper portion, a second upper portion, and a lower portion, the first upper portion and the second upper portion contact the spacer layer, and the lower portion contacts the channel region and is located above the first insulating layer.

5. The transistor structure of claim 4, wherein further comprising: the contact region is at least partially formed in the first recess, wherein the second upper portion of the first conductive region contacts the contact region, and the side insulating layer separates the first upper portion and the lower portion of the first conductive region from the contact region.

6. The transistor structure of claim 1, wherein: the conductive region of the adjacent transistor structure is at least partially formed in the first recess, and the conductive region of the adjacent transistor structure is electrically isolated from the first conductive region.

7. The transistor structure of claim 1, wherein: at least a portion of the channel region is located below the gate electrode and the spacer layer, and a length of the channel region is not less than a sum of a length of the gate electrode and a length of the spacer layer.

8. The transistor structure of claim 1, wherein: a high-stress dielectric layer is formed above the first conductive region, the spacer layer, and the gate electrode.

9. A transistor structure, characterized by A transistor structure, comprising: a silicon substrate, comprising a silicon surface; a gate electrode, located above the silicon surface; a spacer layer, covering a sidewall of the gate electrode; a first recess, wherein a first insulating layer is formed in the first recess and covers a bottom surface of the first recess; a channel region, wherein at least a portion of the channel region is located under the gate and the spacer layer; and a first conductive region formed between the spacer layer and a side insulating layer, wherein a side surface portion of the first conductive region is covered by a first portion of the side insulating layer, and a side surface portion of a conductive region of a neighboring transistor structure located beside the transistor structure is covered by a second portion of the side insulating layer; wherein a top surface and a portion of a side surface of the first conductive region are in contact with a contact region, a top surface and a portion of a side surface of the conductive region of the neighboring transistor structure are in contact with the contact region, and the contact region is in contact with a side surface of the first portion of the side insulating layer and a side surface of the second portion of the side insulating layer.

10. The transistor structure of claim 9, wherein: The first conductive region is partially formed in the first recess, and the side insulating layer is partially formed in the first recess.

11. The transistor structure of claim 10, wherein: The first conductive region is located above the first insulating layer.

12. The transistor structure of claim 11, wherein: The first conductive region includes a first upper portion, a second upper portion, and a lower portion, the first upper portion and the second upper portion are in contact with the spacer layer, and the lower portion is in contact with the channel region and is located above the first insulating layer.

13. The transistor structure of claim 12, wherein Further comprising: the contact region is at least partially formed in the first recess, wherein the second upper portion of the first conductive region is in contact with the contact region, and the side insulating layer separates the first upper portion and the lower portion of the first conductive region from the contact region.

14. The transistor structure of claim 9, wherein: The first conductive region includes silicon, silicon carbide, or silicon germanium.

15. The transistor structure of claim 9, wherein Further comprising: a second conductive region partially formed in a second recess; a further side insulating layer partially formed in the second recess; and a further contact region partially formed in the second recess; wherein the second conductive region includes a first upper portion, a second upper portion, and a lower portion, the lower portion of the second conductive region is in contact with the channel region, the second upper portion of the second conductive region is in contact with the further contact region, and the further side insulating layer separates the first upper portion and the lower portion of the second conductive region from the further contact region.

16. The transistor structure of claim 9, wherein Further comprising: a further spacer layer, wherein the further spacer layer covers a further sidewall of the gate, and a length of the channel region is not less than a sum of a length of the gate, a length of the spacer layer, and a length of the further spacer layer.

17. The transistor structure of claim 16, wherein: The spacer layer and the further spacer layer are regrown spacer layers.

18. The transistor structure of claim 16, wherein Further comprising: a lightly doped drain region located under the spacer layer.

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