Totem-pole bridgeless power factor correction device, power supply and power supply system
By adjusting the transistors in parallel in the control module of the totem pole bridgeless power factor correction device, controlling their conduction sequence and delay, the problems of current spikes and common-mode interference caused by common-mode voltage switching in the totem pole PFC circuit are solved, achieving more stable current transmission and reducing leakage current spikes.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- INVENTCHIP TECH CO LTD
- Filing Date
- 2025-07-29
- Publication Date
- 2026-07-07
AI Technical Summary
The totem-pole PFC circuit suffers from current spikes and common-mode interference caused by the switching of common-mode voltage during the positive and negative half-cycles of the AC power supply, resulting in leakage current spikes in the chassis.
In the control module of the totem pole bridgeless power factor correction device, the first and second adjustment transistors are connected in parallel. By controlling their conduction sequence and delay, the common-mode switching speed is reduced and leakage current spikes are decreased.
It effectively reduces common-mode interference and leakage current spikes, and improves the performance of PFC circuits.
Smart Images
Figure CN224473214U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of integrated circuit technology, and in particular to a totem pole bridgeless power factor correction device, power supply and power supply system. Background Technology
[0002] The novel PFC circuit employing totem-pole (TTP) power factor correction can significantly reduce losses. However, totem-pole PFC experiences a large common-mode voltage switching during the positive and negative half-cycles of the AC power supply. The switching amplitude is equal to the PFC output voltage, typically 400V, and the switching point occurs when the AC input voltage crosses zero. This large common-mode voltage switching causes current spikes at the AC zero-crossing point, leading to common-mode interference in subsequent circuits and leakage current spikes in the chassis. Utility Model Content
[0003] In view of this, the present invention proposes a totem pole bridgeless power factor correction device. The device includes a power factor correction module and a control module. The power factor correction module is used to correct the power factor of the AC power input. The power factor correction module includes a first transistor, a second transistor, a third transistor, a fourth transistor, and an inductor. The control module includes a first input signal processing circuit, a second input signal processing circuit, a first driving component, a second driving component, a first adjustment transistor, and a second adjustment transistor.
[0004] In this configuration, the first transistor, the third transistor, the fourth transistor, and the second transistor are connected in sequence. One end of the inductor is connected to the connection point between the first transistor and the second transistor, and the other end of the inductor is connected to one end of the AC power supply. The other end of the AC power supply is connected to the connection point between the third transistor and the fourth transistor. The third transistor and the fourth transistor are used for AC rectification, and the first transistor and the second transistor are used for power factor correction.
[0005] The first output terminal and the second output terminal of the first input signal processing circuit are respectively connected to the input terminal of the first driving component and the gate of the first adjusting transistor, and the output terminal of the first driving component is connected to the gate of the third transistor.
[0006] The first and second output terminals of the second input signal processing circuit are respectively connected to the input terminal of the second driving component and the gate of the second adjusting transistor, and the output terminal of the second driving component is connected to the gate of the fourth transistor.
[0007] The first adjustment transistor and the second adjustment transistor are connected in parallel to the third transistor and the fourth transistor, respectively.
[0008] In one possible implementation, the first adjustment transistor is disposed on a separate base island and integrated with the control module in the same package, and the second adjustment transistor is fabricated on the same semiconductor substrate as the control module.
[0009] In one possible implementation, the first input signal processing circuit includes a level conversion circuit, and the second input signal processing circuit includes a logic processing circuit, wherein the control module includes:
[0010] The first signal input pin and the first drive input pin are both connected to the level conversion circuit. The level conversion circuit is used to convert the gate drive signal input to the first signal input pin and the first drive input pin, and output them to the gate of the first adjustment transistor and the input terminal of the first drive component, respectively.
[0011] The high-voltage output pin is connected to the drain of the first regulating transistor and the connection point between the first transistor and the third transistor.
[0012] The second signal input pin and the second drive input pin, and the gate control signals connected to the second signal input pin and the second drive input pin are respectively output to the gate of the second adjustment transistor and the input terminal of the second drive component through the logic processing circuit.
[0013] In one possible implementation, the first input signal processing circuit includes a level conversion circuit and a first delay unit, and the second input signal processing circuit includes a logic processing circuit and a second delay unit, wherein the control module includes:
[0014] The first signal input pin is connected to the level conversion circuit. The level conversion circuit is used to convert the level of the gate drive signal input to the first signal input pin and output it to the gate of the first adjustment transistor and the first delay circuit, respectively. The output terminal of the first delay circuit is connected to the input terminal of the first drive component.
[0015] The high-voltage output pin is connected to the drain of the first regulating transistor and the connection point between the first transistor and the third transistor.
[0016] The second signal input pin receives a gate control signal that is output through the logic processing circuit to the gate of the second adjustment transistor and the input of the second delay. The output of the second delay is connected to the input of the second driving component.
[0017] In one possible implementation, when the AC power supply crosses zero in the positive direction, the second adjusting transistor turns on first, and after a preset time, the fourth transistor turns on; or
[0018] When the AC power supply crosses zero in the negative direction, the first adjusting transistor turns on first, and after a preset time, the third transistor turns on.
[0019] In one possible implementation, the on-current of the first regulating transistor and the second regulating transistor is much smaller than the on-current of the third transistor and the fourth transistor.
[0020] The on-current of both the first and second regulating transistors is less than 50mA.
[0021] In one possible implementation, the connection point of the third transistor and the fourth transistor is connected to the first terminal of the adjusting capacitor, and the second terminal of the adjusting capacitor is grounded.
[0022] In one possible implementation, the control module is a high-voltage control module.
[0023] According to one aspect of the present invention, a power supply is provided, the power supply including the totem pole bridgeless power factor correction device.
[0024] According to one aspect of the present invention, a power supply system is provided, the power supply system including the aforementioned power source.
[0025] This embodiment of the invention sets up a first adjustment transistor and a second adjustment transistor in the control module of the totem pole bridgeless power factor correction device, and the first adjustment transistor and the second adjustment transistor are respectively connected in parallel to the third transistor and the fourth transistor. This can reduce the discharge speed of the connection point of the third transistor and the fourth transistor, thereby slowing down the common mode switching speed, reducing common mode interference, and thus reducing leakage current spikes.
[0026] Other features and aspects of the present invention will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description
[0027] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of the present invention together with the specification and serve to explain the principles of the present invention.
[0028] Figure 1 A schematic diagram of a bridgeless power factor correction device for totem poles according to an embodiment of the present invention is shown.
[0029] Figure 2 A schematic diagram of a bridgeless power factor correction device for totem poles according to an embodiment of the present invention is shown.
[0030] Figure 3 A schematic diagram of a bridgeless power factor correction device for totem poles according to an embodiment of the present invention is shown. Detailed Implementation
[0031] Various exemplary embodiments, features, and aspects of the present invention will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.
[0032] As used herein, the terms “comprising,” “including,” “having,” or variations thereof are open-ended and include one or more of the stated features, integrals, elements, steps, components, or functions, but do not exclude the presence or addition of one or more other features, integrals, elements, steps, components, functions, or groups thereof.
[0033] When an element is referred to as “connected,” “coupled,” “responding,” or a variation thereof relative to another element, it may be directly connected, coupled, or responding to another element, or there may be an intermediate element present.
[0034] Although the terms first, second, third, etc., may be used herein to describe various elements / operations, these elements / operations should not be limited by these terms. These terms are only used to distinguish one element / operation from another. Therefore, without departing from the teachings of this inventive concept, a first element / operation in some embodiments may be referred to as a second element / operation in other embodiments.
[0035] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.
[0036] Furthermore, to better illustrate this utility model, numerous specific details are provided in the following detailed embodiments. Those skilled in the art should understand that this utility model can be implemented even without certain specific details. In some instances, methods, means, components, and circuits well-known to those skilled in the art have not been described in detail, in order to highlight the main points of this utility model.
[0037] Please see Figure 1 , Figure 1 A schematic diagram of a bridgeless power factor correction device for totem poles according to an embodiment of the present invention is shown.
[0038] like Figure 1 As shown, the device includes a power factor correction module 10 and a control module 20. The power factor correction module 10 is used to correct the power factor of the AC input power supply. The power factor correction module 10 includes a first transistor Q1, a second transistor Q2, a third transistor Q3, a fourth transistor Q4, and an inductor L. The control module 20 includes a first input signal processing circuit 230, a second input signal processing circuit 240, a first drive component 210, a second drive component 220, a first adjustment transistor Qs1, and a second adjustment transistor Qs2.
[0039] In this configuration, the first transistor Q1, the third transistor Q3, the fourth transistor Q4, and the second transistor Q2 are connected in sequence. One end of the inductor L is connected to the connection point of the first transistor Q1 and the second transistor Q2, and the other end of the inductor L is connected to one end of the AC power supply. The other end of the AC power supply is connected to the connection point of the third transistor Q3 and the fourth transistor Q4. The third transistor Q3 and the fourth transistor Q4 are used for AC rectification, and the first transistor Q1 and the second transistor Q2 are used for power factor correction.
[0040] The first output terminal and the second output terminal of the first input signal processing circuit 230 are respectively connected to the input terminal of the first driving component and the gate of the first adjusting transistor, and the output terminal of the first driving component 210 is connected to the gate of the third transistor Q3.
[0041] The first output terminal and the second output terminal of the second input signal processing circuit 240 are respectively connected to the input terminal of the second driving component and the gate of the second adjustment transistor. The output terminal of the second driving component 220 is connected to the gate of the fourth transistor Q4. The first adjustment transistor Qs1 and the second adjustment transistor Qs2 are respectively connected in parallel on the third transistor Q3 and the fourth transistor Q4.
[0042] This embodiment of the invention sets up a first adjustment transistor Qs1 and a second adjustment transistor Qs2 in the control module 20 of the totem pole bridgeless power factor correction device. The first adjustment transistor Qs1 and the second adjustment transistor Qs2 are respectively connected in parallel to the third transistor Q3 and the fourth transistor Q4. This structure can reduce the discharge rate of the connection point of the third transistor Q3 and the fourth transistor Q4, thereby slowing down the common mode switching speed, reducing common mode interference, and thus reducing leakage current spikes.
[0043] In this embodiment of the present invention, the first adjusting transistor Qs1 and the second adjusting transistor Qs2 can be configured to turn on before the parallel transistors when the AC power supply crosses zero, thereby reducing the discharge rate at the connection point of the third transistor Q3 and the fourth transistor Q4.
[0044] In this embodiment of the invention, the common-mode voltage refers to a significant and rapid voltage change, typically 400V, between the power ground of the totem-pole PFC and the AC power ground before and after the AC zero-crossing. If the PFC controller is on the PFC power ground at this time, a 400V common-mode voltage jump will be observed on the AC detection signal (usually a differential signal). For the circuitry following the ACDC, a voltage jump will be observed in the PFC stage as a whole. Common-mode interference refers to interference signals acting simultaneously on two signal lines, causing interference to subsequent processing circuits even if the relative voltages of the two signal lines do not change. Leakage current typically refers to the leakage current from the ACDC circuit to the chassis; due to the common-mode jump, a current spike will appear at the moment of the jump.
[0045] The present invention does not limit the specific implementation of the first input signal processing circuit 230, the second input signal processing circuit 240, the first driving component 210, and the second driving component 220. Those skilled in the art can implement them by adopting relevant circuit schemes according to actual conditions and needs. Of course, the control module may also include corresponding driving components for the first transistor Q1 and the second transistor Q2, which will not be elaborated here. For example, the first driving component 210 and the second driving component 220 may include buffer amplifiers.
[0046] This embodiment of the invention does not limit the specific types of the first adjustment transistor Qs1 and the second adjustment transistor Qs2. For example, they can be metal-oxide-semiconductor field-effect transistors (MOSFETs) or insulated-gate bipolar transistors (IGBTs). The transistors can be based on silicon carbide (SiC) or gallium nitride (GaN) to improve performance.
[0047] For example, the first adjusting transistor Qs1 and the second adjusting transistor Qs2 can be low-current transistors. In one possible implementation, the on-state current of both the first adjusting transistor Qs1 and the second adjusting transistor Qs2 can be less than 50mA. Preferably, the on-state current of the first adjusting transistor Qs1 and the second adjusting transistor Qs2 can be less than 10mA. Thus, this embodiment of the invention, through the use of low-current adjusting transistors, can further reduce the voltage drop speed at the midpoint of the slow transistor (the connection point of the third transistor Q3 and the fourth transistor Q4) when AC crosses zero, and can more effectively reduce the common-mode switching speed, reduce common-mode interference and leakage current spikes.
[0048] This utility model embodiment does not limit the specific method for determining whether the AC power supply has crossed zero, positively crossed zero, or negatively crossed zero. Those skilled in the art can use relevant technologies to implement it according to actual conditions and needs.
[0049] In one example, the third transistor Q3 and the fourth transistor Q4 can both be metal-oxide-semiconductor field-effect transistors (MOSFETs), while the first transistor Q1 and the second transistor Q2 can be MOSFETs based on silicon carbide (SiC) or gallium nitride (GaN) to improve performance.
[0050] For example, such as Figure 2 As shown, the first transistor Q1, the second transistor Q2, the third transistor Q3, and the fourth transistor Q4 can all be NMOS transistors. The first terminal of the inductor L is electrically connected to the first terminal of the AC power supply (e.g., the positive terminal). The second terminal of the inductor L is electrically connected to the source of the first transistor Q1 and the drain of the second transistor Q2. The drain of the first transistor Q1 is electrically connected to the drain of the third transistor Q3. The source of the third transistor Q3 is electrically connected to the drain of the fourth transistor Q4 and the second terminal of the AC power supply (e.g., the negative terminal). The source of the second transistor Q2 is electrically connected to the source of the fourth transistor Q4.
[0051] For example, such as Figure 1 , Figure 2As shown, the first adjustment transistor Qs1 and the second adjustment transistor Qs2 are connected in parallel with the third transistor Q3 and the fourth transistor Q4, respectively. The drain of the first adjustment transistor Qs1 is connected to the drain of the third transistor Q3, and the source of the first adjustment transistor Qs1 is connected to the source of the third transistor Q3. The drain of the second adjustment transistor Qs2 is connected to the drain of the fourth transistor Q4, and the source of the second adjustment transistor Qs2 is connected to the source of the fourth transistor Q4.
[0052] For example, such as Figure 1 , Figure 2 As shown, the connection point of the third transistor Q3 and the fourth transistor Q4 is the connection point of the source of the third transistor Q3 and the drain of the fourth transistor Q4, which is also the midpoint of the PFC slow transistor.
[0053] Of course, the PFC circuit may also include other components, and this embodiment of the present invention does not limit this. Those skilled in the art can implement it by referring to relevant technologies according to actual conditions and needs.
[0054] In one possible implementation, the control module 20 can be a high-voltage driver module (HVIC). This embodiment of the invention does not limit the specific process of integrating the first regulating transistor Qs1 and the second regulating transistor Qs2 into the control module 20 to obtain the high-voltage driver module HVIC. For example, this embodiment of the invention can use high-voltage processes such as BCD / SOI, and achieve high-voltage withstand capability above 400V through dielectric isolation (such as deep trench isolation DTI, buried oxide layer).
[0055] This embodiment of the invention integrates the first adjustment transistor Qs1, the second adjustment transistor Qs2, the first input signal processing circuit 230, the second input signal processing circuit 240, and various driving components, eliminating the need for additional power devices and significantly reducing costs.
[0056] In one possible implementation, the first adjustment transistor Qs1 is disposed on a separate substrate and integrated with the control module 20 in the same package, while the second adjustment transistor Qs2 is fabricated on the same semiconductor substrate as the control module 20. In this embodiment, the source of the first adjustment transistor Qs1 is connected to the junction point (midpoint of the slow transistor) of the third transistor Q3 and the fourth transistor Q4. Since the first adjustment transistor Qs1 cannot share a substrate with the control module 20, this embodiment places it on a separate substrate, using physical isolation (such as deep trench isolation DTI, insulating layers, etc.) to separate different functional areas (such as high-voltage devices and low-voltage control circuits) into independent regions, avoiding electrical signal crosstalk or thermal coupling problems. The second adjustment transistor Qs2 can share a substrate with the control module 20, thereby reducing costs.
[0057] The present invention does not limit the specific implementation of the first input signal processing circuit 230 and the second input signal processing circuit 240. Those skilled in the art can implement them according to the actual situation and needs using relevant technologies. The following is an exemplary description.
[0058] Please see Figure 2 , Figure 2 A schematic diagram of a bridgeless power factor correction device for totem poles according to an embodiment of the present invention is shown.
[0059] In one possible implementation, the first input signal processing circuit 230 includes a level conversion circuit 2310, and the second input signal processing circuit 240 includes a logic processing circuit 2410, such as... Figure 2 As shown, the control module 20 includes:
[0060] The first signal input pin HI2 and the first drive input pin HI1 are both connected to the level conversion circuit 2310. The level conversion circuit 2310 is used to convert the level of the gate drive signal input to the first signal input pin HI2 and the first drive input pin HI1, and output them to the gate of the first adjustment transistor Qs1 and the input terminal of the first drive component 210, respectively. This embodiment of the invention does not limit the specific implementation of the level conversion circuit 2310; those skilled in the art can implement it according to actual conditions and needs, referring to relevant technologies. For example, the voltage of the gate drive signal input to the first signal input pin HI2 and the first drive input pin HI1 can be less than the power supply voltage VDD (e.g., 20V). This embodiment of the invention can use the level conversion circuit 2310 to convert the gate drive signal input to the first signal input pin HI2 and the first drive input pin HI1 from 0 to 20V to 0 to 400V to meet the high-side drive voltage requirements.
[0061] The high-voltage output pin HV is connected to the drain of the first regulating transistor Qs1, and the connection point between the first transistor Q1 and the third transistor Q3 (e.g., Figure 2 As shown, the connection point is the drain of the first transistor Q1 and the drain of the third transistor Q3; for example, the voltage at the connection point between the high voltage output pin HV and the drain of the first regulating transistor Qs1, and between the first transistor Q1 and the third transistor Q3 is 400V.
[0062] The gate control signals connected to the second signal input pin LI2 and the second drive input pin LI1 are respectively output to the gate of the second adjustment transistor Qs2 and the input terminal of the second drive component 220 through the logic processing circuit 2410. This embodiment of the invention does not limit the specific implementation of the logic processing circuit 2410. The logic processing circuit 2410 can be composed of AND gates, OR gates, NOT gates, etc., and those skilled in the art can configure it according to actual conditions and needs.
[0063] Of course, the first input signal processing circuit 230 may also include a corresponding logic processing circuit. This embodiment of the present invention does not limit this. For example, the logic processing circuit in the first input signal processing circuit 230 may perform operations such as signal splitting (dividing a signal into two or more paths).
[0064] Through the above implementation, this utility model embodiment only requires the addition of a first signal input pin HI2. The first signal input pin HI2 receives the gate drive signals of the first adjustment transistor Qs1 and the second adjustment transistor Qs2. Of course, the external controller can adaptively adjust the gate drive signals input to the first drive input pin HI1 and the second drive input pin HI1 and the delay duration of the first signal input pin HI2, so as to realize that when the AC power supply crosses zero in the positive direction, the second adjustment transistor is turned on first, and after a preset time, the fourth transistor is turned on; or when the AC power supply crosses zero in the negative direction, the first adjustment transistor is turned on first, and after a preset time, the third transistor is turned on.
[0065] Please see Figure 3 , Figure 3 A schematic diagram of a bridgeless power factor correction device for totem poles according to an embodiment of the present invention is shown.
[0066] In one possible implementation, the first input signal processing circuit 230 includes a level conversion circuit 2310 and a first delay unit 2320, and the second input signal processing circuit 240 includes a logic processing circuit 2410 and a second delay unit 2420, such as... Figure 3 As shown, the control module 20 includes:
[0067] The first signal input pin HI2 is connected to the level conversion circuit 2310. The level conversion circuit 2310 is used to convert the level of the gate drive signal input to the first signal input pin HI2 and output it to the gate of the first adjustment transistor Qs1 and the first delay circuit 2320 respectively. The output terminal of the first delay circuit 2320 is connected to the input terminal of the first drive component 210.
[0068] The high-voltage output pin HV is connected to the drain of the first regulating transistor Qs1 and the connection point of the first transistor Q1 and the third transistor Q3; for example, the voltage between the high-voltage output pin HV and the connection point of the first regulating transistor Qs1 and the third transistor Q3 is 400V.
[0069] The second signal input pin LI2, the gate control signal connected to the second signal input pin LI2 is output to the gate of the second adjustment transistor and the input terminal of the second delay unit 2420 respectively through the logic processing circuit 2410, and the output terminal of the second delay unit 2420 is connected to the input terminal of the second driving component 220.
[0070] For example, the delay duration (preset duration) of the first delay unit 2320 and the second delay unit 2420 can be set according to actual conditions and needs, and this utility model embodiment does not limit this.
[0071] By setting a first delay unit 2320 and a second delay unit 2420, this embodiment of the utility model can reduce the use of external pins and maintain the original control module packaging.
[0072] In this embodiment of the invention, the control module 20 and the power factor correction module 10 can be detachable modules. When it is necessary to replace the control module 20 or the power factor correction module 10, this embodiment of the invention can easily replace any module. For example, the connection between the output terminal of the first driving component 210 and the gate of the third transistor Q3, the connection between the output terminal of the second driving component 220 and the gate of the fourth transistor Q4, the connection between the high voltage output pin HV and the drain of the first adjusting transistor Qs1, the connection between the first transistor Q1 and the third transistor Q3, and the connection between the first adjusting transistor Qs1 and the second adjusting transistor Qs2 and the power factor correction module 10 can be disassembled as needed to realize module replacement and maintenance.
[0073] Of course, the control module 20 may also have other pins. For example, the first drive component 210 may include a drive power pin (such as HB), which can be connected to the upper transistor drive power supply. For example, a bootstrap power supply method can be used. For example, the first drive component 210 may also include a ground pin, which can be connected to the source of the first transistor Q1; the second drive component 220 may include a lower transistor drive pin, which can be connected to the lower transistor drive power supply VCC.
[0074] In one possible implementation, when the AC power supply crosses zero in the positive direction, the second adjusting transistor Qs2 is turned on for a preset time, and then the fourth transistor Q4 is turned on (when the AC power supply crosses zero in the positive direction, the second adjusting transistor turns on first, and after a preset time, the fourth transistor turns on); or
[0075] When the AC power supply crosses zero in the negative direction, the first adjusting transistor Qs1 is turned on for a preset time, and then the third transistor Q3 is turned on (when the AC power supply crosses zero in the negative direction, the first adjusting transistor is turned on first, and then the third transistor is turned on after a preset time).
[0076] The present invention does not limit the specific size of the preset duration. Those skilled in the art can set it according to actual conditions and needs. For example, the preset duration can be set to be less than the zero-crossing dead zone duration.
[0077] In one possible implementation, the on-current of the first regulating transistor Qs1 and the second regulating transistor Qs2 is much smaller than the on-current of the third transistor and the fourth transistor, wherein the on-current of the first regulating transistor Qs1 and the second regulating transistor Qs2 can both be less than 50mA.
[0078] In one possible implementation, such as Figure 2 and Figure 3As shown, in this embodiment of the invention, an adjustment capacitor C1 can be connected in parallel at the midpoint of the slow transistor (the connection point of the third transistor Q3 and the fourth transistor Q4) to further slow down the common-mode voltage switching speed. For example, the connection point of the third transistor Q3 and the fourth transistor Q4 is connected to the first end of the adjustment capacitor C1, and the second end of the adjustment capacitor C1 is grounded.
[0079] Of course, the second terminal of the adjusting capacitor C1 can also be connected to the PFC output bus.
[0080] For example, in one possible implementation, the present invention may also provide adjustment capacitors separately between the source and drain of the third transistor Q3 and / or between the source and drain of the fourth transistor Q4 to further slow down the common-mode voltage switching speed.
[0081] This embodiment of the invention does not limit the type or size of the adjusting capacitor; those skilled in the art can set it according to actual conditions and needs.
[0082] This embodiment of the invention does not limit the specific implementation of the control module 20. Those skilled in the art can implement it using related technologies. For example, the control module 20 can be a PFC controller, which may include a processing component and a signal generation component. The processing component controls the control signal generation component to generate gate control signals to control the conduction state of each transistor. Exemplarily, the processing component includes, but is not limited to, a separate processor, discrete components, or a combination of a processor and discrete components. The processor may include a controller in an electronic device with instruction execution capabilities. The processor can be implemented in any suitable manner, for example, by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components. Within the processor, the executable instructions can be executed through hardware circuits such as logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers.
[0083] The control module 20 is used for:
[0084] Before the AC power supply crosses zero in the positive direction, the first transistor Q1, the second transistor Q2, the third transistor Q3, the fourth transistor Q4, the first adjustment transistor Qs1, and the second adjustment transistor Qs2 are all in the off state. At this time, the connection point (i.e., the midpoint of the slow transistor) of the third transistor Q3 and the fourth transistor Q4 is in the floating state.
[0085] When the AC power supply crosses zero in the positive direction, the second adjusting transistor Qs2 is turned on. After a preset delay, the fourth transistor Q4 is turned on, and the power factor correction module 10 enters the positive half-cycle operating state. In this way, the second adjusting transistor Qs2 slowly completes the midpoint voltage switching of the slow transistor. Therefore, when the fourth transistor Q4 is turned on, there will be no rapid common-mode switching with a large voltage, similar to the effect of zero-voltage turn-on or low-voltage turn-on. For example, the second adjusting transistor Qs2 can be a low-current transistor. By using the second adjusting transistor Qs2, the voltage pull-down speed at the midpoint of the slow transistor can be reduced, effectively reducing the common-mode switching speed, common-mode interference, and leakage current spikes.
[0086] Before the AC power supply crosses zero in the negative direction, the first transistor Q1, the second transistor Q2, the third transistor Q3, the fourth transistor Q4, the first adjustment transistor Qs1, and the second adjustment transistor Qs2 are all in the off state. At this time, the connection point (i.e., the midpoint of the slow transistor) of the third transistor Q3 and the fourth transistor Q4 is in the floating state.
[0087] When the AC power supply crosses zero in the negative direction, the first adjusting transistor Qs1 is turned on. After a preset delay, the third transistor Q3 is turned on, and the power factor correction module 10 enters the negative half-cycle operating state. In this way, the first adjusting transistor Qs1 slowly completes the midpoint voltage switching of the slow transistor. Therefore, when the third transistor Q3 is turned on, there will be no rapid common-mode switching with a large voltage, similar to the effect of zero-voltage turn-on or low-voltage turn-on. For example, the first adjusting transistor Qs1 can be a low-current transistor. By using the first adjusting transistor Qs1, the voltage pull-down speed at the midpoint of the slow transistor can be reduced, effectively reducing the common-mode switching speed, common-mode interference, and leakage current spikes.
[0088] In one possible implementation, the control module 20 is further configured to:
[0089] When the power factor correction module 10 enters the positive half-cycle operating state, it controls the second adjustment transistor Qs2 to turn off;
[0090] When the power factor correction module 10 enters the negative half-cycle operating state, it controls the first adjustment transistor Qs1 to turn off.
[0091] In this embodiment of the invention, when the power factor correction module 10 enters the positive half-cycle operating state, the second adjustment transistor Qs2 is controlled to disconnect; when the power factor correction module 10 enters the negative half-cycle operating state, the first adjustment transistor Qs1 is controlled to disconnect, thereby reducing power consumption and computing resources.
[0092] Of course, when the power factor correction module 10 enters the positive half-cycle operating state, the second adjustment transistor Qs2 can also be in the on state; when the power factor correction module 10 enters the negative half-cycle operating state, the first adjustment transistor Qs1 can also be in the on state, that is, the second adjustment transistor Qs2 can be turned off synchronously with the fourth transistor Q4, and the first adjustment transistor Qs1 can be turned off synchronously with the third transistor Q3.
[0093] The totem pole bridgeless power factor correction device of this utility model has a slower zero-crossing switching speed and less common-mode interference when the AC crosses zero, which can reduce the leakage current spike of the chassis and improve the working performance of PFC.
[0094] According to one aspect of the present invention, a power supply is provided, the power supply including the totem pole bridgeless power factor correction device.
[0095] According to one aspect of the present invention, a power supply system is provided, the power supply system including the aforementioned power source.
[0096] The various embodiments of the present invention have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical applications, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.
Claims
1. A bridgeless power factor correction device for totem poles, characterized in that, The device includes a power factor correction module and a control module. The power factor correction module is used to correct the power factor of the AC power input. The power factor correction module includes a first transistor, a second transistor, a third transistor, a fourth transistor, and an inductor. The control module includes a first input signal processing circuit, a second input signal processing circuit, a first driving component, a second driving component, a first adjustment transistor, and a second adjustment transistor. In this configuration, the first transistor, the third transistor, the fourth transistor, and the second transistor are connected in sequence. One end of the inductor is connected to the connection point between the first transistor and the second transistor, and the other end of the inductor is connected to one end of the AC power supply. The other end of the AC power supply is connected to the connection point between the third transistor and the fourth transistor. The third transistor and the fourth transistor are used for AC rectification, and the first transistor and the second transistor are used for power factor correction. The first output terminal and the second output terminal of the first input signal processing circuit are respectively connected to the input terminal of the first driving component and the gate of the first adjusting transistor, and the output terminal of the first driving component is connected to the gate of the third transistor. The first and second output terminals of the second input signal processing circuit are respectively connected to the input terminal of the second driving component and the gate of the second adjusting transistor, and the output terminal of the second driving component is connected to the gate of the fourth transistor. The first adjustment transistor and the second adjustment transistor are connected in parallel to the third transistor and the fourth transistor, respectively.
2. The totem pole bridgeless power factor correction device according to claim 1, characterized in that, The first adjustment transistor is disposed on a separate base island and integrated with the control module in the same package, and the second adjustment transistor is fabricated on the same semiconductor substrate as the control module.
3. The totem pole bridgeless power factor correction device according to claim 1, characterized in that, The first input signal processing circuit includes a level conversion circuit, the second input signal processing circuit includes a logic processing circuit, and the control module includes: The first signal input pin and the first drive input pin are both connected to the level conversion circuit. The level conversion circuit is used to convert the gate drive signal input to the first signal input pin and the first drive input pin, and output them to the gate of the first adjustment transistor and the input terminal of the first drive component, respectively. The high-voltage output pin is connected to the drain of the first regulating transistor and the connection point between the first transistor and the third transistor. The second signal input pin and the second drive input pin, and the gate control signals connected to the second signal input pin and the second drive input pin are respectively output to the gate of the second adjustment transistor and the input terminal of the second drive component through the logic processing circuit.
4. The totem pole bridgeless power factor correction device according to claim 1, characterized in that, The first input signal processing circuit includes a level conversion circuit and a first delay unit; the second input signal processing circuit includes a logic processing circuit and a second delay unit; wherein, the control module includes: The first signal input pin is connected to the level conversion circuit. The level conversion circuit is used to convert the level of the gate drive signal input to the first signal input pin and output it to the gate of the first adjustment transistor and the first delay circuit, respectively. The output terminal of the first delay circuit is connected to the input terminal of the first drive component. The high-voltage output pin is connected to the drain of the first regulating transistor and the connection point between the first transistor and the third transistor. The second signal input pin receives a gate control signal that is output through the logic processing circuit to the gate of the second adjustment transistor and the input of the second delay. The output of the second delay is connected to the input of the second driving component.
5. The totem pole bridgeless power factor correction device according to claim 1, characterized in that, When the AC power supply crosses zero in the positive direction, the second adjusting transistor turns on first, and after a preset time, the fourth transistor turns on; or When the AC power supply crosses zero in the negative direction, the first adjusting transistor turns on first, and after a preset time, the third transistor turns on.
6. The totem pole bridgeless power factor correction device according to any one of claims 1-4, characterized in that, The on-state currents of the first and second regulating transistors are much smaller than those of the third and fourth transistors. The on-current of both the first and second regulating transistors is less than 50mA.
7. The totem pole bridgeless power factor correction device according to claim 1, characterized in that, The connection point of the third transistor and the fourth transistor is connected to the first terminal of the adjusting capacitor, and the second terminal of the adjusting capacitor is grounded.
8. The totem pole bridgeless power factor correction device according to claim 1, characterized in that, The control module is a high-voltage control module.
9. A power supply, characterized in that, The power supply includes the totem pole bridgeless power factor correction device as described in any one of claims 1-8.
10. A power supply system, characterized in that, The power supply system includes the power source as described in claim 9.