A variable doping planar gate silicon carbide VDMOS device and its preparation process

Abstract

The present invention relates to the field of MOS semiconductor technology, and discloses a variable-doped planar gate silicon carbide VDMOS device and a preparation process. The device comprises a plurality of MOS cells arranged in parallel, wherein a single MOS cell comprises a drain, a semiconductor epitaxial layer, a source, and a gate; the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P+ layer, an N well layer, and a P well layer; a lightly doped N layer is provided in the middle of the N drift layer of the single MOS cell; and a laterally symmetric P-layer is provided inside the single MOS cell and on the left and right sides of the N drift layer, wherein the corresponding side cross-sectional profiles of the laterally symmetric P-layers on both sides are arc-shaped. By arranging a lightly doped N layer in the middle of the N drift layer and introducing arc-shaped laterally symmetric P-layers on both sides, the present invention optimizes the electric field distribution of the device, reduces local electric field concentration, and significantly improves the breakdown voltage. Moreover, the contact between the laterally symmetric P-layer and the N substrate layer enhances the charge balancing capability and reduces leakage current.

Description

Technical Field

[0001] The present invention relates to the field of MOS semiconductor technology, and in particular to a variable-doped planar gate silicon carbide VDMOS device and a preparation process thereof. Background Art

[0002] Silicon carbide (SiC) VDMOS devices have attracted much attention in the field of power electronics due to their high breakdown voltage, low on-resistance and excellent high-temperature performance.

[0003] An existing patent discloses a highly reliable planar gate silicon carbide VDMOS with variable doping and its fabrication method (publication number CN119300419A). Metal is deposited on the underside of a silicon carbide substrate to form a drain metal layer; epitaxial growth is performed on the side of the silicon carbide substrate to form a drift layer; a barrier layer is formed, followed by etching and ion implantation to form a first N-type region, a second N-type region, and a P-type well region. The technology disclosed in this patent suffers from the problem of localized electric field concentration in its planar gate structure, which reduces breakdown voltage and causes reliability issues. Furthermore, the drift region doping concentration must strike a balance between on-resistance and breakdown voltage, a balance that existing technologies struggle to achieve. High concentrations of N-type doping can easily induce parasitic bipolar conduction, leading to latch-up and limiting device reliability. Summary of the Invention

[0004] In order to solve the existing technical problems, the present invention provides a variable doping planar gate silicon carbide VDMOS device and a preparation process, which solves the problems in the above-mentioned background technology.

[0005] To solve the above technical problems, according to one aspect of the present invention, more specifically, a variable doping planar gate silicon carbide VDMOS device is provided, comprising a plurality of mutually parallel MOS cells, wherein a single MOS cell comprises a drain, a semiconductor epitaxial layer, a source, and a gate; the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P+ layer, an N well layer, and a P well layer; a lightly doped N layer is provided in the middle of the N drift layer of a single MOS cell;

[0006] Laterally symmetrical P-layers are provided inside a single MOS cell and on the left and right sides of the N drift layer. The corresponding side cross-sectional profiles of the laterally symmetrical P-layers on both sides are arc-shaped. The bottom ends of the laterally symmetrical P-layers are in contact with the N substrate layer.

[0007] Furthermore, a heavily doped N layer is formed at the inner bottom of the lightly doped N layer by ion implantation, and the bottom of the heavily doped N layer is in contact with the N substrate layer.

[0008] Furthermore, a rectangular P-layer is formed in the middle area of the heavily doped N layer by ion implantation, and the bottom end of the rectangular P-layer is in contact with the N substrate layer.

[0009] Furthermore, a heavily doped N-type half layer is formed at the inner bottom of the lightly doped N layer by ion implantation, and the bottom of the heavily doped N-type half layer contacts the N substrate layer; the cross-sectional profile of the heavily doped N-type half layer is semi-elliptical.

[0010] Furthermore, a lightly doped N-type half layer is formed in the middle region of the heavily doped N-type half layer by ion implantation, and the bottom end of the lightly doped N-type half layer is in contact with the N substrate layer.

[0011] Furthermore, a semicircular P-layer is formed in the middle area of the heavily doped N-type half layer by ion implantation, and the bottom end of the semicircular P-layer is in contact with the N substrate layer.

[0012] A process for preparing a planar gate silicon carbide VDMOS device with variable doping, comprising:

[0013] S1. epitaxially growing an N substrate layer, an N drift layer, a P+ layer, an N well layer, and a P well layer in sequence on the semiconductor epitaxial layer by chemical vapor deposition;

[0014] S2, forming a lightly doped N layer in the middle region of the N drift layer by low-dose nitrogen ion implantation, followed by high-temperature annealing to activate the doped ions;

[0015] S3. Use photolithography to define arc-shaped mask windows on both sides of the N drift layer, and form a laterally symmetrical P-layer by boron ion implantation to ensure that its bottom end contacts the N substrate layer. After the ion implantation, perform an annealing process to repair lattice damage.

[0016] S4, forming a heavily doped N layer in the bottom region of the lightly doped N layer by high-dose nitrogen ion implantation, and performing high-temperature annealing after the ion implantation to activate the impurities;

[0017] S5. In the middle area of the heavily doped N layer, boron ions are implanted using a rectangular mask window to form a rectangular P-layer, and then annealed.

[0018] S6. Using a semi-elliptical mask design, high-concentration nitrogen ion implantation is performed at the bottom of the lightly doped N-type layer to form a heavily doped N-type half layer with a semi-elliptical cross-section.

[0019] S7, implanting low-dose nitrogen ions into the middle region of the heavily doped N-type half layer to form a lightly doped N-type half layer, and performing annealing.

[0020] S8. Using a semicircular mask, perform boron ion implantation in the middle region of the heavily doped N-type half layer to form a semicircular P-layer, and after annealing, ensure that it is in contact with the N substrate layer;

[0021] S9. Deposit and pattern the metal layers in sequence through photolithography or sputtering process to form ohmic contacts and Schottky contacts of the drain, source and gate.

[0022] The present invention provides a process for preparing a planar gate silicon carbide VDMOS device with variable doping. Compared with the prior art, the present method has the following effects:

[0023] 1. The present invention arranges a lightly doped N layer in the middle of the N drift layer and introduces arc-shaped laterally symmetric P-layers on both sides. This optimizes the electric field distribution of the device, reduces local electric field concentration, and significantly improves the breakdown voltage. In addition, the contact between the laterally symmetric P-layer and the N substrate layer enhances the charge balance capability and reduces leakage current.

[0024] 2. The present invention further reduces the on-resistance by introducing a heavily doped N layer at the bottom of the lightly doped N layer, and at the same time improves the carrier injection efficiency through high-concentration doping, thereby improving the switching performance of the device.

[0025] 3. The present invention achieves local charge compensation by implanting a rectangular P-layer in a heavily doped N-layer, suppresses the parasitic bipolar effect, enhances the anti-latch capability of the device, and maintains low on-resistance.

[0026] 4. The present invention optimizes the lateral distribution of carriers, reduces edge electric field spikes, and improves the dynamic response speed and reliability of the device by adopting a heavily doped N-type half layer with a semi-elliptical cross-section. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 Schematic diagram of the structure of implementation 1 of the present invention;

[0028] Figure 2 Schematic diagram of the structure of implementation 2 of the present invention;

[0029] Figure 3 Schematic diagram of the structure of implementation 3 of the present invention;

[0030] Figure 4 It is a structural diagram of implementation 4 of the present invention;

[0031] Figure 5 Schematic diagram of the structure of implementation 5 of the present invention;

[0032] Figure 6 Schematic diagram of the structure of implementation 6 in the present invention.

[0033] In the figure: 1. drain; 2. N substrate layer; 3. N drift layer; 4. source; 5. gate; 6. lightly doped N layer; 7. laterally symmetrical P-layer; 8. P+ layer; 9. N well layer; 10. P well layer; 11. heavily doped N layer; 12. rectangular P-layer; 13. heavily doped N-type half layer; 14. lightly doped N-type half layer; 15. semicircular P-layer; 91. heavily doped N well layer; 92. lightly doped N well layer. DETAILED DESCRIPTION

[0034] In order to make the technical solution of the present invention clearer, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0035] like Figure 1-6 As shown, according to one aspect of the present invention, a process for preparing a planar gate silicon carbide VDMOS device with variable doping is provided, comprising:

[0036] Step 1: Epitaxially grow an N substrate layer 2, an N drift layer 3, a P+ layer 8, an N well layer 9, and a P well layer 10 in sequence on the semiconductor epitaxial layer by chemical vapor deposition; epitaxially grow an N substrate layer 2, an N drift layer 3, a P+ layer 8, an N well layer 9, and a P well layer 10 in sequence by chemical vapor deposition to construct the basic epitaxial structure of the device, ensuring that the thickness and doping concentration of each functional layer are controllable.

[0037] Step 2: Low-dose nitrogen ion implantation (energy range: 50-200 keV, dose: ) to form a lightly doped N layer 6, followed by high-temperature annealing (1600-1800°C, in an inert gas environment) to activate the doped ions; a lightly doped N layer 6 is formed in the middle region of the N drift layer 3 (low-dose nitrogen ion implantation + high-temperature annealing) to reduce the drift region resistance and optimize the conduction characteristics.

[0038] Step 3: Use photolithography to define arc-shaped mask windows on both sides of the N drift layer 3, and implant boron ions (energy: 100-300 keV, dose: ) to form a laterally symmetrical P-layer 7 to ensure that its bottom end is in contact with the N substrate layer, and an annealing process (1500-1700°C) is performed after ion implantation to repair lattice damage; boron ions are implanted through arc-shaped mask windows on both sides of the N drift layer 3 to form a laterally symmetrical P-layer 7, which evenly disperses the electric field and avoids local electric field concentration, while at the same time contacting the N substrate layer to enhance the charge balancing ability.

[0039] Step 4: In the bottom region of the lightly doped N layer 6, high-dose nitrogen ion implantation (energy: 200-400 keV, dose: ) to form a heavily doped N layer 11, and after ion implantation, high-temperature annealing (1700-1900°C) is performed to activate the impurities; high-dose nitrogen ions are implanted at the bottom of the lightly doped N layer 6 to form a heavily doped N layer 11, thereby increasing the carrier concentration, reducing the on-resistance, and activating the impurities through high-temperature annealing.

[0040] Step 5: In the middle area of the heavily doped N layer 11, a rectangular mask window is used to perform boron ion implantation (energy: 50-150 keV, dose: ) to form a rectangular P-layer 12 and anneal it (1600-1800°C); implant the rectangular P-layer 12 into the middle of the heavily doped N-layer 11 to neutralize excess electrons, suppress the parasitic bipolar effect, and improve the anti-latch capability.

[0041] Step 6: High-concentration nitrogen ion implantation (energy: 300-500 keV, dose: ), forming a heavily doped N-type half layer 13 with a semi-elliptical cross-section; a semi-elliptical mask design is used to form a heavily doped N-type half layer 13 at the bottom of the lightly doped N layer 6, thereby optimizing the lateral electric field distribution, reducing carrier scattering, and improving dynamic response.

[0042] Step 7: Low-dose nitrogen ion implantation (energy: 100-250 keV, dose: ), forming a lightly doped N-type half layer 14, and performing annealing treatment; implanting the lightly doped N-type half layer 14 into the heavily doped N-type half layer 13 to form a concentration gradient, optimize the carrier migration path, and reduce conduction loss.

[0043] Step 8: Use a semicircular mask to implant boron ions into the middle area of the heavily doped N-type half layer 13 (energy: 80-180 keV, dose: , forming a semicircular P-layer 15, and ensuring that it is in contact with the N substrate layer 2 after annealing; implanting the semicircular P-layer 15 in the middle of the heavily doped N-type half layer 13 to enhance the charge compensation effect and balance the trade-off relationship between breakdown voltage and on-resistance.

[0044] Step 9: Deposit and pattern metal layers in sequence through photolithography or sputtering process to form ohmic contacts and Schottky contacts of the drain 1 , source 4 and gate 5 .

[0045] Example 1

[0046] like Figure 1As shown, a variable-doped planar-gate silicon carbide VDMOS device comprises several juxtaposed MOS cells. Each MOS cell includes a drain 1, a semiconductor epitaxial layer, a source 4, and a gate 5. The semiconductor epitaxial layer includes an N substrate layer 2, an N drift layer 3, a P+ layer 8, an N well layer 9, and a P well layer 10. The device is characterized by a lightly doped N layer 6 positioned in the center of the N drift layer 3 of each MOS cell. Laterally symmetric P-layers 7 are positioned within the MOS cell, on either side of the N drift layer 3. The corresponding side cross-sectional profiles of the two lateral symmetric P-layers 7 are arc-shaped. The bottom ends of the lateral symmetric P-layers 7 contact the N substrate layer 2. The lightly doped N layer 6 is formed by low-dose nitrogen ion implantation to reduce drift region resistance. The arc-shaped P-layer 7 is implanted with boron ions through a photolithographically defined mask window. Its symmetrical structure evenly disperses the electric field. Combined with high-temperature annealing to repair lattice defects, it ensures effective activation of the doped ions.

[0047] By placing a lightly doped N layer 6 in the center of the N-drift layer and introducing arc-shaped, laterally symmetric P-layers 7 on either side, the device's electric field distribution is optimized, local electric field concentration is reduced, and the breakdown voltage is significantly increased. Furthermore, the contact between the laterally symmetric P-layer 7 and the N substrate layer 2 enhances charge balance and reduces leakage current.

[0048] Example 2

[0049] like Figure 2 As shown, a heavily doped N layer 11 is formed at the bottom of the lightly doped N layer 6 by ion implantation. The bottom of the heavily doped N layer 11 contacts the N substrate layer 2. High-dose nitrogen ion implantation is used to form the heavily doped N layer 11 at the bottom of the lightly doped N layer. The high-dose implantation increases the carrier concentration, and high-temperature annealing (1700-1900°C) fully activates the impurities, forming a low-resistance channel and reducing conduction losses.

[0050] The heavily doped N layer 11 is introduced at the bottom of the lightly doped N layer 6 to further reduce the on-resistance. At the same time, the high concentration doping improves the carrier injection efficiency and improves the switching performance of the device.

[0051] Example 3

[0052] like Figure 3 As shown, a heavily doped N layer 11 is formed at the bottom of the lightly doped N layer 6 through ion implantation. The bottom of the heavily doped N layer 11 contacts the N substrate layer 2. A rectangular P-layer 12 is formed in the middle region of the heavily doped N layer 11 through ion implantation. The bottom of the rectangular P-layer 12 contacts the N substrate layer 2. Boron ions are implanted through a rectangular mask window to form the rectangular P-layer 12 in the middle of the heavily doped N layer. This structure balances the charge distribution by neutralizing the high-concentration electrons through hole injection, and an annealing process ensures the stability of the doped region.

[0053] Implanting a rectangular P-layer 12 in the heavily doped N-layer 11 achieves local charge compensation, suppresses the parasitic bipolar effect, enhances the anti-latch capability of the device, and maintains low on-resistance.

[0054] Example 4

[0055] like Figure 4 As shown, a heavily doped N-type half-layer 13 is formed at the bottom of the lightly doped N-layer 6 through ion implantation. The bottom of heavily doped N-type half-layer 13 contacts the N substrate layer 2. The cross-sectional profile of heavily doped N-type half-layer 13 is semi-elliptical. High-concentration nitrogen ion implantation using a semi-elliptical mask allows the semi-elliptical doped layer to better conform to the electric field distribution. After annealing, a smooth doping gradient is formed, reducing carrier scattering at the interface.

[0056] The heavily doped N-type half layer 13 with a semi-elliptical cross section is used to optimize the lateral distribution of carriers, reduce edge electric field spikes, and improve the dynamic response speed and reliability of the device.

[0057] Example 5

[0058] like Figure 5 As shown, ion implantation forms a heavily doped N-type half-layer 13 at the bottom of the lightly doped N-type layer 6. Ion implantation also forms a lightly doped N-type half-layer 14 in the middle region of the heavily doped N-type half-layer 13. The bottom of the lightly doped N-type half-layer 14 contacts the N substrate layer 2. Low-dose nitrogen ion implantation is used to form the lightly doped N-type half-layer 14 in the center of the heavily doped region, creating a high-to-low concentration gradient. This optimizes the carrier migration path and reduces energy loss during conduction.

[0059] A lightly doped N-type half layer 14 is formed inside the heavily doped N-type half layer 13 , and the trade-off between on-resistance and switching loss is further reduced through gradient doping design, thereby improving efficiency in high-frequency applications.

[0060] Example 6

[0061] like Figure 6 As shown, a heavily doped N-type half-layer 13 is formed at the bottom of the lightly doped N-type layer 6 through ion implantation. A semicircular P-layer 15 is also formed in the middle region of the heavily doped N-type half-layer 13 through ion implantation. The bottom of the semicircular P-layer 15 contacts the N substrate layer 2. Boron ion implantation is performed through a semicircular mask to form the semicircular P-layer 15. Its geometric structure matches the electric field distribution, effectively neutralizing excess electrons in the heavily doped N-type half-layer. After annealing, it ensures ohmic contact with the substrate and reduces the risk of leakage.

[0062] The introduction of a semicircular P-layer 15 into the heavily doped N-type half layer 13 enhances the charge compensation effect and improves the trade-off between breakdown voltage and on-resistance, making it suitable for high-voltage and high-power scenarios.

[0063] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A variable doping planar gate silicon carbide VDMOS device, comprising a plurality of mutually parallel MOS cells, wherein a single MOS cell comprises a drain (1), a semiconductor epitaxial layer, a source (4) and a gate (5); the semiconductor epitaxial layer comprises an N substrate layer (2), an N drift layer (3), a P+ layer (8), an N well layer (9) and a P well layer (10), characterized in that: A lightly doped N layer (6) is provided in the middle of the N drift layer (3) of a single MOS cell; A laterally symmetrical P-layer (7) is provided inside a single MOS cell and on the left and right sides of the N drift layer (3), and the corresponding side cross-sectional profiles of the laterally symmetrical P-layer (7) on both sides are arc-shaped; the bottom end of the laterally symmetrical P-layer (7) is in contact with the N substrate layer (2); A heavily doped N layer (11) is formed at the inner bottom of the lightly doped N layer (6) by ion implantation, and the bottom of the heavily doped N layer (11) is in contact with the N substrate layer (2); A rectangular P-layer (12) is formed in the inner middle region of the heavily doped N layer (11) by ion implantation, and the bottom end of the rectangular P-layer (12) is in contact with the N substrate layer (2).

2. A variable doping planar gate silicon carbide VDMOS device, comprising a plurality of mutually parallel MOS cells, wherein a single MOS cell comprises a drain (1), a semiconductor epitaxial layer, a source (4) and a gate (5); the semiconductor epitaxial layer comprises an N substrate layer (2), an N drift layer (3), a P+ layer (8), an N well layer (9) and a P well layer (10), characterized in that: A lightly doped N layer (6) is provided in the middle of the N drift layer (3) of a single MOS cell; A laterally symmetrical P-layer (7) is provided inside a single MOS cell and on the left and right sides of the N drift layer (3), and the corresponding side cross-sectional profiles of the laterally symmetrical P-layer (7) on both sides are arc-shaped; the bottom end of the laterally symmetrical P-layer (7) is in contact with the N substrate layer (2); A heavily doped N-type half layer (13) is formed at the inner bottom of the lightly doped N-layer (6) by ion implantation, and the bottom of the heavily doped N-type half layer (13) is in contact with the N substrate layer (2); the cross-sectional profile of the heavily doped N-type half layer (13) is in a semi-elliptical shape; A semicircular P-layer (15) is formed in the inner middle region of the heavily doped N-type half layer (13) by ion implantation, and the bottom end of the semicircular P-layer (15) is in contact with the N substrate layer (2).

Images