Carbon-based semiconductor device and preparation method thereof

Abstract

The invention provides a carbon-based semiconductor device and a preparation method thereof. The carbon-based semiconductor device includes: a substrate; the channel layer is made of a carbon-based material; an oxide layer; a gate electrode; the side walls are formed on the two sides of the grid electrode, each side wall is in a bent shape comprising a first part and a second part, the first part extends in the first direction, the second part extends in the second direction, the first direction is the direction perpendicular to the surface of the substrate, and the second direction is the direction parallel to the surface of the substrate. The drain electrode is located on the outer side of the side wall on one side of the grid electrode, and the drain electrode and the grid electrode are separated through the side wall on one side; the source electrode is positioned on the outer side of the side wall on the other side of the grid electrode; the source electrode and the grid electrode are separated through the side wall on the other side. According to the carbon-based semiconductor device disclosed by the invention, the side wall can form a widened transverse isolation region at the bottom of the gate, so that the regulation and control capability on a channel is remarkably enhanced, a short channel effect is effectively inhibited, gate-source / drain parasitic capacitance is reduced, leakage current is reduced, and the like.

Description

Technical Field

[0001] This disclosure relates to a carbon-based semiconductor device and a method for fabricating the same. Background Technology

[0002] In semiconductor device manufacturing, the gate sidewall is a critical structure primarily used to isolate the gate from the source or drain regions, suppress short-channel effects, improve gate control capability, and effectively reduce parasitic capacitance and leakage current, thus significantly affecting the device's electrical performance.

[0003] As semiconductor devices continue to shrink, carbon-based semiconductors (such as carbon nanotubes and graphene) are strong candidates for breaking through the physical limits of silicon materials. Although the fabrication of carbon-based semiconductor devices draws on the framework of silicon-based processes, it faces more severe challenges in the gate sidewall integration stage. These challenges stem from the strong chemical inertness of carbon materials, the complex interface states, and the higher requirements for sidewall thickness, contour, and dielectric compatibility at the nanoscale. Traditional sidewall processes are difficult to apply directly to carbon-based systems. Summary of the Invention

[0004] This disclosure provides a carbon-based semiconductor device and a method for fabricating the same.

[0005] According to one aspect of this disclosure, a carbon-based semiconductor device is provided, comprising: a substrate; a channel layer disposed on the substrate, the channel layer being made of a carbon-based material; an oxide layer disposed on the channel layer; a gate disposed on the oxide layer; sidewalls formed on both sides of the gate, the sidewalls being shaped as a bend including a first portion and a second portion, the first portion extending along a first direction and the second portion extending along a second direction, the first direction being a direction perpendicular to the surface of the substrate and the second direction being a direction parallel to the surface of the substrate; a drain located outside one sidewall of the gate, the drain and the gate being spaced apart by the one sidewall; and a source located outside the other sidewall of the gate, the source and the gate being spaced apart by the other sidewall.

[0006] According to one aspect of the technical solution, by designing the sidewall as a bent shape including a vertically extending first part and a horizontally extending second part, a widened lateral isolation region can be formed at the bottom of the gate, which significantly enhances the channel control capability, effectively suppresses short-channel effects, reduces gate-source / drain parasitic capacitance, and reduces leakage current, thereby improving the switching ratio, operating frequency and energy efficiency of carbon-based semiconductor devices.

[0007] According to at least one embodiment of the carbon-based semiconductor device of the present disclosure, the angle between the plane of the outer end of the second portion and the upper surface of the oxide layer is greater than 90°.

[0008] According to the technical solution of this embodiment, the electric field concentration effect caused by traditional right-angle or acute-angle structures can be avoided, significantly reducing the local electric field intensity at the gate edge, thereby suppressing the resulting hot carrier injection (HCI) and gate oxide reliability degradation. At the same time, this passivation profile can improve the step coverage of subsequent metal deposition or dielectric layer coverage, enhancing the long-term stability and process robustness of semiconductor devices.

[0009] According to at least one embodiment of the carbon-based semiconductor device of the present disclosure, the carbon-based material is carbon nanotubes or graphene.

[0010] According to the technical solution of this embodiment, when carbon nanotubes (CNTs) are used as the channel layer, the short-channel effect can be significantly suppressed by the strong gate control capability of the bent sidewalls and the low-damage single-step etching process. When graphene is used as the channel layer, electrostatic control can be enhanced by the bent sidewalls with widened bottom. This effectively compensates for its zero bandgap defect and significantly improves the on / off ratio and subthreshold characteristics of graphene transistors while avoiding interface damage and performance degradation caused by wet processes to carbon-based channels.

[0011] According to at least one embodiment of the carbon-based semiconductor device of the present disclosure, in the second direction, the relationship between the size d2 of the second portion and the size d1 of the first portion is d2≥2×d1.

[0012] According to the technical solution of this embodiment, the distance between the source region and the drain region can be significantly increased, effectively suppressing the short-channel effect.

[0013] According to at least one embodiment of the carbon-based semiconductor device of the present disclosure, the oxide layer is made of silicon oxide and the sidewalls are made of silicon nitride.

[0014] According to the technical solution of this embodiment, when silicon oxide (SiO2) is used as the oxide layer, it can form a relatively low interface state density with the carbon-based channel layer, providing good interface compatibility and process maturity. Simultaneously, as a reliable gate dielectric or etch stop layer, it ensures dimensional controllability and structural stability during the sidewall forming process. When silicon nitride (Si3N4) is used as the sidewall, it provides a high dielectric constant, excellent etch selectivity (especially compared to silicon oxide), and good resistance to ion penetration. Thus, while ensuring precise forming of the bent shape contour, it effectively enhances gate isolation performance, suppresses leakage current, and improves the long-term reliability of semiconductor devices under high temperature or high electric field conditions.

[0015] According to one aspect of this disclosure, a method for fabricating a carbon-based semiconductor device according to any embodiment of this disclosure is provided, comprising: sequentially fabricating the substrate, the channel layer, the oxide layer, and the temporary gate; depositing a sidewall dielectric layer, wherein the sidewall dielectric layer covers the oxide layer and the temporary gate; performing a first dry etching on the sidewall dielectric layer using a first etching gas to form polymer layers on both sides of the sidewall dielectric layer; performing a second dry etching using a second etching gas to remove other sidewall dielectric layers other than the sidewall dielectric layer covered by the polymer layer; removing the polymer layer to form the sidewall; and removing the temporary gate to fabricate a gate, a source, and a drain to obtain the carbon-based semiconductor device.

[0016] According to one technical solution, a bent-shaped sidewall is constructed through a two-step dry etching process. This two-step dry strategy avoids traditional multilayer stacking and wet processes, significantly simplifying the process and reducing fabrication costs. Simultaneously, leveraging the inherent anisotropy of dry etching and the polymer's self-regulating mechanism, the uniformity and repeatability of key sidewall dimensions (especially the bottom width d2) are greatly improved, effectively suppressing short-channel effects and parasitic capacitance.

[0017] According to the preparation method of at least one embodiment of the present disclosure, the first etching gas includes a gas capable of providing fluorine radicals, a carbon-fluorine gas with a high carbon-to-fluorine ratio, and an inert gas, wherein the carbon-fluorine gas with a high carbon-to-fluorine ratio is a carbon-fluorine gas with a carbon-to-fluorine ratio ≥ 1:3, and the second etching gas is a gas or a mixture of gases with an etching rate to the sidewall dielectric layer greater than that to the oxide layer.

[0018] According to the technical solution of this embodiment, based on the aforementioned first etching gas composition structure, the carbon-to-fluorine ratio and ion energy in the plasma can be synergistically controlled. Based on the aforementioned second etching gas composition structure, its etching rate for the sidewall dielectric layer is significantly higher than that for the oxide layer. This ensures efficient removal of the unprotected sidewall dielectric layer while maximally protecting the underlying temporary gate and channel layer from over-etching damage. Through the combined strategy of the first and second etching gases, both the ability to form bent shape contours and process selectivity are considered. This achieves self-aligned construction of the bottom widened sidewalls while ensuring the integrity of critical interfaces in carbon-based semiconductor devices.

[0019] According to the preparation method of at least one embodiment of the present disclosure, the proportion of the high carbon-to-fluorine ratio gas in the first etching gas can be controlled so that the polymer layer is thicker in the direction toward the sidewall dielectric layer.

[0020] According to the technical solution of this embodiment, precise control of the sidewall bottom width can be achieved without additional process steps, significantly enhancing the electric field shielding capability of the gate edge to the near-source or near-drain end of the channel. This effectively suppresses the short-channel effect while reducing gate-source or gate-drain overlap parasitic capacitance, thereby improving the switching characteristics and high-frequency performance of the semiconductor device.

[0021] According to the preparation method of at least one embodiment of the present disclosure, the gas capable of providing fluorine radicals is selected from at least one of trifluoromethane (CHF3) and fluoromethane (CH3F), the high carbon-to-fluorine ratio fluorocarbon gas is selected from at least one of octafluorocyclobutane (C4F8), hexafluoroethane (C2F6), octafluoropentene (C5F8) and hexafluorobutadiene (C4F6), and the inert gas is selected from at least one of argon (Ar), helium (He), and nitrogen (N2).

[0022] According to the technical solution of this embodiment, a dynamic balance between polymer generation, etching, and ion bombardment is achieved, enabling precise control of the profile of the bent sidewall (especially the bottom width) through gas ratio.

[0023] According to the preparation method of at least one embodiment of the present disclosure, the second etching gas is selected from at least one of trifluoromethane (CHF3), carbon tetrafluoride (CF4), and fluoromethane (CH3F).

[0024] According to the technical solution of this embodiment, a high etching rate for silicon nitride (Si3N4) and a high selectivity for silicon oxide (SiO2) can be achieved while maintaining the stability of the sidewall polymer layer. This precisely preserves the bottom protective area of ​​the bent shape contour, ensuring controllable sidewall morphology, uniform critical dimensions, and avoiding over-etching damage to the underlying carbon-based channel and gate dielectric layer. Attached Figure Description

[0025] The accompanying drawings illustrate exemplary embodiments of the present disclosure and, together with the description thereof, serve to explain the principles of the present disclosure. These drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification.

[0026] Figure 1 This is a flowchart illustrating one method for preparing sidewalls. Figure 2 yes Figure 1 The schematic diagram of the structure corresponding to step S310 in the preparation method shown.

[0027] Figure 3 yes Figure 1 The schematic diagram of the structure corresponding to step S320 in the preparation method shown.

[0028] Figure 4 yes Figure 1 The schematic diagram of the structure corresponding to step S330 in the preparation method shown.

[0029] Figure 5 yes Figure 1 The schematic diagram of the structure corresponding to step S340 in the preparation method shown.

[0030] Figure 6 This is a schematic diagram of the structure of a carbon-based semiconductor device according to one embodiment of the present disclosure.

[0031] Figure 7 This is a schematic flowchart of a method for fabricating a carbon-based semiconductor device according to one embodiment of the present disclosure.

[0032] Figure 8 This is a schematic diagram of the structure corresponding to step S410 in a carbon-based semiconductor device fabrication method according to an embodiment of the present disclosure.

[0033] Figure 9 This is a schematic diagram of the structure corresponding to step S430 in a carbon-based semiconductor device fabrication method according to an embodiment of the present disclosure.

[0034] Figure 10 This is a schematic diagram of the structure corresponding to step S450 in a carbon-based semiconductor device fabrication method according to an embodiment of the present disclosure. Detailed Implementation

[0035] The present disclosure will now be described in further detail with reference to the accompanying drawings and examples. It should be understood that the specific examples described herein are for illustrative purposes only and are not intended to limit the scope of the disclosure. Furthermore, it should be noted that, for ease of description, only the parts relevant to the present disclosure are shown in the accompanying drawings.

[0036] It should be noted that, where there is no conflict, the embodiments and features described in this disclosure can be combined with each other. The technical solutions of this disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0037] Unless otherwise stated, the exemplary implementations / embodiments shown are to be understood as providing exemplary features of various details that provide ways in which the technical concepts of this disclosure can be implemented in practice. Therefore, unless otherwise stated, the features of various implementations / embodiments may be additionally combined, separated, interchanged and / or rearranged without departing from the technical concepts of this disclosure.

[0038] The use of crosshairs and / or shading in the accompanying drawings is generally used to clarify the boundaries between adjacent components. Thus, unless otherwise stated, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for the specific material, material properties, dimensions, proportions, commonalities between the illustrated components, or any other characteristics, properties, etc., of the components. Furthermore, in the accompanying drawings, the dimensions and relative dimensions of components may be exaggerated for clarity and / or descriptive purposes. When exemplary embodiments can be implemented differently, a specific process sequence may be performed in a different order than that described. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of their description. Furthermore, the same reference numerals denote the same components.

[0039] When a component is referred to as being "on" or "above" another component, "connected to," or "joined to" another component, the component may be directly on, directly connected to, or directly joined to the other component, or there may be intermediate components. However, when a component is referred to as being "directly on" another component, "directly connected to," or "directly joined to" another component, there are no intermediate components. Therefore, the term "connection" can refer to a physical connection, an electrical connection, etc., and may or may not have intermediate components.

[0040] For descriptive purposes, this disclosure may use spatial relative terms such as “below,” “under,” “below,” “down,” “above,” “above,” “higher,” and “side (e.g., in a “sidewall”)” to describe the relationship between one component and another component as shown in the accompanying drawings. In addition to the orientations depicted in the drawings, the spatial relative terms are also intended to encompass different orientations of the device during use, operation, and / or manufacture. For example, if the device in the drawings is flipped, a component described as “below” or “under” another component or feature would subsequently be positioned “above” said other component or feature. Thus, the exemplary term “below” can encompass both “above” and “below” orientations. Furthermore, the device may be otherwise positioned (e.g., rotated 90 degrees or in other orientations), thus interpreting the spatial relative descriptive terms used herein accordingly.

[0041] In semiconductor device manufacturing, the gate sidewall, as a critical isolation structure, plays a decisive role in suppressing short-channel effects, improving gate control capabilities, and reducing parasitic capacitance and leakage current. Among them, bent sidewalls have more compact physical dimensions and better electrical isolation performance, theoretically showing the potential to outperform traditional rectangular sidewalls. Although carbon-based devices (such as transistors based on carbon nanotubes or graphene) follow the silicon-based manufacturing framework, the strong chemical inertness of the material surface, the complex interface states, and the further miniaturization of feature sizes make sidewall integration face more stringent challenges.

[0042] If a bent sidewall is to be fabricated, the current fabrication method typically employs... Figure 1 The preparation method shown. Figure 1 A schematic flowchart illustrating the fabrication process of the bent-shaped sidewall is shown. Figure 1 The method shown includes steps S310 to S340.

[0043] In step S310, on the fabricated gate 140, a stop dielectric layer 130 (silicon dioxide, SiO2), a sidewall dielectric layer 120 (silicon nitride, Si3N4), and a sacrificial dielectric layer 110 (silicon dioxide, SiO2) are sequentially deposited using chemical vapor deposition (CVD) or atomic layer deposition (ALD) processes. Figure 2 As shown.

[0044] In step S320, utilizing the anisotropic characteristics of dry etching, the sacrificial dielectric layer 110 on top of the gate 140 is selectively removed, exposing the sidewall dielectric layer 120 below the sacrificial dielectric layer 110, while retaining the stop dielectric layer 130 at the sidewall. Figure 3 As shown.

[0045] In step S330, wet etching is performed using a hot phosphoric acid solution. In this wet etching, the hot phosphoric acid solution has a much higher selectivity for silicon nitride (Si3N4) than for silicon dioxide (SiO2) to remove the exposed sidewall dielectric layer 120 from step S320, forming an approximately "D" shaped profile, as shown below. Figure 4 As shown.

[0046] In step S340, the remaining sidewall and surface stop dielectric layer 130 are simultaneously removed by dry etching, ultimately obtaining a bent-shaped sidewall structure, such as... Figure 5 As shown. This dry etching process employs process conditions (e.g., fluorine-based plasma) that have a high etching selectivity for silicon dioxide (SiO2) relative to silicon nitride (Si3N4), ensuring that silicon dioxide (SiO2) is efficiently removed while silicon nitride (Si3N4), which forms the main body of the sidewalls, is retained, thereby precisely shaping the contour of the bent shape.

[0047] While the aforementioned process for fabricating bent sidewalls can achieve the desired bent shape, it requires multiple alternating steps of dry and wet etching, resulting in complex procedures, long cycles, and high costs. In particular, the inherent isotropic nature of wet etching easily leads to sidewall morphology distortion and critical dimension fluctuations. Furthermore, the cumulative deviations and material damage during the multi-step etching process further weaken the process window and repeatability, making it difficult to balance morphological accuracy, interface integrity, and mass production feasibility in the fabrication of advanced carbon-based devices. This severely restricts the practical application of bent sidewalls in high-performance carbon-based transistors.

[0048] Therefore, this disclosure proposes the following technical solution, which provides a carbon-based semiconductor device and a method for fabricating the carbon-based semiconductor device. In this technical solution, a bent-shaped sidewall is directly constructed using a single-step dry etching process with a high carbon-to-fluorine ratio gas. This technical solution utilizes (CF2) generated in situ by plasma at the sidewall sidewalls and bottom corners during the etching process. n Fluorocarbon-like polymers, used as self-aligned passivation layers, leverage the inherent anisotropy of dry etching to achieve a unique folded shape profile with lateral extension at the bottom and vertical contraction at the sidewalls, without relying on multilayer dielectric stacking or multiple etching or cleaning steps. By precisely controlling the ratio of carbon to fluorine sources in the etching gas, the deposition rate and thickness distribution of the fluorocarbon polymer can be dynamically adjusted, thereby independently controlling the bottom width of the sidewalls. The fabrication method disclosed herein reduces process flow and wafer fabrication costs. At advanced process nodes, it is more conducive to the precise control of critical dimension (CD) uniformity and sidewall morphology. Furthermore, compared to rectangular sidewalls, it can more effectively suppress short-channel effects, reduce gate-source or gate-drain parasitic capacitance, and decrease subthreshold leakage current.

[0049] Figure 6 A schematic diagram of the structure of a carbon-based semiconductor device according to one embodiment of this disclosure is shown. Figure 6 As shown, the carbon-based semiconductor device includes a substrate 210, a channel layer 220 on the substrate 210, an oxide layer 230 on the channel layer 220, a gate 240 on the oxide layer 230, sidewalls 250 formed on both sides of the gate 240, and a drain 260 and a source 270 on both sides of the gate 240.

[0050] The channel layer 220 is made of a carbon-based material. As one possible implementation, the carbon-based material can be carbon nanotubes (CNTs) or graphene. When carbon nanotubes are used as the channel layer 220, the strong gate control capability of the bent sidewalls and the low-damage single-step etching process can significantly suppress short-channel effects and inter-device crosstalk. When graphene is used as the channel layer 220, the electrostatic control can be enhanced by the bent sidewalls with widened bottom. This effectively compensates for its zero bandgap defect and significantly improves the on / off ratio and subthreshold characteristics of graphene transistors while avoiding interface damage and performance degradation caused by wet processing of carbon-based channels.

[0051] The sidewall 250 has a bent shape including a first part 251 and a second part 252. The first part 251 extends along a first direction, and the second part 252 extends along a second direction. The first direction is perpendicular to the surface of the substrate 210, and the second direction is parallel to the surface of the substrate 210.

[0052] In one possible implementation, the angle between the plane at the outer end of the second portion 252 and the upper surface of the oxide layer 230 is greater than 90°. This implementation avoids the electric field concentration effect (i.e., acute angle effect) caused by conventional right-angle or acute-angle structures, significantly reducing the local electric field intensity at the gate edge, thereby suppressing the resulting hot carrier injection (HCI) and gate oxide reliability degradation. Simultaneously, this passivation profile improves the step coverage of subsequent metal deposition or dielectric layer coverage, reduces the risk of voids or wire breaks, and enhances the long-term stability and process robustness of the semiconductor device.

[0053] In one possible implementation, in the second direction, the relationship between the size d2 of the second portion 252 and the size d1 of the first portion 251 is d2 ≥ 2 × d1. This implementation significantly enhances the electric field shielding capability of the gate 240 to the channel layer 220 near the source or drain region, effectively suppressing short-channel effects.

[0054] In one possible implementation, the oxide layer 230 is made of silicon oxide (SiO2), and the sidewall 250 is made of silicon nitride (Si3N4). Using silicon oxide (SiO2) as the oxide layer 230 allows for a relatively low interface state density with the channel layer 220, providing good interface compatibility and process maturity. Simultaneously, it serves as a reliable gate dielectric or etch stop layer, ensuring dimensional controllability and structural stability during the sidewall 250 forming process. Using silicon nitride (Si3N4) as the sidewall 250 provides a high dielectric constant, excellent etch selectivity (especially compared to silicon oxide), and good resistance to ion penetration. This ensures precise forming of the bent shape profile while effectively enhancing the isolation performance of the gate 240, suppressing leakage current, and improving the long-term reliability of the semiconductor device under high temperature or high electric field conditions.

[0055] The drain 260 is located on one sidewall of the gate 240 (e.g., Figure 6 The source 270 is located on the other side wall of the gate 240 (as shown in the image). Figure 6 The drain 260 is located outside the right-side sidewall and is separated from it by the other sidewall. As an example, the drain 260 can be a stacked structure, which may include a Pd / SC layer 261, a Ti layer 262, and a TiN layer 263. Additionally, the drain 260 may include a metal pad 264. The source 270 can be a stacked structure, which may include a Pd / SC layer 271, a Ti layer 272, and a TiN layer 273. Additionally, the source 270 may include a metal pad 274. The gate 240 may include an HfO2 layer 241, a Ti+TiN layer 242, and a metal pad 243.

[0056] Figure 7 A schematic flowchart of a method for fabricating a carbon-based semiconductor device according to one embodiment of this disclosure is shown. Figure 7 The method shown includes steps S410 to S460.

[0057] In step S410, a substrate 210, a channel layer 220, an oxide layer 230, and a temporary gate 260 are sequentially fabricated, as follows: Figure 8 As shown.

[0058] In one possible implementation, a silicon (Si) substrate is used as the substrate 210, a channel layer 220 is formed using carbon nanotubes (CNTs), an oxide layer 230 is formed using silicon oxide (SiO2), and a temporary gate 260 is formed using amorphous silicon (a-Si). During fabrication, the substrate 210 is first constructed, followed by the formation of the channel layer 220 composed of carbon nanotubes (CNTs) on the substrate 210. Then, silicon oxide (SiO2) is deposited on the surface of the channel layer 220 as the oxide layer 230, and finally, the temporary gate 260 is formed through photolithography and deposition processes. This temporary gate 260 is used for subsequent self-aligned source or drain regions and sidewall locations.

[0059] In step S420, a sidewall dielectric layer 270 is deposited, wherein the sidewall dielectric layer 270 covers the oxide layer 230 and the temporary gate 260.

[0060] As one possible implementation, a silicon nitride (Si3N4) layer is conformally deposited on the surface of the overall structure obtained in step S410 as a sidewall dielectric layer 270 using chemical vapor deposition (CVD) or atomic layer deposition (ALD). This sidewall dielectric layer 270 needs to have good step coverage and thickness uniformity to ensure the consistency of the sidewall morphology during subsequent anisotropic etching and to provide a chemical basis for polymer selective deposition.

[0061] In step S430, the sidewall dielectric layer 270 is subjected to a first dry etching using a first etching gas, forming polymer layers 280 on both sides of the sidewall dielectric layer 270, such as... Figure 9 As shown.

[0062] As one possible implementation, a plasma dominated by a high carbon-to-fluorine ratio gas (such as C4F8 or C5F8) is used for the first dry etching. This plasma preferentially deposits (CF2)-containing gases in low-ion bombardment regions (such as the sidewalls and bottom corners of the temporary gate 260). n Due to the properties of the fluorocarbon polymer in the unit, a polymer layer 280 is formed on the vertical sidewalls and bottom corners of the sidewall dielectric layer 270. This polymer layer 280 serves as a masking layer for subsequent etching.

[0063] In step S440, a second dry etching process is performed using a second etching gas to remove the other sidewall dielectric layers 270 outside the sidewall dielectric layers 270 covered by the polymer layer 280.

[0064] In the second dry etching process, the gas used is switched from the first etching gas to the second etching gas. This second etching gas is a highly selective etching gas, mainly composed of fluorine, which efficiently removes the unprotected sidewall dielectric layer 270 in the top and horizontal regions while maintaining the stability of the polymer layer 280. Because the polymer layer 280 has a shielding effect against ion bombardment, only the exposed areas of the sidewall dielectric layer 270 are etched, thus initially defining the outline of the bent sidewall.

[0065] In step S450, the polymer layer 280 is removed to form the sidewall 250, as shown below. Figure 10 As shown.

[0066] As one possible implementation, in removing the polymer layer 280, oxygen plasma ashing or a weakly oxidizing wet cleaning can be used to selectively remove residual fluorocarbon polymers, exposing the underlying bent-shaped sidewall structure.

[0067] Oxygen plasma ashing is a dry cleaning process widely used in semiconductor manufacturing. It is mainly used to remove photoresist or organic polymer residues (such as fluorocarbon polymers deposited during etching).

[0068] Weak oxidizing wet cleaning refers to a type of wet cleaning process that uses a liquid chemical solution with mild oxidizing power and low corrosiveness (such as diluted ammonia or hydrogen peroxide mixture) to selectively remove organic contaminants (such as photoresist residue, fluorocarbon polymers, hydrocarbon contaminants, etc.) at a low temperature, while minimizing oxidative damage or structural destruction to sensitive materials (such as carbon nanotubes, graphene, metal electrodes, and ultrathin gate dielectrics).

[0069] It should be noted that when performing this step, oxidation damage to the channel layer 220 must be avoided, therefore the process conditions must be mild and controllable.

[0070] In step S460, the temporary gate 260 is removed, and the gate 240, source 270, and drain 260 are fabricated to obtain a carbon-based semiconductor device, such as... Figure 6 As shown. Specifically, for the drain 260, a Pd / SC layer 261, a Ti layer 262, and a TiN layer 263 can be deposited sequentially, and finally a metal pad 264 can be filled; for the source 270, a Pd / SC layer 271, a Ti layer 272, and a TiN layer 273 can be deposited sequentially, and finally a metal pad 274 can be filled; for the gate 240, an HfO2 layer 241 and a Ti+TiN layer 242 can be deposited sequentially, and finally a metal pad 243 can be filled. Additionally, an oxide layer (SiO2) 280 can be filled last.

[0071] As one possible implementation, the removal of the temporary gate 260 can be achieved using selective wet etching or dry etching processes. After removing the temporary gate 260, the central region of the underlying oxide layer 230 is exposed. Subsequently, using the sidewall 250 as a self-aligned mask, the source 270 and drain 260 are first formed in the exposed channel region. Then, in the opening region corresponding to the temporary gate 260, a work function metal layer and a conductive filling layer are sequentially deposited, and the final gate 240 is formed by chemical mechanical polishing. This completes the integration of a high-performance carbon-based semiconductor device.

[0072] In steps S410 to S460, the bent sidewalls are constructed through a two-step dry etching process. This two-step dry etching strategy avoids traditional multilayer stacking and wet processes, significantly simplifying the process and reducing fabrication costs. Simultaneously, leveraging the inherent anisotropy of dry etching and the polymer's self-regulating mechanism, the uniformity and repeatability of key sidewall dimensions (especially the bottom width d2) are greatly improved, effectively suppressing short-channel effects and parasitic capacitance.

[0073] In one possible implementation, the first etching gas includes a gas capable of providing fluorine radicals, a fluorocarbon gas with a high carbon-to-fluorine ratio, and an inert gas. The fluorocarbon gas with a high carbon-to-fluorine ratio is a fluorocarbon gas with a carbon-to-fluorine ratio ≥ 1:3. The second etching gas is a gas or a mixture thereof where the etching rate of the sidewall dielectric layer 270 is greater than the etching rate of the oxide layer 230.

[0074] Based on the aforementioned first etching gas composition, the carbon-to-fluorine ratio and ion energy in the plasma can be synergistically controlled. Based on the aforementioned second etching gas composition, the etching rate of the sidewall dielectric layer 270 is significantly higher than that of the oxide layer 230. This ensures efficient removal of the unprotected sidewall dielectric layer 270 while maximally protecting the underlying temporary gate 260 and channel layer 220 from over-etching damage. Through the combined strategy of the first and second etching gases, both the ability to form bent shapes and process selectivity are balanced. This achieves self-aligned construction of the widened bottom sidewalls while ensuring the integrity of critical interfaces in carbon-based semiconductor devices.

[0075] As one possible implementation, the proportion of a high carbon-to-fluorine ratio gas in the first etching gas can be controlled so that the polymer layer 280 is thicker in the direction toward the sidewall dielectric layer 270.

[0076] By controlling the proportion of a high carbon-to-fluorine ratio gas in the first etching gas, the concentration of carbon radicals in the plasma can be enhanced. This promotes preferential deposition of fluorocarbon polymers in regions with lower ion bombardment energy (especially the bottom corners and near-horizontal surfaces of the sidewall dielectric layer 270). This results in a significant increase in the thickness of the polymer layer 280 towards the bottom of the sidewall dielectric layer 270. This thickness gradient distribution facilitates stronger bottom lateral protection in the subsequent second dry etching, allowing the etching profile to naturally evolve into a bent shape structure with a wide bottom and narrow sidewalls (d2 ≥ 2d1). Through this implementation, precise control of the sidewall bottom width can be achieved without additional process steps, significantly enhancing the electric field shielding capability of the gate edge to the near-source or near-drain end of the channel. This effectively suppresses short-channel effects while reducing gate-source or gate-drain overlap parasitic capacitance, improving the switching characteristics and high-frequency performance of the semiconductor device.

[0077] As one possible implementation, the gas capable of providing fluorine radicals is selected from at least one of trifluoromethane (CHF3) and fluoromethane (CH3F). The high carbon-to-fluorine ratio fluorocarbon gas is selected from at least one of octafluorocyclobutane (C4F8), hexafluoroethane (C2F6), octafluoropentene (C5F8), and hexafluorobutadiene (C4F6). The inert gas is selected from at least one of argon (Ar), helium (He), and nitrogen (N2).

[0078] The first etching gas obtained through this embodiment can stably release an appropriate amount of fluorine radicals in the plasma, providing controllable basic etching capability and avoiding etching stagnation caused by excessive polymerization. The high carbon-to-fluorine ratio gas, after cracking, generates high-concentration carbon radicals and long-chain fluorocarbon fragments, significantly enhancing the deposition rate and stability of the polymer layer 280 at the bottom corner of the sidewall. The introduction of inert gas optimizes plasma density and ion bombardment directionality, improving etching anisotropy. The synergistic effect of the three types of gases achieves a dynamic balance between polymer generation, etching, and ion bombardment, allowing the contour of the bent sidewall (especially the bottom width) to be precisely controlled through gas ratios.

[0079] As one possible implementation, the second etching gas is selected from at least one of trifluoromethane (CHF3), carbon tetrafluoride (CF4), and fluoromethane (CH3F).

[0080] The second etching gas obtained through this embodiment can achieve a high etching rate for silicon nitride (Si3N4) and a high selectivity for silicon oxide (SiO2) while maintaining the stability of the sidewall polymer layer 280. This precisely preserves the bottom protective area of ​​the bent shape contour, ensuring controllable sidewall morphology, uniform critical dimensions, and avoiding over-etching damage to the underlying carbon-based channel and gate dielectric layer.

[0081] In the description of this specification, the references to terms such as "one embodiment / mode," "some embodiments / modes," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment / mode or example is included in at least one embodiment / mode or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment / mode or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments / modes or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments / modes or examples described in this specification, as well as the features of different embodiments / modes or examples.

[0082] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this disclosure, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0083] Those skilled in the art should understand that the above embodiments are merely for illustrating the present disclosure and are not intended to limit the scope of the disclosure. Those skilled in the art can make other changes or modifications based on the above disclosure, and these changes or modifications still fall within the scope of the present disclosure.

Claims

1. A carbon-based semiconductor device, characterized in that, include: Substrate; A channel layer located above the substrate, the channel layer being made of a carbon-based material; An oxide layer located above the channel layer; A gate located above the oxide layer; The sidewalls formed on both sides of the gate are bent in shape, including a first part and a second part. The first part extends along a first direction, and the second part extends along a second direction. The first direction is perpendicular to the surface of the substrate, and the second direction is parallel to the surface of the substrate. A drain located outside one sidewall of the gate, the drain and the gate being spaced apart by the sidewall; as well as The source is located outside the other sidewall of the gate, and the source and the gate are spaced apart by the other sidewall.

2. The carbon-based semiconductor device as described in claim 1, characterized in that, The angle between the plane at the outer end of the second part and the upper surface of the oxide layer is greater than 90°.

3. The carbon-based semiconductor device as described in claim 1, characterized in that, The carbon-based material is either carbon nanotubes or graphene.

4. The carbon-based semiconductor device as described in claim 1, characterized in that, In the second direction, the relationship between the size d2 of the second part and the size d1 of the first part is d2≥2×d1.

5. The carbon-based semiconductor device according to any one of claims 1 to 4, characterized in that, The oxide layer is made of silicon oxide, and the sidewalls are made of silicon nitride.

6. A method for preparing the carbon-based semiconductor device according to any one of claims 1 to 5, characterized in that, include: The substrate, the channel layer, the oxide layer, and the temporary gate are fabricated sequentially. A sidewall dielectric layer is deposited, wherein the sidewall dielectric layer covers the oxide layer and the temporary gate; The sidewall dielectric layer is subjected to a first dry etching using a first etching gas to form polymer layers on both sides of the sidewall dielectric layer. The other sidewall dielectric layers, excluding the sidewall dielectric layer covered by the polymer layer, are removed by a second dry etching process using a second etching gas. Remove the polymer layer to form the sidewall; Remove the temporary gate, and fabricate the gate, source, and drain to obtain the carbon-based semiconductor device.

7. The preparation method according to claim 6, characterized in that, The first etching gas includes a gas capable of providing fluorine radicals, a carbon-fluorine gas with a high carbon-to-fluorine ratio, and an inert gas, wherein the carbon-fluorine gas with a high carbon-to-fluorine ratio is a carbon-fluorine gas with a carbon-to-fluorine ratio ≥ 1:3, and the second etching gas is a gas or a mixture of gases with an etching rate for the sidewall dielectric layer greater than that for the oxide layer.

8. The preparation method according to claim 7, characterized in that, The proportion of the high carbon-to-fluorine ratio gas in the first etching gas can be controlled so that the polymer layer is thicker in the direction toward the sidewall dielectric layer.

9. The preparation method according to claim 7 or 8, characterized in that, The gas capable of providing fluorine radicals is selected from at least one of trifluoromethane and fluoromethane; the high carbon-to-fluorine ratio fluorocarbon gas is selected from at least one of octafluorocyclobutane, hexafluoroethane, octafluoropentene, and hexafluorobutadiene; and the inert gas is selected from at least one of argon, helium, and nitrogen.

10. The preparation method according to claim 7 or 8, characterized in that, The second etching gas is selected from at least one of trifluoromethane, carbon tetrafluoride, and fluoromethane.

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