Semiconductor device and preparation method thereof

Abstract

The invention discloses a semiconductor device and a preparation method thereof, the semiconductor device comprises a back electrode, a substrate and an epitaxial structure which are laminated, and a heterojunction structure is arranged in the epitaxial structure; the source electrode structure and the drain electrode structure are both located on the side, away from the substrate, of the epitaxial structure; the source electrode structure comprises a source electrode located in the active region and a source electrode power supply electrode located in the passive region, the drain electrode structure comprises a drain electrode located in the active region, the source electrode power supply electrode and the drain electrode form ohmic contact with the epitaxial structure, and the source electrode power supply electrode is electrically connected with the source electrode and is electrically connected with the back electrode through a source electrode through hole; along the first direction, the source electrode through hole is located at one side of the active region; the auxiliary through hole is located between the active area and the source electrode through hole in the first direction, and the auxiliary through hole penetrates through the two-dimensional electron gas. By adopting the technical means, the auxiliary through hole penetrating through the two-dimensional electron gas is arranged, so that the stray capacitance between the source electrode structure and the drain electrode structure can be reduced, and the working performance of the device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular, to a semiconductor device and a method for manufacturing the same. Background Art

[0002] Due to the characteristics of gallium nitride semiconductor material such as large bandgap width, high electron saturation drift velocity, high breakdown field strength, and good thermal conductivity, it has become a current research hotspot.

[0003] For semiconductor devices, in traditional designs, the back metal electrode is usually electrically connected to the source electrode through a via, and the back metal electrode exists on the entire back of the device, resulting in the formation of a parasitic capacitance between the drain and the source, which affects the performance of the device.

[0004] Therefore, how to improve the performance of semiconductor devices is an urgent problem to be solved currently. Summary of the Invention

[0005] The present invention provides a semiconductor device and a method for manufacturing the same to reduce the parasitic capacitance between the source electrode structure and the drain electrode structure, thereby improving the working performance of the semiconductor device.

[0006] In a first aspect, an embodiment of the present invention provides a semiconductor device, including:

[0007] A back electrode, a substrate, and an epitaxial structure, which are stacked, and a heterojunction structure is provided in the epitaxial structure;

[0008] A source electrode structure and a drain electrode structure, both located on a side of the epitaxial structure away from the substrate; the source electrode structure includes a source located in the active region and a source power supply electrode located in the passive region, the drain electrode structure includes a drain located in the active region, the source power supply electrode and the drain both form ohmic contacts with the epitaxial structure, the source power supply electrode is electrically connected to the source, and is electrically connected to the back electrode through a source via; along a first direction, the source via is located on a side of the active region; the first direction is parallel to the plane where the substrate is located;

[0009] An auxiliary via, located between the active region and the source via along the first direction, and the auxiliary via penetrates through the heterojunction structure.

[0010] Optionally, along a second direction, the length of the auxiliary via is greater than the length of the active region; the second direction is parallel to the plane where the substrate is located and intersects with the first direction.

[0011] Optionally, along the first direction, the average opening diameter of the auxiliary via is greater than the average opening diameter of the source via.

[0012] Optionally, the auxiliary through-hole is filled with an auxiliary medium, and the average dielectric constant of the auxiliary medium is less than the average dielectric constant of the film layer penetrated by the auxiliary through-hole.

[0013] Optionally, the auxiliary medium includes a solid medium, and the back electrode covers the auxiliary through-hole.

[0014] Optionally, the auxiliary medium includes air, the back electrode includes a hollowed-out portion, and the hollowed-out portion exposes at least part of the auxiliary through-hole.

[0015] Optionally, the epitaxial structure includes a channel layer and a barrier layer on a side of the channel layer away from the substrate, and the heterojunction structure is disposed between the channel layer and the barrier layer;

[0016] The auxiliary through-hole penetrates at least the substrate and the channel layer; or, the auxiliary through-hole penetrates at least the barrier layer and the channel layer.

[0017] Optionally, the first direction is the same as the extending direction of the source electrode;

[0018] Or, the first direction is the same as the arranging direction of the source electrode and the drain electrode.

[0019] Optionally, the first direction is the same as the extending direction of the source electrode;

[0020] The semiconductor device further includes a gate electrode structure, the gate electrode structure includes a gate located in the active region and a gate power supply electrode located in the passive region, and the gate power supply electrode is electrically connected to the gate;

[0021] The source power supply electrode is located on a side of the gate power supply electrode away from the active region, or the source power supply electrode is located on a side of the drain power supply electrode away from the active region.

[0022] In a second aspect, an embodiment of the present invention further provides a method for manufacturing a semiconductor device, including:

[0023] Providing a substrate and preparing an epitaxial structure on one side of the substrate; a heterojunction structure is disposed in the epitaxial structure;

[0024] Preparing a source electrode structure and a drain electrode structure on a side of the epitaxial structure away from the substrate; the source electrode structure includes a source located in the active region and a source power supply electrode located in the passive region, the drain electrode structure includes a drain located in the active region, the source power supply electrode and the drain both form an ohmic contact with the epitaxial structure, and the source is electrically connected to the source;

[0025] Fabricate a source via and an auxiliary via, where the source via penetrates through the substrate and the epitaxial structure, and the auxiliary via penetrates through at least the heterojunction structure; along a first direction, the auxiliary via is located between the source via and the active region, and the first direction is parallel to the plane where the substrate is located;

[0026] Fabricate a back electrode, where the back electrode is electrically connected to the source power supply electrode through the source via.

[0027] Optionally, fabricating the source via and the auxiliary via includes:

[0028] Fabricate the source via and the auxiliary via using the same masking process.

[0029] Optionally, before fabricating the back electrode, further include:

[0030] Fill the auxiliary via with an auxiliary dielectric, where the average dielectric constant of the auxiliary dielectric is less than the average dielectric constant of the film layer penetrated by the auxiliary via;

[0031] Fill the source via with a connection dielectric, where the connection dielectric is electrically connected to the source power supply electrode;

[0032] Fabricating the back electrode includes:

[0033] Fabricate a full-surface back electrode, where the back electrode covers the auxiliary via, and the back electrode is electrically connected to the connection dielectric or the back electrode is reused as the connection dielectric.

[0034] Optionally, before fabricating the back electrode, further include:

[0035] Fill the auxiliary via with a sacrificial dielectric;

[0036] Fabricating the back electrode includes:

[0037] Fabricate a full-surface back electrode;

[0038] Pattern the back electrode to form a hollowed-out portion in the back electrode, where the hollowed-out portion exposes at least part of the auxiliary via;

[0039] Remove the sacrificial dielectric through the hollowed-out portion.

[0040] In the technical solution of the embodiment of the present invention, since both the source and the drain form ohmic contacts with the epitaxial structure, that is to say, the drain and the source are electrically connected to the two-dimensional electron gas in the heterojunction structure, and there is a lateral parasitic capacitance between the source electrode structure and the drain electrode structure. By setting an auxiliary via between the active region and the source via, and the auxiliary via penetrates through the two-dimensional electron gas, the lateral parasitic capacitance between the source electrode structure and the drain electrode structure can be reduced, and the performance of the semiconductor device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 FIG. 0 is a top view schematic diagram of a semiconductor device provided by an embodiment of the present invention;

[0042] Figure 2 FIG. Figure 1 1 is a schematic cross-sectional structure diagram of a semiconductor device provided by an embodiment of the present invention along the section line A-A';

[0043] Figure 3 FIG. 2 is a top view schematic diagram of another semiconductor device provided by an embodiment of the present invention;

[0044] Figure 4 FIG. Figure 3 2 is a schematic cross-sectional structure diagram of a semiconductor device provided by an embodiment of the present invention along the section line B-B';

[0045] Figure 5 FIG. Figure 1 3 is a schematic cross-sectional structure diagram of another semiconductor device provided by an embodiment of the present invention along the section line A-A';

[0046] Figure 6 FIG. Figure 1 4 is a schematic cross-sectional structure diagram of yet another semiconductor device provided by an embodiment of the present invention along the section line A-A';

[0047] Figure 7 FIG. 5 is a top view schematic diagram of yet another semiconductor device provided by an embodiment of the present invention;

[0048] Figure 8 FIG. 6 is a schematic flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0049] Figure 9 FIG. Figure 8 7 is a process flow chart of a method for manufacturing a corresponding semiconductor device;

[0050] Figure 10 FIG. 8 is a schematic flow chart of another method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0051] Figure 11 FIG. Figure 10 9 is a process flow chart of a method for manufacturing a corresponding semiconductor device;

[0052] Figure 12 FIG. 10 is a schematic flow chart of yet another method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0053] Figure 13 FIG. Figure 12 11 is a process flow chart of a method for manufacturing a corresponding semiconductor device. DETAILED DESCRIPTION OF THE INVENTION

[0054] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0055] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily need to describe a specific order or sequence. It should be understood that such used data can be interchanged under appropriate circumstances so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. In addition, the term "comprising" and any variations thereof are intended to cover non-exclusive inclusion.

[0056] Figure 1 A top view schematic diagram of a semiconductor device provided by an embodiment of the present invention, Figure 2 is Figure 1 a schematic cross-sectional structure diagram of a semiconductor device along the section line A-A', as Figure 1 and Figure 2 shown. The semiconductor device includes: a back electrode 10, a substrate 20, and an epitaxial structure 30, which are stacked; a heterojunction structure is provided in the epitaxial structure 30; a source electrode structure 40 and a drain electrode structure 50 are both located on the side of the epitaxial structure 30 away from the substrate 20; the source electrode structure 40 includes a source 401 located in the active region aa and a source power supply electrode 402 located in the passive region bb, the drain electrode structure 50 includes a drain 501 located in the active region aa, the source 401 and the drain 501 both form an ohmic contact with the epitaxial structure 30, the source power supply electrode 402 is electrically connected to the source 401, and is electrically connected to the back electrode 10 through a source via 60; along the first direction (the X direction shown in the figure), the source via 60 is located on one side of the active region aa; the first direction X is parallel to the plane where the substrate 20 is located; an auxiliary via 70 is located between the active region aa and the source via 60 along the first direction X, and the auxiliary via 70 penetrates the heterojunction structure.

[0057] Specifically, continue to refer to Figure 1, a semiconductor device may include an active region aa and a passive region bb. The active region aa can be understood as a region where a two-dimensional electron gas (2DEG), electrons, or holes exist below it. Its working state and characteristics are affected by an external circuit, and it is the active working region of the semiconductor device. The passive region bb participates in the operation of the semiconductor device, but its working state is not affected by the external circuit. For example, a lead-out structure of the electrodes in the active region aa can be provided in the passive region bb, and the passive region bb can be arranged around the active region aa. There is a two-dimensional electron gas in the active region aa, and there is a small amount of two-dimensional electron gas in the passive region bb due to leakage.

[0058] Furthermore, the semiconductor device further includes a source electrode structure 40 and a drain electrode structure 50 located on the side of the epitaxial structure 30 away from the substrate 20. The source electrode structure 40 includes a source 401 located in the active region aa and a source power supply electrode 402 located in the passive region bb. The drain electrode structure 50 includes a drain 501 located in the active region aa and a drain power supply electrode 502 located in the passive region bb. Both the source 401 and the drain 501 can form an ohmic contact with the epitaxial structure 30. Exemplarily, the source 401 can be used as the input end of the semiconductor device, and the drain 501 can be used as the output end of the semiconductor device. The source power supply electrode 402 can be understood as a source pad. The source 401 in the active region aa can be connected to the source power supply electrode 402 located in the passive region bb. The source 401 receives a voltage signal through the source power supply electrode 402 to ensure the normal operation of the semiconductor device. The drain power supply electrode 502 can be understood as a drain pad. The drain 501 in the active region aa can be connected to the drain power supply electrode 502 located in the passive region bb. The drain 501 can receive a voltage signal through the drain power supply electrode 502 to ensure the normal operation of the semiconductor device. Furthermore, the semiconductor device may further include a gate electrode structure 80 located on the side of the epitaxial structure 30 away from the substrate 20. The gate electrode structure 80 may include a gate 801 located in the active region aa and a gate power supply electrode 802 located in the passive region bb. The gate 801 can be used as the control end of the semiconductor device. The current flow between the source 401 and the drain 501 can be realized by controlling the voltage of the gate 801. That is, when a certain voltage is applied to the gate 801, a current will be generated between the source 401 and the drain 501. By changing the voltage of the gate 801, the current between the source 401 and the drain 501 can be controlled. The gate power supply electrode 802, that is, the gate pad, is connected to the gate 801 in the active region aa to provide a gate voltage signal to ensure the normal operation of the semiconductor device.

[0059] It should be noted that Figure 1For example, a semiconductor device including a plurality of source electrodes 401, a plurality of drain electrodes 501, and a plurality of gate electrodes 801 is taken as an example for illustration, that is, the semiconductor device is a multi-cell structure; it can be understood that the semiconductor device may also include only one source electrode 401, one drain electrode 501, and one gate electrode 801, that is, the semiconductor device is a single-cell structure. The embodiments of the present invention do not limit whether the semiconductor device is a single-cell structure or a multi-cell structure.

[0060] Continuing to refer to Figure 1 and Figure 2 As shown, the semiconductor device provided by the embodiments of the present invention further includes a back electrode 10, and the back electrode 10 is electrically connected to the source power supply electrode 402 through a source via 60, thereby realizing the transmission of the source signal. The back electrode 10 may adopt a stacked layer of one or more metals mainly composed of gold, and the embodiments of the present invention do not specifically limit the material of the back electrode 10.

[0061] Since there is an opposing region between the drain electrode structure 50 and the back electrode 10 in the thickness direction of the semiconductor device, there is a longitudinal parasitic capacitance between the drain electrode structure 50 and the back electrode 10; and because both the source 401 and the drain 501 form ohmic contacts with the two-dimensional electron gas, there is a lateral parasitic capacitance between the source electrode structure 40 and the drain electrode structure 50 in the horizontal direction. The relatively large parasitic capacitance between the source electrode structure 40 and the drain electrode structure 50 affects the performance of the semiconductor device.

[0062] Based on this, in the embodiments of the present invention, an auxiliary via 70 is provided between the active region aa and the source via 60 along the first direction X. The auxiliary via 70 penetrates the heterojunction structure, and thus the auxiliary via 70 can penetrate the heterojunction structure, so that the parasitic capacitance between the source power supply electrode 402 and the drain 501 can be reduced along the first direction X, and then the parasitic capacitance between the source electrode structure 40 and the drain electrode structure 50 can be reduced, improving the performance of the semiconductor device.

[0063] It should be noted that along the first direction X, the auxiliary via 70 can be located at any position between the source via 60 and the active region aa, that is, it can be located at the edge position close to the active region aa, or at the edge position close to the source via 60, or at the intermediate position between the source via 60 and the active region aa.

[0064] For a gallium nitride radio frequency power amplifier, by reducing the parasitic capacitance between the source electrode structure 40 and the drain electrode structure 50, the device efficiency and gain can be improved. For a gallium nitride power electronic device, by reducing the parasitic capacitance between the source electrode structure 40 and the drain electrode structure 50, the device switching speed can be improved.

[0065] Based on the above embodiments, the semiconductor device further includes a substrate 20, which can be one or a combination of gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, indium phosphide, gallium arsenide, silicon carbide, diamond, sapphire, germanium, silicon, or any other material capable of growing group III nitrides. The epitaxial structure 30 located on one side of the substrate 20 can be formed by one or more of group III-V nitrides such as gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum nitride, or indium aluminum gallium nitride.

[0066] Exemplarily, continuing to refer to Figure 2 , the epitaxial structure 30 can include a nucleation layer 301, a buffer layer 302, a channel layer 303, and a barrier layer 304; the channel layer 303 and the barrier layer 304 can form a heterojunction structure.

[0067] Exemplarily, continuing to refer to Figure 2 , the material of the nucleation layer 301 can be aluminum nitride, which is located between the substrate 20 and the buffer layer 302. The nucleation layer 301 affects parameters such as the crystal quality, surface morphology, and electrical properties of the heterojunction material above. The nucleation layer 301 varies with different substrate materials and mainly serves to match the substrate material and the semiconductor material layer in the heterojunction structure.

[0068] Exemplarily, continuing to refer to Figure 2 , the buffer layer 302 is located on one side of the substrate 20. The material of the buffer layer 302 can be gallium nitride, and the buffer layer 302 can include iron atoms, which is beneficial to achieving the high-resistance performance of the buffer layer 302, ensuring that vertical leakage can be blocked and improving the pinch-off performance of the semiconductor device. The buffer layer 302 can serve to bond the semiconductor material layers that need to be grown next and can also protect the substrate 20 from being invaded by some metal ions. The material of the buffer layer 302 can be group III nitride materials such as AlGaN, GaN, or AlGaInN.

[0069] Exemplarily, continuing to refer to Figure 2 , the channel layer 303 can be a group III nitride, such as Al x Ga 1－x N, where 0 ≤ x < 1, that is, at the interface between the channel layer 303 and the barrier layer 304, which is the energy of the conduction band edge of the channel layer 303 is less than the energy of the conduction band edge of the barrier layer 304. Exemplarily, x = 0 indicates that the channel layer 303 is GaN. The channel layer 303 can also be other group III nitrides, such as InGaN or AlInGaN. The channel layer 303 can be undoped or unintentionally doped. The channel layer 303 can also be a multi-layer structure, such as a combination of superlattice, GaN, or AlGaN.

[0070] Exemplarily, continuing to refer to Figure 2, the barrier layer 304 can be AlN, AlInN, AlGaN or AlInGaN. The barrier layer 304 has a sufficient thickness and a sufficiently high Al component to form a significant carrier concentration at the interface between the channel layer 303 and the barrier layer 304.

[0071] Exemplarily, continuing to refer to Figure 2 , the channel layer 303 can include GaN, and the barrier layer 304 can include AlGaN, that is, the material of the barrier layer 304 has a higher bandgap than the material of the channel layer 303, and the channel layer 303 can also have a greater electron affinity than the barrier layer 304. Due to the bandgap difference between the barrier layer 304 and the channel layer 303 and the piezoelectric effect at the interface between the barrier layer 304 and the channel layer 303, a two-dimensional electron gas is formed at the channel layer 303 and the barrier layer 304.

[0072] It can be understood that the epitaxial structure 30 can also include a cap layer, and the cap layer is located on the surface of the barrier layer 304 away from the substrate 20. The cap layer can reduce surface states, reduce surface leakage of subsequent semiconductor devices, and suppress current collapse, thereby improving the performance and reliability of the epitaxial structure 30 and the semiconductor device.

[0073] For the semiconductor device provided by the embodiment of the present invention, since both the source electrode and the drain electrode form an ohmic contact with the epitaxial structure, that is to say, the drain electrode and the source electrode are electrically connected to the two-dimensional electron gas in the active region and the heterojunction structure, and there is a parasitic capacitance between the source electrode structure and the drain electrode structure. By providing an auxiliary via hole between the active region and the source via hole, and the auxiliary via hole penetrates the heterojunction structure, that is, the electrical connection between the active region and the source via hole is blocked, the parasitic capacitance between the source electrode structure and the drain electrode structure can be reduced, and the performance of the semiconductor device can be improved.

[0074] Optionally, continuing to refer to Figure 1 and Figure 2 , along the second direction (the Y direction shown in the figure), the length between the two outermost boundaries of the auxiliary via hole 70 is greater than the length of the active region aa in this direction; the second direction Y is parallel to the plane where the substrate 20 is located and intersects with the first direction X. It can be understood that along the second direction, the auxiliary via hole 70 can be a single via hole, then the length of the auxiliary via hole 70 (that is, the length between the two outermost boundaries) is greater than the length of the active region aa; the auxiliary via hole 70 can also be an arrangement of at least two along the second direction, then the length between the two outermost boundaries of all the auxiliary via holes 70 is greater than the length of the active region aa.

[0075] Specifically, along the second direction Y, the length of the auxiliary through-hole 70 is greater than the length of the active region aa, so that the parasitic capacitance between the source electrode structure 40 and the drain electrode structure 50 can be further reduced through the auxiliary through-hole 70, which is beneficial to ensuring the working performance of the semiconductor device.

[0076] Optionally, continue to refer to Figure 2 , along the first direction X, the average opening diameter of the auxiliary through-hole 70 is greater than the average opening diameter of the source through-hole 60.

[0077] It can be understood that, ideally, the cross-sectional shapes of the source through-hole 60 and the auxiliary through-hole 70 can both be rectangular. However, due to the limitation of the production process accuracy, the cross-sectional shapes of the source through-hole 60 and the auxiliary through-hole 70 are approximately trapezoidal. Therefore, the average opening diameter can be used to measure the opening widths of the auxiliary through-hole 70 and the source through-hole 60.

[0078] Specifically, along the first direction X, the average opening diameter of the auxiliary through-hole 70 is greater than the average opening diameter of the source through-hole 60. Exemplarily, the average opening diameter of the auxiliary through-hole 70 can be 5 μm. Since the auxiliary through-hole 70 penetrates the two-dimensional electron gas, setting a larger average opening diameter can further improve the blocking effect on the two-dimensional electron gas. In addition, since a material with a smaller dielectric constant can be filled in the auxiliary through-hole 70, it is beneficial to further reduce the parasitic capacitance between the source electrode structure 40 and the drain electrode structure 50, and thus can further improve the performance of the semiconductor device.

[0079] Optionally, Figure 3 is a top view schematic diagram of another semiconductor device provided by an embodiment of the present invention. The figure, Figure 4 is Figure 3 a schematic cross-sectional structure diagram of a semiconductor device along the section line B-B' provided, as Figures 1 - 4 shown, an auxiliary medium 701 is filled in the auxiliary through-hole 70, and the average dielectric constant of the auxiliary medium 701 is smaller than the average dielectric constant of the film layer penetrated by the auxiliary through-hole 70.

[0080] Specifically, since the auxiliary through-hole 70 can penetrate the substrate 20 and the epitaxial structure 30, that is to say, the auxiliary through-hole 70 penetrates multiple film layers. The average dielectric constant of the film layer can be understood as the average value of the dielectric constants of different film layers. The average dielectric constant of the auxiliary medium 701 is smaller than the average dielectric constant of the film layer penetrated by the auxiliary through-hole 70, and thus the parasitic capacitance between the source electrode structure 40 and the drain electrode structure 50 can be reduced, and the performance of the semiconductor device can be improved.

[0081] As a feasible implementation manner, continue to refer to Figure 1 and Figure 2, the auxiliary medium 701 includes a solid medium 7011, and the back electrode 10 covers the auxiliary via 70. Specifically, the dielectric constant of the solid medium 7011 is less than the average dielectric constant of the film layer penetrated by the auxiliary via 70, thereby reducing the parasitic capacitance between the source electrode structure 40 and the drain electrode structure 50 and improving the performance of the semiconductor device.

[0082] As another feasible implementation, referring to Figure 3 and Figure 4 , the auxiliary medium 701 includes air, and the back electrode 10 includes a hollowed-out portion 101, and the hollowed-out portion 101 exposes at least a part of the auxiliary via 70.

[0083] Specifically, the auxiliary medium 701 includes air, that is, no other material is filled in the auxiliary via 70. During the preparation of the semiconductor device, after the auxiliary via 70 is prepared, a sacrificial material can be filled into the auxiliary via 7 first to prevent the back electrode material from being deposited into the auxiliary via 70 during the subsequent preparation of the back electrode 10. After the back electrode 10 is prepared, the hollowed-out portion 101 can be formed by etching the back electrode 10 so that the hollowed-out portion 101 exposes the auxiliary via 70. That is to say, along the thickness direction of the semiconductor device, the hollowed-out portion 101 overlaps with the auxiliary via 70, that is, the sacrificial material can be removed through the hollowed-out portion 101. In this way, on the one hand, the diversity of the setting of the auxiliary via 70 can be improved, and on the other hand, the parasitic capacitance between the source electrode structure 40 and the drain electrode structure 50 can be reduced, improving the performance of the semiconductor device.

[0084] It should be noted that Figure 4 only shows the technical solution in which the hollowed-out portion 101 completely exposes the auxiliary via 70. It can be understood that the hollowed-out portion 101 can also only expose a part of the auxiliary via 70. The specific setting manner of the hollowed-out portion 101 and the auxiliary via 70 in the embodiments of the present invention is not limited, as long as it is ensured that the hollowed-out portion 101 overlaps with the auxiliary via 70, and the sacrificial medium filled in the auxiliary via 70 can be removed through the hollowed-out portion 101.

[0085] Optionally, Figure 5 is Figure 1 another schematic cross-sectional structure diagram of the semiconductor device along the section line A-A', Figure 6 is Figure 1 yet another schematic cross-sectional structure diagram of the semiconductor device along the section line A-A', as Figure 2 , Figure 4 , Figure 5 and Figure 6As shown, the epitaxial structure 30 includes a channel layer 303 and a barrier layer 304 on the side of the channel layer 303 away from the substrate 20, and a heterojunction structure is provided between the channel layer 303 and the barrier layer 304; the auxiliary through hole 70 penetrates at least the substrate 20 and the channel layer 303; alternatively, the auxiliary through hole 70 penetrates at least the barrier layer 304 and the channel layer 303.

[0086] As a feasible implementation manner, continue to refer to Figure 2 and Figure 4 , the auxiliary through hole 70 completely penetrates the substrate 20 and the epitaxial structure 30. As another feasible implementation manner, continue to refer to Figure 5 , the auxiliary through hole 70 penetrates at least the substrate 20 and the channel layer 303, that is, the upper surface of the auxiliary through hole 70 stops at the junction position between the channel layer 303 and the barrier layer 304 and does not penetrate the barrier layer 304. Alternatively, the upper surface of the auxiliary through hole 70 can also stop inside the barrier layer 304, that is, partially penetrate the barrier layer (not shown in the figure). As yet another feasible implementation manner, continue to refer to Figure 6 , the auxiliary through hole 70 penetrates at least the barrier layer 304 and the channel layer 303, that is, after the epitaxial structure 30 is fabricated on one side of the substrate 20, the auxiliary through hole 70 is provided in the direction pointing from the epitaxial structure 30 to the substrate 20, so that the auxiliary through hole 70 can penetrate the barrier layer 304 and the channel layer 303. In summary, on the one hand, the diversity of the setting of the auxiliary through hole 70 can be realized, and on the other hand, the parasitic capacitance between the source electrode structure 40 and the drain electrode structure 50 can be reduced by the auxiliary through hole 70 penetrating the heterojunction structure, thereby improving the performance of the semiconductor device.

[0087] Optionally, Figure 7 is a top view schematic diagram of another semiconductor device provided by an embodiment of the present invention. As shown in Figure 1 and Figure 7 , the first direction is the same as the extending direction of the source electrode 401; alternatively, the first direction is the same as the arrangement direction of the source electrode 401 and the drain electrode 501.

[0088] Furthermore, continue to refer to Figure 1 , the first direction is the same as the extending direction of the source electrode 401; the conductor device further includes a gate electrode structure 80, the gate electrode structure 80 includes a gate 801 located in the active region aa and a gate power supply electrode 802 located in the passive region bb, and the gate power supply electrode 802 is electrically connected to the gate 801; the source power supply electrode 402 is located on the side of the gate power supply electrode 802 away from the active region aa, or the source power supply electrode 402 is located on the side of the drain power supply electrode 502 away from the active region aa.

[0089] Preferably, when the source power supply electrode 402 is located on the side of the gate power supply electrode 802 away from the active region aa, the auxiliary via 70 is located between the source power supply electrode 402 and the gate power supply electrode 802; or when the source power supply electrode 402 is located on the side of the drain power supply electrode 502 away from the active region aa, the auxiliary via 70 is located between the source power supply electrode 402 and the drain power supply electrode 502. Such a setting is beneficial to reducing the process difficulty, reducing the risk of device failure, and preventing the auxiliary via 70 from affecting the device during the etching process.

[0090] As a feasible implementation manner, the source power supply electrode 402 is located on one side of the gate power supply electrode 802 and close to the edge of the semiconductor device, so that the degree of freedom in the design of the source power supply electrode 402 can be improved.

[0091] It can be understood that Figure 1 Only the technical solution in which the source power supply electrode 402 is located on the side of the gate power supply electrode 802 away from the active region aa is shown. It can be understood that the source power supply electrode 402 is located on the side of the drain power supply electrode 502 away from the active region aa, that is to say, the source power supply electrode 402 can be located on one side of the drain power supply electrode 802 and close to the edge of the semiconductor device. In this way, by setting the auxiliary via 70, the parasitic capacitance between the source electrode structure 40 and the drain electrode structure 50 can be reduced.

[0092] As another feasible implementation manner, continue to refer to Figure 7 , the first direction is the same as the arrangement direction of the source 401 and the drain 501, that is, along the arrangement direction of the source 401 and the drain 501, the source power supply electrode 402 can be located at the edge position of the semiconductor device. In this way, a diversified setting of the semiconductor device can be realized, and the degree of freedom in setting the source power supply electrode 402 in the passive region bb can be improved.

[0093] It should be understood that from the perspective of semiconductor device design, embodiments of the present invention can reduce the parasitic capacitance between the source electrode structure and the drain electrode structure by providing auxiliary vias, thereby improving the performance of semiconductor devices. The semiconductor devices include but are not limited to: high-power high electron mobility transistors (HEMTs) operating in high-voltage and high-current environments, transistors with a silicon-on-insulator (SOI) structure, gallium arsenide (GaAs)-based transistors, metal-oxide-semiconductor field-effect transistors (MOSFETs), metal-insulator-semiconductor field-effect transistors (MISFETs), double heterojunction field-effect transistors (DHFETs), junction field-effect transistors (JFETs), metal-semiconductor field-effect transistors (MESFETs), metal-insulator-semiconductor heterojunction field-effect transistors (MISHFETs), or other field-effect transistors. The auxiliary vias provided in the semiconductor devices according to embodiments of the present invention can be widely used in the manufacturing fields of semiconductor devices such as radio frequency and microwave, and power electronics. In particular, for gallium nitride electronic devices with a large bandgap, high electron mobility, high breakdown field strength, and good thermal conductivity, the advantages are more obvious, and they can better meet the high-performance requirements of rapidly developing fields such as electronic communication.

[0094] Based on the same inventive concept, embodiments of the present invention also provide a method for manufacturing a semiconductor device. Figure 8 FIG. is a schematic flowchart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention. Figure 9 is Figure 8 a corresponding process flowchart of a method for manufacturing a semiconductor device, as Figure 8 and Figure 9 shown, the method for manufacturing a semiconductor device includes:

[0095] S101. Provide a substrate and fabricate an epitaxial structure on one side of the substrate; a heterojunction structure is provided in the epitaxial structure.

[0096] Specifically, the heterojunction structure can generate a two-dimensional electron gas. A two-dimensional electron gas is retained between the channel layer and the barrier layer in the active region, and the two-dimensional electron gas in the passive region is removed through treatment, but there may be a small amount of two-dimensional electron gas due to leakage.

[0097] Specifically, continue to refer to Figure 9 In step a1 of [reference], the substrate 20 can be one or a combination of gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, indium phosphide, gallium arsenide, silicon carbide, diamond, sapphire, germanium, silicon, etc. The substrate 20 can also be any other material capable of growing group III nitrides. The epitaxial structure 30 on one side of the substrate 20 can be formed by one or more of group III-V nitrides such as gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum nitride, or indium aluminum gallium nitride.

[0098] S102. Fabricate a source electrode structure and a drain electrode structure on the side of the epitaxial structure away from the substrate; the source electrode structure includes a source in the active region and a source power supply electrode in the passive region, the drain electrode structure includes a drain in the active region, both the source and the drain form an ohmic contact with the epitaxial structure, and the source power supply electrode is electrically connected to the source.

[0099] Specifically, continue to refer to Figure 9 In step b1 of [reference], both the source 401 and the drain 501 can form an ohmic contact with the epitaxial structure 30. Exemplarily, the source 401 can be used as the input end of the semiconductor device, and the drain 501 can be used as the output end of the semiconductor device. It should be noted that the semiconductor device may further include a gate 801, and the gate 801 can be used as the control end of the semiconductor device. The current flow between the source 401 and the drain 501 can be achieved by controlling the voltage of the gate 801. That is, when a certain voltage is applied to the gate 801, a current will be generated between the source 401 and the drain 501, and the current between the source 401 and the drain 501 can be controlled by changing the voltage of the gate 801.

[0100] S103. Fabricate a source via hole and an auxiliary via hole. The source via hole penetrates through the substrate and the epitaxial structure, and the auxiliary via hole penetrates at least through the heterojunction structure; along a first direction, the auxiliary via hole is located between the source via hole and the active region, and the first direction is parallel to the plane where the substrate is located.

[0101] Specifically, continue to refer to Figure 9In step c1, the substrate 20 and the epitaxial structure 30 can be etched simultaneously by an etching process to form a source via 60 and an auxiliary via 70. Along the first direction X, by arranging the auxiliary via 70 between the active region aa and the source via 60, and the auxiliary via 70 penetrating the heterojunction structure, the contact between the source electrode 401 and the two-dimensional electron gas can be blocked in the passive region bb. In this way, the parasitic capacitance between the source electrode structure 40 and the drain electrode structure 50 can be reduced along the first direction X, thereby improving the performance of the semiconductor device.

[0102] Furthermore, the source via 60 and the auxiliary via 70 are prepared by the same mask process. By the same mask process, the source via 60 and the auxiliary via 70 with the same depth can be prepared, or the source via 60 and the auxiliary via 70 with different depths can be prepared by a grayscale mask process. In this way, the process flow can be simplified, and only one photomask can be used to prepare two vias.

[0103] It should be noted that the grayscale mask process can provide variable transmittance at different positions on the mask plane, that is, the transmittance of light is different at different positions on the same plane. The same mask process can adopt a half-tone mask (HTM) process. The HTM process forms two different film thicknesses by exposing through the partial light-transmitting characteristics of specific regions.

[0104] S104. Prepare a back electrode, and the back electrode is electrically connected to the source power supply electrode through the source via.

[0105] Specifically, continue to refer to Figure 9 In step d1, a back electrode 10 is prepared on the side of the substrate 20 away from the epitaxial structure 30. That is to say, the back electrode 10 is located on the lower surface of the substrate 20. The back electrode 10 is electrically connected to the source power supply electrode 402 through the source via 60. The metal material in the source via 60 can be the same as the metal material used for the back electrode 10.

[0106] In the method for preparing a semiconductor device provided in this embodiment of the present invention, by arranging an auxiliary via between the active region and the source via, and the auxiliary via penetrating the two-dimensional electron gas, the contact between the source and the two-dimensional electron gas can be blocked in the passive region, that is, the parasitic capacitance between the source electrode structure and the drain electrode structure can be reduced, and the performance of the semiconductor device can be improved. In addition, by using the same mask process to prepare the source via and the auxiliary via, the process flow can be simplified, and only one photomask can be used to prepare two vias, saving production costs.

[0107] Optionally, Figure 10 is a schematic flowchart of another method for preparing a semiconductor device provided in an embodiment of the present invention. Figure 11 For Figure 10Process flow chart of a preparation method of a corresponding semiconductor device Figure 10 and Figure 11 Based on the above embodiments, the operations before preparing the back electrode and the operations for preparing the back electrode are elaborated in detail. For example Figure 10 and Figure 11 As shown, the preparation method of the semiconductor device includes:

[0108] S201. Provide a substrate and prepare an epitaxial structure on one side of the substrate; a heterojunction structure is provided in the epitaxial structure.

[0109] S202. Prepare a source electrode structure and a drain electrode structure on the side of the epitaxial structure away from the substrate; the source electrode structure includes a source located in the active region and a source power supply electrode located in the passive region, the drain electrode structure includes a drain located in the active region, both the source and the drain form ohmic contacts with the epitaxial structure, and the source power supply electrode is electrically connected to the source.

[0110] S203. Prepare a source via hole and an auxiliary via hole. The source via hole penetrates through the substrate and the epitaxial structure, and the auxiliary via hole penetrates through at least the heterojunction structure; along a first direction, the auxiliary via hole is located between the source via hole and the active region, and the first direction is parallel to the plane where the substrate is located.

[0111] S204. Fill an auxiliary medium in the auxiliary via hole, and the average dielectric constant of the auxiliary medium is less than the average dielectric constant of the film layer penetrated by the auxiliary via hole.

[0112] Specifically, continue to refer to Figure 11 Step d2 in. Fill the auxiliary medium 701 in the auxiliary via hole. The auxiliary via hole 70 penetrates through multiple film layers. That is, the average dielectric constant of the film layer can be understood as the average value of the dielectric constants of different film layers. The average dielectric constant of the auxiliary medium is less than the average dielectric constant of the film layer penetrated by the auxiliary via hole 70, thereby reducing the parasitic capacitance between the source electrode structure and the drain electrode structure and improving the performance of the semiconductor device.

[0113] Exemplarily, the auxiliary medium 701 can be a solid medium 7011.

[0114] It should be noted that Figure 11 Step a2, step b2 and step c2 in respectively correspond to Figure 11 Step a1, step b1 and step c1 in.

[0115] S205. Fill a connection medium in the source via hole, and the connection medium is electrically connected to the source power supply electrode.

[0116] Specifically, continue to refer to Figure 11In step d2, a connection medium 601 is filled in the source via, and the source power supply electrode 402 is connected to the back electrode 10 in the subsequent process through the connection medium 601 in the source via 60. The connection medium 601 belongs to a dielectric and mainly contains metal materials.

[0117] S206. Prepare a whole-surface back electrode that covers the auxiliary via, and the back electrode is electrically connected to the connection medium in the source via, or the back electrode is reused as the connection medium. The back electrode is electrically connected to the source power supply electrode through the source via.

[0118] Specifically, continue to refer to Figure 11 In step e1, the back electrode 10 covers the auxiliary via 70, and the back electrode 10 is electrically connected to the source power supply electrode 402 through the source via 60. Further, the back electrode 10 is electrically connected to the connection medium 601, or the back electrode 10 is reused as the connection medium 601. That is to say, the connection medium 601 in the source via 60 can be filled with a material different from that of the back electrode 10 or the same material as the back electrode 10.

[0119] The method for manufacturing a semiconductor device provided by the embodiment of the present invention can reduce the parasitic capacitance between the source electrode structure and the drain electrode structure by filling an auxiliary medium with a smaller dielectric constant in the auxiliary via, thereby improving the performance of the semiconductor device.

[0120] Optionally, Figure 12 is a schematic flow chart of another method for manufacturing a semiconductor device provided by the embodiment of the present invention, Figure 13 is Figure 12 a process flow chart of a corresponding method for manufacturing a semiconductor device, Figure 12 and Figure 13 On the basis of the above embodiments, the operations before and during the preparation of the back electrode are elaborated in detail. As Figure 12 and Figure 13 shown, the method for manufacturing a semiconductor device includes:

[0121] S301. Provide a substrate and prepare an epitaxial structure on one side of the substrate; a heterojunction structure is provided in the epitaxial structure.

[0122] S302. Prepare a source electrode structure and a drain electrode structure on the side of the epitaxial structure away from the substrate; the source electrode structure includes a source located in the active region and a source power supply electrode located in the passive region, the drain electrode structure includes a drain located in the active region, both the source and the drain form an ohmic contact with the epitaxial structure, and the source power supply electrode is electrically connected to the source.

[0123] S303. Prepare a source via and an auxiliary via. The source via penetrates through the substrate and the epitaxial structure, and the auxiliary via penetrates through at least the heterojunction structure; along a first direction, the auxiliary via is located between the source via and the active region, and the first direction is parallel to the plane where the substrate is located.

[0124] S304. Fill the auxiliary via with a sacrificial dielectric.

[0125] Specifically, continue to refer to Figure 13 Step d3 in. To prevent the back electrode material from depositing into the auxiliary via 70 during the preparation of the entire back electrode, fill the auxiliary via with a sacrificial dielectric 7012. Exemplarily, the sacrificial dielectric 7012 can be a material such as photoresist, so as to remove the sacrificial dielectric in the auxiliary via 70 subsequently.

[0126] It should be noted that Figure 13 Step a3, step b3, and step c3 in respectively correspond to Figure 11 Step a1, step b1, and step c1 in.

[0127] S305. Prepare an entire back electrode, and the back electrode is electrically connected to the source power supply electrode through the source via.

[0128] Specifically, continue to refer to Figure 13 Step e2 in to prepare the entire back electrode 10.

[0129] S306. Pattern the back electrode to form a hollowed-out portion in the back electrode, and the hollowed-out portion exposes at least part of the auxiliary via.

[0130] Specifically, continue to refer to Figure 13 Step f in to pattern the back electrode 10 to form a hollowed-out portion 101 in the back electrode 10, and the hollowed-out portion 101 exposes at least part of the auxiliary via 70, so as to facilitate removing the sacrificial dielectric 7012 through the hollowed-out portion 101.

[0131] It should be noted that Figure 13 Only the technical solution where the hollowed-out portion 101 completely exposes the auxiliary via 70 is shown. In this way, it is more beneficial to remove the sacrificial dielectric 7012 subsequently. It can be understood that the hollowed-out portion 101 can also only expose a part of the auxiliary via 70.

[0132] S307. Remove the sacrificial dielectric through the hollowed-out portion.

[0133] Specifically, continue to refer to Figure 13In step g, the sacrificial dielectric 7012 is removed through the hollow portion 101. Exemplarily, when the sacrificial dielectric 7012 is a photoresist, the sacrificial dielectric 7012 can be removed through the hollow portion 101 by using a developer. That is to say, the auxiliary dielectric filled in the auxiliary through-hole 70 in the finally obtained semiconductor device is air. Since the dielectric constant of air is small, the parasitic capacitance between the source electrode structure 40 and the drain electrode structure 50 can be reduced through the auxiliary through-hole 70, thereby improving the performance of the semiconductor device.

[0134] In the technical solution provided by the embodiment of the present invention, the auxiliary through-hole is filled with air. Since the dielectric constant of air is small, the parasitic capacitance between the source electrode structure and the drain electrode structure can be reduced in this way, thereby improving the performance of the semiconductor device.

[0135] Note that the above is only a preferred embodiment of the present invention and the technical principles applied. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein. Various obvious changes, re-adjustments and substitutions can be made by those skilled in the art without departing from the protection scope of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments. Without departing from the concept of the present invention, more other equivalent embodiments can be included, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A semiconductor device, characterized in that, Comprising: A back electrode, a substrate, and an epitaxial structure, wherein the back electrode, the substrate, and the epitaxial structure are stacked, and a heterojunction structure is provided in the epitaxial structure; A source electrode structure and a drain electrode structure, both located on a side of the epitaxial structure away from the substrate; The source electrode structure includes a source located in an active region and a source power supply electrode located in a passive region. The drain electrode structure includes a drain located in the active region. The source and the drain both form ohmic contacts with the epitaxial structure. The source power supply electrode is electrically connected to the source and is electrically connected to the back electrode through a source via hole. Along a first direction, the source via hole is located on one side of the active region. The first direction is parallel to the plane where the substrate is located; An auxiliary via hole, located between the active region and the source via hole along the first direction, and the auxiliary via hole penetrates through the heterojunction structure.

2. The semiconductor device according to claim 1, wherein Along a second direction, the length between the two outermost boundaries of the auxiliary via hole is greater than the second direction length of the active region. The second direction is parallel to the plane where the substrate is located and intersects with the first direction.

3. The semiconductor device according to claim 1, wherein Along the first direction, the average opening diameter of the auxiliary via hole is greater than the average opening diameter of the source via hole.

4. The semiconductor device according to claim 1, characterized in that, The auxiliary via hole is filled with an auxiliary medium, and the average dielectric constant of the auxiliary medium is less than the average dielectric constant of the film layer penetrated by the auxiliary via hole.

5. The semiconductor device according to claim 4, characterized in that, The auxiliary medium includes a solid medium, and the back electrode covers the auxiliary via hole.

6. The semiconductor device according to claim 4, wherein The auxiliary medium includes air, and the back electrode includes a hollowed-out portion that exposes at least a part of the auxiliary via hole.

7. The semiconductor device according to claim 1, wherein The epitaxial structure includes a channel layer and a barrier layer located on a side of the channel layer away from the substrate, and the heterojunction structure is provided between the channel layer and the barrier layer; The auxiliary via hole penetrates at least the substrate and the channel layer; or, the auxiliary via hole penetrates at least the barrier layer and the channel layer.

8. The semiconductor device according to claim 1, wherein The first direction is the same as the extending direction of the source; Or, the first direction is the same as the arranging direction of the source and the drain.

9. The semiconductor device according to claim 1, wherein, The first direction is the same as the extending direction of the source; The semiconductor device further includes a gate electrode structure, and the gate electrode structure includes a gate located in the active region and a gate power supply electrode located in the passive region. The gate power supply electrode is electrically connected to the gate; The source power supply electrode is located on a side of the gate power supply electrode away from the active region, or the source power supply electrode is located on a side of the drain power supply electrode away from the active region.

10. A method for manufacturing a semiconductor device, characterized in that, Comprising: Providing a substrate and preparing an epitaxial structure on one side of the substrate; A heterojunction structure is provided in the epitaxial structure; Preparing a source electrode structure and a drain electrode structure on a side of the epitaxial structure away from the substrate. The source electrode structure includes a source located in an active region and a source power supply electrode located in a passive region. The drain electrode structure includes a drain located in the active region. The source and the drain both form ohmic contacts with the epitaxial structure. The source power supply electrode is electrically connected to the source; Fabricate a source via and an auxiliary via, where the source via penetrates through the substrate and the epitaxial structure, and the auxiliary via penetrates through at least the heterojunction structure; along a first direction, the auxiliary via is located between the source via and the active region, and the first direction is parallel to the plane where the substrate is located; Fabricate a back electrode, where the back electrode is electrically connected to the source power supply electrode through the source via.

11. The preparation method according to claim 10, characterized in that, Fabricate a source via and an auxiliary via, including: Fabricate the source via and the auxiliary via using the same mask process.

12. The preparation method according to claim 10, wherein Before fabricating the back electrode, further include: Fill the auxiliary via with an auxiliary dielectric, where the average dielectric constant of the auxiliary dielectric is less than the average dielectric constant of the film layer penetrated by the auxiliary via; Fill the source via with a connection dielectric, where the connection dielectric is electrically connected to the source power supply electrode; Fabricate a back electrode, including: Fabricate a full-surface back electrode, where the back electrode covers the auxiliary via, and the back electrode is electrically connected to the connection dielectric or the back electrode is reused as the connection dielectric.

13. The preparation method according to claim 10, wherein Before fabricating the back electrode, further include: Fill the auxiliary via with a sacrificial dielectric; Fabricate a back electrode, including: Fabricate a full-surface back electrode; Pattern the back electrode to form a hollowed-out portion in the back electrode, where the hollowed-out portion exposes at least part of the auxiliary via; Remove the sacrificial dielectric through the hollowed-out portion.

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