Semiconductor device based on heterostructure with back contact region and process for manufacturing same

Abstract

The invention relates to a semiconductor device based on a heterostructure having a back contact region and a process for manufacturing the same. A device based on a heterostructure including a working body and a method of manufacturing the device are provided, the device having a wafer and an epitaxial multilayer extending on the wafer in a direction from a front surface to an upper surface of the wafer. To form the active region, a conductive region of a conductive material is formed on the epitaxial multilayer. In order to form a contact region for biasing the first conductive region: a front trench is formed in the working body, starting from the upper surface of the wafer toward the rear surface as far as the contact surface; on the contact surface, a conductive region is formed within the front trench and is in electrical contact with the first conductive region; a rear trench is formed in the working body, starting from the rear surface toward the upper surface up to the contact surface; and on the contact surface, a back metallization layer is formed on the back surface of the wafer and within the back trench.

Description

Technical Field

[0001] The present disclosure relates to a transistor device based on a heterostructure having a back contact region (such as a high electron mobility transistor (HEMT) device) and a manufacturing process thereof. The present disclosure also relates to a HEMT device for radio frequency (RF) applications. Background Art

[0002] As is well known, HEMT devices are field effect transistor devices based on heterostructures, and they are widely spreading due to the possibility of operating at high voltages, high breakdown voltages, and high electron density and mobility.

[0003] HEMT devices for RF applications generally have better RF performance than similar silicon laterally diffused metal oxide semiconductor (LDMOS) devices.

[0004] The operation of a transistor device based on a heterostructure is based on the formation of a two-dimensional charge carrier (electron) gas at the interface between two different semiconductor materials (usually AlGaN / GaN layers) within the semiconductor heterostructure.

[0005] The transistor device has an active region where the two-dimensional carrier gas forms a conductive channel between two conductive regions (source region and drain region). In addition, the formation of the two-dimensional carrier gas within the active region is electrostatically modulated by the gate region.

[0006] In a HEMT device, the semiconductor heterostructure is grown on a wafer of a different material (such as silicon (Si) or silicon carbide (SiC)) relative to the materials forming the heterostructure.

[0007] In some HEMT devices such as those for RF applications, the source region is electrically contacted from the back of the HEMT device.

[0008] Figure 1 An intermediate step of a known manufacturing process of a HEMT device is shown. In Figure 1 , a semiconductor heterostructure 3 based on a GaN layer has been grown on the front side of a wafer 5 of silicon or silicon carbide. A source metal layer 6 of TiAlCu or gold has been formed on the semiconductor heterostructure 3 and forms the source region.

[0009] A back metal layer 7 of nickel or copper extends on the back side of the wafer 5.

[0010] To form a contact via for the source region, a trench 8 is formed from the back of the wafer 5 through the back metal layer 7 and the wafer 5 until the semiconductor heterostructure 3. The back metal layer 7 is used as a hard mask to form the trench 8.

[0011] Subsequently, Figure 2, from the back of the wafer 5 and through the trench 8 up to the source metal layer 6, the portion of the semiconductor heterostructure 3 exposed by the trench 8 is removed.

[0012] This method allows the use of the same photolithography mask (i.e., the post-metal layer 7) to remove portions of the wafer 5 and the semiconductor heterostructure 3. However, it has been confirmed that this method is difficult to control due to the low etch selectivity between the GaN forming the semiconductor heterostructure 3 and the source metal layer 6.

[0013] In fact, both the semiconductor heterostructure 3 and the source metal layer 6 are etched using a chlorine-based etchant solution.

[0014] In addition, this method makes the implementation of post-etching processes aimed at suppressing the corrosion of the source metal layer 6 (such as when the source metal layer 6 is based on aluminum) and the integration of HEMT devices with other devices (such as if the integration is completed by bonding) difficult.

[0015] Therefore, this method requires a lower manufacturing process yield and a higher manufacturing cost.

[0016] In addition, in known HEMT devices, the lattice mismatch between the material forming the semiconductor heterostructure and the wafer can cause mechanical stress in the wafer. During the dicing of the wafer, the residual mechanical stress can cause cracks and dislocations to propagate towards the active region of the HEMT device, and the HEMT device is very likely to break or malfunction.

[0017] According to one method, before dicing the wafer, an external sealing ring and an internal sealing ring surrounding the active region are formed in the HEMT device.

[0018] The external sealing ring is formed by removing the portion of the semiconductor heterostructure around the active region through the thickness of the semiconductor heterostructure.

[0019] The internal sealing ring is formed by removing the portion of the dielectric layer formed on the HEMT device, around the active region, and between the active region and the external sealing ring. Then the trench formed across both ends of the dielectric layer is filled with a metal layer stack.

[0020] The external sealing ring and the internal sealing ring reduce the risk of crack and dislocation propagation during wafer dicing.

[0021] However, the formation of the external sealing ring and the internal sealing ring requires the introduction of additional manufacturing steps, which may reduce the yield of the entire manufacturing process and increase its cost.

[0022] The purpose of the present disclosure is to overcome at least some of the disadvantages of the prior art. Summary of the Invention

[0023] Accordingly, a transistor device and a manufacturing process based on a heterostructure (such as a HEMT) are provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Reference is now made to the accompanying drawings, in which embodiments of the present disclosure are described by way of non-limiting examples only:

[0025] Figure 1 and Figure 2 show a cross-section of a known HEMT device in a subsequent manufacturing step;

[0026] Figure 3 show a top view of a HEMT device according to one embodiment;

[0027] Figure 4A show Figure 3 a cross-section of a portion of the seal ring region of the HEMT device along the Figure 3 section line IVA-IVA;

[0028] Figure 4B show Figure 3 a cross-section of a portion of the active region of the HEMT device along the Figure 3 section line IVB-IVB;

[0029] Figures 5A to 11A show a HEMT device in a subsequent manufacturing step Figure 3 along the Figure 3 section line IVA-IVA; and

[0030] Figures 5B to 11B show a HEMT device in a subsequent manufacturing step Figure 3 along the Figure 3 section line IVB-IVB. DETAILED DESCRIPTION

[0031] The following description refers to the arrangements shown in the accompanying drawings; accordingly, expressions such as "above", "below", "upper", "lower", "right", "left", "top", "bottom" and the like are related to the accompanying drawings and should not be construed in a limiting manner.

[0032] Figure 3 , Figure 4A and Figure 4B show a heterostructure-based field effect transistor device (such as a high electron mobility transistor (HEMT) device 20) in a Cartesian reference system XYZ, which includes a first axis X, a second axis Y, and a third axis Z.

[0033] The HEMT device 20 is formed in the die 21 and includes an active region 23 and an outer seal ring 25 surrounding the active region 23.

[0034] In this embodiment, the HEMT device 20 further includes an inner seal ring 27 that surrounds the active region 23 and is disposed between the active region 23 and the outer seal ring 25.

[0035] As Figure 4A and Figure 4B can be seen, the die 21 includes a substrate 30 and an epitaxial multilayer 31 extending on the substrate 30.

[0036] The substrate 30 can be formed of one or more layers of silicon, silicon carbide, gallium nitride (GaN), sapphire (Al2O3), or other materials. The substrate 30 can be made of a semiconductor material, such as silicon or silicon carbide.

[0037] The substrate 30 has a front surface 30A and a back surface 30B that face each other.

[0038] The substrate 30 can have a thickness measured along a third axis Z between the front surface 30A and the back surface 30B, for example, between 40 μm and 120 μm. For RF applications, the substrate 30 can have a thin thickness, for example, between 60 μm and 100 μm.

[0039] The epitaxial multilayer 31 extends from the front surface 30A of the substrate 30 to an upper surface 31A and includes a buffer region 32 and a semiconductor heterostructure 33.

[0040] The epitaxial multilayer 31 can have a thickness measured along a third axis Z between the front surface 30A and the upper surface 31A, between 1.5 μm and 5 μm.

[0041] Optionally, the buffer region 32, which is a material different from the substrate 30 (such as AlN, AlGaN, GaN, SiC), extends between the substrate 30 and the semiconductor heterostructure 33 and can be used to allow the semiconductor heterostructure 33 to grow epitaxially on the substrate 30.

[0042] The semiconductor heterostructure 33 is configured to accommodate a two-dimensional gas of (mobile) charge carriers such as electrons.

[0043] Specifically, the semiconductor heterostructure 33 includes two or more compound semiconductor materials that are different from each other and include elements from Group III and Group V of the periodic table.

[0044] The semiconductor heterostructure 33 can be based on GaN, that is, it includes layers containing GaN (such as GaN and alloys including GaN).

[0045] Specifically, although not shown herein, the semiconductor heterostructure 33 may include a channel layer (such as gallium nitride (GaN) or an alloy including gallium nitride (such as InGaN), such as GaN); and a barrier layer, such as a compound based on a ternary or quaternary gallium nitride alloy (such as Al x Ga 1-x N, AlInGaN, In x Ga 1-x N, Al x In 1-x Al, AlScN, such as aluminum gallium nitride (AlGaN)), and the channel layer and the barrier layer cover each other.

[0046] The semiconductor heterostructure 33 forms an upper surface 31A.

[0047] The outer seal ring 25 is a trench (hereinafter referred to as the outer trench 25) that extends along the third axis Z through the thickness of the epitaxial multilayer 31.

[0048] In this embodiment, the outer seal ring 25 also extends partially into the substrate 30 until the lower surface 40. This can allow for the optimization of the manufacturing of this HEMT device and reduce its manufacturing cost.

[0049] In this embodiment, the width of the outer trench 25 (i.e., the width measured along the first axis X in the Figure 4A cross-section) has a decreasing trend from the upper surface 31A towards the lower surface 40. For example, the sidewalls of the outer trench 25 may have a slope of less than 60°, as discussed in detail below with reference to Figure 7A .

[0050] Specifically, the outer trench 25 has a width W SR,t at the upper surface 31A of the epitaxial multilayer 31, which is between, for example, 10 μm and 100 μm, and has a width W SR,b at the lower surface 40, and this width W SR,b is less than the width W SR,t and is between, for example, 5 μm and 95 μm.

[0051] As discussed below, the profile (depth and width trend) of the third axis Z along the outer trench 25 indicates the specific manufacturing process for forming the outer trench 25.

[0052] The inner seal ring 27 includes a metal layer stack 42 that extends on the epitaxial multilayer 31, such as being in direct contact with it on the upper surface 31A.

[0053] In this embodiment, the stack 42 includes a contact region 43 on the epitaxial multilayer 31, and the contact region 43 is made of, for example, Ti, Ta, Al, AlCu, AlSiCu, Au, Ni, and other metal materials; an intermediate region 44 on the contact region 43, and the intermediate region 44 is made of, for example, Ti, Al, AlCu, AlSiCu, Ni, Au, and other metal materials; and an upper region 45 on the intermediate region 44, and the upper region is made of, for example, Ti, Al, AlCu, AlSiCu, Ni, Au, and other metal materials.

[0054] As Figure 3 and Figure 4B shown, the HEMT device 20 includes a source region 50, a drain region 51, and a gate region 52 in the active region 23, which respectively form the source electrode S, the drain electrode D, and the gate electrode G of the HEMT device 20.

[0055] The source region 50 and the drain region 51 extend in contact with the epitaxial multilayer 31 and are respectively formed by a plurality of conductive layers (such as metal layers), and these conductive layers are arranged one on top of the other.

[0056] Specifically, each of the source region 50 and the drain region 51 includes: respective functional portions 50A, 51A made of, for example, Ti, Ta, Al, AlCu, AlSiCu, Au, Ni, and other metal materials, which are in electrical contact (such as ohmic contact) with the semiconductor heterostructure 33; respective first contact portions 50B, 51B made of, for example, Ti, Al, AlCu, AlSiCu, Au, Ni, and other metal materials extending on the respective functional portions 50A, 51A; and respective second contact portions 50C, 51C made of, for example, Ti, Al, AlCu, AlSiCu, Au, Ni, and other metal materials extending on the respective first contact portions 50B, 51B.

[0057] The gate region 52 includes a respective functional portion 52A configured to modulate the formation of 2DEG in the semiconductor heterostructure 33.

[0058] The characteristics of the functional portion 52A depend on the type of the HEMT device 20 (normally-on type or normally-off type). For example, in order to obtain a normally-on device, the functional portion 52A can be made of a metal material, such as to obtain a normally-on device; or in order to obtain a normally-off device, the functional portion 52A can be made of a semiconductor material (such as p-GaN).

[0059] In the case of a HEMT device for RF applications, the HEMT device can be a normally-on type, and for example, the functional portion 52A can be made of a metal material.

[0060] The functional part 52A extends between the functional parts 50A and 51A of the source region 50 and the drain region 51 respectively on the semiconductor heterostructure 33.

[0061] The gate region 52 can be of the insulating type, i.e., it includes an insulating region in contact with the semiconductor heterostructure 33.

[0062] The gate region 52 further includes a gate contact region (not shown here) of a conductive material (such as a metal material) in electrical contact with the functional part 52A for biasing the gate region 52 in use.

[0063] For simplicity, in Figure 3 , the corresponding functional parts 50A, 51A, and 52A of the source 50, drain 51, and gate 52 regions are shown.

[0064] The HEMT device 20 further includes a source contact region 60 extending in the active region 23 ( Figure 4B ) for biasing the source region 50 in use.

[0065] The source contact region 60 includes a front trench 61 extending along the third axis Z from the upper surface 31A through the epitaxial multilayer 30, and a back trench 62 extending along the third axis Z from the back surface 30B of the substrate 30 through the substrate 30 towards the front surface 30A of the substrate 31.

[0066] Specifically, the front trench 61 extends along the third axis Z until it reaches the contact surface 65, and the back trench 62 extends along the third axis Z until it reaches the contact surface 65.

[0067] In fact, the contact surface 65 defines the front trench 61 at the bottom and the back trench 62 at the top.

[0068] In this embodiment, the front trench 61 extends through the thickness of the epitaxial multilayer 31 and for the thickness of the substrate 30. In other words, in this embodiment, the contact surface 65 extends within the substrate 30.

[0069] In this embodiment, the width of the front trench 61 (i.e., the width measured along the first axis X in the Figure 4B cross-section) has a decreasing trend from the upper surface 31A until the contact surface 65. For example, the sidewall of the front trench 61 can have a slope of less than 60°, as will be discussed in detail below with reference to Figure 7B .

[0070] Specifically, the front trench 61 has a width W G,t at the upper surface 31A of the epitaxial multilayer 31, which is between, for example, 15 μm and 100 μm, and has a width W G,b at the contact surface 65, and this width WG,b less than the width W G,t and, for example, between 10 μm and 95 μm.

[0071] As discussed below, the profile (depth and width trends) along the third axis Z of the front trench 61 indicates the specific manufacturing process used to form the front trench 61.

[0072] In one embodiment, the outer trench 25 and the front trench 61 may have the same profile; this may allow for simplification and cost reduction of the manufacturing process.

[0073] The rear trench 62 has a width W measured along the first axis X at the contact surface 65 S , the width W S being different from the width W of the front trench 61 G,b . In this embodiment, the width W of the rear trench 62 S is less than the width W of the front trench 61 G,b .

[0074] This allows for ensuring good contact between the front trench 61 and the rear trench 62.

[0075] The width W S may, for example, be between 8 μm and 93 μm.

[0076] Depending on the process used to form the rear trench 62, the width of the rear trench 62 measured along the first axis X may have a decreasing or substantially constant trend from the rear surface 30B towards the contact surface 65 along the third axis Z.

[0077] The first contact portion 50B and the second contact portion 50C of the source region 50 extend within the front trench 61.

[0078] Specifically, the first contact portion 50B extends on the contact surface 65 and also extends conformally with the sidewalls of the front trench 61. This can ensure that the first contact portion 50B of the source region 50 is continuous between the contact surface 65 and the corresponding functional portion 50A, and thus ensure a good electrical connection.

[0079] A post - metallization region 70 including one or more layers (such as Au, Cu, Al, AlCu, AlSiCu, and other metallic materials) extends on the rear side of the die 21.

[0080] Specifically, on the contact surface 65, the post - metallization region 70 extends on the rear surface 30B of the substrate 30 and within the rear trench 62. The post - metallization region 70 may extend conformally on the sidewalls of the rear trench 62 to obtain a good electrical connection.

[0081] The post-metallization region 70 contacts a first contact portion 50B of the source region 50 within the front trench 61.

[0082] The post-metallization region 70 can be used as a contact electrode for biasing the source region 50.

[0083] An insulating layer can extend on the front side of the die 41, for example, for optimizing the electrical performance of the HEMT device 20, for passivating the HEMT device 20, and / or for other reasons related to the fabrication of the HEMT device 20 (such as serving as a growth, deposition, and / or etching mask).

[0084] A sealing layer 72, such as aluminum oxide, aluminum nitride, silicon oxide, or silicon nitride, can have a portion 72B that is within the active region 23 (i.e., towards the inside within the inner sealing ring 27( Figure 4B ))), on the upper surface 31A on the side of the functional portion 52A of the gate region 52, and extends partially over the contact portion 50A of the source region 50 and the contact portion 51A of the drain region 51. The sealing layer can also have a portion 72A on the upper surface 31A that extends outside the active region 23( Figure 4A ), i.e., extends outside the inner sealing ring 27.

[0085] An insulating layer 73, such as silicon nitride or silicon oxide, can have a portion 73B that extends inside the inner sealing ring 27 over the portion 72B of the sealing layer 72, and a portion 73A that extends outside the inner sealing ring 27 over the portion 72A of the sealing layer 72.

[0086] An insulating layer 74, such as TEOS, silicon oxide, or silicon nitride, can have a portion 74B that extends inside the inner sealing ring 27 over the die 21, for example, within the active region 23 above portions of the source 50, drain 51, and gate 52 regions( Figure 4B ); and a portion 74A that extends outside the inner sealing ring 27 over the die 21( Figure 4A ), above the insulating layer 73 or directly on the epitaxial multilayer 31.

[0087] As Figure 4A can be seen, the inner sealing ring 27 extends along the third axis Z through the entire thickness of the insulating layer 72, the insulating layer 73, and the insulating layer 74, up to the upper surface 31A of the epitaxial multilayer 31. The stack 42 forming the inner sealing ring 27 is an interruption of the insulating layer 72, the insulating layer 73, and the insulating layer 74. In other words, what is disposed inside the inner sealing ring 27 (within Figure 3In the view, the portions 72B, 73B, and 74B of the insulating layers 72, 73, and 74 facing the center of the die 21 are separated by the portions 72A, 73A, and 74A of the insulating layers 72, 73, and 74 disposed outside the inner sealing ring 27 (towards the outer periphery of the die 41).

[0088] Specifically, the insulating layer 74 may also extend within the outer groove 25 forming the outer sealing ring 25, such as conformally extending on the walls of the groove 25.

[0089] Another insulating layer 75, such as silicon nitride and / or polyimide and polyamide, may extend over the insulating layer 74 and the second contact portions 50C and 51C, for example, in such a way that an upper passivation layer of the HEMT device 20 is formed.

[0090] The HEMT device 20 may also include a field plate region 80 of a conductive material (e.g., the same material as the portions 50B and 51B), which extends between the source region 50 and the drain region 51 above the upper surface 31 (at a certain distance from the upper surface 31) in the active region 23. For example, in Figure 4B the field plate region 80 extends over the insulating layer 73.

[0091] The source contact region 60 provides a good electrical connection (such as for RF applications) and high reliability for the source region 50 of the HEMT device 20.

[0092] In addition, the presence of the outer sealing ring and the inner sealing ring allows further improvement in the reliability of the HEMT device 20.

[0093] Hereinafter, the manufacturing process steps of the HEMT device 20 are described with reference to Figure 4A and Figure 4B the cross-sections.

[0094] Specifically, Figures 5A to 11A shows Figure 4A the subsequent manufacturing steps of the portion of the sealing ring region shown, and Figures 5B to 11B shows Figure 4B the subsequent manufacturing steps of the portion of the active region 23 shown.

[0095] Therefore, in the description of the manufacturing process, the elements common to those already described with reference to Figure 4A and 4B are indicated by the same reference numerals and are not described in further detail.

[0096] Figure 5A and Figure 5BShows a working body 100 including a wafer 130, which is formed of, for example, one or more layers of silicon, silicon carbide, gallium nitride (GaN), sapphire (Al2O3), or other materials. In this embodiment, the wafer 130 is of a semiconductor material (such as silicon or silicon carbide).

[0097] The wafer 130 has a front surface 130A and a back surface 130B that face each other.

[0098] The wafer 130 is intended to form a substrate 30.

[0099] An epitaxial multilayer 31 has been grown on the wafer 130.

[0100] In addition, contact regions 43 ( Figure 5A ), as well as functional portions 50A, 51A, and 52A of the source 50, drain 51, and gate 52 regions ( Figure 5B ) have been formed on the epitaxial multilayer 31, respectively.

[0101] The regions 43 and portions 50A, 51A can be formed starting from the same metal layer, for example, by deposition and subsequent selective removal or by masked deposition and lift-off.

[0102] Still referring to Figure 5A and Figure 5B , a working sealing layer 133, such as alumina, aluminum nitride, silicon oxide, or silicon nitride, which is intended to form a sealing layer 72, is formed on the front side of the working body 100.

[0103] Subsequently, Figure 6A and Figure 6B , an insulating layer 73 is formed on the working sealing layer 133. For example, the insulating layer 73 can be formed by blanket deposition and subsequent masking, lithography, and etching steps.

[0104] At portions of the semiconductor heterostructure 33 that are intended to form an external trench 25 ( Figure 4A ) and a front trench 61 ( Figure 4B ) respectively, two openings 135, 136 are formed through the insulating layer 73 and the working sealing layer 133.

[0105] The openings 135, 136 expose the upper surface 31A of the epitaxial multilayer 31.

[0106] Then, Figure 7A and 7B , the external trench 25 is formed in the opening 135, and the front trench 61 is formed in the opening 136.

[0107] Specifically, a mask 140, such as a material that can be patterned by lithography (such as photoresist), is formed on the working body 100. The mask 140 has two windows 137 and 138 within the openings 135 and 136, respectively.

[0108] As a first approximation, the window 138 may have a width W as described with reference to the front trench 61 along the first axis X G,t ( Figure 4B ).

[0109] As a first approximation, the window 137 may have a width W as described with reference to the external trench 25 along the first axis X SR,t ( Figure 4A )

[0110] To form the external trench 25 and the front trench 61, an etchant configured to remove the material forming the epitaxial multilayer 31 is used to remove (etch) the epitaxial multilayer 31 within the windows 137 and 138.

[0111] For example, in the case where the epitaxial multilayer 31 includes a GaN-based material, the etchant may be a chlorine-based mixture.

[0112] The removal of the epitaxial multilayer 31 may be plasma-mediated etching in an environment including Cl2, BCl3, and Ar.

[0113] The use of BCl3 can allow control of the etching rate and the slope of the sidewalls 145 and 146 of the trenches 25 and 61. Increasing the BCl3 concentration allows reducing the etching rate and decreasing the slope of the sidewalls 145 and 146 (i.e., it allows obtaining trenches with a greater difference between the upper width at the surface 31A and the lower width at the surfaces 40 and 65).

[0114] The use of Ar allows control of the etching rate, the selectivity of the etching to the mask 140, and the profile of the trenches 25 and 61. Increasing the Ar concentration allows increasing the selectivity to the mask 140 and increasing the slope of the sidewalls 145 and 146 (i.e., it allows obtaining trenches with a more uniform width along the third axis Z; in other words, it allows obtaining a smaller difference between the upper width at the surface 31A and the lower width at the surfaces 40 and 65).

[0115] In one embodiment, the etchant may be adjusted such that the sidewalls 145 and 146 form an angle α less than 60° in a direction parallel to the first axis X, and the angle α is between 30° and 60°.

[0116] The etching time may be selected as a function of the thickness of the epitaxial multilayer 31 and the desired thickness of the trenches 25 and 61.

[0117] For example, the fact that the trenches 25, 61 are formed such that the surfaces 40, 65 extend within the wafer 130 can ensure the complete removal of the epitaxial multilayer 31 and thus optimize the fabrication of the present HEMT device. For example, in the case where the wafer 130 is silicon, the portions of the trenches 25, 61 extending within the wafer 130 can be formed through the openings 137, 138 and over-etched with the same etchant used for removing the epitaxial multilayer 31, with respect to the etching time required for removing the epitaxial multilayer 31. For example, in the case where the wafer 130 is silicon carbide, the portions of the trenches 25, 61 extending within the wafer 130 can be formed from the back side.

[0118] Then the mask 140 is removed.

[0119] In this embodiment, the same mask 140 is used to form the external trench 25 and the front trench 61. This allows for obtaining good uniformity of thickness and width between the external trench 25 and the front trench 61 across both ends of the entire die 21 and between different dies obtained by cutting the working body 100.

[0120] Furthermore, the fact that the same etching mask 140 is used to form the external trench 25 and the front trench 61 allows for the simultaneous formation of the external trench 25 and the front trench 61 (in other words, with the same etching step). Thus, the external trench 25 and the front trench 61 can have the same profile (the same depth along the third axis Z and the same slope of the sidewalls 145, 146).

[0121] Then, as Figure 8A 、 Figure 8B shown, the metal layer 150 is deposited and patterned to form the intermediate region 44 of the internal sealing ring 27, the first contact portions 50B, 51B of the source 50 and drain 51 regions, and also to form the field plate region 80 in this embodiment.

[0122] A slope of the sidewall 146 of the front trench 61 lower than 60° can ensure good continuity (consistency) of the metal layer 150 between the contact surface 65 and the functional portion 50A within the front trench 61.

[0123] Subsequently, Figure 9A 、 Figure 9B , for example, through deposition, photolithography, and etching steps, an insulating layer 74 is formed on the working body 100. A slope of the sidewall 145 of the external trench 25 lower than 60° can ensure good continuity (consistency) of the insulating layer 74 between the lower surface 40 and the upper surface 31A.

[0124] In Figure 10A and 10BIn [the figure], a metal layer 151 is deposited on a working body 100 and patterned to form an upper region 45 of an internal seal ring 27 and second contact portions 50C, 51C of source 50 and drain 51 regions.

[0125] Still referring to Figure 10A , Figure 10B , a passivation layer 75 is formed on the front side of the working body 100.

[0126] Subsequently, Figure 11A , Figure 11B , the wafer 130 is thinned starting from the back surface 130B until a thickness, for example, between 40 μm and 120 μm is obtained, as previously discussed with reference to the substrate 30. Thinning may be optional. Thinning may be useful in the case where the HEMT device 20 is used for RF applications.

[0127] A mask 160 is formed on the back surface 130B of the wafer. The mask 160 has a window 162 that exposes a portion of the wafer 130 below the contact surface 65.

[0128] The width of the window 162 is smaller than the width of the window 138 ( Figure 7B ).

[0129] A back trench 62 is formed by removing the portion of the wafer 130 exposed by the mask 160 starting from the back surface 130B until the contact surface 65. For example, in the case where the wafer 130 is silicon or silicon carbide, a fluorine-based etchant can be used to remove the wafer 130.

[0130] The windows 138 and 162 of the mask 140 and the mask 160 are not self-aligned with each other respectively. Thus, the fact that the width of the window 162 (formed after the mask 140) is smaller than the width of the window 138 allows compensation for possible lithographic misalignment in the formation of the mask 140 and the mask 160 to obtain good alignment between the trench 61 and the trench 62, and thus obtain a good electrical connection between the portion 50B of the source region 50 and the post-metallization layer 70.

[0131] For example, in order to thin the wafer 130 and form the back trench 62, a temporary support (not shown here) can be bonded to the front side of the working body 100.

[0132] Subsequently, a post-metallization layer 70 is deposited on the back side of the working body 100, on the back surface 130B, and within the back trench 62 by a means not shown here.

[0133] Finally, the final manufacturing steps follow, which are not shown here and are known per se, such as cutting the working body 100 and forming electrical connections, thereby obtaining the HEMT device 20.

[0134] The fact that the source contact region 60 is formed by removing the material forming the epitaxial multilayer 31 from the front side of the working body 100 and removing the material forming the wafer 130 from the back side of the working body 100 allows for accurate control of the formation of the front trench 61 and the back trench 62.

[0135] In fact, both the epitaxial multilayer 31 and the wafer 130 can be removed using a highly selective etchant, such as when the semiconductor heterostructure 33 is based on a layer containing GaN.

[0136] Specifically, such as when the wafer 130 is silicon or silicon carbide, the etchant for removing the wafer 130 can have high selectivity with respect to the metal material forming the first contact portion 50B of the source region 50 within the front trench 61 (such as if based on aluminum). Thus, the formation of the source contact region 60 can accordingly have a lower risk of damaging the metal region within the front trench 61.

[0137] Therefore, the formation of the source contact region 60 can have a high yield.

[0138] In addition, in the illustrated embodiment, the same mask 140 can be used to simultaneously form the front trench 61 and the external trench 25. This allows for optimizing the number of manufacturing steps for forming the external seal ring 25 and the source contact region 60. Thus, the HEMT device 20 can have a lower manufacturing cost and a higher manufacturing yield.

[0139] Finally, modifications and variations can be made to the HEMT device and its manufacturing process described and illustrated herein without departing from the scope of the present disclosure.

[0140] For example, the front trench 61 can be formed after the back trench 62. In this case, the width of the front trench 61 can be smaller than the width of the back trench 62.

[0141] The external trench 25 and the front trench 61 can be formed using two different masks and / or etching steps.

[0142] Depending on the specific design layout, the front trench 61 and the back trench 62 can have equal or different trends along the second axis Y. For example, the front trench 61 and / or the back trench 62 can extend in the shape of an elongated strip along the second axis Y, or they can have different shapes.

[0143] The source contact region 60 can be one of a plurality of source contact regions.

[0144] In an alternative embodiment, the back contact region can be used to contact different conductive regions of the transistor device from the back, such as contacting the drain region 51 instead of the source region 50. In this case, the first contact portion 51B of the drain region 51 can extend within the front trench 61.

[0145] For example, the source region 50 and the drain region 51 can have different numbers of contact portions, depending on the number of interconnect metal layers of the HEMT device.

[0146] Depending on the specific application, the top view layout of the source, drain, and gate regions can be different from Figure 3 that shown.

[0147] The functional portions 50A of the source region 50 and the functional portion 51A of the drain region 51 can also extend within the semiconductor heterostructure 33.

[0148] The contact surface 65 of the source contact region 60 may not extend within the substrate 30 either; for example, it can extend within the epitaxial multilayer 31 or at the front surface 30A of the substrate 30.

[0149] For example, the inner seal ring 27 and / or the outer seal ring 25 may not be present.

[0150] Finally, the different embodiments described above can be combined to provide other solutions.

[0151] A process for manufacturing a heterostructure-based transistor device (20) starting from a working body (100), the working body being generally comprised of a wafer (130) and an epitaxial multilayer (31), the wafer having a front surface (130A) and a back surface (130B), the epitaxial multilayer (31) extending on the wafer along a first direction (Z) from the front surface of the wafer until an upper surface (31A), the manufacturing process comprising: forming an active region (23), including forming a first conductive region (50A) of conductive material on the epitaxial multilayer; and forming a contact region (60) for biasing the first conductive region, wherein forming the contact region includes: forming a front trench (61) in the working body (100), starting from the upper surface (31A) of the epitaxial multilayer and towards the back surface (130B) of the wafer until a contact surface (65); forming a conductive region (50B, 50C) that extends within the front trench (61) and is in electrical contact with the first conductive region (50A) on the contact surface (65); forming a back trench (62) in the working body (100), starting from the back surface (130B) of the wafer and towards the upper surface of the epitaxial multilayer until the contact surface; and forming a back metallization layer (70) on the back surface of the wafer and within the back trench on the contact surface.

[0152] Forming the front trench includes forming a first etch mask (140) having a window (138) on the upper surface (31A) of the epitaxial multilayer (31), the window (138) having a first width (W G,t ) along a second direction (X) transverse to the first direction (Z), and forming the rear trench (62) includes forming a second etch mask (160) having a window (162) on the rear surface (130B) of the wafer (130), the window (162) having a second width (W S ) different from the first width along the second direction (X).

[0153] The front trench (61) is formed before the rear trench (62), and the first width is greater than the second width.

[0154] The manufacturing process further includes forming an external seal ring (25) around the active region (23), wherein forming the external seal ring includes forming an external trench (25) in the working body (100), starting from the upper surface (31A) of the epitaxial multilayer and extending towards the rear surface (130B) of the wafer until the lower surface (40).

[0155] The external trench (25) and the front trench (61) are formed using the same etch mask (140).

[0156] The front trench (61) extends through the thickness of the epitaxial multilayer (31) along the first direction (Z).

[0157] The contact surface (65) is disposed within the wafer (130).

[0158] The front trench (61) has a width measured along a second direction (X) transverse to the first direction (Z), and the width decreases from the upper surface (31A) towards the contact surface (65).

[0159] The front trench (61) has sidewalls (146), and the sidewalls (146) form an angle (α) less than 60° between the sidewalls and a direction parallel to the second direction (X), the second direction (X) being transverse to the first direction (Z).

[0160] The epitaxial multilayer (31) includes a GaN-based semiconductor heterostructure (33).

[0161] The wafer (130) is a semiconductor material (such as silicon or silicon carbide).

[0162] A transistor device (20) based on a heterostructure is generally described as including: a die (21) including a substrate (30) and an epitaxial multilayer (31), the substrate (30) having a front surface (30A) and a back surface (30B), the epitaxial multilayer (31) extending on the substrate along a first direction (Z) from the front surface of the substrate until an upper surface (31A); an active region (23) including a first conductive region (50A) of conductive material on the epitaxial multilayer; and a contact region (60) for biasing the first conductive region, wherein the contact region includes a front trench (61) that extends in the die (21) from the upper surface (31A) of the epitaxial multilayer toward the back surface (30B) of the substrate until a contact surface (65); conductive regions (50B, 50C) that extend within the front trench (61) on the contact surface (65) and are in electrical contact with the first conductive region; a back trench (62) that extends in the die (21) from the back surface (30B) of the substrate toward the upper surface of the epitaxial multilayer until the contact surface (65); and a back metallization layer (70) that extends on the contact surface on the back surface (30B) of the substrate and within the back trench.

[0163] The front trench (61) has a first width (W G,t ) at the upper surface (31A) along a second direction (X) transverse to the first direction (Z), for example between 15 μm and 100 μm, and has a second width (W G,b ) at the contact surface (65) along the second direction that is less than the first width, for example between 10 μm and 95 μm.

[0164] The device further includes an external seal ring (25) that extends around the active region (23) and includes an external trench in the die that extends from the upper surface (31A) of the epitaxial multilayer toward the back surface (30B) of the substrate until a lower surface (40), the external trench having the same profile as the front trench (61), such as the same depth and the same slope of the sidewalls.

[0165] The device is for radio frequency applications, and the substrate has a thickness between 40 μm and 120 μm along the first direction (Z).

[0166] The various embodiments described above can be combined to provide other embodiments. All U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications, and non-patent publications cited in this specification and / or listed in the application data sheet are hereby incorporated by reference in their entirety. If it is necessary to adopt the concepts of various patents, applications, and publications to provide other embodiments, the various aspects of the embodiments can be modified.

[0167] In view of the foregoing description, these and other modifications may be made to the embodiments. Generally, in the following claims, the terms used should not be construed as limiting the claims to the specific embodiments disclosed in this specification and the claims, but should be construed to include all possible embodiments and the full scope of equivalents to such claims. Accordingly, the claims are not limited by the present disclosure.

Claims

1. A method for manufacturing a device, the device comprising a working body, the working body comprising a wafer and an epitaxial multilayer, the wafer having a front surface and a rear surface, the epitaxial multilayer extending on the wafer along a first direction from the front surface of the wafer to an upper surface, the method comprising: forming an active region, including forming a first conductive region of conductive material on the epitaxial multilayer; as well as forming a contact region for biasing the first conductive region, The contact area includes: forming a front trench in the working body, starting from the upper surface of the epitaxial multilayer towards the rear surface of the wafer, until a contact surface; forming a conductive region on the contact surface extending within the front trench and in electrical contact with the first conductive region; forming a rear trench in the working body, starting from the rear surface of the wafer towards the upper surface of the epitaxial multilayer, up to the contact surface; and A rear metallization layer is formed on the rear surface of the wafer and within the rear trenches over the contact surface.

2. The method of claim 1 , wherein forming the front trench comprises forming a first etch mask having a first window on the upper surface of the epitaxial multilayer, the first window having a first width along a second direction transverse to the first direction; and The forming of the rear trench includes forming a second etching mask having a second window on the rear surface of the wafer, wherein the second window has a second width along the second direction that is different from the first width. 3 . The method of claim 2 , wherein the front trench is formed before the rear trench, and the first width is greater than the second width.

4. The method according to claim 1, further comprising forming an outer seal ring around the active area, wherein forming the outer seal ring comprises: An outer trench is formed in the working body starting from the upper surface of the epitaxial multilayer towards the rear surface of the wafer to the lower surface. The method of claim 4 , wherein the outer trench and the front trench are formed using a same etching mask. The method of claim 1 , wherein the front trench extends through the thickness of the epitaxial multilayer along the first direction. The method of claim 6 , wherein the contact surface is arranged within the wafer. 8 . The method of claim 1 , wherein the front trench has a width measured along the second direction transverse to the first direction, the width decreasing from the upper surface toward the contact surface.

9. The method of claim 1, wherein the front trench has sidewalls that form an angle between the sidewalls and a direction parallel to the second direction, the angle being less than 60°, the second direction being transverse to the first direction.

10. The method of claim 1, wherein the epitaxial multilayer comprises a GaN-based semiconductor heterostructure.

11. The method of claim 1, wherein the wafer is a semiconductor material of silicon or silicon carbide.

12. A device comprising: A die comprising a substrate having a front surface and a back surface and an epitaxial multilayer on the substrate extending along a first direction from the front surface of the substrate to an upper surface; an active region comprising a first conductive region of conductive material on the epitaxial multilayer; as well as a contact region for biasing the first conductive region, The contact area includes: a front trench extending in the die from the upper surface of the epitaxial multilayer toward the rear surface of the substrate up to a contact surface; a conductive region extending within the front trench on the contact surface and in electrical contact with the first conductive region; a back trench extending in the die from the back surface of the substrate towards the upper surface of the epitaxial multilayer up to the contact surface; and A back metallization layer extends on the back surface of the substrate and within the back trench over the contact surface.

13. The device of claim 12, wherein the front trench has a first width between 15 μm and 100 μm at the upper surface along a second direction transverse to the first direction, and has a second width between 10 μm and 95 μm along the second direction at the contact surface, the second width being smaller than the first width.

14. The device according to claim 12 further includes an external sealing ring extending around the active area and including an external trench extending in the tube core from the upper surface of the epitaxial multilayer toward the back surface of the substrate to a lower surface, the external trench having the same profile as the front trench and the same depth and the same slope as the sidewall.

15. The device of claim 12, wherein the device is for radio frequency applications, and wherein the substrate has a thickness along the first direction of between 40 μm and 120 μm.

16. A device comprising: a die having an active area and a substrate, the substrate comprising a first surface and a second surface opposite the first surface; an epitaxial multilayer on the first surface of the substrate, the epitaxial multilayer extending in a first direction from the first surface to an upper surface of the substrate; as well as A trench extends through the epitaxial multilayer in the first direction and partially within the substrate to a lower surface, the trench having a first width along a second direction at the upper surface and a second width along the second direction at the lower surface. 17 . The device of claim 16 , wherein the first width is between 10 μm and 100 μm, and the second width is smaller than the first width.

18. The device of claim 16, wherein the epitaxial multilayer has a thickness between 1.5 μm and 5 μm between the first surface and the upper surface. 19 . The device according to claim 16 , wherein the trench comprises a sidewall, and a width of the sidewall decreases along the second direction from the upper surface toward the lower surface.

20. The device of claim 19, wherein the sidewalls have a slope lower than 60°.

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