Organic semiconductor heterojunction photon synaptic transistor and preparation method thereof

Abstract

The invention belongs to an organic field effect transistor, and particularly relates to an organic semiconductor heterojunction photon synapse transistor and a preparation method thereof. The organic semiconductor heterojunction photon synapse transistor comprises a source electrode, a drain electrode, an organic active layer, a gate insulating layer and a gate electrode, the organic active layer is composed of an N, N '-disalicylidene group-1, 3-diaminopropane layer and a pentacene layer. The transistor provided by the invention has good transistor field effect and photon flash memory performance, has good light control synapse performance, and can realize various types of light synapse functions. And the device is mainly dominated by NSP, the photoresponse rate and the photoresponse dynamic range at 435 nm are maximum, and the near ultraviolet light can be well identified. Due to the relative stability of the small molecule material, the performance of the device does not decline within the temperature range of 120 DEG C, and meanwhile self-adaptive learning can be achieved at different temperatures.

Description

Technical Field

[0001] The present invention belongs to organic field-effect transistors, and particularly relates to an organic semiconductor heterojunction photon synaptic transistor and a preparation method thereof. Background Art

[0002] Photon synaptic transistors have attracted extensive attention in neuromorphic computing due to their high-speed operation, energy efficiency, and the ability to simulate synaptic plasticity through optical stimulation. These devices typically rely on light to initiate the charge transfer process, effectively mimicking the dynamic behavior of biological synapses, which are crucial for learning and memory functions in the human brain. By utilizing light as a stimulus source, photon synaptic transistors provide a powerful tool for brain-inspired computing architectures, where speed, precision, and efficiency are of utmost importance. This unique mechanism gives them great potential in multiple application fields such as artificial intelligence systems, advanced robotics, sensor processing networks, and cognitive computing platforms. Their ability to process and store information makes them a key research area for developing more complex and energy-efficient computing technologies. However, despite these advantages, the implementation of photon synaptic transistors in practical applications still faces significant challenges, especially in terms of temperature stability. Temperature fluctuations can profoundly affect the performance of these devices, leading to degradation of response characteristics and reduced learning efficiency. This problem is particularly critical in environments where temperature control is difficult.

[0003] Therefore, it is of great significance to provide an organic semiconductor heterojunction photon synaptic transistor with temperature stability. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide, in view of the deficiencies of the prior art, an organic semiconductor heterojunction photon synaptic transistor with temperature stability and a preparation method thereof, providing new ideas for the development of temperature-stable photon synaptic devices.

[0005] To solve the above technical problem, the present invention discloses an organic semiconductor heterojunction photon synaptic transistor, which includes a source-drain electrode, an organic active layer, a gate insulating layer, and a gate arranged successively from top to bottom; wherein, the organic active layer is composed of an N,N'-disalicylidene-1,3-diaminopropane layer and a pentacene layer.

[0006] wherein, the source-drain electrode is copper, and the thickness is 80 - 110 nm; Specifically, in some embodiments of the present invention, the thickness of the source-drain electrode is 100 nm.

[0007] wherein, the thickness of the N,N'-disalicylidene-1,3-diaminopropane layer is 15 - 30 nm; the thickness of the pentacene layer is 30 - 50 nm; Specifically, in some embodiments of the present invention, the thickness of the N,N'-disalicylidene-1,3-diaminopropane layer is 20 - 30 nm; the thickness of the pentacene layer is 30 - 50 nm.

[0008] Among them, the gate insulating layer is silicon dioxide with a thickness of 50 - 300 nm; Specifically, in some embodiments of the present invention, the thickness of the gate insulating layer is 50 nm.

[0009] Among them, the gate electrode is highly doped silicon.

[0010] The present invention also provides a method for preparing the above-mentioned organic semiconductor heterojunction photon synaptic transistor, including the following steps: S1. Grow a gate insulating layer on the surface of the gate electrode, cut it, then clean it, and then blow dry the surface liquid for drying, and finally perform ultraviolet ozone treatment; S2. Spin-coat an N,N'-disalicylidene-1,3-diaminopropane solution on the gate insulating layer after the ultraviolet ozone treatment in S1, and form an N,N'-disalicylidene-1,3-diaminopropane layer on the gate insulating layer after annealing; S3. Evaporate a pentacene layer and source-drain electrodes in sequence on the N,N'-disalicylidene-1,3-diaminopropane layer, and then the organic semiconductor heterojunction photon synaptic transistor is obtained.

[0011] Among them, in S1, the size after cutting is 1.5 cm × 1.5 cm.

[0012] Among them, in S1, the specific steps of the cleaning are ultrasonic cleaning with acetone, ethanol and deionized water in sequence, the cleaning time is 25 - 30 min for each, and the ultraviolet ozone treatment is 5 min.

[0013] Among them, in S2, the concentration of the N,N'-disalicylidene-1,3-diaminopropane solution is 3 - 5 mg / mL, and the solvent is chloroform; Specifically, in some embodiments of the present invention, the concentration of the N,N'-disalicylidene-1,3-diaminopropane solution is 3 mg / mL; Specifically, the N,N'-disalicylidene-1,3-diaminopropane (NSP) molecule has good solubility due to the presence of two hydroxyl groups, and can be formed into a film by solution spin-coating. Moreover, the NSP molecule contains multiple active sites, and its structure can be regulated by functional group modification to control the electron transfer ability, thereby optimizing the performance parameters of the device.

[0014] Among them, for the spin-coating, the specific process parameters are: maintaining at a rotation speed of 300 - 500 rpm for 5 - 10 s and then at 1000 - 3000 rpm for 25 - 35 s; Specifically, in some embodiments of the present invention, for the spin coating, the process parameters are specifically as follows: maintaining at 500 rpm for 9 s and then at 3000 rpm for 30 s.

[0015] Among them, for the annealing, the temperature is 60 - 80 °C and the time is 20 - 40 min; Specifically, in some embodiments of the present invention, for the annealing, the temperature is 60 °C and the time is 20 min.

[0016] Among them, the evaporation coating is vacuum evaporation coating, and its speed is 0.1 - 1 Å s -1 , and the vacuum degree during evaporation coating is less than 5×10 -4 Pa; Specifically, in some embodiments of the present invention, the speed of the vacuum evaporation coating is 1 Å s -1 .

[0017] Among them, when evaporating the source-drain electrodes, the length and width of the channel covered by the mask plate are 100 µm and 1500 µm respectively.

[0018] Beneficial effects: 1. The photon synaptic transistor provided by the present invention has the characteristics of simple structure and easy operation. The organic functional layer is formed into a film by solution spin coating, and the device structure is a bottom-gate top-contact structure. The synaptic plasticity is studied by measuring the current between the source-drain copper electrodes.

[0019] 2. The photon synaptic transistor provided by the present invention has excellent optical synaptic performance and has a precisely controllable response to light stimulation, indicating its potential as a neuromorphic device.

[0020] 3. The photon synaptic transistor provided by the present invention has good device optical response performance regulated by the received optical power. As the optical power increases, the optical responsivity and dynamic range of the device almost linearly increase.

[0021] 4. The photon synaptic transistor provided by the present invention is mainly dominated by NSP, and has the largest optical responsivity and optical response dynamic range at 435 nm. The device has good recognition of near-ultraviolet light.

[0022] 5. The photon synaptic transistor provided by the present invention benefits from the relative stability of the small molecule material. The optical synaptic function and optical responsivity remain good in the range of 20 °C to 120 °C, and the performance does not decline. At the same time, adaptive learning rules can be realized at different temperatures.

[0023] 6. The present invention provides valuable insights for the development of temperature-stable photon synaptic devices and demonstrates the potential of the defect variation at the pentacene and NSP interface in improving the performance of neuromorphic computing systems. These findings contribute to advancing the field of nanoengineered devices, making them more effective and reliable for future applications in adaptive computing. Description of the Drawings

[0024] The present invention will be further described in detail below with reference to the drawings and specific embodiments, and the above and / or other advantages of the present invention will become clearer.

[0025] Figure 1 Schematic diagram of the structure of the organic semiconductor heterojunction photon synaptic transistor of the present invention; wherein, 1 is the source-drain electrode, 2 is the pentacene layer, 3 is the N,N'-disalicylidene-1,3-diaminopropane layer, 4 is the gate insulating layer, and 5 is the gate.

[0026] Figure 2 Output curve of the photon synaptic transistor device of the present invention.

[0027] Figure 3 Transfer curve of the photon synaptic transistor device of the present invention.

[0028] Figure 4 Forward storage of the photon synaptic transistor device of the present invention.

[0029] Figure 5 Negative storage of the photon synaptic transistor device of the present invention.

[0030] Figure 6 Transfer curve shift of the photon synaptic transistor device of the present invention at different optical wavelengths.

[0031] Figure 7 UV-visible absorption spectra of NSP and pentacene.

[0032] Figure 8 Response of the photon synaptic transistor device of the present invention to the duration of optical pulses.

[0033] Figure 9 Optical stimulation PPF response and PPF index of the photon synaptic transistor device of the present invention.

[0034] Figure 10 Schematic diagram of a set of PTP for testing the device of the photon synaptic transistor device of the present invention at different light intensities.

[0035] Figure 11 Schematic diagram showing that increasing the number of optical pulses of the photon synaptic transistor device of the present invention results in a larger EPSC.

[0036] Figure 12Schematic diagram of the relationship between the optical responsivity and dynamic range of the photon synaptic transistor device of the present invention and the light intensity.

[0037] Figure 13 Schematic diagram of the relationship between the optical responsivity and dynamic range of the photon synaptic transistor device of the present invention and the light wavelength.

[0038] Figure 14 Schematic diagram of the relationship between the threshold voltage shift of the photon synaptic transistor device of the present invention and the light wavelength.

[0039] Figure 15 A set of PTP data measured for the photon synaptic transistor device of the present invention at 20 °C to 120 °C.

[0040] Figure 16 Schematic diagram of the PTP index and synaptic weight of the photon synaptic transistor device of the present invention from 20 °C to 120 °C.

[0041] Figure 17 Schematic diagram of the optical responsivity and dynamic range of the photon synaptic transistor device of the present invention from 20 °C to 120 °C.

[0042] Figure 18 Schematic diagram of the Pavlovian conditioning experiment.

[0043] Figure 19 Pavlovian conditioning simulation process of the photon synaptic transistor device of the present invention at 20 °C.

[0044] Figure 20 Pavlovian conditioning simulation process of the photon synaptic transistor device of the present invention at 100 °C. Detailed implementation manners

[0045] In the following examples, the experimental methods are all conventional methods unless otherwise specified; the reagents and materials are all commercially available unless otherwise specified.

[0046] The highly doped silicon used in the following examples (product name: single-polished silicon oxide wafer; oxidation thickness: 50 ± 5 nm; resistivity: 0.001 - 0.005 Ω·cm; type: N; crystal orientation: <100>) was purchased from Suzhou Jingsi Electronic Technology Co., Ltd.; N,N'-disalicylidene-1,3-diaminopropane (NSP) and pentacene were purchased from TCI Company.

[0047] The present invention provides an organic semiconductor heterojunction photon synaptic transistor with temperature stability, and its overall structure is a vertical structure. The specific structure is as Figure 1As shown in the figure, from top to bottom, it successively includes: source-drain electrode 1, pentacene layer 2, N,N'-disalicylidene-1,3-diaminopropane layer 3, gate insulating layer 4, and gate electrode 5. Among them, the pentacene layer 2 and the N,N'-disalicylidene-1,3-diaminopropane layer 3 together constitute the organic active layer. Among them, the source-drain electrode is a copper electrode, the gate insulating layer is silicon dioxide, the gate electrode is highly doped silicon, the NSP structural formula is as shown in Formula I, and the pentacene structural formula is as shown in Formula II.

[0048]

[0049] Formula I

[0050] Formula II Example 1: Preparation of an organic semiconductor heterojunction photonic synaptic transistor This example provides a preparation method of an organic semiconductor heterojunction photonic synaptic transistor with temperature stability, including the following steps: S1. Grow a 50-nm-thick silicon dioxide layer (completed by Suzhou Jingsi Electronic Technology Co., Ltd.) on the surface of the highly doped silicon gate electrode to obtain the gate insulating layer. Take it as the substrate, cut it into a size of 1.5 cm × 1.5 cm, put the cut substrate into acetone, ethanol, and deionized water respectively and ultrasonicate for about 20 minutes. After taking it out, dry the surface with high-purity nitrogen and place it in a glass petri dish. Then place the petri dish in an oven at 120 °C and dry it for about 20 minutes; perform ultraviolet ozone treatment on the dried sample for 5 minutes; S2. Dissolve the NSP powder in chloroform solvent to prepare a solution with a concentration of 3 mg / mL; S3. Use a pipette to suck the solution prepared in S2 and spin-coat and film on the gate insulating layer of the substrate treated in S1 according to the process of maintaining at 500 rpm for 9 s and then at 3000 rpm for 30 s. Then transfer it to an oven and anneal at 60 °C for 20 min to obtain the N,N'-disalicylidene-1,3-diaminopropane layer, and the thickness of the N,N'-disalicylidene-1,3-diaminopropane layer is 20 - 30 nm; S4. Put the sample treated in S3 into a vacuum evaporation system, and successively evaporate the pentacene layer and the source-drain electrode, controlling the evaporation rate to be 1 Å s -1 , and the vacuum degree in the evaporation chamber is always maintained at less than 5×10 -4 Pa. The thickness of the pentacene layer is 30 - 50 nm, and the thickness of the source-drain electrode is 100 nm; among them, when evaporating the source-drain electrode, the channel length and width of the covered mask plate are 100 µm and 1500 µm respectively. After evaporation, the photonic synaptic transistor is obtained.

[0051] Example 2: Performance Test of Organic Semiconductor Heterojunction Photonic Synaptic Transistor In the following examples, a Keithley 4200 semiconductor parameter analyzer was used to test the photonic synaptic transistor.

[0052] To study the electrical properties of the photonic synaptic transistor, the transfer characteristic curve and output characteristic curve of the device were measured under dark conditions. The source-drain voltage was scanned from 0 V to -15 V to obtain the output curves of the photonic synaptic transistor under the bias of gate voltages of 0 V, -3 V, -6 V, -9 V, -12 V, and -15 V, respectively; the gate voltage was scanned from 10 V to -30 V under the condition of a fixed source-drain voltage of -15 V to obtain the transfer curve of the photonic synaptic transistor. Figure 2 is the output curve of the photonic synaptic transistor device Figure 3 is the transfer curve of the photonic synaptic transistor device. From Figure 2 and Figure 3 the output and transfer curves, it can be seen that the device has good field effect. The output curve clearly shows the channel current regulated by the gate voltage, and the linear region and saturation region are obvious. The transfer curve with a source-drain voltage of -15 V was set, and the carrier mobility μ = 0.12 cm 2 / Vs was calculated by linear fitting of the saturation region.

[0053] To study the positive storage ability and negative storage ability of the photonic synaptic transistor, first, a +30 V gate voltage for 1 s and natural light pulses were applied for programming operations, while a -30 V, 1 s negative gate voltage was used for erasing operations. Figure 4 shows the positive storage ability of the device. From Figure 4 it can be seen that after the optical programming operation, the transfer curve basically moves in the positive direction, indicating that electrons are trapped in the N,N'-disalicylidene-1,3-diaminopropane layer. After the electrical erasing operation, the transfer curve can move back to its initial state, meaning the release of the trapped electrons. Different from the positive operation, the writing condition was changed to a gate voltage of -40 V, and the erasing condition was changed to a gate voltage of +40 V. Figure 5 shows the negative storage ability of the device. From Figure 5 it can be seen that the transfer curve moves in the negative direction after writing. These results confirm the good field effect and bipolar storage ability of the device.

[0054] To study the influence of light with different wavelengths on the photonic synaptic transistor, the changes in the transfer curve of the photonic synaptic transistor were studied by setting no light illumination and applying light illuminations with wavelengths of 400 nm, 420 nm, 435 nm, 500 nm, 600 nm, and 650 nm, respectively. The illumination duration was 3 s, and the illumination intensity was 20 mW cm -2 .Figure 6 Schematic diagram for realizing different degrees of shift of the transfer curve by applying light of different wavelengths. It can be seen from Figure 6 that as the light wavelength decreases, the degree of positive shift of the transfer curve becomes larger, meaning the generation and capture of more photo-generated carriers. The results show that the photon synaptic transistor has excellent photon flash memory performance and light-regulated synaptic plasticity.

[0055] Figure 7 UV-visible absorption spectra of NSP and pentacene. It can be seen from Figure 7 that the absorption bands of the two materials do not overlap at all, and the absorption peak of NSP is located at about 435 nm.

[0056] In a biological synapse, after the presynaptic membrane is stimulated, a response current will be generated in the postsynaptic membrane, which is called excitatory postsynaptic current (EPSC). To study the effect of light pulse duration on the photon synaptic transistor, the gate voltage was fixed at -15 V and the light intensity was 2.0 mW / cm 2 , and the EPSC responses under light stimulation times of 0.2 s, 0.5 s, 1.0 s, 1.5 s, and 2.0 s were tested. Figure 8 Response of the photon synaptic transistor device to the light pulse duration. It can be seen from Figure 8 that increasing the duration of a single light stimulus will result in a higher EPSC and slower decay.

[0057] Simulating the paired-pulse facilitation (PPF) effect on the photon synaptic transistor, the photon synapse shows an obvious PPF effect. The generation of PPF can be attributed to the short time interval between the two stimuli. When the second stimulus reaches the presynaptic neuron, the neurotransmitters released by the previous stimulus still remain in the synaptic cleft. Therefore, PPF is directly related to the time interval between the applied stimuli. Figure 9 Optical stimulation PPF response and PPF index of the photon synaptic transistor device of the present invention. It can be seen from Figure 9 that the photon synaptic transistor prepared by the present invention has an obvious PPF effect. On this basis Figure 9 it also shows the corresponding PPF increment after changing the pulse interval, where the PPF index is defined as the percentage increase in the second current peak compared to the first current peak. As the time interval increases, the PPF increment decreases significantly and finally approaches 0.

[0058] Post-tetanic potentiation (PTP) is similar to PPF, which refers to the phenomenon that the synaptic weight increases within a certain time under repeated high-frequency stimulation. The PTP test can quantify the response characteristics of the device to high-frequency stimulation by adjusting the light pulse parameters (such as frequency, duration). A group of PTPs were tested by changing the light intensity and the number of light stimuli. Figure 10A set of PTP schematic diagrams for testing the device of the photon synaptic transistor device under different light intensities, with the number of light stimuli being 10 for each light intensity. Figure 11 Schematic diagram showing that increasing the number of light pulses leads to a larger EPSC for the photon synaptic transistor device under the same light intensity, with the light intensity being 2.0 mW / cm 2 . From Figure 10 and Figure 11 , it can be seen that increasing the intensity and number of light pulses will result in a larger EPSC. These results indicate that the device has excellent optical synaptic performance and a precisely controllable response to light stimuli, demonstrating its potential as a neuromorphic device.

[0059] Figure 12 Schematic diagram showing the relationship between the optical responsivity and dynamic range of the photon synaptic transistor device of the present invention and the light intensity Figure 13 Schematic diagram showing the relationship between the optical responsivity and dynamic range of the photon synaptic transistor device of the present invention and the light wavelength, where the optical responsivity is defined as the ratio of the photocurrent to the incident optical power, and the dynamic range is defined as the ratio of the maximum input optical power to the minimum receivable optical power. From Figure 12 it can be seen that as the optical power increases, the dynamic range of the optical responsivity of the device almost linearly increases, indicating good optical response performance of the device regulated by the optical power. From Figure 13 it can be seen that the connection is similar to the absorption spectrum of the material, and the optical responsivity and dynamic range are the highest at the absorption peak of NSP at 435 nm, and slightly weaker at around 600 nm of the absorption peak of pentacene, indicating the optical response of the device dominated by NSP.

[0060] Figure 14 Schematic diagram showing the relationship between the threshold voltage shift of the photon synaptic transistor device of the present invention and the light wavelength, showing the relationship between the shift of the threshold voltage in the transfer curve of the device, that is, the storage window, and the incident light wavelength Figure 14 is extracted from Figure 6 the threshold voltage shift of each transfer curve in the data, and statistically plotted. From Figure 14 it can be seen that as the wavelength shortens to near ultraviolet, the energy of the incident light is greater, and the more excitonic pairs are excited, so the transfer curve shifts more positively.

[0061] Figure 15 A set of PTP data for online testing of the device at intervals of 20 °C from 20 °C to 120 °C. From Figure 15 it can be seen that the device performance is very stable before 100 °C, and continuous light stimulation makes the channel current continuously increase, and the relaxation current slowly decays after removing the light. At 120 °C, there are small fluctuations in the dark current and relaxation current of the device, but the PTP still continues to increase.

[0062] Figure 16Schematic diagram of the PTP index and synaptic weight of the photon synaptic transistor device of the present invention from 20 °C to 120 °C Figure 17 Schematic diagram of the optical responsivity and dynamic range of the photon synaptic transistor device of the present invention from 20 °C to 120 °C, where the PTP index is defined as the percentage increase of the tenth peak relative to the first peak, and the synaptic weight is defined as the percentage increase of the current value when it stabilizes after the tenth peak stimulation. From Figure 16 and Figure 17 It can be seen that generally, as the temperature increases, the optical responsivity of the device increases, but the PTP index and the percentage of synaptic weight decrease. This is because the intrinsic excitation of the semiconductor material leads to an increase in intrinsic carriers when the temperature rises, and more charge generation and separation occur under illumination. At the same time, the increase in temperature affects the properties of the organic semiconductor thin film, resulting in a decrease in crystallinity, an increase in physical defects, and a decrease in relaxation current. Specifically, since pentacene has a certain crystallinity, when the temperature rises, the crystallinity of pentacene decreases. At this time, a high density of physical defects will be generated between the pentacene and the NSP interface and the electrode interface, affecting the capture and de-capture of charges, resulting in a decrease in carrier mobility. At the same time, the change in temperature affects the energy barrier between pentacene and the electrode and NSP, increasing the contact resistance. The contact area between the three interfaces in the device becomes larger, and at the same time, due to the defects at the interface, the charge recombination is accelerated, resulting in a faster relaxation speed of the photocurrent. These changes in the device at high temperatures can achieve different degrees of learning-forgetting, which is beneficial to simulating more advanced neuromorphic functions.

[0063] Figure 18 Schematic diagram of Pavlov's classical conditioning experiment. Pavlov's classical conditioning experiment is specifically as follows: At first, when food is provided to a dog, the dog will secrete saliva naturally, while the ringing of a bell will not cause the dog to produce saliva; then every time the dog is fed, the bell is rung at the same time. After repeated exposure for a period of time, the dog associates the food with the bell, and as long as the bell rings, even without food, the dog will drool. Here, the food is an unconditioned stimulus (US), which can cause an unconditioned response (UR), that is, drooling; while the ringing of the bell is a conditioned stimulus (CS). Training the dog to drool is a conditioned response (CR). In Pavlov's experiment, the dog would secrete saliva naturally when it received food, but initially had no response to the ringing of the bell. By repeatedly pairing the bell with the food, the dog learned to associate the bell with the food, and ultimately the ringing of the bell itself caused saliva secretion.

[0064] Perform Pavlov's classical conditioning experiment on the photon synaptic transistor device prepared by the present invention, using a series of -2 V electrical pulse signals as the conditioned stimulus and a 435 nm wavelength optical signal as the unconditioned stimulus, and setting a threshold current I , exceeding IA current level of 1 nA corresponds to the "salivating" behavior, which represents the salivary behavior of the dog. The Pavlovian classical conditioning experiment was carried out at 20 °C and 100 °C respectively. Figure 19 This is the Pavlovian conditioning simulation process of the photon synaptic transistor device of the present invention at 20 °C. Figure 20 This is the Pavlovian conditioning simulation process of the photon synaptic transistor device of the present invention at 100 °C. As can be seen from Figure 19 and Figure 20 , compared with that at 20 °C, the current increases faster at 100 °C, indicating that the training process is faster and the learning efficiency of the dog is higher. However, at the same time, due to the faster current relaxation, the forgetting speed of the dog is also faster, indicating that the retention time of learning is shorter. Therefore, although the learning process is shorter, more frequent relearning and consolidation processes are required. These results show that multi-mode learning rules can be realized in the device, which is beneficial to realizing adaptive and more intelligent neuromorphic functions.

[0065] The present invention provides an idea for an organic semiconductor heterojunction photon synaptic transistor and its preparation method. There are many methods and ways to specifically implement this technical solution. The above is only the preferred embodiment of the present invention. It should be pointed out that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present invention. Each component not clearly defined in this embodiment can be implemented by existing technologies.

Claims

1. An organic semiconductor heterojunction photonic synaptic transistor, characterized in that, The organic semiconductor heterojunction photonic synaptic transistor includes a source-drain electrode, an organic active layer, a gate insulating layer, and a gate electrode, which are sequentially arranged from top to bottom; Among them, the organic active layer is composed of an N,N'-disalicylidene-1,3-diaminopropane layer and a pentacene layer.

2. The organic semiconductor heterojunction photonic synaptic transistor according to claim 1, wherein The source-drain electrode is copper with a thickness of 80-110 nm.

3. The organic semiconductor heterojunction photonic synaptic transistor according to claim 1, characterized in that, The thickness of the N,N'-disalicylidene-1,3-diaminopropane layer is 15-30 nm; the thickness of the pentacene layer is 30-50 nm.

4. The organic semiconductor heterojunction photonic synaptic transistor according to claim 1, wherein The gate insulating layer is silicon dioxide with a thickness of 50-300 nm.

5. The organic semiconductor heterojunction photonic synaptic transistor according to claim 1, characterized in that, The gate electrode is highly doped silicon.

6. The preparation method of the organic semiconductor heterojunction photonic synaptic transistor according to any one of claims 1 to 5, characterized in that, It includes the following steps: S1. Grow a gate insulating layer on the surface of the gate electrode, cut and clean it, then blow dry the surface liquid for drying, and finally perform ultraviolet ozone treatment; S2. Spin-coat an N,N'-disalicylidene-1,3-diaminopropane solution on the gate insulating layer after the ultraviolet ozone treatment in S1, and form an N,N'-disalicylidene-1,3-diaminopropane layer on the gate insulating layer after annealing; S3. Evaporate a pentacene layer and a source-drain electrode on the N,N'-disalicylidene-1,3-diaminopropane layer in sequence to obtain the organic semiconductor heterojunction photonic synaptic transistor.

7. The preparation method according to claim 6, characterized in that, The concentration of the N,N'-disalicylidene-1,3-diaminopropane solution is 3-5 mg / mL, and the solvent is chloroform.

8. The preparation method according to claim 6, wherein, For the spin-coating, the specific process parameters are: maintaining at a rotation speed of 300-500 rpm for 5-10 s and then at 1000-3000 rpm for 25-35 s.

9. The preparation method according to claim 6, characterized in that, For the annealing, the temperature is 60-80 °C and the time is 20-40 min.

10. The preparation method according to claim 6, characterized in that, The evaporation coating is vacuum evaporation coating, and its speed is 0.1~1 Å s -1 , and the vacuum degree during evaporation coating is less than 5×10 -4 Pa.

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