Solid-state imaging element, imaging device, and method for controlling solid-state imaging element

Abstract

In such a solid-state imaging element using a global shutter system, the dynamic range is expanded. The solid-state imaging device is provided with a first transfer transistor, a second transfer transistor, and an overflow gate. The first transfer transistor transfers the charge from the photoelectric conversion element to the charge holding unit. The second transfer transistor transfers charge from one of the charge holding unit and the photoelectric conversion element to the first floating diffusion layer. The overflow gate causes the charge overflowing from the photoelectric conversion element to be held in the second floating diffusion layer.

Description

Technical Field

[0001] The present technology relates to a solid-state imaging device. More specifically, the present technology relates to a solid-state imaging device including an analog memory for each pixel, an imaging device, and a control method for the solid-state imaging device. Background Art

[0002] Conventionally, since there is no rolling shutter distortion and it is suitable for imaging moving objects, the global shutter method in which the exposure of all pixels starts and ends simultaneously can be used in a solid-state imaging device. For example, a solid-state imaging device has been proposed in which an analog memory is provided at a preceding stage of a floating diffusion section (FD), and charges from a photoelectric conversion element are transferred to the analog memory (see, for example, Patent Document 1). In this solid-state imaging device, reading is performed sequentially line by line, and during the time from the end of exposure to the reading of a selected line, the charges are held in the analog memory of the selected line. List of Cited Documents Patent Documents

[0003] Patent Document 1: PCT International Application Publication No. 2017-536780 Summary of the Invention Technical Problem to be Solved by the Invention

[0004] In the above conventional technology, the global shutter method is implemented by controlling the analog memory to hold charges during the time from the end of exposure to the reading of a selected line. However, in the above solid-state imaging device, it is difficult to expand the dynamic range. By imaging multiple pieces of image data with different exposure times and synthesizing them, the dynamic range can be expanded, but this is not preferable because the number of captured images and power consumption increase.

[0005] The present technology has been created in view of this situation, and an object of the present technology is to expand the dynamic range of a solid-state imaging device using the global shutter method. Solution to the Technical Problem

[0006] The present technology has been proposed to solve the above problems, and a first aspect thereof is a solid-state imaging device and a control method therefor, the solid-state imaging device including: a first transfer transistor that transfers charges from a photoelectric conversion element to a charge holding section; a second transfer transistor that transfers charges from one of the charge holding section and the photoelectric conversion element to a first floating diffusion layer; and an overflow gate that causes charges overflowing from the photoelectric conversion element to be held in a second floating diffusion layer. This brings an effect of expanding the dynamic range.

[0007] In addition, in the first aspect, the second transfer transistor may transfer charge from the charge holding unit to the first floating diffusion layer, and the overflow gate may hold the charge overflowing from the photoelectric conversion element in the second floating diffusion layer. This results in the effect that a signal corresponding to the voltage of the second floating diffusion layer is read as the signal at the time of overflow.

[0008] In addition, in the first aspect, it may further include: a first source follower circuit that amplifies and outputs the voltage of the first floating diffusion layer; and a second source follower circuit that amplifies and outputs the voltage of the second floating diffusion layer. This results in the effect that signals obtained by amplifying the voltages of the first and second floating diffusion layers are read out simultaneously.

[0009] In addition, in the first aspect, it may further include a source follower circuit that amplifies and outputs the voltage of the second floating diffusion layer, and the first floating diffusion layer may be connected to the second floating diffusion layer. This results in the effect of reducing the number of source follower circuits.

[0010] In addition, in the first aspect, it may further include: a conversion efficiency control transistor that opens and closes the path between the first floating diffusion layer and the third floating diffusion layer; a connection transistor that opens and closes the path between the second floating diffusion layer and the third floating diffusion layer; and a source follower circuit that amplifies and outputs the voltage of the first floating diffusion layer. This results in the effect of achieving a pipeline operation.

[0011] In addition, in the first aspect, the capacitance value of the third floating diffusion layer may be 10 times or more that of either the first or the second floating diffusion layer. This results in the effect of reducing noise.

[0012] In addition, in the first aspect, a plurality of pixel circuits may share the first floating diffusion layer and the source follower circuit, and in each of the plurality of pixel circuits, there may be provided the photoelectric conversion element, the second and third floating diffusion layers, the charge holding unit, the first and second transfer transistors, the overflow gate, and the conversion efficiency control transistor. This results in the effect of reducing the circuit scale of each pixel.

[0013] In addition, in the first aspect, it may further include: a first source follower circuit that amplifies the voltage of the first floating diffusion layer and outputs the amplified voltage as a first voltage; a second source follower circuit that amplifies the voltage of the second floating diffusion layer and outputs the amplified voltage as a second voltage; and a sample and hold circuit that holds the second voltage. This results in the effect of improving the image quality.

[0014] In addition, in the first aspect, the second voltage may include: a reset level when initializing the second floating diffusion layer; and a signal level corresponding to the amount of charge accumulated in the second floating diffusion layer, and the sample-and-hold circuit may include: a first capacitive element that holds the reset level; and a second capacitive element that holds the signal level. This brings the effect of performing correlated double sampling (CDS) processing.

[0015] In addition, in the first aspect, the second voltage may include: a reset level when initializing the second floating diffusion layer; and a signal level corresponding to the amount of charge accumulated in the second floating diffusion layer. The reset level may include first and second reset levels for converting charge into voltage with different conversion efficiencies from each other, the signal level may include first and second signal levels with different conversion efficiencies from each other, and the sample-and-hold circuit may include a plurality of capacitive elements that respectively hold the first and second reset levels and the first and second signal levels. This brings the effect of further expanding the dynamic range.

[0016] In addition, in the first aspect, the second transfer transistor may transfer charge from the photoelectric conversion element to the first floating diffusion layer, the first transfer transistor may transfer the charge overflowing from the photoelectric conversion element to the charge holding portion, and the overflow gate may transfer the overflow charge from the charge holding portion to the second floating diffusion layer and cause the charge to be held in the second floating diffusion layer. This brings the effect of suppressing deterioration of linearity.

[0017] In addition, a second aspect of the present technology is an imaging device, including: a first transfer transistor that transfers charge from a photoelectric conversion element to a charge holding portion; a second transfer transistor that transfers charge from one of the charge holding portion and the photoelectric conversion element to a first floating diffusion layer; an overflow gate that causes the charge overflowing from the photoelectric conversion element to be held in the second floating diffusion layer; and a signal processing circuit that synthesizes a first pixel signal corresponding to the voltage of the first floating diffusion layer and a second pixel signal corresponding to the voltage of the second floating diffusion layer. This brings the effect of expanding the dynamic range of an image captured by the imaging device. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a block diagram showing a configuration example of an imaging device according to a first embodiment of the present technology. Figure 2 is a block diagram showing a configuration example of a solid-state imaging element according to a first embodiment of the present technology. Figure 3 is a circuit diagram showing a configuration example of a pixel according to a first embodiment of the present technology. Figure 4 is a block diagram showing a configuration example of a column signal processing circuit according to a first embodiment of the present technology. Figure 5 is a timing chart showing an example of exposure control of a solid-state imaging device according to a first embodiment of the present technology. Figure 6 is a timing chart showing an example of a read operation of a solid-state imaging device according to a first embodiment of the present technology. Figure 7 is an example of a potential diagram of a pixel according to a first embodiment of the present technology. Figure 8 is a flowchart showing an example of an operation of a solid-state imaging device according to a first embodiment of the present technology. Figure 9 is a circuit diagram showing a configuration example of a pixel according to a second embodiment of the present technology. Figure 10 is a timing chart showing an example of exposure control of a solid-state imaging device according to a second embodiment of the present technology. Figure 11 is a timing chart showing an example of a read operation of a solid-state imaging device according to a second embodiment of the present technology. Figure 12 is an example of a potential diagram of a pixel according to a second embodiment of the present technology. Figure 13 is a circuit diagram showing a configuration example of a pixel according to a third embodiment of the present technology. Figure 14 is a timing chart showing an example of exposure control of a solid-state imaging device according to a third embodiment of the present technology. Figure 15 is a timing chart showing an example of a read operation of a solid-state imaging device according to a third embodiment of the present technology. Figure 16 is an example of a potential diagram of a pixel according to a third embodiment of the present technology. Figure 17 is a circuit diagram showing a configuration example of a pixel block in a fourth embodiment of the present technology. Figure 18 is a circuit diagram showing a configuration example of a pixel according to a fifth embodiment of the present technology. Figure 19 is a timing chart showing an example of exposure control of a solid-state imaging device according to a fifth embodiment of the present technology. Figure 20 is a timing chart showing an example of a read operation of a solid-state imaging device according to a fifth embodiment of the present technology. Figure 21 This is an example of a potential diagram of a pixel according to the fifth embodiment of the present technology. Figure 22 This is a circuit diagram showing an example of the structure of a pixel according to the sixth embodiment of the present technology. Figure 23 This is a circuit diagram showing an example of the structure of a sample-and-hold circuit according to the first modification of the sixth embodiment of the present technology. Figure 24 This is a circuit diagram showing an example of the structure of a sample-and-hold circuit according to the second modification of the sixth embodiment of the present technology. Figure 25 This is a circuit diagram showing an example of the structure of a sample-and-hold circuit according to the third modification of the sixth embodiment of the present technology. Figure 26 This is a circuit diagram showing an example of the structure of a pixel according to the seventh embodiment of the present technology. Figure 27 This is a circuit diagram showing an example of the structure of a sample-and-hold circuit according to the seventh embodiment of the present technology. Figure 28 This is a timing diagram showing an example of the exposure control of a solid-state imaging device according to the seventh embodiment of the present technology. Figure 29 This is an example of a potential diagram of a pixel according to the seventh embodiment of the present technology. Figure 30 This is a block diagram showing a schematic structural example of a vehicle control system. Figure 31 This is an explanatory diagram showing an example of the installation position of an imaging unit. Detailed Embodiments

[0019] Hereinafter, modes for implementing the present technology (hereinafter referred to as embodiments) will be described. The description will be made in the following order. 1. First Embodiment (Example of Holding Overflow Charge in One of Two FDs) 2. Second Embodiment (Example of Reducing a Source Follower Circuit and Holding Overflow Charge in One of Two FDs) 3. Third Embodiment (Example of Holding Overflow Charge in One of Two FDs and Performing a Pipeline Operation) 4. Fourth Embodiment (Example of Having One of Two FDs Hold Overflow Charge and Sharing an FD) 5. Fifth Embodiment (Example of Holding Overflow Charge in an Analog Memory) 6. Sixth Embodiment (Example of Holding Overflow Charge in One of Two FDs and Sampling and Holding a Level) 7. Seventh Embodiment (Example of Holding Overflow Charge in One of Two FDs, Switching Conversion Efficiency, and Sampling and Holding Level) 8. Application Example of Mobile Body

[0020] <1. First Embodiment> [Configuration Example of Imaging Device] Figure 1 FIG. is a block diagram showing a configuration example of an imaging device 100 according to the first embodiment of the present technology. The imaging device 100 is a device that captures image data and includes an imaging lens 110, a solid-state imaging element 200, a recording unit 120, and an imaging control unit 130. As the imaging device 100, a digital camera or an electronic device having an imaging function (such as a smartphone, a personal computer, etc.) is assumed.

[0021] The solid-state imaging element 200 captures image data under the control of the imaging control unit 130. The solid-state imaging element 200 supplies image data to the recording unit 120 via a signal line 209.

[0022] The imaging lens 110 converges light and guides the light to the solid-state imaging element 200. The imaging control unit 130 controls the solid-state imaging element 200 to capture image data. For example, the imaging control unit 130 supplies an imaging control signal including a vertical synchronization signal VSYNC to the solid-state imaging element 200 via a signal line 139. The recording unit 120 records image data.

[0023] Here, the vertical synchronization signal VSYNC is a signal indicating an imaging timing, and a periodic signal with a constant frequency (such as 60 Hz, etc.) is used as the vertical synchronization signal VSSYNC.

[0024] Note that although the imaging device 100 records image data, the image data can be transmitted to the outside of the imaging device 100. In this case, an external interface for transmitting image data is also provided. Alternatively, the imaging device 100 can also display image data. In this case, a display unit is also provided.

[0025] [Configuration Example of Solid-State Imaging Element] Figure 2 FIG. is a block diagram showing a configuration example of a solid-state imaging element 200 according to the first embodiment of the present technology. The solid-state imaging element 200 includes: a vertical scanning circuit 211, a pixel array unit 220, a timing control circuit 212, a digital-to-analog converter (DAC) 213, a load MOS circuit block 250, and a column signal processing circuit 260. In the pixel array unit 220, a plurality of pixels 300 are arranged in a two-dimensional grid pattern. In addition, each circuit in the solid-state imaging element 200 is provided in, for example, a single semiconductor chip.

[0026] Hereinafter, a group of pixels 300 arranged in the horizontal direction is referred to as a "row", and a group of pixels 300 arranged in a direction perpendicular to the row is referred to as a "column".

[0027] The timing control circuit 212 controls the operation timings of the vertical scan circuit 211, the DAC 213, and the column signal processing circuit 260 in synchronization with the vertical synchronization signal VSYNC from the imaging control unit 130.

[0028] The DAC 213 generates a sawtooth ramp signal through digital-to-analog (DA) conversion. The DAC 213 supplies the generated ramp signal to the column signal processing circuit 260.

[0029] The vertical scan circuit 211 sequentially selects and drives rows to output analog pixel signals. Each pixel 300 performs photoelectric conversion on incident light to generate an analog pixel signal. The pixel 300 supplies the pixel signal to the column signal processing circuit 260 via the load MOS circuit block 250.

[0030] In the load MOS circuit block 250, MOS transistors for supplying a constant current are provided for each column.

[0031] The column signal processing circuit 260 performs signal processing such as analog-to-digital (AD) conversion processing or CDS processing on the pixel signals for each column. The column signal processing circuit 260 supplies image data including the processed signals to the recording unit 120. Note that the column signal processing circuit 260 is an example of the signal processing circuit described in the claims.

[0032] [Pixel Structure Example] Figure 3 is a circuit diagram showing a structural example of a pixel 300 according to a first embodiment of the present technology. The pixel 300 includes: a photoelectric conversion element 311, transfer transistors 312 and 314, an analog memory 313, an OFG transistor 315, FDs 321 and 322, and source follower circuits 340 and 350. The source follower circuit 340 includes: a reset transistor 341, an amplification transistor 342, and a selection transistor 343, and the source follower circuit 350 includes: a reset transistor 351, an amplification transistor 352, and a selection transistor 353. In addition, vertical signal lines 308 and 309 are wired in the vertical direction for each column.

[0033] The photoelectric conversion element 311 generates charges by performing photoelectric conversion on incident light. The transfer transistor 312 transfers the charges from the photoelectric conversion element 311 to the analog memory 313 according to the transfer signal TRY received from the vertical scan circuit 211. Note that the transfer transistor 312 is an example of the first transfer transistor described in the claims.

[0034] The analog memory 313 holds electric charges. For example, a multi-gate metal-oxide-semiconductor (MOS) transistor is used as the analog memory 313. Note that the analog memory 313 is an example of the charge holding section described in the claims.

[0035] The transfer transistor 314 transfers electric charges from the analog memory 313 to the FD 321 according to the transfer signal TRG received from the vertical scan circuit 211. Note that the transfer transistor 314 is an example of the second transfer transistor described in the claims.

[0036] The OFG transistor 315 opens and closes the path between the photoelectric conversion element 311 and the FD 322 according to the control signal OFG from the vertical scan circuit 211. In addition, the OFG transistor 315 serves as an overflow gate that holds the charges overflowing from the photoelectric conversion element 311 in the FD 322 in the cutoff state.

[0037] The FDs 321 and 322 accumulate electric charges and generate a voltage according to the amount of the electric charges. Note that the FDs 321 and 322 are examples of the first and second floating diffusions described in the claims.

[0038] The reset transistor 341 initializes the FD 321 according to the reset signal RSTa received from the vertical scan circuit 211. The amplification transistor 342 amplifies the voltage of the FD 321. The selection transistor 343 outputs the amplified voltage signal as a pixel signal to the vertical signal line 308 according to the selection signal SEL from the vertical scan circuit 211. With this circuit configuration, the source follower circuit 340 amplifies and outputs the voltage of the FD 321.

[0039] The connection configuration of the reset transistor 351, the amplification transistor 352, and the selection transistor 353 is similar to the connection configuration of the reset transistor 341, the amplification transistor 342, and the selection transistor 343. However, the reset transistor 351 initializes the FD 322 according to the reset signal RSTb from the vertical scan circuit 211, and the selection transistor 353 outputs the pixel signal to the vertical signal line 309.

[0040] Note that the source follower circuits 340 and 350 are examples of the first and second source follower circuits described in the claims.

[0041] At the start of exposure, the vertical scan circuit 211 turns on all the OFG transistors 315 and reset transistors 351 of all the pixels in the pulse period by the control signal OFG and the reset signal RSTb. Therefore, the photoelectric conversion elements 311 of all the pixels are initialized, and exposure starts simultaneously in all the pixels.

[0042] Then, immediately before the exposure ends, the vertical scanning circuit 211 turns on the reset transistors 341 and transfer transistors 314 of all pixels within the pulse period through the reset signal RSTa and the transfer signal TRG. Accordingly, the FDs 321 and the analog memory 313 are initialized.

[0043] At the end of the exposure, the vertical scanning circuit 211 turns on the transfer transistors 312 of all pixels within the pulse period through the transfer signal TRY. As a result, the charge is transferred from the photoelectric conversion element 311 to the analog memory 313, and the exposure ends for all pixels. In this way, the control of starting and ending the exposure simultaneously for all pixels is called the global shutter method.

[0044] After the exposure is completed, the vertical scanning circuit 211 sequentially selects and drives the rows, and each time a row is selected, the column signal processing circuit 260 reads the pixel signals from that row.

[0045] The vertical scanning circuit 211 turns on the selection transistors 343 and 353 of the selected row within the readout period through the selection signal SEL. In addition, during the readout period, the vertical scanning circuit 211 turns on the reset transistors 341 of the selected row within the pulse period through the reset signal RSTa. Accordingly, the FD 321 is initialized. Hereinafter, the level of the pixel signal when the FD 321 or 322 is initialized is referred to as the "P-phase" or "reset level". The column signal processing circuit 260 reads the reset level via the vertical signal line 308. The reset level from the vertical signal line 308 is set as Pa.

[0046] In addition, in an environment with relatively high illuminance, the FD 322 holds the charge overflowing from the photoelectric conversion element 311 via the OFG transistor 315. Hereinafter, the voltage of the pixel signal according to the amount of charge accumulated in the FD 321 or FD 322 is referred to as the "D-phase" or "signal level". During the period of reading the reset level Pa, the column signal processing circuit 260 reads the signal level via the vertical signal line 309. The signal level from the vertical signal line 309 is represented by Db.

[0047] After reading the reset level Pa and the signal level Db, the vertical scanning circuit 211 turns on the transfer transistors 314 of the selected row within the pulse period through the transfer signal TRG. At the same time, the vertical scanning circuit 211 turns on the reset transistors 351 of the selected row within the pulse period through the reset signal RSTb. Through these controls, the charge is transferred to the FD 321, and the FD 322 is initialized. The column signal processing circuit 260 reads the signal level via the vertical signal line 308 and reads the reset level via the vertical signal line 309. The signal level from the vertical signal line 308 is Da, and the reset level from the vertical signal line 309 is Pb.

[0048] As described above, after exposure by the global shutter method, the vertical scanning circuit 211 sequentially selects and drives rows. Each time a row is selected, the column signal processing circuit 260 reads the reset level Pa and the signal level Db, and then reads the signal level Da and the reset level Rb.

[0049] [Example Configuration of Column Signal Processing Circuit] Figure 4 FIG. is a block diagram showing an example configuration of the column signal processing circuit 260 according to the first embodiment of the present technology.

[0050] In the load MOS circuit block 250, a plurality of load MOS transistors 251 each supplying a constant current id2 are arranged. Each load MOS transistor 251 is connected to each vertical signal line. Since two vertical signal lines (308 and 309) are wired for each column, if the number of columns is M (M is an integer), the number of load MOS transistors 251 is 2×M.

[0051] The column signal processing circuit 260 includes a plurality of ADCs 261 and a digital signal processing circuit 262. Each ADC 261 is connected to each vertical signal line. Since two vertical signal lines are wired for each column, the number of ADCs 261 is 2×M.

[0052] The digital signal processing circuit 262 includes: a plurality of selectors 263, a plurality of memories 264, a plurality of subtractors 265, and a synthesis processing unit 266. A selector 263, a memory 264, and a subtractor 265 are arranged for each ADC 261. Since the number of ADCs 261 is 2×M, the number of selectors 263, the number of memories 264, and the number of subtractors 265 are also 2×M.

[0053] The ADC 261 converts an analog pixel signal from the corresponding vertical signal line into a digital signal using the ramp signal Rmp from the DAC 213. The ADC 261 supplies the digital signal to the digital signal processing circuit 262. For example, a single-slope ADC including a comparator and a counter is provided as the ADC 261.

[0054] The vertical signal line 308 outputs the signal level Da after the reset level Pa of the pixel signal, while the vertical signal line 309 outputs the reset level Pb after the signal level Db of the pixel signal. Each ADC 261 sequentially performs AD conversion on the reset level and the signal level, and supplies the result of the AD conversion to the corresponding selector 263.

[0055] Selector 263 switches the output destination of the digital signal (reset level or signal level) from ADC 261 under the control of the timing control circuit 212. Selector 263 corresponding to the vertical signal line 308 causes the memory 264 to hold the reset level Pa and supplies the signal level Da to the subtractor 265. On the other hand, selector 263 corresponding to the vertical signal line 309 causes the memory 264 to hold the signal level Db and supplies the reset level Pb to the subtractor 265.

[0056] The subtractor 265 obtains the difference between the signal (reset level or signal level) held in the corresponding memory 264 and the signal from the corresponding selector 263. The subtractor 265 corresponding to the vertical signal line 308 subtracts the reset level Pa held in the memory 264 from the signal level Da from the selector 263 and supplies the result as the net signal level SIGa to the synthesis processing unit 266. On the other hand, the subtractor 265 corresponding to the vertical signal line 309 subtracts the reset level Pb from the selector 263 from the signal level Db held in the memory 264 and supplies the result as the net signal level SIGb to the synthesis processing unit 266. As described above, the process of obtaining the difference between the reset level and the signal level corresponds to the CDS process.

[0057] The synthesis processing unit 266 performs a synthesis process of adding the signal levels SIGa and SIGb for each column. The synthesis processing unit 266 performs various types of signal processing on the image data having the synthesized signal and supplies the processed image data to the recording unit 120.

[0058] The signal level SIGa is a level corresponding to the amount of charge transferred to the analog memory 313. The signal level SIGb is a level corresponding to the amount of charge overflowing from the photoelectric conversion element 311 and is generated at high illuminance. Therefore, by adding these signal levels, the dynamic range of the image data can be expanded.

[0059] Here, a comparative example is assumed in which a plurality of pieces of image data are captured using different exposure times and synthesized. The dynamic range can also be expanded by the method of the comparative example. However, in the comparative example, multiple images need to be taken each time of synthesis, and there is a possibility that the power consumption increases and the frame rate decreases compared to the case where no synthesis is performed.

[0060] On the other hand, in the configuration in which the SIGb at the time of overflow is synthesized with the signal level SIGa for each pixel, the number of imaging times is only once, and the power consumption and the frame rate can be improved compared to the comparative example.

[0061] [Operation example of solid-state imaging device] Figure 5is a timing chart showing an example of the exposure control of the solid-state imaging device 200 according to the first embodiment of the present technology. The vertical scanning circuit 211 supplies a high-level reset signal RSTb and a control signal OFG to all rows (i.e., all pixels) during the period from the moment T0 immediately before the start of exposure to the moment T1 at which exposure starts. Accordingly, the photoelectric conversion elements 311 of all pixels are initialized, and exposure starts simultaneously in all pixels.

[0062] Here, when n is an integer from 1 to n, RSTa_[n], RSTb_[n], OFG_[n], TRG_[n], and SEL_[n] represent the signals of the n-th row.

[0063] Then, the vertical scanning circuit 211 supplies a high-level reset signal RSTa and a high-level transfer signal TRG to all pixels during the pulse period starting from the moment T2 immediately before the start of exposure. Accordingly, the analog memories 313 are reset in all pixels.

[0064] The vertical scanning circuit 211 supplies a high-level transfer signal TRY to all pixels during the pulse period starting from the moment T3 at which exposure ends. Accordingly, the charges are transferred to the analog memories 313 in all pixels, and exposure ends simultaneously in all pixels.

[0065] Figure 6 is a timing chart showing an example of the read operation of the solid-state imaging device 200 according to the first embodiment of the present technology. The vertical scanning circuit 211 sequentially selects and drives rows during the read period after exposure ends, and causes the column signal processing circuit 260 to perform reading. In the figure, Rn represents the read period of the n-th row. After reading all rows, the next exposure starts. In the figure, IG0 is the image data generated by the first exposure, and IG1 is the image data generated by the second exposure.

[0066] During the read period of the n-th row from the moment T10 to the moment T13, the vertical scanning circuit 211 supplies a high-level selection signal SEL to the n-th row. The vertical scanning circuit 211 supplies a high-level reset signal RSTa to the n-th row during the pulse period starting from the moment T11 of the read period. Accordingly, the FD 321 is initialized, and the reset level Pa is read. In addition, the signal level Db at the time of overflow is read in parallel with the reading of the reset level Pa.

[0067] Then, the vertical scanning circuit 211 supplies a high-level reset signal RSTb and a high-level transfer signal TRG to the n-th row during the pulse period starting from the moment T12. Accordingly, the charges are transferred to the FD 321, and the signal level Da is read. In addition, the FD 322 is initialized, and the reset level Pb is read.

[0068] Figure 7 This is an example of the potential diagram of pixel 300 according to the first embodiment of the present technology. In the figure, a shows a cross-sectional view of pixel 300.

[0069] In the figure, b is a potential diagram showing the state of pixel 300 at the start of exposure. As shown in b in the figure, the photoelectric conversion element 311 is initialized.

[0070] C in the figure is a potential diagram showing the state of pixel 300 during exposure. As shown in c in the figure, charges are generated in the photoelectric conversion element 311, and the charges overflowing from the photoelectric conversion element 311 are accumulated in FD 322.

[0071] In the figure, d is a potential diagram showing the state of pixel 300 immediately before the end of exposure. As shown in d in the figure, the vertical scan circuit 211 turns on the transfer transistor 314 immediately before transfer, and the analog memory 313 is initialized.

[0072] In the figure, e is a potential diagram showing the state of pixel 300 immediately after the end of exposure. As shown in e in the figure, charges are transferred from the photoelectric conversion element 311 to the analog memory 313. Then, the vertical scan circuit 211 initializes FD 321. Next, the reset level Pa and the signal level Db at the time of overflow are read.

[0073] F in the figure is a potential diagram showing the state of pixel 300 when reading the signal level Da. As shown in f in the figure, the vertical scan circuit 211 transfers charges from the analog memory 313 to FD 321. Then, the signal level Da is read.

[0074] In the figure, g is a potential diagram showing the state of pixel 300 when FD 322 is initialized. As shown in g in the figure, FD322 is initialized.

[0075] In the figure, h is a potential diagram showing the state of pixel 300 when reading the signal level Pb. In f, g, and h in the figure, for the sake of convenience of explanation, the signal level Da and the signal level Pb are described as being read sequentially, but in fact, they can be read simultaneously.

[0076] Figure 8 This is a flowchart showing an operation example of the solid-state imaging device 200 according to the first embodiment of the present technology. For example, when a predetermined application program for capturing image data is executed, this operation starts.

[0077] The solid-state imaging device 200 performs exposure by the global shutter method (step S901). Then, the solid-state imaging device 200 selects a row and reads the reset level Pa and the signal level Db at the time of overflow for that row (step S902). Next, the solid-state imaging device 200 reads the signal level Da of the selected row and the reset level Pb on the overflow side (step S903).

[0078] The solid-state imaging device 200 performs CDS processing to obtain each of the differences between the reset level Pa and the signal level Da and between the reset level Pb and the signal level Db (step S904). The solid-state imaging device 200 performs combining processing to add the signals after CDS processing (step S905), and determines whether the selected row is the last row (step S906).

[0079] In the case where the selected row is not the last row (step S906: No), the solid-state imaging device 200 repeatedly executes step S902 and subsequent steps. On the other hand, in the case where the selected row is the last row (step S906: Yes), the solid-state imaging device 200 ends the imaging process.

[0080] Note that in the case of continuously capturing a plurality of pieces of image data, the solid-state imaging device 200 repeatedly executes the processing of steps S901 to S906 in synchronization with the vertical synchronization signal.

[0081] As described above, according to the first embodiment of the present technology, since the OFG transistor 315 causes the FD 322 to hold the charge overflowing from the photoelectric conversion element 311, it is possible to expand the dynamic range while suppressing the number of captured images and power consumption.

[0082] <2. Second Embodiment> In the above-described first embodiment, the source follower circuits 340 and 350 are provided for each pixel, but in this configuration, two vertical signal lines and two ADCs are required for each column. The solid-state imaging device 200 of the second embodiment is different from that of the first embodiment in that the source follower circuit 340 and the ADC are removed.

[0083] Figure 9 is a circuit diagram showing a configuration example of the pixel 300 according to the second embodiment of the present technology. The pixel 300 of the second embodiment is different from that of the first embodiment in that the source follower circuit 340 is not provided. In addition, the vertical signal line 308 is not wired, and only one vertical signal line 309 is wired for each column. In addition, the FD 321 is connected to the FD 322, and the reset signal RST from the vertical scanning circuit 211 is input to the gate of the reset transistor 351.

[0084] In addition, in the second embodiment, different from the first embodiment, the signal level Db, the reset level (P-phase), and the signal level Da are read sequentially for each row.

[0085] In addition, in the column signal processing circuit 260, one ADC 261 is provided for each column. In addition, the column signal processing circuit 260 holds the signal level Db and the reset level (P-phase), and obtains the difference therebetween as SIGb. Next, the column signal processing circuit 260 obtains the difference between the signal level Da and the P-phase as SIGa, and performs a combining process of adding SIGa and SIGb.

[0086] Figure 10 is a timing chart showing an example of the exposure control of the solid-state imaging device 200 according to the second embodiment of the present technology. From the moment T0 immediately before the start of exposure to the moment T1 when exposure starts, the vertical scanning circuit 211 supplies a high-level reset signal RST and a high-level control signal OFG to all pixels. Therefore, the photoelectric conversion elements 311 of all pixels are initialized, and exposure starts simultaneously in all pixels.

[0087] Then, the vertical scanning circuit 211 supplies a high-level transfer signal TRY to all pixels in the pulse period starting from the moment T2 when exposure ends. Therefore, charges are transferred to the analog memory 313 in all pixels, and exposure ends simultaneously in all pixels. Note that, different from the first embodiment, the initialization of the FD 321 immediately before exposure is not performed.

[0088] Figure 11 is a timing chart showing an example of the read operation of the solid-state imaging device 200 according to the second embodiment of the present technology.

[0089] During the read period of the n-th row from the moment T10 to the moment T13, the vertical scanning circuit 211 supplies a high-level selection signal SEL to the n-th row. The signal level Db at the time of overflow is read within a predetermined period starting from the moment T10.

[0090] The vertical scanning circuit 211 supplies a high-level reset signal RST to the n-th row in the pulse period starting from the moment T11 after reading the signal level Db. Therefore, the FD 321 and the FD 322 are initialized, and the reset level (P-phase) is read.

[0091] Then, the vertical scanning circuit 211 supplies a high-level transfer signal TRG to the n-th row in the pulse period starting from the moment T12. Therefore, charges are transferred to the FD 211, and the signal level Da is read.

[0092] Figure 12This is an example of the potential diagram of pixel 300 according to the second embodiment of the present technology. In the figure, a shows a cross-sectional view of pixel 300.

[0093] In the figure, b is a potential diagram showing the state of pixel 300 at the start of exposure. As shown in b in the figure, the photoelectric conversion element 311 is initialized.

[0094] C in the figure is a potential diagram showing the state of pixel 300 during exposure. As shown in c in the figure, charges are generated in the photoelectric conversion element 311, and the charges overflowing from the photoelectric conversion element 311 are accumulated in FD 322.

[0095] In the figure, d is a potential diagram showing the state of pixel 300 immediately after the end of exposure. As shown in d in the figure, the charges are transferred from the photoelectric conversion element 311 to the analog memory 313. Then, the reading of the signal level Db during overflow is performed.

[0096] In the figure, e is a potential diagram showing the state of pixel 300 when FD 321 and 322 are initialized. At this time, the reset level is read.

[0097] F in the figure is a potential diagram showing the state of pixel 300 when the signal level Da is read. As shown in f in the figure, the vertical scanning circuit 211 transfers the charges from the analog memory 313 to FD 321. Then, the reading of the signal level Da is performed.

[0098] In the figure, g is a potential diagram showing the state of pixel 300 at the start of the next exposure. As shown in g in the figure, the photoelectric conversion element 311 is initialized again.

[0099] As described above, according to the second embodiment of the present technology, since the source follower circuit 340 is removed, it is possible to easily increase the number of pixels.

[0100] <3. Third Embodiment> In the above second embodiment, the overflow charges are held in FD 322, but in this configuration, the photoelectric conversion element 311 cannot be initialized via FD 322 during the reading process. In other words, a pipelined operation for starting the next exposure cannot be achieved during the reading. The solid-state imaging device 200 of the third embodiment is different from the second embodiment in that an FD and a transistor are added to achieve a pipelined operation.

[0101] Figure 13This is a circuit diagram showing an example of the structure of pixel 300 according to the third embodiment of the present technology. The pixel 300 of the third embodiment is different from that of the second embodiment in that the source follower circuit 350 on the overflow side is omitted instead of the source follower circuit 340. However, the reset transistor 351 is not removed. In addition, the pixel 300 of the third embodiment is different from that of the second embodiment in that it further includes a connection transistor 316, an FDG transistor 317, a metal-insulator-metal (MIM) capacitor 318, and an FD 323.

[0102] The connection transistor 316 opens and closes the path between the FD 322 and the FD 323 according to the control signal CON from the vertical scanning circuit 211. The FDG transistor 317 opens and closes the path between the FD 321 and the FD 323 according to the control signal FDG from the vertical scanning circuit 211. The MIM capacitor 318 is connected to the FD 323. Note that the FDG transistor 317 is an example of the conversion efficiency control transistor described in the claims. In addition, the FD 323 is an example of the third floating diffusion layer described in the claims.

[0103] Here, for example, it is assumed that the capacitance value of the FD 321 is approximately the same as that of the FD 322. In addition, from the perspective of reducing noise, the capacitance value of the FD 323 is preferably more than 10 times that of the FD 321 (or the FD 322).

[0104] In addition, in the third embodiment, similar to the second embodiment, the signal levels Db, the set level (P phase), and the signal level Da are sequentially read for each row. Then, during the readout period, the vertical scanning circuit 211 can start the next exposure. This is because at the end of the exposure, the overflow charge is transferred from the FD 322 to the MIM capacitor 318.

[0105] Figure 14 This is a timing chart showing an example of the exposure control of the solid-state imaging device 200 according to the third embodiment of the present technology. From the moment T0 immediately before the start of the exposure to the moment T1 when the exposure starts, the vertical scanning circuit 211 supplies a high-level reset signal RSTb and a high-level control signal OFG to all pixels. Therefore, the photoelectric conversion elements 311 of all pixels are initialized, and the exposure starts simultaneously in all pixels.

[0106] Then, immediately before the end of the exposure, the vertical scanning circuit 211 turns on the reset transistor 341, the transfer transistor 314, and the FDG transistor 317 of all pixels within the pulse period through the reset signal RSTa, the transfer signal TRG, and the control signal FDG. Therefore, the FD 321, the FD 323, and the analog memory 313 are initialized.

[0107] The vertical scanning circuit 211 supplies a high-level transfer signal TRY and a control signal CON to all the pixels within a pulse period starting from the moment T3 when the exposure ends. Accordingly, charges are transferred to the analog memories 313 of all the pixels, and the charges are transferred from the FD 322 to the MIM capacitor 318, and the exposure ends simultaneously in all the pixels.

[0108] Figure 15 is a timing chart showing an example of the read operation of the solid-state imaging device 200 according to the third embodiment of the present technology.

[0109] During the read period of the n-th row from the moment T10 to the moment T14, the vertical scanning circuit 211 supplies a high-level selection signal SEL to the n-th row. The vertical scanning circuit 211 supplies a high-level control signal FDG to the n-th row within a pulse period starting from the immediately subsequent moment T11. Accordingly, charges are transferred from the FD 323 to the FD 321, and the signal level Db at the time of overflow is read.

[0110] The vertical scanning circuit 211 supplies a high-level reset signal RSTa and a high-level control signal FDG to the n-th row within a pulse period starting from the moment T12 after reading the signal level Db. Accordingly, the FDs 321 and 323 are initialized, and the reset level (P-phase) is read.

[0111] Then, the vertical scanning circuit 211 supplies a high-level transfer signal TRG to the n-th row within a pulse period starting from the moment T13. Accordingly, charges are transferred to the FD 321, and the signal level Da is read. At this time, a high-level control signal FDG is supplied as needed.

[0112] In addition, since the overflow charges have been transferred from the FD 322 to the MIM capacitor 318 at the end of the exposure, the vertical scanning circuit 211 can start the next exposure during the reading of each row. Accordingly, a pipelined operation in which the next exposure is started during the reading can be achieved.

[0113] Figure 16 is an example of the potential diagram of the pixel 300 according to the third embodiment of the present technology. In the figure, a shows a cross-sectional view of the pixel 300.

[0114] In the figure, b is a potential diagram showing the state of the pixel 300 at the start of the exposure. As shown in b in the figure, the photoelectric conversion element 311 is initialized.

[0115] C in the figure is a potential diagram showing the state of the pixel 300 being exposed. As shown in c in the figure, charges are generated in the photoelectric conversion element 311, and the charges overflowing from the photoelectric conversion element 311 are accumulated in the FD 322.

[0116] In the figure, d is a potential diagram showing the state of pixel 300 immediately after the end of exposure. As shown by d in the figure, the vertical scanning circuit 211 turns on the transfer transistor 312 and transfers the charge from the photoelectric conversion element 311 to the analog memory 313. In addition, the vertical scanning circuit 211 turns on the connection transistor 316 to transfer the charge from the FD 322 to the MIM capacitor 318.

[0117] Then, as shown by e in the figure, after the pulse period has passed, the vertical scanning circuit 211 turns off the transfer transistor 312 and the connection transistor 316. At this time, since the overflow charge is transferred to the MIM capacitor 318, the vertical scanning circuit 211 can start the next exposure.

[0118] In the figure, f is a potential diagram showing the state of pixel 300 when reading the signal level Db. As shown by f in the figure, the vertical scanning circuit 211 turns on the FDG transistor 317 and transfers the charge from the MIM capacitor 318 to the FD 321. Then, the reading of the signal level Db is performed.

[0119] Then, as shown by g in the figure, the vertical scanning circuit 211 turns off the FDG transistor.

[0120] In the figure, h is a potential diagram showing the state of pixel 300 when reading the reset level. As shown by h in the figure, the vertical scanning circuit 211 initializes the FD 321 and the FD 323. Then, the reading of the reset level is performed.

[0121] In the figure, i is a potential diagram showing the state of pixel 300 during charge transfer. As shown by i in the figure, the vertical scanning circuit 211 turns on the transfer transistor 314 to transfer the charge from the analog memory 313 to the FD 321.

[0122] Next, as shown by j in the figure, the vertical scanning circuit 211 turns off the transfer transistor 314 after the end of the pulse period. Then, the reading of the signal level Da is performed.

[0123] As described above, according to the third embodiment of the present technology, the vertical scanning circuit 211 controls the connection transistor 316 at the end of exposure and transfers the overflow charge from the FD 322 to the MIM capacitor 318, enabling a pipelined operation.

[0124] <4. Fourth Embodiment> In the above third embodiment, the FD 321 and the source follower circuit 340 are provided for each pixel, but in this configuration, it is difficult to reduce the circuit scale of each pixel. The solid-state imaging device 200 of the fourth embodiment is different from the third embodiment in that the FD 321 and the source follower circuit 340 are shared by a plurality of pixels.

[0125] Figure 17 This is a circuit diagram showing an example of the structure of pixel block 221 in the fourth embodiment of the present technology. In the fourth embodiment, the pixel array section 220 is divided into a plurality of pixel blocks 221. In each pixel block 221, a plurality of pixels sharing the common FD 321 and source follower circuit 340 are arranged. For example, four pixels in a 2-row × 2-column arrangement are arranged in pixel block 221.

[0126] For example, pixel circuits 310-1, 310-2, 310-3, and 310-4, FD 321, and source follower circuit 340 are provided in pixel block 221.

[0127] In pixel circuit 310-2, a photoelectric conversion element 311, transfer transistors 312 and 314, analog memory 313, OFG transistor 315, and FD 322 are arranged. In pixel circuit 310-2, a reset transistor 351, connection transistor 316, FDG transistor 317, MIM capacitor 318, and FD 323 are also provided. These connection structures are similar to the connection structures of the third embodiment. The circuit structures of pixel circuits 310-1, 310-3, and 310-4 are similar to the circuit structure of pixel circuit 310-2.

[0128] In addition, pixel circuits 310-1, 310-2, 310-3, and 310-4 share FD 321 and source follower circuit 340. By this sharing, compared with the third embodiment in which FD 321 and source follower circuit 340 are provided for each pixel, the circuit scale of each pixel can be reduced.

[0129] Note that the number of pixels sharing FD 321, etc. is not limited to four pixels and can be two pixels, eight pixels, etc. In addition, the sharing structure of the fourth embodiment can also be applied to the first embodiment and the second embodiment.

[0130] As described above, according to the fourth embodiment of the present technology, since a plurality of pixels share FD 321, etc., the circuit scale of each pixel can be reduced compared with the third embodiment.

[0131] <5. Fifth Embodiment> In the above-described first embodiment, overflow charge is held in FD 322. However, in this structure, due to the influence of fitted pattern noise (FPN) caused by the dark current of FD321, the linearity deteriorates. The solid-state imaging device 200 according to the fifth embodiment is different from the first embodiment in that overflow charge is held in analog memory 313.

[0132] Figure 18 This is a circuit diagram showing an example of the structure of pixel 300 according to the fifth embodiment of the present technology. The pixel 300 of the fifth embodiment is different from that of the first embodiment in that the source follower circuit 340 is not provided, and the FDG transistor 317 is also provided.

[0133] In addition, the transfer transistor 314 transfers charges from the photoelectric conversion element 311 to the FD 321 according to the transfer signal TRG. The transfer transistor 312 transfers the charges overflowing from the photoelectric conversion element 311 to the analog memory 313 according to the control signal OFY. The OFG transistor 315 transfers the overflow charges from the analog memory 313 to the FD 322 and causes the FD 322 to hold the charges. The FDG transistor 317 opens and closes the path between the FD 321 and the FD 322 according to the control signal FDG. The FD 321 is connected to the gate of the amplification transistor 352.

[0134] Figure 19 This is a timing diagram showing an example of the exposure control of the solid-state imaging device 200 according to the fifth embodiment of the present technology. During the period from the moment T0 immediately before the start of exposure to the moment T1 when the exposure starts, the vertical scanning circuit 211 supplies a high-level reset signal RST, a control signal OFG, and a control signal OFY to all pixels. Therefore, the photoelectric conversion elements 311 of all pixels are initialized, and the exposure starts simultaneously in all pixels.

[0135] Then, the vertical scanning circuit 211 supplies a high-level reset signal RSTa and a high-level control signal FDG to all pixels in the pulse period starting from the moment T2 immediately before the end of the exposure period. Therefore, the FDs 321 and 322 of all pixels are initialized.

[0136] The vertical scanning circuit 211 supplies a high-level transfer signal TRG and a high-level control signal OFG to all pixels in the pulse period starting from the moment T3 when the exposure ends. Therefore, charges are transferred from the photoelectric conversion element 311 to the FD 321, and the overflow charges are transferred from the analog memory 313 to the FD 322, and the exposure of all pixels ends.

[0137] Figure 20 This is a timing diagram showing an example of the read operation of the solid-state imaging device 200 according to the fifth embodiment of the present technology.

[0138] During the read period of the nth row from the moment T10 to the moment T13, the vertical scanning circuit 211 supplies a high-level selection signal SEL to the nth row. The signal level Da is read during the pre-time period starting from the moment T10.

[0139] During the pulse period starting at time T11 after the read signal level Da is read, the vertical scanning circuit 211 supplies a high-level transfer signal TRG, a high-level control signal OFG, and a high-level control signal FDG to the n-th row. As a result, charge is transferred from the FD 322 to the FD 321, and the signal level Db at the time of overflow is read.

[0140] Then, during the pulse period starting at time T12 after the read signal level Db is read, the vertical scanning circuit 211 supplies a high-level reset signal RST, a high-level transfer signal TRG, a high-level control signal OFG, and a high-level control signal FDG to the n-th row. As a result, the FD 321 and the FD 322 are initialized, and the reset level (P-phase) is read.

[0141] Figure 21 This is an example of the potential diagram of the pixel 300 according to the fifth embodiment of the present technology. In the figure, a shows a cross-sectional view of the pixel 300.

[0142] In the figure, b is a potential diagram showing the state of the pixel 300 at the start of exposure. As shown in b in the figure, the photoelectric conversion element 311 is initialized.

[0143] C in the figure is a potential diagram showing the state of the pixel 300 during exposure. As shown in c in the figure, charge is generated in the photoelectric conversion element 311, and the charge overflowing from the photoelectric conversion element 311 accumulates in the analog memory 313.

[0144] In the figure, d is a potential diagram showing the state of the pixel 300 immediately before the end of exposure. As shown in d in the figure, the vertical scanning circuit 211 turns on the reset transistor 351 and the FDG transistor 317, and initializes the FD 321 and the FD 322.

[0145] In the figure, e is a potential diagram showing the state of the pixel 300 at the end of exposure. As shown in e in the figure, the vertical scanning circuit 211 turns on the transfer signal TRG and the control signal OFG. As a result, charge is transferred from the photoelectric conversion element 311 to the FD 321, and the overflow charge is transferred from the analog memory 313 to the FD 322. Then, the read of the signal level Da is performed.

[0146] In the figure, f is a potential diagram showing the state of the pixel 300 when the signal level Db is read. As shown in f in the figure, the vertical scanning circuit 211 turns on the transfer signal TRG, the control signal OFG, and the control signal FDG. As a result, charge is transferred from the FD 322 to the FD 321, and the read of the signal level Db is performed.

[0147] In the figure, g is a potential diagram showing the state of pixel 300 at the read reset level. As shown by g in the figure, the vertical scanning circuit 211 turns on the reset transistor 351, transfer transistor 314, OFG transistor 315, and FDG transistor 317. Accordingly, FD 321 and FD 322 are initialized, and the read of the reset level is performed.

[0148] In the figure, h is a potential diagram showing the state of pixel 300 at the start of the next exposure. As shown by f in the figure, the photoelectric conversion element 311 is initialized again.

[0149] As shown, by having the analog memory 313 hold the charge overflowing from the photoelectric conversion element 311, deterioration of linearity can be suppressed.

[0150] As described above, according to the fifth embodiment of the present technology, since the charge overflowing from the photoelectric conversion element 311 is stored in the analog memory 313, deterioration of linearity can be suppressed as compared with the case where the overflow charge is held in FD 322.

[0151] <6. Sixth Embodiment> In the first embodiment described above, the charge is held in the analog memory 313 located at the pre-stage of FD 321. As described above, the method of holding the charge in the analog memory 313 before charge-voltage conversion is called the charge domain method. In this charge domain method, it is difficult to achieve miniaturization and an increase in the saturation capacity in order to ensure the area of the analog memory 313. The solid-state imaging device 200 of the sixth embodiment is different from that of the first embodiment in that a sample-and-hold circuit 400 is added.

[0152] Figure 22 is a circuit diagram showing a configuration example of pixel 300 according to the sixth embodiment of the present technology. In pixel 300 of the sixth embodiment, the selection transistor 353 is not provided. Further, pixel 300 of the sixth embodiment is different from that of the first embodiment in that it further includes a switch 354, a switching transistor 355, a precharge transistor 356, a current source transistor 357, and a sample-and-hold circuit 400. The switch 354, switching transistor 355, precharge transistor 356, and current source transistor 357 are provided in the source follower circuit 350.

[0153] The switch 354 selects the power supply voltage VDD or the voltage Vread under the control of the vertical scanning circuit 211, and supplies the selected voltage to the drain of the amplifying transistor 352. The power supply voltage VDD is selected when the sample-and-hold circuit 400 samples and holds a level. On the other hand, the voltage Vread is selected when the level is read from the sample-and-hold circuit 400 and AD conversion is performed for each row.

[0154] Here, the voltage Vread is set to the value shown in the following formula. Vread = VDD - Vgs - Vft In the above formula, Vgs represents the gate-source voltage of the amplifying transistor 352. Vft is the amount of change in the potential of the FD 322 caused by the reset feedthrough of the reset transistor 351.

[0155] By switching to the voltage Vread during reading, the amplifying transistor 352 is turned off, and the noise generated in the transistor can be reduced.

[0156] The switching transistor 355 opens and closes the path between the source of the amplifying transistor 352 and the sample-and-hold circuit 400 according to the control signal SW from the vertical scanning circuit 211.

[0157] The precharge transistor 356 opens and closes the path between the switching transistor 355 and the current source transistor 357 according to the control signal PC from the vertical scanning circuit 211.

[0158] In addition, the sample-and-hold circuit 400 includes capacitor elements 411 and 412, selection transistors 421 and 422, and a reset transistor 431, an amplifying transistor 432, and a selection transistor 433.

[0159] One ends of the capacitor elements 411 and 412 are commonly connected to the pre-stage node that is the connection node of the switching transistor 355 and the precharge transistor 356. The selection transistors 421 and 422 are inserted in parallel between the other ends of the capacitor elements 411 and 412 and a predetermined post-stage node.

[0160] The selection transistor 421 opens and closes the path between the capacitor element 411 and the post-stage node according to the selection signal S1 received from the vertical scanning circuit 211. The selection transistor 422 opens and closes the path between the capacitor element 412 and the post-stage node according to the selection signal S2 received from the vertical scanning circuit 211.

[0161] Under the control of the selection transistors 421 and 422, the vertical scanning circuit 211 can cause the capacitor elements 411 and 412 to hold the reset level and the signal level. Note that the capacitor elements 411 and 412 are examples of the first and second capacitor elements described in the claims.

[0162] The reset transistor 431 initializes the subsequent-stage node according to the reset signal RB received from the vertical scanning circuit 211. The amplifying transistor 432 amplifies the voltage of the subsequent-stage node. The selection transistor 433 outputs the amplified voltage signal as a pixel signal to the vertical signal line 309 according to the selection signal SEL.

[0163] In addition, the circuits and elements in the solid-state imaging device 200 are dispersedly arranged on each of the stacked pixel chips 201 and circuit chips 202. For example, the elements before the switching transistor 355 of the pixel 300 are arranged in the pixel chip 201, and the remaining elements of the pixel 300 and the circuits at the subsequent stage of the pixel 300 are arranged in the circuit chip 202. Note that the circuits and elements in the solid-state imaging device 200 can also be dispersedly arranged on three or more semiconductor chips. In addition, the circuits and elements can be arranged on one semiconductor chip without forming a stacked structure.

[0164] As shown in the figure, the method in which the sample-and-hold circuit 400 samples and holds the level after charge-voltage conversion is called the voltage domain method. Compared with the voltage domain method, the above-mentioned charge domain method reduces random noise, but it is difficult to achieve miniaturization and an increase in the saturation capacity. On the other hand, in the voltage domain system, compared with the charge domain system, it is very easy to achieve miniaturization and an increase in the saturation capacitance, but it will increase random noise. By holding the overflow-side level less affected by random noise through the voltage domain method, it is possible to achieve miniaturization and an increase in the saturation capacity while suppressing random noise. This can lead to an improvement in image quality.

[0165] In the sixth embodiment, the control of the reset signals RSTa and RSTb, the control signal OFG, and the transmission signals TRY and TRG from the start to the end of exposure is similar to Figure 10 that shown.

[0166] In addition, the vertical scanning circuit 211 turns on the selection transistors 421 of all pixels through the selection signal S1 within a certain period from the pulse transmission of the reset signal RSTb. Therefore, the reset level Pb is sampled and held in the capacitive element 411.

[0167] In addition, the vertical scanning circuit 211 turns on the selection transistors 422 of all pixels through the selection signal S2 within a certain period from the pulse transmission time of the transmission signal TRY. Therefore, the signal level Db is sampled and held in the capacitive element 412.

[0168] In addition, the power supply voltage VDD is selected by the switch 354 during exposure, and the voltage Vread .

[0169] Then, during the readout period, the vertical scanning circuit 211 turns on the reset transistor 431 of the selected row through the reset signal RB within the pulse period.

[0170] Immediately after the initialization of the post-stage node, the vertical scanning circuit 211 turns on the selection transistor 421 of the selected row through the selection signal S1 for a certain period. At this time, the reset levels Pa and Pb are read.

[0171] After reading the reset levels Pa and Pb, the vertical scanning circuit 211 turns on the selection transistor 421 of the selected row through the selection signal S1 for a certain period. At this time, the readout signal levels Da and Db are read.

[0172] In addition, during the readout period, the selection transistors 343 and 433 of the selected row are controlled to be in the conducting state.

[0173] As described above, according to the sixth embodiment of the present technology, the sample-and-hold circuit 400 samples and holds the reset level Rb and the signal level Db on the overflow side, thereby enabling improvement in image quality.

[0174] [First Modification Example] In the above sixth embodiment, the sample-and-hold circuit 400 sequentially outputs the reset level Rb and the signal level Db via the vertical signal line 309. However, with this configuration, it is difficult to further increase the readout speed. The solid-state imaging device 200 of the first modification example of the sixth embodiment is different from the sixth embodiment in that the sample-and-hold circuit 400 outputs the reset level Rb and the signal level Db simultaneously via two vertical signal lines.

[0175] Figure 23 FIG. is a circuit diagram showing a configuration example of the sample-and-hold circuit 400 according to the first modification example of the sixth embodiment of the present technology. The reset transistor 431 is removed from the sample-and-hold circuit 400 of the first modification example of the sixth embodiment. In addition, the sample-and-hold circuit 400 includes amplification transistors 432-1 and 432-2 and selection transistors 433-1 and 433-2 instead of the amplification transistor 432 and the selection transistor 433.

[0176] In addition, the switch 354, the switching transistor 355, and the precharge transistor 356 are not provided in the pre-stage source follower circuit 350. In addition, in addition to the vertical signal line 308 (not shown), vertical signal lines 309-1 and 309-2 are provided for each column wiring.

[0177] The selection transistor 421 turns on and off the path between the connection node of the amplification transistor 352 and the current source transistor 357 and one end of the capacitor element 411. The selection transistor 422 turns on and off the path between the connection node of the amplification transistor 352 and the current source transistor 357 and one end of the capacitor element 412.

[0178] The amplification transistor 432-1 amplifies the voltage at one end of the capacitor element 411, and the selection transistor 433-1 outputs the pixel signal to the vertical signal line 309-1. The amplification transistor 432-2 amplifies the voltage at one end of the capacitor element 412, and the selection transistor 433-2 outputs the pixel signal to the vertical signal line 309-2. In addition, in the column signal processing circuit 260, three ADCs 261 are provided for each column.

[0179] The sample-and-hold circuit 400 can output the reset level Rb and the signal level Db simultaneously via the vertical signal lines 309-1 and 309-2. In addition, compared with the sixth embodiment, it is not necessary to initialize the post-stage node through the reset transistor 341 during reading, so that the reading speed can be further improved.

[0180] As described above, according to the first modification of the sixth embodiment of the present technology, since the sample-and-hold circuit 400 outputs the reset level Rb and the signal level Db via two vertical signal lines, it is not necessary to initialize the post-stage node during reading. Therefore, the reading speed can be further improved.

[0181] [Second Modification] In the above-described sixth embodiment, the selection transistors 421 and 422 are inserted in parallel between the capacitor elements 411 and 422 and the post-stage node. However, in this configuration, it is difficult to further reduce the circuit scale. The solid-state imaging device 200 according to the second modification of the sixth embodiment is different from the sixth embodiment in that the selection transistors 421 and 422 are connected in series.

[0182] Figure 24 is a circuit diagram showing a configuration example of the sample-and-hold circuit 400 according to the second modification of the sixth embodiment of the present technology. The reset transistor 431 is removed from the sample-and-hold circuit 400 according to the second modification of the sixth embodiment.

[0183] In addition, the switch 354, the switching transistor 355 and the precharge transistor 356 are not provided in the source follower circuit 350 at the previous stage.

[0184] In addition, selection transistors 421 and 422 are inserted in series between the connection node of amplifier transistor 352 and current source transistor 357 and amplifier transistor 432. A capacitive element 412 is inserted between the connection node of selection transistors 421 and 422 and the ground node, and a capacitive element 411 is inserted between the connection node of selection transistors 421 and amplifier transistor 432 and the ground node.

[0185] For example, the control method of the sample-and-hold circuit 400 is described in "ISSCC 2019, Chen Xu et al., Stacked global shutter CMOS imager with SC-type hybrid GS pixels and self-inflection point calibration single-frame HDR, and on-chip binarization algorithm for intelligent vision applications".

[0186] As described above, according to the second modification of the sixth embodiment of the present technology, since selection transistors 421 and 422 are connected in series, the reset transistor 431 can be removed.

[0187] [Third Modification Example] In the above sixth embodiment, selection transistors 421 and 422 are inserted in parallel between capacitive elements 411 and 422 and the subsequent-stage node. However, in this configuration, it is difficult to further reduce the circuit scale. The solid-state imaging device 200 of the third modification example of the sixth embodiment is different from the sixth embodiment in that selection transistor 422 and capacitive element 411 are connected in series, and a capacitive element 412 is inserted between their connection node and the ground node.

[0188] Figure 25 It is a circuit diagram showing a configuration example of the sample-and-hold circuit 400 according to the third modification example of the sixth embodiment of the present technology. Selection transistor 421 is removed from the sample-and-hold circuit 400 of the third modification example of the sixth embodiment.

[0189] In addition, the switch 354, switching transistor 355, and precharge transistor 356 are not provided in the source follower circuit 350 of the previous stage.

[0190] Selection transistor 422 and capacitive element 411 are inserted in series between the connection node of amplifier transistor 352 and current source transistor 357 and the subsequent-stage node. Capacitive element 412 is inserted between the connection node of selection transistor 422 and capacitive element 411 and the ground terminal.

[0191] For example, the control method of the sample-and-hold circuit 400 is described in "ISSCC 2020, Jae-kyu Lee et al., 2.1e- temporal noise and -105dB parasitic photosensitivity back-illuminated 2.3μm pixel voltage-domain global shutter CMOS image sensor using high-capacity DRAM capacitor technology".

[0192] As described above, according to the third modification of the sixth embodiment of the present technology, since the selection transistor 422 and the capacitor element 411 are connected in series, and the capacitor element 412 is inserted between the connection node and the ground node, the selection transistor 421 can be omitted.

[0193] <7. Seventh Embodiment> In the above-described first embodiment, the sample-and-hold circuit 400 samples and holds the reset level Rb and the signal level Db, but with this configuration, it is difficult to further expand the dynamic range. The solid-state imaging device 200 of the seventh embodiment is different from the sixth embodiment in that the conversion efficiency is switched in a multi-stage manner.

[0194] Figure 26 It is a circuit diagram showing a configuration example of the pixel 300 according to the seventh embodiment of the present technology. The pixel 300 of the seventh embodiment is different from the sixth embodiment in that it further includes an FCG transistor 319, an FDG transistor 317, and a MIM capacitor 318. In addition, transistors and capacitors are added to the sample-and-hold circuit 400.

[0195] The FCG transistor 319 opens and closes the path between the reset transistor 351 and the FDG transistor 317 according to a control signal FCG from the vertical scanning circuit 211. In addition, one end of the MIM capacitor 318 is connected to the connection node between the reset transistor 351 and the FCG transistor 319. The FDG transistor 317 opens and closes the path between the FCG transistor 319 and the FD322 according to the control signal FDG.

[0196] The conversion efficiency in the case where only the FDG transistor 317 is in the on state among the FCG transistor 319 and the FDG transistor 317 is lower than the case where both of these transistors are in the off state. In addition, when both the FCG transistor 319 and the FDG transistor 317 are on, the conversion efficiency is lower than the case where only the FDG transistor 317 is on. As described above, by controlling each of the FCG transistor 319 and the FDG transistor 317, the conversion efficiency can be switched in a three-stage manner. The highest conversion efficiency is referred to as "high conversion gain (HCG)", and the lowest conversion efficiency is referred to as "low conversion gain (LCG)". The intermediate conversion efficiency between HCG and LCG is referred to as "medium conversion gain (MCG)".

[0197] Figure 27 It is a circuit diagram showing a configuration example of the sample-and-hold circuit 400 according to the seventh embodiment of the present technology. The sample-and-hold circuit 400 of the seventh embodiment is different from the sixth embodiment in that it further includes capacitor elements 413, 414, 415, 416 and selection transistors 423, 424, 425, and 426.

[0198] The connection configurations of the capacitor elements 411 and 412 and the selection transistors 421 and 422 are similar to those of the sixth embodiment.

[0199] One end of each of the capacitor elements 413, 414, 415, and 416 is commonly connected to the pre-stage node. The selection transistor 423 opens and closes the path between the other end of the capacitor element 413 and the post-stage node according to the selection signal S3 from the vertical scanning circuit 211. The selection transistor 424 opens and closes the path between the other end of the capacitor element 414 and the post-stage node according to the selection signal S4 from the vertical scanning circuit 211. The selection transistor 425 opens and closes the path between the other end of the capacitor element 415 and the post-stage node according to the selection signal S5 from the vertical scanning circuit 211. The selection transistor 426 opens and closes the path between the other end of the capacitor element 416 and the post-stage node according to the selection signal S6 from the vertical scanning circuit 211.

[0200] Note that the capacitor elements 413 and 414 are examples of the third and fourth capacitor elements described in the claims.

[0201] Under the control of the selection transistors 421 to 426, the vertical scanning circuit 211 can hold the capacitor elements 411 to 416 at six different levels.

[0202] The column signal processing circuit 260 performs CDS processing for each conversion efficiency of each stage and synthesizes these pixel signals. Therefore, the dynamic range can be expanded.

[0203] Note that the switching transistor 355 may also be omitted. In addition, although the conversion efficiency is switched in three levels, the conversion efficiency may also be switched in two levels or multiple levels of four levels or more. In this case, the number of capacitor elements and selection transistors is adjusted according to the number of levels of the conversion efficiency. In addition, the first modification of the sixth embodiment can be applied to the seventh embodiment.

[0204] Figure 28 is a timing chart showing an example of the exposure control of the solid-state imaging device according to the seventh embodiment of the present technology.

[0205] During the period from the moment T0 immediately before the start of exposure to the moment T1, the vertical scanning circuit 211 supplies the high-level reset signals RSTa, RSTb, and RB and the transfer signal TRG to all pixels. Therefore, exposure starts in all pixels.

[0206] In addition, the vertical scanning circuit 211 sets the control signals FDG and FCG, selection signals S1 to S6, and control signal PC of all pixels to high level at time T0, and sets the control signal OFG and reset signal RB of all pixels to low level at time T1.

[0207] Then, the vertical scanning circuit 211 sets the selection signal S5 of all pixels to low level at time T2. Therefore, the reset level Pb corresponding to LCG is sampled and held.

[0208] At the moment T3 when the exposure starts, the vertical scanning circuit 211 sets the control signals FDG and FCG of all pixels to low level, and sets the selection signal SEL to high level. Therefore, MIMVDD, which is the level of the MIM capacitor 318, drops.

[0209] At the moment T4 when the exposure ends, the vertical scanning circuit 211 returns the selection signal SEL of all pixels to low level. Therefore, MIMVDD increases.

[0210] Then, the vertical scanning circuit 211 sets the control signals FDG and FCG and transfer signal TRY of all pixels to high level at time T5, and sets the control signal FCG and transfer signal TRY to low level at time T6. Therefore, charges are transferred to the analog memory 313.

[0211] Then, the vertical scanning circuit 211 sets the transfer signal TRG and selection signal SEL of all pixels to high level at time T7, and sets the selection signal S3 and reset signal RB to low level. The vertical scanning circuit 211 sets the transfer signal TRG and selection signal SEL of all pixels to low level at time T8, and sets the reset signal RB to high level. Therefore, the reset level Pb corresponding to MCG is sampled and held.

[0212] Then, the vertical scanning circuit 211 sets the selection signal S1 and reset signal RB of all pixels to low level at time T9, and sets the control signal OFG and reset signal RB to high level at time T10 to set the selection signal S2 to low level. Therefore, the reset level Pb corresponding to HCG is sampled and held.

[0213] Then, the vertical scanning circuit 211 sets the control signal OFG and reset signal RB of all pixels to low level at time T11, and sets the control signals FDG and OFG and reset signal RB to high level at time T12 to set the selection signal S4 to low level. Therefore, the signal level Db corresponding to HCG is sampled and held.

[0214] Then, the vertical scanning circuit 211 sets the control signal OFG and the reset signal RB to low level for all pixels at time T13, and sets the control signals FCG and OFG and the reset signal RB to high level at time T14 to set the selection signal S6 to low level. Accordingly, the signal level Db corresponding to MCG is sampled and held.

[0215] Then, the vertical scanning circuit 211 sets the control signal OFG and the reset signal RB to low level for all pixels at time T15, and sets the control signals FDG, FCG, and PC to low level at time T16. Accordingly, the signal level Db corresponding to LCG is sampled and held.

[0216] At the time of reading, in parallel with reading the reset level Pa and the signal level Da of the selected row, the reset level Pb corresponding to HCG, MCG, and LCG and the signal levels Db corresponding to HCG, MCG, and LCM are sequentially read.

[0217] Figure 29 is an example of a potential diagram of a pixel according to the seventh embodiment of the present technology. In the figure, a shows a cross-sectional view of the pixel 300.

[0218] In the figure, b is a potential diagram showing the state of the pixel 300 during exposure. As shown in b in the figure, the photoelectric conversion element 311 is initialized.

[0219] In the figure, c is a potential diagram showing the state of the pixel 300 when holding the reset level Pb corresponding to LCG.

[0220] In the figure, d is a potential diagram showing the state of the pixel 300 during exposure. As shown in d in the figure, the charge overflowing from the photoelectric conversion element 311 is transferred to the FD or the MIM capacitor 318 at the subsequent stage of the OFG transistor 315. In addition, the level of the MIM capacitor 318 drops during exposure.

[0221] In the figure, e is a potential diagram showing the state of the pixel 300 at the end of exposure. As shown in e in the figure, the level of the MIM capacitor 318 is raised.

[0222] In the figure, f is a potential diagram showing the state of the pixel 300 immediately after exposure. As shown in f in the figure, the transfer transistor 312, the FDG transistor 317, and the FCG transistor 319 are turned on, and the dark current of the FD is averaged.

[0223] In the figure, g is a potential diagram showing the state of pixel 300 when the signal level Db corresponding to MCG and the reset level Pb are maintained. As shown by g in the figure, charge is transferred to FD 321, and the FDG transistor 317 is turned on. Further, in g of the figure, the capacitance of the MIM capacitor 318 is small, and the charge of the photoelectric conversion element 311 cannot be fully accepted, and the charge remains in the photoelectric conversion element 311.

[0224] In the figure, h is a potential diagram showing the state of pixel 300 when the reset level Pb corresponding to HCG is maintained.

[0225] In the figure, i is a potential diagram showing the state of pixel 300 when the signal level Db corresponding to HCG is maintained. As shown by i in the figure, the charge remaining in the photoelectric conversion element 311 is transferred to FD 322.

[0226] In the figure, j is a potential diagram showing the state of pixel 300 when the signal level Db corresponding to MCG is maintained.

[0227] In the figure, k is a potential diagram showing the state of pixel 300 when the signal level Db corresponding to LCG is maintained.

[0228] As described above, according to the seventh embodiment of the present technology, since the conversion efficiency is switched in a three-level manner, the dynamic range can be expanded compared to the sixth embodiment.

[0229] <8. Application Examples of Mobile Bodies> The technology of the present invention (this technology) can be applied to various products. For example, the technology of the present invention can be implemented in the form of a device mounted on any type of mobile body such as an automobile, an electric vehicle, a hybrid vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, a drone, a ship, or a robot.

[0230] Figure 30 is a block diagram showing a schematic configuration example of a vehicle control system as an example of a mobile body control system to which the technology of the present invention can be applied.

[0231] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. In Figure 30 the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside vehicle information detection unit 12030, an inside vehicle information detection unit 12040, and an integrated control unit 12050. Further, as a functional configuration of the integrated control unit 12050, a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network interface (I / F) 12053 are shown.

[0232] The drive system control unit 12010 controls the operation of devices related to the vehicle's drive system according to various types of programs. For example, the drive system control unit 12010 serves as a control device for the following devices: a driving force generation device such as an internal combustion engine or a drive motor for generating the vehicle's driving force, a driving force transmission mechanism for transmitting the driving force to the wheels, a steering mechanism for adjusting the vehicle's steering angle, and a braking device for generating the vehicle's braking force, etc.

[0233] The body system control unit 12020 controls the operation of various types of devices provided on the vehicle according to various types of programs. For example, the body system control unit 12020 serves as a control device for a keyless entry system, a smart key system, an electric window device, or various lights such as headlights, reverse lights, brake lights, turn signal lights, or fog lights. In this case, radio waves transmitted from a mobile device substituting for a key or signals from various types of switches can be input to the body system control unit 12020. The body system control unit 12020 receives the input of these radio waves or signals and controls the vehicle's door lock device, electric window device, or lights, etc.

[0234] The vehicle exterior information detection unit 12030 detects information outside the vehicle including the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected to the imaging unit 12031. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image of the outside of the vehicle and receives the captured image. Based on the received image, the vehicle exterior information detection unit 12030 can perform detection processing of objects such as people, vehicles, obstacles, signs, or characters on the road surface, or can perform processing for detecting the distance to the above objects.

[0235] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or can output the electrical signal as ranging information. In addition, the light received by the imaging unit 12031 can be visible light, or can be invisible light such as infrared light.

[0236] The vehicle interior information detection unit 12040 detects information inside the vehicle. The vehicle interior information detection unit 12040 is connected, for example, to a driver state detection unit 12041 that detects the driver's state. The driver state detection unit 12041 includes, for example, a camera that images the driver. Based on the detection information input from the driver state detection unit 12041, the vehicle interior information detection unit 12040 can calculate the driver's fatigue level or the driver's concentration level, or can determine whether the driver is dozing off.

[0237] The microcomputer 12051 can calculate the control target values of the driving force generating device, the steering mechanism, or the braking device based on the information of the outside or inside of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040, and output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an advanced driver assistance system (ADAS), and the ADAS functions include collision avoidance or impact mitigation of the vehicle, following driving based on the inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, or vehicle lane departure warning, etc.

[0238] In addition, by controlling the driving force generating device, the steering mechanism, the braking device, etc. based on the information of the outside or inside of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040, the microcomputer 12051 can perform cooperative control aimed at realizing autonomous driving, etc., and the autonomous driving enables the vehicle to drive autonomously without relying on the driver's operation.

[0239] Furthermore, based on the information about the outside of the vehicle obtained by the outside vehicle information detection unit 12030, the microcomputer 12051 can output a control command to the body system control unit 12020. For example, the microcomputer 12051 can perform cooperative control aimed at preventing glare by controlling the headlight to change from high beam to low beam according to the position of the vehicle ahead or the oncoming vehicle detected by the outside vehicle information detection unit 12030.

[0240] The sound and image output unit 12052 sends the output signal of at least one of sound and image to an output device that can visually or auditorily notify information to the passengers of the vehicle or the outside of the vehicle. In Figure 30 the example, as the output device, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are shown. For example, the display unit 12062 can include at least one of an in-vehicle display and a head-up display.

[0241] Figure 31 is a diagram showing an example of the installation position of the imaging unit 12031.

[0242] In Figure 31 it, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0243] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, rearview mirror, rear bumper, rear door, and the upper part of the windshield inside the vehicle compartment of the vehicle 12100. The imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the upper part of the windshield inside the vehicle compartment mainly obtain images in front of the vehicle 12100. The imaging units 12102 and 12103 provided at the rearview mirror mainly obtain images on both sides of the vehicle 12100. The imaging unit 12104 provided at the rear bumper or rear door mainly obtains images behind the vehicle 12100. The imaging unit 12105 provided at the upper part of the windshield inside the vehicle is mainly used to detect a vehicle ahead, pedestrians, obstacles, traffic lights, traffic signs, or lanes, etc.

[0244] Note that Figure 31 An example of the imaging ranges of the imaging units 12101 to 12104 is shown. The imaging range 12111 represents the imaging range of the imaging unit 12101 provided at the front nose. The imaging ranges 12112 and 12113 represent the imaging ranges of the imaging units 12102 and 12103 provided at the rearview mirror, respectively. The imaging range 12114 represents the imaging range of the imaging unit 12104 provided at the rear bumper or rear door. For example, by superimposing the image data captured by the imaging units 12101 to 12104, a bird's-eye view image of the vehicle 12100 as viewed from above is obtained.

[0245] At least one of the imaging units 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0246] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can determine the distance of each three-dimensional object within the imaging ranges 12111 to 12114 and the temporal change of the distance (relative speed with respect to the vehicle 12100), and thus extract the closest three-dimensional object as the vehicle ahead. In particular, the closest three-dimensional object exists on the driving path of the vehicle 12100 and travels in substantially the same direction as the vehicle 12100 at a predetermined speed (for example, equal to or greater than 0 km / h). In addition, the microcomputer 12051 can preset the inter-vehicle distance to be maintained with the vehicle ahead and perform automatic braking control (including following stop control) or automatic acceleration control (including following start control), etc. Therefore, cooperative control such as autonomous driving can be performed, which aims to make the vehicle travel autonomously without relying on the driver's operation.

[0247] For example, based on the distance information obtained from imaging units 12101 to 12104, the microcomputer 12501 can classify the three-dimensional object data of a three-dimensional object into three-dimensional object data of a two-wheeled vehicle, a standard vehicle, a large vehicle, a pedestrian, a utility pole, and other three-dimensional objects, extract the classified three-dimensional object data, and use the extracted three-dimensional object data to automatically avoid obstacles. For example, the microcomputer 12051 identifies the obstacles around the vehicle 12100 as obstacles that the driver of the vehicle 12100 can visually identify and obstacles that the driver of the vehicle 12100 has difficulty visually identifying. Then, the microcomputer 12051 determines a collision risk indicating the risk of collision with each obstacle. When the collision risk is equal to or higher than a set value and thus there is a possibility of collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or the display unit 12062, and performs forced deceleration or avoidance steering via the drive system control unit 12010. Therefore, the microcomputer 12051 can assist driving to avoid collisions.

[0248] At least one of the imaging units 12101 to 12104 can be an infrared camera that detects infrared rays. The microcomputer 12051 can identify a pedestrian, for example, by determining whether there is a pedestrian in the captured images of the imaging units 12101 to 12104. For example, such identification of a pedestrian is performed through the following steps: a step of extracting feature points in the captured images of the imaging units 12101 to 12104 that are infrared cameras; and a step of performing a pattern matching process on a series of feature points representing the object contour to determine whether it is a pedestrian. If the microcomputer 12051 determines that there is a pedestrian in the captured images of the imaging units 12101 to 12104 and thus identifies the pedestrian, the audio and image output unit 12052 controls the display unit 12062 so that a square contour line for emphasis is displayed in a superimposed manner on the identified pedestrian. The audio and image output unit 12052 can also control the display unit 12062 to display an icon or the like representing the pedestrian at a desired position.

[0249] Examples of a vehicle control system to which the technology according to the present disclosure can be applied have been described above. For example, the technology according to the present disclosure can be used for the imaging unit 12031 in the above configuration. Specifically, Figure 1 the imaging device 100 in can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the imaging unit 12031, the dynamic range can be expanded by the global shutter method, and a captured image that is easier to view can be obtained, thereby reducing the driver's fatigue.

[0250] Note that the above-described embodiments illustrate examples for embodying the present technology, and there is a corresponding relationship between each matter in the embodiments and each invention-specific matter in the claims. Similarly, there is a corresponding relationship between the invention-specific matters in the claims and the matters with the same names in the embodiments of the present technology. However, the present technology is not limited to the embodiments, and can be implemented by applying various modifications to the embodiments without departing from the scope of the present technology.

[0251] Note that the effects described in this specification are merely examples and are not restrictive, and other effects can also be achieved.

[0252] Note that the present technology may also have the following configuration. (1) A solid-state imaging device, comprising: A first transfer transistor that transfers charge from a photoelectric conversion element to a charge holding section; A second transfer transistor that transfers charge from one of the charge holding section and the photoelectric conversion element to a first floating diffusion layer; and An overflow gate that holds charge overflowing from the photoelectric conversion element in a second floating diffusion layer. (2) The solid-state imaging device according to (1) above, wherein the second transfer transistor transfers charge from the charge holding section to the first floating diffusion layer, and the overflow gate holds charge overflowing from the photoelectric conversion element in the second floating diffusion layer. (3) The solid-state imaging device according to (2) above, further comprising: A first source follower circuit that amplifies and outputs the voltage of the first floating diffusion layer; and A second source follower circuit that amplifies and outputs the voltage of the second floating diffusion layer. (4) The solid-state imaging device according to (2) above, further comprising: A source follower circuit that amplifies and outputs the voltage of the second floating diffusion layer, wherein the first floating diffusion layer is connected to the second floating diffusion layer. (5) The solid-state imaging device according to (2) above, further comprising: A conversion efficiency control transistor that opens and closes a path between the first floating diffusion layer and a third floating diffusion layer; A connection transistor that opens and closes a path between the second floating diffusion layer and the third floating diffusion layer; and A source follower circuit that amplifies and outputs the voltage of the first floating diffusion layer. (6)The solid-state imaging device according to (5) above, wherein the capacitance value of the third floating diffusion layer is 10 times or more the capacitance value of any one of the first floating diffusion layer and the second floating diffusion layer. (7)The solid-state imaging device according to (5) or (6) above, wherein a plurality of pixel circuits share the first floating diffusion layer and the source follower circuit, and in each of the plurality of pixel circuits, the photoelectric conversion element, the second floating diffusion layer, and the third floating diffusion layer, the charge holding unit, the first transfer transistor, the second transfer transistor, the overflow gate, and the conversion efficiency control transistor are provided. (8)The solid-state imaging device according to (2) above, further comprising: a first source follower circuit that amplifies the voltage of the first floating diffusion layer and outputs the amplified voltage as a first voltage; a second source follower circuit that amplifies the voltage of the second floating diffusion layer and outputs the amplified voltage as a second voltage; and a sample and hold circuit that holds the second voltage. (9)The solid-state imaging device according to (8) above, wherein the second voltage includes: a reset level when the second floating diffusion layer is initialized; and a signal level corresponding to the amount of charge accumulated in the second floating diffusion layer, and the sample and hold circuit includes: a first capacitor element that holds the reset level; and a second capacitor element that holds the signal level. (10)The solid-state imaging device according to (8) above, wherein the second voltage includes: a reset level when the second floating diffusion layer is initialized; and a signal level corresponding to the amount of charge accumulated in the second floating diffusion layer, the reset level includes a first reset level and a second reset level for converting charge into voltage and having different conversion efficiencies, the signal level includes a first signal level and a second signal level having different conversion efficiencies, and the sample and hold circuit includes a plurality of capacitor elements that respectively hold the first reset level, the second reset level, the first signal level, and the second signal level. (11)The solid-state imaging device according to (1) above, wherein The second transfer transistor transfers the charge from the photoelectric conversion element to the first floating diffusion layer. The first transfer transistor transfers the charge overflowing from the photoelectric conversion element to the charge holding unit, and the overflow gate transfers the overflowing charge from the charge holding unit to the second floating diffusion layer and holds the charge in the second floating diffusion layer. (12) An imaging device, comprising: A first transfer transistor that transfers charge from a photoelectric conversion element to a charge holding unit; A second transfer transistor that transfers charge from one of the charge holding unit and the photoelectric conversion element to a first floating diffusion layer; An overflow gate that holds the charge overflowing from the photoelectric conversion element in a second floating diffusion layer; and A signal processing circuit that synthesizes a first pixel signal corresponding to the voltage of the first floating diffusion layer and a second pixel signal corresponding to the voltage of the second floating diffusion layer. (13) A method for controlling a solid-state imaging element, the control method comprising: A first transfer process in which a first transfer transistor transfers charge from a photoelectric conversion element to a charge holding unit; A second transfer process in which a second transfer transistor transfers charge from one of the charge holding unit and the photoelectric conversion element to a first floating diffusion layer; and A process in which an overflow gate holds the charge overflowing from the photoelectric conversion element in a second floating diffusion layer. List of reference numerals

[0253] 100 Imaging device 110 Imaging lens 120 Recording unit 130 Imaging control unit 200 Solid-state imaging element 201 Pixel chip 202 Circuit chip 211 Vertical scanning circuit 212 Timing control circuit 213 DAC 220 Pixel array unit 221 Pixel block 250 Load MOS circuit block 251 Load MOS transistor 260 Column signal processing circuit 261 ADC 262 Digital signal processing circuit 263 Selector 264 Memory 265 Subtractor 266 Synthesis processing unit 300 Pixel 310-1 to 310-4 Pixel circuits 311 Photoelectric conversion element 312, 314 Transfer transistors 313 Analog memory 315 OFG transistor 316 Connection transistor 317 FDG transistor 318 Metal-insulator-metal (MIM) capacitor 319 FCG transistor 321, 322, 323 FD 340, 350 Source follower circuits 341, 351, 431 Reset transistors 342, 352, 432, 432-1, 432-2 Amplification transistors 343, 353, 421 to 426, 433, 433-1, 433-2 Selection transistors 354 Switch 355 Switching transistor 356 Precharge transistor 357 Current source transistor 400 Sample and hold circuit 411 to 416 Capacitor elements 12031 Imaging unit

Claims

1. A solid-state imaging device, comprising: A first transfer transistor that transfers charge from a photoelectric conversion element to a charge holding unit; A second transfer transistor that transfers charge from one of the charge holding unit and the photoelectric conversion element to a first floating diffusion layer; And An overflow gate that holds charge overflowing from the photoelectric conversion element in a second floating diffusion layer.

2. The solid-state imaging device according to claim 1, wherein The second transfer transistor transfers charge from the charge holding unit to the first floating diffusion layer, and The overflow gate holds charge overflowing from the photoelectric conversion element in the second floating diffusion layer.

3. The solid-state imaging device according to claim 2, further comprising: A first source follower circuit that amplifies and outputs the voltage of the first floating diffusion layer; And A second source follower circuit that amplifies and outputs the voltage of the second floating diffusion layer.

4. The solid-state imaging device according to claim 2, further comprising: A source follower circuit that amplifies and outputs the voltage of the second floating diffusion layer, Wherein the first floating diffusion layer is connected to the second floating diffusion layer.

5. The solid-state imaging device according to claim 2, further comprising: A conversion efficiency control transistor that opens and closes a path between the first floating diffusion layer and a third floating diffusion layer; A connection transistor that opens and closes a path between the second floating diffusion layer and the third floating diffusion layer; And A source follower circuit that amplifies and outputs the voltage of the first floating diffusion layer.

6. The solid-state imaging device according to claim 5, wherein The capacitance value of the third floating diffusion layer is more than 10 times the capacitance value of either the first floating diffusion layer or the second floating diffusion layer.

7. The solid-state imaging device according to claim 5, wherein A plurality of pixel circuits share the first floating diffusion layer and the source follower circuit, and In each of the plurality of pixel circuits, there are provided the photoelectric conversion element, the second floating diffusion layer and the third floating diffusion layer, the charge holding unit, the first transfer transistor and the second transfer transistor, the overflow gate and the conversion efficiency control transistor.

8. The solid-state imaging device according to claim 2, further comprising: A first source follower circuit that amplifies the voltage of the first floating diffusion layer and outputs the amplified voltage as a first voltage; A second source follower circuit that amplifies the voltage of the second floating diffusion layer and outputs the amplified voltage as a second voltage; And A sample and hold circuit that holds the second voltage.

9. The solid-state imaging device according to claim 8, wherein The second voltage includes: a reset level when the second floating diffusion layer is initialized; And a signal level corresponding to the amount of charge accumulated in the second floating diffusion layer, and The sample and hold circuit includes: A first capacitor element that holds the reset level; And A second capacitor element that holds the signal level.

10. The solid-state imaging device according to claim 8, wherein The second voltage includes: a reset level when the second floating diffusion layer is initialized; and a signal level corresponding to the amount of charge accumulated in the second floating diffusion layer. The reset level includes a first reset level and a second reset level for converting charge into voltage and having different conversion efficiencies from each other. The signal level includes a first signal level and a second signal level having different conversion efficiencies from each other, and the sample-and-hold circuit includes a plurality of capacitor elements that respectively hold the first reset level, the second reset level, the first signal level, and the second signal level.

11. The solid-state imaging device according to claim 1, wherein the second transfer transistor transfers charge from the photoelectric conversion element to the first floating diffusion layer, the first transfer transistor transfers the charge overflowing from the photoelectric conversion element to the charge holding section, and the overflow gate transfers the overflowing charge from the charge holding section to the second floating diffusion layer and causes the charge to be held in the second floating diffusion layer.

12. An imaging device, comprising: a first transfer transistor that transfers charge from a photoelectric conversion element to a charge holding section; a second transfer transistor that transfers charge from one of the charge holding section and the photoelectric conversion element to a first floating diffusion layer; an overflow gate that causes the charge overflowing from the photoelectric conversion element to be held in a second floating diffusion layer; and a signal processing circuit that synthesizes a first pixel signal corresponding to the voltage of the first floating diffusion layer and a second pixel signal corresponding to the voltage of the second floating diffusion layer.

13. A control method for a solid-state imaging device, the control method comprising: a first transfer process in which a first transfer transistor transfers charge from a photoelectric conversion element to a charge holding section; a second transfer process in which a second transfer transistor transfers charge from one of the charge holding section and the photoelectric conversion element to a first floating diffusion layer; and a process in which an overflow gate causes the charge overflowing from the photoelectric conversion element to be held in a second floating diffusion layer.

Images