Apparatus and method for staggered timing of skip refresh operations

Abstract

Embodiments of the present disclosure relate to devices and methods for staggering the timing of skip refresh operations on a memory. Memory cells of a memory can need to periodically perform refresh operations. In some cases, when the charge retention characteristics of the memory cells of the memory exceed the auto-refresh frequency, the auto-refresh operation can be periodically skipped. To reduce peak current consumption during refresh operations, the skip refresh operations can be staggered across different portions of the memory. In one example, the skip refresh operations can be staggered in time among memory dies of the memory to limit the number of memory dies performing auto-refresh operations to a maximum number. In another example, the skip refresh operations can be staggered in time among memory banks of a single memory array to limit the number of memory banks performing auto-refresh operations to a maximum number.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims the benefit of earlier filing date under 35 U.S.C. § 119 to U.S. Patent Application No. 16 / 432,604 filed June 5, 2019. The content of this application is incorporated herein by reference in its entirety and for all purposes. BACKGROUND

[0003] Information can be stored on individual memory cells of a memory as a physical signal (e.g., an electric charge on a capacitive element). The memory can be volatile memory, and the physical signal can decay over time, which can degrade or destroy the information stored in the memory cell. It can be necessary to periodically refresh the information in the memory cell by restoring the physical signal to an initial value, e.g., by rewriting the information.

[0004] As the size of memory components decreases, the density of memory cells greatly increases. Automatic refresh operations can be performed in which a sequence of memory cells are periodically refreshed. Repeated access to a particular memory cell or group of memory cells, often referred to as a ‘row hammer,’ can cause an increased rate of degradation of data in nearby memory cells. In addition to automatic refresh operations, it can be necessary to identify and refresh memory cells affected by row hammering in targeted refresh operations. Targeted refresh operations can occur interspersed between automatic refresh operations. SUMMARY

[0005] Example devices are described herein. One example device can include a first memory die configured to receive a refresh signal and perform an auto-refresh operation in response to a first activation of the refresh signal and skip an auto-refresh operation in response to a second activation of the refresh signal, and a second memory die configured to receive the refresh signal and skip an auto-refresh operation in response to the first activation of the refresh signal and perform an auto-refresh operation in response to the second activation of the refresh signal. Additionally or alternatively, the first memory die and the second memory die can each be configured to perform a target refresh operation concurrently in response to a third activation of the refresh signal. Additionally or alternatively, the first memory die can be configured to perform the auto-refresh operation on a plurality of rows of memory cells in response to the first activation of the refresh signal, and the second memory die can be configured to perform the auto-refresh operation on a plurality of rows of memory cells in response to the second activation of the refresh signal. Additionally or alternatively, the example device can further include a memory package including the first memory die and the second memory die. Additionally or alternatively, the example device can further include a memory module including the first memory die and the second memory die. Additionally or alternatively, the first memory die can be configured to determine whether to perform the auto-refresh operation or skip the refresh operation based on an internal setting in response to an activation of the refresh signal. Additionally or alternatively, the internal setting is determined based on a value programmed in a fuse bank. Additionally or alternatively, the first memory die includes a refresh address control circuit configured to determine a mode of auto-refresh operation and skip refresh operation based on the internal setting.

[0006] Another example device can include a memory array having a first memory bank and a second memory bank, and a refresh control circuit configured to receive a refresh signal. In response to a first activation of the refresh signal, the refresh control circuit can be configured to cause an auto-refresh operation to be performed on a group of memory cell rows of the first memory bank and to cause an auto-refresh operation to be skipped for the second memory bank. In response to a second activation of the refresh signal, the refresh control circuit can be configured to cause an auto-refresh operation to be skipped for the first memory bank and to cause an auto-refresh operation to be performed on a group of memory cell rows of the second memory bank. Additionally or alternatively, the refresh control circuit can be configured to cause an auto-refresh operation to be skipped for both the first bank and the second bank at the same frequency and at different phases determined based on activation of a reset signal. Additionally or alternatively, the refresh control circuit can be configured to cause an auto-refresh operation to be skipped for the first bank based on a first count value of a first counter having a predetermined value and to be configured to cause an auto-refresh operation to be skipped for the second bank based on a second count value of a second counter having the predetermined value. Each of the first counter and the second counter can be adjustable in response to each activation of the refresh signal. Additionally or alternatively, the refresh control circuit can be configured to initialize the first counter to a different count value than the second counter. Additionally or alternatively, in response to a third activation of the refresh signal, the refresh control circuit can be configured to cause a target refresh operation to be performed on a hammering victim row of memory cells of a row of the first memory bank and to cause a target refresh operation to be performed on a hammering victim row of memory cells of a row of the second memory bank. Additionally or alternatively, in response to a third activation of the refresh signal, the refresh control circuit can be configured to cause an auto-refresh operation to be performed on a second group of memory cell rows of the first memory bank and to cause a target refresh operation to be performed on a second group of memory cell rows of the second memory bank.

[0007] An example memory is described herein. An example memory can include a plurality of memory cells, an interface configured to provide a refresh signal in response to a refresh command, a first refresh control circuit configured to receive the refresh signal, and a second refresh control circuit configured to receive the refresh signal. In response to a first activation of the refresh signal, the first refresh control circuit can be configured to cause a first type of refresh operation to be performed on rows of a first group of the plurality of memory cells, and in response to a second activation of the refresh signal, the first refresh control circuit can be configured to cause all refresh operations to be skipped for the first group of the plurality of memory cells. Further in response to the first activation of the refresh signal, the second refresh control circuit can be configured to cause all refresh operations to be skipped for a second group of the plurality of memory cells, and further in response to the second activation of the refresh signal, the second refresh control circuit can be configured to cause the first type of refresh operation to be performed on rows of the second group of the plurality of memory cells. Additionally or alternatively, the memory can further include a memory die including a first memory bank and a second memory bank. The first memory bank can include the first group of the plurality of memory cells and the second memory bank can include the second group of the plurality of memory cells. Additionally or alternatively, the memory can further include a first memory die including the first group of the plurality of memory cells and a second memory die including the second group of the plurality of memory cells. Additionally or alternatively, in response to a third activation of the refresh signal, the first refresh control circuit can be configured to cause a second type of refresh operation to be performed on a second row of the first group of the plurality of memory cells, where in response to the third activation of the refresh signal, the second refresh control circuit can be configured to cause the second type of refresh operation to be performed on a second row of the second group of the plurality of memory cells. Additionally or alternatively, the first type of refresh operation is an auto-refresh operation and the second type of refresh operation is a target refresh operation. Additionally or alternatively, the first refresh control circuit can be configured to cause all refresh operations to be skipped for the first group of the plurality of memory cells at a same frequency as the second refresh control circuit is configured to cause all refresh operations to be skipped for the second group of the plurality of memory cells with respect to activation of the refresh signal. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 is a block diagram of a semiconductor device according to an embodiment of the disclosure.

[0009] Figure 2 is a block diagram of a master / slave configuration of a memory package according to an embodiment of the disclosure.

[0010] Figure 3 is a block diagram of a memory array according to embodiments of the disclosure.

[0011] Figure 4 is a block diagram of a memory module according to embodiments of the disclosure.

[0012] Figure 5 is a block diagram of a refresh control circuit according to embodiments of the disclosure.

[0013] Figure 6 is a block diagram of a row decoder according to embodiments of the disclosure.

[0014] Figure 7 is an exemplary timing diagram of a refresh operation in a memory device according to embodiments of the disclosure.

[0015] Figure 8 is an exemplary timing diagram of a refresh operation in a memory package according to embodiments of the disclosure.

[0016] Figure 9 is a flowchart of a method for interleaved refresh operations according to embodiments of the disclosure. DETAILED DESCRIPTION

[0017] The following description of certain examples is merely exemplary in nature and is in no way intended to limit the scope of the disclosure, its application, or uses. In the following detailed description of embodiments of the application, reference is made to the accompanying drawings that form a part hereof, and in which are shown by way of illustration specific embodiments in which the described systems and methods can be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the presently disclosed systems and methods, and it is to be understood that other embodiments can be utilized, and that structural and logical changes can be made without departing from the spirit and scope of the present disclosure. Furthermore, the following detailed description is not to be understood in a restrictive sense and is not to be construed as limiting the scope of the embodiments of the present disclosure. Exemplary embodiments are described herein with reference to drawings that may

[0018] Memory devices can include multiple memory units. Memory units can store information and can be organized at intersections of word lines (rows) and bit lines (columns). Word lines and bit lines can be organized into memory banks, and a memory device can include a single memory die or multiple memory dies. Each memory die can include multiple memory banks. In some examples, one or more memory dies can be organized into a memory package. In some embodiments, memory dies of a memory package can be stacked on one another. In some embodiments, multiple memory packages or multiple single-die memory devices can be organized into a memory module. A memory device can receive one or more command signals that can indicate operations in one or more dies of one or more memory packages. Memory dies can be coupled to command signals collectively, can receive commands from a master die and / or an interface chip, and / or can receive commands individually. For example, a packaged memory die can receive a refresh signal that can control timing of refresh operations in the memory die.

[0019] In some examples, information in memory units can decay over time. Memory units can be refreshed row by row. During a refresh operation, information in one or more rows can be read out and then written back to the respective rows. A refresh command (e.g., an auto-refresh command AREF) can control timing of refresh operations. In some embodiments, a memory device can generate one or more “pumps” that can be internal refresh signals activated in response to receiving an activation of a refresh command. A memory die can be capable of performing more than one type of refresh operation in response to a refresh command and / or a refresh pump. For example, a memory die can skip all refresh operations (e.g., not perform refresh operations), perform an auto-refresh operation, or perform a targeted refresh operation. A memory die can have internal logic configured to determine which type of refresh operation to perform and / or can receive a signal (e.g., from an interface and / or a controller) indicating which type of refresh operation should be performed. In some examples, a memory die can be capable of performing a combination of different operations during one refresh command.

[0020] During an auto-refresh operation (e.g., initiated by an activation of an auto-refresh command AREF and / or an activation of a pump), a memory die can refresh groups of rows of a memory array. From one auto-refresh operation to the next, groups of rows to be refreshed can be selected according to a predetermined order or pattern. An auto-refresh operation can cycle and refresh all rows of a memory array of a memory die within a specified period of time to prevent data loss (e.g., each row can be refreshed within a specified maximum refresh period of time). The specified maximum refresh period of time can be based on a normal rate of data degradation in a memory unit.

[0021] During a targeted refresh operation, one or more particular rows of memory cells of a memory array can be refreshed in response to detecting an attack on a particular row. Repeated accesses to a particular row of memory (e.g., an aggressor row) can cause an increase in the rate of decay in adjacent rows (e.g., victim rows) due to, for example, electromagnetic coupling between the rows. Information in the victim rows can decay at a rate such that if the data is not refreshed until the next automatic refresh operation for the row, the data can be lost. To prevent the loss of information, the aggressor row can need to be identified and then a targeted refresh operation can be performed on one or more associated victim rows. In some embodiments, the targeted refresh operation can "steal" a time slot that would otherwise be used for an automatic refresh operation (e.g., activation of a pump, activation of an automatic refresh command AREF).

[0022] In some instances, an automatic refresh command AREF can be provided to a memory die at a higher frequency than is necessary to reliably maintain information stored in the memory cells of the memory die. Thus, in some instances, the charge retention characteristics of the memory cells of a memory die can allow for periodic skipping of refresh operations, which can reduce power consumption during those refresh cycles.

[0023] Controlling the amount of current consumed by a memory device during a refresh operation can be important. Generally, an automatic refresh operation can consume more current than a targeted refresh operation because more rows can be refreshed during a given automatic refresh operation than during a given targeted refresh operation. Thus, in some instances, if one memory die or all memory banks of a group of memory dies of a memory package or module are performing an automatic refresh operation at the same time, the current consumed can exceed a defined current limit. As previously described, one method of reducing current consumption is to periodically skip refreshes when possible. However, if one memory die or all memory banks of a group of memory dies of a memory package or module are skipping refresh operations at the same time and performing an automatic refresh operation at the same time, the problem of excessive current consumption can persist.

[0024] The present disclosure relates to devices, systems, and methods for staggering the timing of different types of refresh operations. Because a skip refresh operation and a target refresh operation consume less current than an auto-refresh operation, it can be desirable to reduce the number of memory dies (or memory banks of a single memory die) that simultaneously perform an auto-refresh operation by having a first subset of memory dies (or a first subset of memory banks) perform an auto-refresh operation while a second subset of memory dies (or a second subset of memory banks) skip a refresh operation, perform a target refresh operation, or a combination thereof. For example, at a time when a maximum number of memory dies (or memory banks) perform a refresh operation, some of the memory dies (or memory banks) can skip a refresh operation and / or some of the memory dies (or memory banks) can perform a target refresh operation without performing an auto-refresh operation. In example implementations, each of the memory dies can skip a refresh operation at a different activation of a refresh timing command (e.g., an auto-refresh command AREF and / or a pump). Thus, a first memory die can skip a refresh operation and a second die can perform an auto-refresh operation in response to a first activation of a refresh timing signal, and the first memory die can perform an auto-refresh operation and the second die can skip a refresh operation in response to a second activation of the refresh timing signal.

[0025] Figure 1 is a block diagram of a semiconductor device according to at least one embodiment of the present disclosure. The semiconductor device 100 can be a semiconductor memory device, such as a DRAM device integrated on a single semiconductor chip. Figure 1 The example device 100 can include a memory package, such as a stack 125 of memory dies located on a substrate 123, which can function as (and can be referred to as) an interface. Although certain components in the dies of the stack 125 and certain components on the substrate 123 are shown, other arrangements of components of the device 100 between the stack 125 and the substrate 123 are possible in other example embodiments. In some embodiments, the stack 125 of the device 100 can include multiple dies. In other embodiments, the stack 125 can include a single die.

[0026] For simplicity and clarity of illustration, Figure 1 Only components of one memory die in the stack 125 are shown in FIG. 1. Generally, different memory dies of the stack 125 can each have components similar to one another. In some embodiments, each memory die of the stack 125 can be physically identical to one another. The substrate 123 can function as an interface and can send and receive information (e.g., data, commands) to and from the outside while the memory dies in the stack 125 communicate with the components of the substrate. As described herein, commands and other signals sent by the substrate 123 can be sent to all of the memory dies in the stack 125 or can be addressed separately to individual memory dies of the stack 125.

[0027] The semiconductor device 100 includes a memory array 118. The memory array 118 can be located in a memory die of the stack 125. The memory array 118 is shown to include a plurality of memory banks BANK0-N, the total number of memory banks being 2, 4, 8, 16, etc., including any number in between and any number greater than 16. Each memory bank BANK0-N can include a plurality of word lines WL, a plurality of bit lines BL and / BL, and a plurality of memory cells MC arranged at the intersections of the plurality of word lines WL and the plurality of bit lines BL and / BL. Selection of the word lines WL is performed by a row decoder 108, and selection of the bit lines BL and / BL is performed by a column decoder 110. The row decoder 108 and the column decoder 110 can also be located in the memory die of the stack 125. In Figure 1 In an embodiment, the row decoder 108 includes a respective row decoder for each memory bank and the column decoder 110 includes a respective column decoder for each memory bank. The bit lines BL and / BL are coupled to a respective sense amplifier (SAMP). Read data from the bit lines BL or / BL is amplified by the sense amplifier SAMP and transferred through a complementary local data line (LIOT / B), a transfer gate (TG), and a complementary main data line (MIOT / B) to a read / write amplifier 120. Conversely, write data output from the read / write amplifier 120 is transferred through the complementary main data line MIOT / B, the transfer gate TG, and the complementary local data line LIOT / B to the sense amplifier SAMP and written in the memory cells MC coupled to the bit lines BL or / BL.

[0028] The semiconductor device 100 can employ a plurality of external terminals, including command and address (C / A) terminals coupled to a command and address bus to receive commands and addresses, a chip select (CS) terminal configured to receive a CS signal, clock terminals to receive a clock CK and / CK, data terminals DQ to provide data, and power terminals to receive power potentials VDD, VSS, VDDQ, and VSSQ. The external terminals can be located on the substrate 123.

[0029] An external clock CK and / CK is supplied for the clock terminals, which are provided to the input circuit 112. The external clock can be complementary. The input circuit 112 generates an internal clock ICLK based on the CK and / CK clock. The ICLK clock is provided to the command decoder 110 and an internal clock generator 114. The internal clock generator 114 provides various internal clocks LCLK based on the ICLK clock. The LCLK clock can be used for timing operations of various internal circuits. An internal data clock LCLK is provided to the input / output circuit 122 to time operations of circuits included in the input / output circuit 122, e.g., provided to a data receiver to time reception of write data.

[0030] Memory addresses can be supplied to the C / A terminals. Memory addresses supplied to the C / A terminals are passed to the address decoder 104 via the command / address input circuit 102. The address decoder 104 receives the addresses and supplies a decoded row address XADD to the row decoder 108 and a decoded column address YADD to the column decoder 110. The address decoder 104 can also supply a decoded bank address BADD, which can indicate the bank of the memory array 118 that contains the decoded row address XADD and column address YADD. In some embodiments, the address decoder 104 can also indicate a particular memory die of the stack 125 for activation. Commands can be supplied to the C / A terminals. Examples of commands include timing commands for controlling the timing of various operations, access commands for accessing memory, such as read commands for performing read operations and write commands for performing write operations, as well as other commands and operations. Access commands can be associated with one or more row addresses XADD, column addresses YADD, and bank addresses BADD to indicate the memory cells to be accessed.

[0031] Commands can be provided to the command decoder 106 as internal command signals via the command / address input circuit 102. The command decoder 106 includes circuitry to decode the internal command signals to generate various internal signals and commands for performing operations. For example, the command decoder 106 can provide row command signals to select word lines and column command signals to select bit lines.

[0032] The semiconductor device 100 can receive an access command as a read command. When a read command is received and timely supplied with a bank address, row address, and column address (and optional die address), read data is read from the memory cells of the memory array 118 corresponding to the row and column addresses. The read command is received by the command decoder 106, which provides internal commands so that the read data from the memory array 118 is provided to the read / write amplifiers 120. The read data is output from the data terminals DQ to the outside via the input / output circuit 122.

[0033] The semiconductor device 100 can receive an access command (e.g., a write command). When a write command is received and timely for a bank address, a row address, and a column address (and optional memory die address), write data supplied to data terminals DQ is written to memory cells in the memory array 118 corresponding to the row and column addresses. The write command is received by the command decoder 106, and in response, the command decoder 106 can provide an internal command for the write data to be received by a data receiver in the input / output circuit 122. A write clock can also be provided to an external clock terminal to time the reception of the write data by the data receiver in the input / output circuit 122. The write data is supplied to the read / write amplifiers 120 via the input / output circuit 122 and through the read / write amplifiers 120 to the memory array 118 to be written to the memory cells MC.

[0034] The semiconductor device 100 can also receive a command to cause it to perform a refresh operation. A refresh signal AREF can be a pulsed signal that is activated when the command decoder 106 receives a refresh command. In some embodiments, a refresh command can be issued externally to the memory device 100. In some embodiments, components of the device can periodically generate a refresh command. In some embodiments, the refresh signal AREF can also be activated when an external signal indicates a self-refresh entry command. The refresh signal AREF can be activated immediately following a command input, and thereafter can be expected to be activated cyclically for an internal timing period. Thus, the refresh operation can continue automatically according to a predefined period. A self-refresh exit command can stop the automatic activation of the refresh signal AREF and return to an idle state.

[0035] The refresh signal AREF is supplied to the refresh address control circuit 116. In some examples, each memory die of the stack 125 can include a separate refresh address control circuit 116 for each memory bank of the memory banks BANK0-N. In other examples, each memory die can include a single refresh address control circuit 116. In a predictive refresh operation, the refresh address control circuit 116 supplies a refresh row address RXADD to the row decoder 108, which can refresh the word line WL indicated by the refresh row address RXADD. The refresh address control circuit 116 can control the timing of the refresh operation and can select and provide the refresh address RXADD. The refresh address control circuit 116 can be controlled to vary the details of the refresh address RXADD (e.g., how the refresh address is calculated, the timing of the refresh address), or can operate based on internal logic.

[0036] During a refresh cycle, the memory die can skip refresh operations, perform auto-refresh operations, perform target refresh operations, or some combination thereof. Accordingly, during a skip refresh operation, the refresh address control circuit 116 can not provide a refresh address RXADD. During an auto-refresh operation or a target refresh operation, the refresh address control circuit 116 can provide either one or more auto-refresh addresses (e.g., auto-refresh addresses) or target refresh addresses (e.g., victim addresses), respectively, as the refresh address RXADD. An auto-refresh address can be part of a sequence of addresses provided based on activation of the auto-refresh signal AREF. The refresh address control circuit 116 can cycle through the sequence of auto-refresh addresses at a rate determined by the rate of activation of the auto-refresh signal AREF. Multiple addresses can be provided as the refresh address RXADD as part of an auto-refresh operation. In some embodiments, an address group or address block can be indicated entirely by the refresh address RXADD, and the row decoder 108 can refresh the entire address group or address block.

[0037] The refresh address control circuit 116 can also determine a target refresh address based on the access pattern of nearby addresses in the memory array 118 (e.g., aggressor addresses corresponding to aggressor rows), which is an address that needs to be refreshed (e.g., a victim address corresponding to a victim row). The refresh address control circuit 116 can selectively use one or more signals of the device 100 to calculate the target refresh address RXADD. For example, the refresh address RXADD can be calculated based on the row address XADD provided by the address decoder. In some embodiments, the refresh address control circuit 116 can sample a current value of the row address XADD provided by the address decoder 104 and determine the target refresh address based on one or more of the sampled addresses.

[0038] The target refresh address can be based on a characteristic of the row address XADD received from the address decoder 104 over time. The refresh address control circuit 116 can sample the current row address XADD to determine its characteristic over time. The sampling can occur intermittently, taking each sample based on a random or semi-random timing. The refresh address control circuit 116 can use different methods to calculate the target refresh address based on the sampled row address XADD. For example, the refresh address control circuit 116 can determine whether a given row is an aggressor address, and then calculate and provide as the target refresh address the address of a victim address corresponding to the aggressor address. In some embodiments, more than one victim address can correspond to a given aggressor address. In this case, the refresh address control circuit can queue multiple target refresh addresses, and provide them in order when it is determined that a target refresh address should be provided. The refresh address control circuit 116 can provide the target refresh address immediately, or can queue the target refresh address to be provided at a later time (e.g., in the next time slot available for a target refresh).

[0039] The timing of the refresh address RXADD can be based on the timing of the refresh signal AREF. The refresh address control circuit 116 can have time slots corresponding to the timing of the refresh signal AREF, and can provide no, one, or multiple refresh addresses RXADD during each time slot. In some embodiments, a refresh can be skipped or a target refresh address can be issued during a time slot (e.g., a "steal") that would otherwise be allocated to an auto-refresh address. In some embodiments, multiple refresh operations can be performed in response to activation of the refresh signal AREF. In this example, certain time slots can be reserved for certain types of refresh operations according to some predefined pattern. Based on the predefined pattern, the refresh address control circuit 116 can determine whether to provide a target refresh address, provide no refresh address (e.g., skip refresh), or provide an auto-refresh address during a particular time slot. In some examples, the refresh address control circuit 116 can be configured to override the pattern, e.g., in response to a detected row hammer attack.

[0040] In some embodiments, the refresh address control circuit 116 can include logic, e.g., a state machine and / or a counter, for determining whether to initiate a skip refresh operation, an auto-refresh operation, or a target refresh operation. For example, the refresh address control circuit 116 can count the number of activations of the refresh signal AREF with a counter, and when the counter reaches a maximum value and "rolls over" to a minimum value, a skip refresh operation can be initiated. The logic can also be coupled to settings, e.g., fuse settings, which can be used to change the operation of the logic in a given memory die. In other embodiments, a sequence of refresh operations can occur over many refresh operation cycles.

[0041] Because more addresses can be provided as refresh addresses RXADD during an auto-refresh operation than during a target refresh operation or a skip refresh operation, an auto-refresh operation can consume more current (e.g., more power) than a target refresh operation or a skip refresh operation. To reduce the peak current consumed by semiconductor device 100 at any given point in time during a refresh operation, a skip refresh and / or target refresh operation can be staggered in time with an auto-refresh operation between different memory dies of stack 125 (and / or between different memory banks BANK0-N of a memory array 118 of a particular memory die). Different memory dies of stack 125 can have settings that cause a skip refresh operation and an auto-refresh operation to occur at different times in different memory dies (or different memory banks BANK0-N of a memory die). In one example implementation, refresh address control circuitry 116 of different memory dies in stack 125 can be instructed to have a skip refresh operation at a certain frequency based on a refresh signal (e.g., a skip refresh operation can be performed in response to every n activations of refresh signal AREF). In another example implementation, refresh address control circuitry 116 of a particular die of stack 125 can be instructed to have a skip refresh operation of a corresponding memory bank of a memory bank BANK0-N at a certain frequency based on a refresh signal (e.g., a skip refresh operation can be performed in response to every n activations of refresh signal AREF). Each of the memory dies (e.g., or memory banks BANK0-N of a memory die) can perform a skip refresh operation at the same frequency, but settings (e.g., fuse settings) in each of the memory dies (or memory banks BANK0-N) can offset the phase of the skip refresh operation.

[0042] As previously described, the timing of a skip refresh operation can be staggered in time to reduce the peak power consumed by memory device 100 during a refresh operation. Settings of different memory dies of stack 125 (or different memory banks BANK0-N of a memory die) can be set such that when a maximum number of simultaneous refresh operations occur across one or more memory dies (or one or more of the memory banks BANK0-N), at least one of the memory dies (or at least one of the memory banks BANK0-N) is performing a skip refresh operation instead of an auto-refresh operation.

[0043] Power supply potentials VDD and VSS are supplied to the power supply terminals. The power supply potentials VDD and VSS are supplied to the internal voltage generator circuit 124. The internal voltage generator circuit 124 generates various internal potentials VPP, VOD, VARY, VPERI, etc. based on the power supply potentials VDD and VSS supplied to the power supply terminals. The internal potential VPP is mainly used in the row decoder 108, the internal potentials VOD and VARY are mainly used in the sense amplifiers SAMP included in the memory array 118, and the internal potential VPERI is used in many peripheral circuit blocks.

[0044] Power supply potentials VDDQ and VSSQ are also supplied to the power supply terminals. The power supply potentials VDDQ and VSSQ are supplied to the input / output circuit 122. In some embodiments of the disclosure, the power supply potentials VDDQ and VSSQ supplied to the power supply terminals can be the same potentials as the power supply potentials VDD and VSS supplied to the power supply terminals. In another embodiment of the disclosure, the power supply potentials VDDQ and VSSQ supplied to the power supply terminals can be different potentials from the power supply potentials VDD and VSS supplied to the power supply terminals. The power supply potentials VDDQ and VSSQ supplied to the power supply terminals are used for the input / output circuit 122 so that power supply noise generated by the input / output circuit 122 does not propagate to other circuit blocks.

[0045] Figure 2 is a block diagram of a master / slave configuration of a memory package 200 according to embodiments of the disclosure. In some embodiments, the memory package 200 can be a semiconductor device 100 and an implementation of the memory stack 125. The memory package 200 is representative of one possible organization example of memory dies (and substrates / interfaces) organized into a memory package for use in a memory device. The memory package 200 includes a package substrate 227 having terminals configured to send and receive information to other components external to the memory package 200. The memory package 200 can also include a master memory die (master die or master DRAM) 228, and a plurality of slave memory dies (slave dies or slave DRAMs) 229a-c. The master die 228 sends signals to and receives signals from the substrate 227, and in turn provides signals to and receives signals from the slave dies 229a-c. Although only a single stack of dies 228 and 229a-c is shown, in some embodiments, the package substrate 227 can include multiple stacks of dies. Figure 1

[0046] Embodiments that are generally similar in structure to the memory package 200 can be referred to as 3DS packages, and each of the dies can generally be referred to as a logical rank. Figure 2 ​The memory package 200 shown in FIG. 1 shows an example embodiment having four different memory dies (e.g., a master die 228 and three slave dies 229a-c) connected by wire bonding. In other example embodiments, more or fewer memory dies can be used. For example, some memory stacks can include eight or more memory dies. In some examples, through silicon vias (TSVs) or other techniques can be used to bond multiple memory dies in a stack.

[0047] Each of the master memory die 228 and the slave memory dies 229a-c may include one or more memory arrays (e.g., Figure 1 18). Memory dies 228 and 229a-c may also each include other components of the memory device, such as refresh address control circuitry (e.g., Figure 1 refresh address control circuit 116), and row and column decoders (e.g., Figure 1 108 and 110). Other components of the memory device (e.g., shown on substrate 123) Figure 1 Components of the memory device 100) can be distributed between the substrate 227 and the memory dies 228 and 229a-c. In some embodiments, the master die 228 and each of the slave dies 229a-c can be physically identical to each other.

[0048] The master die 228 can be coupled to the substrate 227 and to the first slave die 229a. The first slave die 229a is coupled to the master die 228 and is also coupled to the next slave die 229b, and so on. The die 228 and 229a-c can be coupled to each other (and to the substrate 227) by various methods. In some embodiments, the die can be coupled together by wire bonding. In some embodiments, the die can be coupled together using through silicon vias (TSVs). In 3DS packaging, there may be additional power constraints based on peak power (and / or current) that may be pulled through the coupling between the die (e.g., wire bonding and / or TSVs).

[0049] Substrate 227 can receive a refresh command configured to cause memory package 200 to be placed in a refresh state. In some embodiments, the command can specify which of memory dies 228 and 229a-c should be placed in the refresh state. When in the refresh state, each of memory dies 228 and 229a-c can perform a refresh operation (e.g., a skip refresh operation, an auto-refresh operation, and / or a target refresh operation). In some embodiments, in response to the refresh command, memory package 200 can place only a subset or group of memory dies 228 and 229a-c (e.g., defined by a logical rank) in the refresh state at the same time. In some instances, after a logical rank begins performing a refresh operation, a minimum amount of time can elapse before the next logical rank can begin performing a refresh operation. Thus, there can be an offset of at least the minimum timing between a first refresh operation of a first logical rank and a first refresh operation of a second logical rank.

[0050] When memory package 200 is in the refresh mode, substrate 227 can receive a refresh command and provide it to master die 228. Master die 228 can decode the refresh command and provide a refresh signal AREF to slave dies 229a-c (as well as to internal components of master die 228). The refresh signal can be activated (e.g., raised to a high logic level) periodically. Each of the logical ranks can receive the refresh signal (e.g., AREF) from the substrate, which can be used to control the timing of refresh operations in the logical rank. In some embodiments, a logical rank (e.g., a group of memory dies 228 and 229a-c) can perform one or more refresh operations in response to each activation of the refresh signal. In some embodiments, a logical rank can start providing activation of a refresh pump signal in response to receiving the refresh signal, and can perform a refresh operation in response to activation of the refresh pump signal.

[0051] In some embodiments, each of the logical ranks can have at least one refresh address control circuit (e.g., Figure 1of the respective memory dies 228 and 229a-c or the respective memory banks of the memory dies 228 and 229a-c. Each of the logical ranks can include settings for determining the timing of the skip refresh, auto-refresh, and target refresh operations. For example, a fuse in each of the memory dies 228 and 229a-c can be used to control the timing and / or pattern of different types of refresh operations in each of the memory dies 228 and 229a-c (or each of the memory banks of each of the memory dies 228 and 229a-c). For example, each of the memory dies 228 and 229a-c (or each memory bank of each of the memory dies 228 and 229a-c) can have a counter such that after a particular number of activations of the refresh signal (and / or the refresh pump signal), the memory dies 228 and 229a-c (or the memory banks of each of the memory dies 228 and 229a-c) can perform a skip refresh operation or a target refresh operation instead of an auto-refresh operation. In some embodiments, the memory dies 228 and 229a-c (or the memory banks of each of the memory dies 228 and 229a-c) can perform a skip refresh operation at the same skip refresh frequency (e.g., after counting the same number of activations of the refresh signal) and can perform a target refresh operation at the same target refresh frequency (e.g., after counting the same number of activations of the refresh signal). However, each of the memory dies 228 and 229a-c (or each memory bank of each of the memory dies 228 and 229a-c) can be configured to offset the skip refresh operation or the target refresh operation in time using a programmed configuration or setting (e.g., changing an initial value of the count). Other embodiments can use other methods to stagger the skip refresh operations and / or to stagger the target refresh operations in time. The staggering can be with respect to other memory dies of the logical rank, or the staggering can be with respect to other memory banks within a single memory die.

[0052] In some embodiments, the master die 228 can determine the timing of the skip refresh, auto-refresh, and target refresh operations in the master die 228 and each of the slave dies 229a-c. For example, the master die 228 can provide a separate skip refresh signal and a separate target refresh signal (e.g., row hammer refresh (RHR)) for each of the slave dies 229a-c. The master die 228 can include internal logic and can time each of the separate target refresh signals it provides to its respective die. As an example operation, when the master die 228 receives a first activation of the refresh signal, it can send a skip refresh signal to the slave die 229a. When the master die 228 receives a second activation of the refresh signal, it can send a skip refresh signal to the slave die 229b. When the master die 228 receives a third activation of the refresh signal, it can send a skip refresh signal to the slave die 229c. The master die 228 can repeat this cycle again on subsequent activations of the refresh signal. Other methods of operation and / or skip refresh patterns can be used in other example embodiments. In other embodiments, each memory die 228 and 229a-c can include control logic to select the memory bank on which to perform the skip refresh operation during each cycle within the memory die (e.g., master die 228 and slave dies 229a-c).

[0053] In some embodiments, the refresh timing settings that control the timing of the skip refresh, auto-refresh, and target refresh operations can be determined at the time of assembly of the memory package 200. In some embodiments, the timing settings can be determined based on the placement of the memory dies 228 and 229a-c relative to each other (e.g., the slave die 229a can take certain timing settings based on its count of memory dies away from the master die 228, etc.). In some other example architectures, the memory dies 228 and 229a-c of a memory package 200 can each receive all commands directly from the package substrate 227, rather than via the master die 228. The operation of such a memory package can be similar to that of the described memory package 200, with the individual memory dies configured (e.g., programmed) to stagger the skip refresh operations relative to the other memory dies or relative to other banks within the memory dies. Staggering the skip refresh operations and the auto-refresh operations across multiple memory dies or memory banks within a memory die can reduce peak current consumption as compared to performing the auto-refresh operations simultaneously across all memory dies or across all memory banks within a memory die.

[0054] Figure 3 is a block diagram of a memory array 300 in accordance with embodiments of the present disclosure. In some embodiments, the memory array 300 can implement Figure 1memory array 112. Memory array 300 includes a plurality of memory banks 332(0)-(15) arranged into memory bank groups 330(0)-(3). Memory bank groups 330(0)-(3) can be physically separated from one another by a peripheral region of memory device 334. While Figure 3 Example memory array 300 includes four memory bank groups 330(0)-(3), each including a respective memory bank of memory banks 332(0)-(15) (e.g., a total of sixteen memory banks 332(0)-(15)), although it is understood that other embodiments can have more or fewer memory banks 332(0)-(15), and that the memory banks can be organized into more or fewer memory bank groups 330(0)-(3), each having more or fewer memory banks. Memory banks 332(0)-(15) and / or memory bank groups 330(0)-(3) can or can not be physically adjacent to one another.

[0055] Each of memory banks 332(0)-(15) includes a plurality of word lines and bit lines, with a plurality of memory cells arranged at the intersections. In some embodiments, rows (word lines) and columns (bit lines) can be further organized within memory banks 332(0)-(15). For example, each of memory banks 332(0)-(15) can include a plurality of memory pads, each containing a plurality of rows and columns. The memory pads can be organized into sets of memory pads. In some embodiments, during an auto-refresh operation, an address can be provided that causes the word lines in a particular memory pad of each set in each memory bank 332(0)-(15) to refresh.

[0056] In some embodiments, a refresh command may be issued to all memory banks 332(0)-(15) collectively, and all memory banks 332(0)-(15) may perform a refresh operation simultaneously. In some embodiments, a refresh command may be issued to a subset of specified memory banks 332(0)-(15). For example, a particular memory bank group (or groups) 330(0)-(3) within the memory banks 332(0)-(15) may begin refreshing. In another example, a portion of the memory banks 332(0)-(15) within each of the memory bank groups 330(0)-(3) (or subset of the groups) may begin refreshing (e.g., the first memory bank 332(00), 332(10), 332(20), 332(30) within each of the memory bank groups 330(0)-(3)). Once a refresh command has been issued to one or more of the memory banks 332(0)-(15), each of the indicated memory banks 332(0)-(15) may simultaneously perform one or more refresh operations. The timing of the skip and auto-refresh operations may be staggered among the indicated memory banks 332(0)-(15) such that a portion of the indicated memory banks 332(0)-(15) performs a skip refresh operation while a portion of the indicated memory banks 332(0)-(15) performs an auto-refresh operation.

[0057] The indicated memory banks in the memory banks being refreshed 332(0)-(15) may have logic and / or programming that configures a first subset of the indicated memory banks to perform an auto-refresh operation while a second subset of the memory banks skips the refresh operation. In some embodiments, the logic / programming may be inherent to the design of the memory array 300, rather than based on settings programmed after the memory device is assembled.

[0058] Each of the memory banks 332(0)-(15) can be connected to a refresh control circuit (e.g., Figure 1 116), the refresh control circuits are configured to issue refresh addresses to corresponding memory banks 332(0)-(15). Each refresh control circuit can receive activation of a refresh signal AREF and can use internal logic to determine whether the provided refresh address should indicate an auto-refresh operation, a target refresh operation, or a skip refresh operation. For example, each refresh control circuit can count the number of auto-refresh operations and perform a target refresh operation or a skip refresh operation after a certain number of auto-refresh operations have been performed. The counters in different refresh control circuits can be initialized to different values ​​to stagger skip refresh operations across different memory banks.

[0059] Figure 4is a block diagram of a memory module 400 according to embodiments of the present disclosure. One or more memory packages (e.g., or memory dies) 425(0)-(8) can be organized together into the memory module 400. The memory packages 425(0)-(8) can be included on one or both sides of the memory module 400. Each of the memory packages 425(0)-(8) can be any arrangement of memory packages, such as Figure 1 the memory device 100 of Figure 2 the memory package 200 of and / or Figure 3 the memory array 300 of In some embodiments, the memory packages 425(0)-(8) can all be the same type of memory package. In other embodiments, the memory packages 425(0)-(8) can include a mix of different types of memory packages that can be used. The controller 426 can provide various command signals to the memory packages 425(0)-(8). In some instances, the memory module 400 can be configured as a dual in-line memory module (DIMM). In other instances, the memory module 400 can be configured as a non-volatile DIMM (NVDIMM) that includes a combination of volatile memory devices (e.g., DRAM) and non-volatile memory devices (e.g., flash memory) (not shown).

[0060] Although Figure 4 the memory module 400 shown has 9 memory packages 425(0)-(8), more or fewer packages 425(0)-(8) can be used in other embodiments. For example, in some embodiments, the memory packages 425(0)-(8) can be organized into different physical ranks. For example, a first side of the module 400 can have a first physical rank (e.g., 9 memory packages 425(0)-(8) as shown in Figure 4 FIG. 1) and a back side of the module 400 can have a second physical rank (e.g., another 9 memory packages on the reverse side of the module 400). In some embodiments, each physical rank can have 18 packages 425(0)-(8) and there can be one or more physical ranks in the memory module 400. The memory module 400 can include a serial presence detect (SPD) chip 427 configured to provide information about the memory module 400, such as the number of memory packages 425(0)-(8), ranks, memory types, etc. The memory module 400 can further include a register 428 configured to store configuration information for the memory module 400 and a phase-locked loop (PLL) circuit 429 configured to control clock timing for the memory module 400.

[0061] Similar to spacing the auto-refresh, targeted refresh, and skip refresh operations apart within the memory packages 425(0)-(8) as described herein, it can also be desirable to manage the refresh timing between the memory packages 425(0)-(8) of the memory module 400. For the sake of brevity, similar components, structures, and / or operations to those previously described will not be repeated. For example, one or more of the memory packages 425(0)-(8) can enter a refresh mode in which one or more of the respective memory dies perform one of an auto-refresh operation, a targeted refresh operation, or a skip refresh operation. In addition to interleaving between memory dies of a given memory package 425(0)-(8) or between memory banks of a given die, the targeted refresh operations and the skip refresh operations can also be interleaved between different packages 425(0)-(8) of the memory module 400 to reduce peak current consumption.

[0062] Figure 5 is a block diagram of a refresh address control circuit 516 according to embodiments of the present disclosure. Certain internal components and signals of the refresh address control circuit 516 are shown to illustrate the operation of the refresh address control circuit 516. A dashed line 532 is shown to represent that in certain embodiments, each of the components (e.g., the refresh address control circuit 516 and the row decoder 508) can correspond to a particular bank of a memory array, and these components can be repeated for each of the memory banks of the memory array. In some embodiments, the components shown within the dashed line 532 can be located in each of the memory banks. Thus, there can be multiple refresh address control circuits 516 and row decoders 508. For the sake of brevity, only the components for a single memory bank will be described. In some embodiments, the refresh address control circuit 516 can implement the refresh address control circuit 116 of FIG. 1, and can be located in each memory die of a memory package. Figure 1

[0063] An interface 531 (e.g., an external memory controller interface or a command decoder interface) can provide one or more signals to the address refresh control circuit 516 and the row decoder 508. The refresh address control circuit 516 can include a sample timing generator 538, an address sampler 537, a row hammer refresh (RHR) state controller 536, and a refresh address generator 539. The interface 531 can provide one or more control signals, such as an auto-refresh signal AREF, and a row address XADD. The refresh state control 536 can determine whether a skip refresh operation, an auto-refresh operation, or a targeted refresh operation should be performed. The refresh state control 536 can indicate different refresh operations in different memory banks or memory dies so as to interleave the skip, targeted, and auto-refresh operations between the memory banks or memory dies. A refresh interleaving circuit 535 can control the refresh state control 536 to interleave the skip, targeted, and auto-refresh operations.

[0064] ​Refresh address control circuit 516 shows components associated with a particular implementation of detecting an aggressor address by sampling an incoming value of row address XADD with random or semi-random timing. Other methods of detecting an aggressor address can be used in other embodiments, and other components can be provided in refresh address control circuit 516.

[0065] Address sampler 537 can sample (e.g., latch) the current row address XADD in response to activation of ArmSample. Address sampler 537 can also provide one or more latched addresses to refresh address generator 539 as a matched address HitXADD. Refresh state control 536 can provide a RHR signal to indicate that a row hammer refresh operation should occur (e.g., a refresh of a victim row corresponding to an identified aggressor row). Refresh state control 536 can also provide an internal refresh signal IREF to indicate that an auto-refresh operation should occur and no signal (or a skip signal SKIP) when no refresh operation should occur. Refresh state control 536 can be used to control the timing of skip refresh operations, targeted refresh operations, and auto-refresh operations. Activation of the SKIP, IREF, and RHR signals can represent activation of a pump signal. It should be noted that for clarity, Figure 5 SKIP signals are depicted, actual implementations can not include any such signals. Instead, for a skip refresh operation, refresh state control 536 can hold the IREF and RHR signals in an inactive state to indicate a skip refresh operation.

[0066] For each of the different banks, there can be a refresh state control 536. Each refresh state control 536 can contain internal logic configured to determine the timing of the signals it provides (e.g., SKIP, IREF, or RHR) to indicate whether a skip, auto, or target refresh operation should be performed in the associated memory bank. In some embodiments, each refresh state control 536 can contain one or more counters, and can provide the SKIP or RHR signals based on the number of occurrences of the refresh signal AREF (and / or the number of occurrences of the IREF signal). In instances where skip refresh operations or target refresh operations are interleaved across memory dies of a memory package or module, each of the different memory banks of a single memory die can be initialized to the same value to align the refresh operations on the single memory die, with some memory dies being initialized to different values. Thus, each refresh state control 536 can generate the same pattern of skip, target, and auto refresh operations, however the patterns can be out of phase with each other such that they are interleaved in time. In some instances, the refresh state control 536 can be coupled to (and / or can contain) a setting, such as a memory die specific fuse setting. In some embodiments, the refresh state control 536 can contain a counter, and can provide the SKIP signal or the RHR signal based on the number of activations of the refresh signal AREF. In some embodiments, the fuse setting can control the initial value of the counter in the refresh state control 536. In this way, different patterns of SKIP, RHR, and IREF signals can be generated in different memory dies (and / or different packages of a module) to interleave the timing of the target refresh operations.

[0067] In instances where skip refresh operations or target refresh operations are interleaved across memory banks of a single memory die, the counters in each refresh state control 536 in each of the different memory banks can be initialized to different values to interleave the refresh operations. Thus, each refresh state control 536 can generate the same pattern of target and auto refresh operations, however the patterns can be out of phase with each other such that they are interleaved in time. In some embodiments, the refresh interleave circuit 535 can provide a signal to the refresh state control circuit 536 to control the interleaving. For example, the refresh interleave circuit 535 can provide a signal to each of the refresh state controls 536 associated with different memory banks, which can indicate when a target refresh operation should be performed. In some embodiments, there can be a single refresh interleave circuit 535 that is coupled to all of the refresh address control circuits 516 of the different memory banks. The refresh interleave circuit 535 can contain internal logic (e.g., counters initialized to different values) that allow it to direct the interleaving between the different memory banks.

[0068] In response to the activation of RHR, the refresh address generator 539 may provide a refresh address RXADD, which may be an auto-refresh address or may be one or more victim addresses corresponding to a victim row of an aggressor row, the aggressor row corresponding to the matching address HitXADD. The row decoder 508 may perform a refresh operation in response to the refresh address RXADD and the row hammer refresh RHR signal. The row decoder 508 may perform an auto-refresh operation based on the refresh address RXADD and the internal refresh signal IREF. The row decoder 508 may not perform a refresh operation in response to the SKIP signal (e.g., or in response to the deactivation of both the RHR and IREF signals).

[0069] In some embodiments, the refresh address control circuit 516 can determine whether a refresh operation is not currently required (e.g., skipped) or whether one or more target refresh operations are currently required. If a refresh is not currently required, the refresh address control circuit 516 can provide a SKIP signal (e.g., deactivate both the IREF and RHR signals). If a target refresh operation is currently required, the refresh address control circuit 516 can provide a target refresh address and activate the RHR signal.

[0070] The refresh address control circuits 516 associated with different groups can each determine the number of target refresh operations to perform based on the characteristics of accesses to the row address XADD (e.g., the number, frequency, and / or pattern of accesses). For example, a first refresh address control circuit 516 associated with a first group containing a plurality of hammered rows can determine that more target refresh operations are required than a second refresh address control circuit 516 associated with a second group containing fewer hammered rows. In some embodiments, refresh operations can occur in cycles (e.g., a certain number of pumps and / or a certain number of AREFs occur), and the refresh address control circuits 516 can determine the number of skip refresh operations or the number of target refresh operations to perform in each cycle. The remaining refresh operations in the cycle can be used for auto-refresh operations. Although different groups can determine to perform different numbers of skip refresh operations or different numbers of target refresh operations, in some instances, skip refresh operations can still be interleaved between different groups and target refresh operations can still be interleaved between different groups. In other instances, skip and refresh operations can be aligned across all groups on a single die, but can be interleaved across different dies.

[0071] Interface 531 may represent one or more components configured to provide signals to components of the memory bank (or banks). For example, interface 531 may represent, for example Figure 1components such as command address input circuitry 102, address decoders 105, and / or command control 106. Interface 531 can provide a row address XADD, an auto-refresh signal AREF, an activate signal ACT, and a precharge signal PRE. Auto-refresh signal AREF can be a periodic signal that can indicate when an auto-refresh operation is occurring. Activate signal ACT can be provided to activate a given bank of memory. Precharge signal PRE can be provided to precharge a given bank of memory. Row address XADD can be a signal that contains a plurality of bits (which can be transmitted serially or in parallel) and can correspond to a particular row of the activated memory bank.

[0072] Sample timing generator 538 provides a sample signal ArmSample. ArmSample can alternate between a low logic level and a high logic level. Activation of ArmSample can be 'pulsed' in which ArmSample rises to a high logic level and then returns to a low logic level. The interval between pulses of ArmSample can be random, pseudo-random, and / or based on one or more signals of the device (e.g., AREF).

[0073] Address sampler 537 can receive row address XADD from interface 531 and ArmSample from sample timing generator 538. When interface 531 directs an access operation (e.g., a read and write operation) to a different row of a memory cell array (e.g., memory cell array 112) of memory 100, Figure 1 XADD can change. Each time address sampler 537 receives an activation (e.g., a pulse) of ArmSample, address sampler 537 can sample the current value of XADD. In some embodiments, address sampler 532 can provide the current sampled value of XADD as a match address HitXADD. Refresh address generator 539 can provide one or more victim addresses associated with match address HitXADD as refresh addresses RXADD.

[0074] In some embodiments, in response to activation of ArmSample, address sampler 537 can determine whether one or more rows are aggressor rows based on the sampled row address XADD and can provide an identified aggressor row as a match address HitXADD. As part of this determination, address sampler 537 can record a current value of XADD (e.g., by latching and / or storing in a register) in response to activation of ArmSample. The current value of XADD can be compared to previously recorded addresses in address sampler 537 (e.g., addresses stored in latches / registers) to determine a pattern of accesses of the sampled address over time. If address sampler 537 determines that the current row address XADD is repeatedly accessed (e.g., is an aggressor row), activation of ArmSample can also cause address sampler 537 to provide the address of the aggressor row as a match address HitXADD. In some embodiments, the match address (e.g., the aggressor address) HitXADD can be stored in a latch circuit for later retrieval by refresh address generator 539. For example, the value of one or more match addresses HitXADD can be stored until the RHR signal indicates a target refresh operation.

[0075] Refresh state control 536 can receive the auto-refresh signal AREF and can provide a row hammer refresh RHR signal, an internal refresh signal IREF, or a SKIP signal (e.g., or deactivate both the RHR and IREF signals). The RHR signal can indicate that a target refresh operation should occur (e.g., that one or more victim rows associated with an identified aggressor HitXADD should be refreshed). The IREF signal can indicate that an auto-refresh operation should occur. The SKIP signal (e.g., deactivation of both the RHR and IREF signals) can indicate that a skip refresh operation should occur. Refresh state control 536 can use internal logic to provide the RHR signal. In some embodiments, refresh state control 536 can include a counter and can provide the SKIP signal or the RHR signal based on a particular number of activations of AREF. In some instances, the SKIP and RHR signals are associated with different counters. The counter (or counters) can be initialized to a particular value (e.g., when the memory is powered on). The particular value can vary between refresh control circuits of a group of memory dies and / or can vary between different memory dies of a memory package or memory module.

[0076] The refresh state control 536 can provide an IREF signal to control the timing of refresh operations. In some embodiments, for each activation of the refresh signal AREF, the refresh state control 536 can activate the IREF signal multiple times. In some embodiments, the IREF signal can be used as a refresh pump signal to control activation of a refresh pump. In some embodiments, each activation of the AREF signal can be associated with multiple activations of the IREF signal, which can be associated with multiple refresh operations, including a mix of target refresh operations, skip refresh operations, and auto-refresh operations. For example, each activation of the IREF signal can be associated with a refresh operation on a refresh address RXADD, while the state of the RHR signal can determine whether the refresh address RXADD is associated with an auto-refresh operation or a target refresh operation, and the state of the SKIP signal can determine whether the refresh address RXADD is associated with an auto-refresh operation or a skip refresh operation. In some embodiments, the IREF signal can be used to indicate that an auto-refresh operation should occur, the RHR signal to indicate that a target refresh operation should occur, and the SKIP signal to indicate that no refresh operation should occur. For example, the SKIP, RHR, and IREF signals can be generated such that they are not active at the same time (e.g., not all at a high logic level at the same time), and each activation of the SKIP signal can be associated with a skip refresh operation, each activation of the IREF signal can be associated with an auto-refresh operation, and each activation of the RHR signal can be associated with a target refresh operation.

[0077] In some embodiments, the refresh state control 536 can count activations of the IREF signal and use the activation (e.g., pump) count of the IREF signal to determine when the SKIP signal or the RHR signal should be provided. In some instances, the counters can be initialized to different values for different refresh control circuits 516. In other instances, the counters can be initialized to the same value within a die. In some embodiments, the refresh state control 536 can receive one or more signals from the refresh interleaving circuit 535, which is configured to direct different refresh state controllers 536 to provide the SKIP signal or the RHR signal. In either of these manners, the skip or target refresh operations and the auto-refresh operations can be interleaved between groups of dies or between dies of a memory package.

[0078] The refresh address generator 539 can receive a row hammer refresh RHR signal and a match address HitXADD. The match address HitXADD can represent an aggressor row. The refresh address generator 539 can determine a location of one or more victim rows based on the match address HitXADD and provide the location as a refresh address RXADD. In some embodiments, the victim rows can include rows that are physically adjacent to the aggressor row (e.g., HitXADD+1 and HitXADD-1). In some embodiments, the victim rows can also include rows that are physically adjacent to the physically adjacent rows of the aggressor row (e.g., HitXADD+2 and HitXADD-2). Other relationships between victim rows and the identified aggressor row can be used in other examples.

[0079] The refresh address generator 539 can determine a value of the refresh address RXADD based on the RHR signal and, in some examples, the SKIP signal. In some embodiments, when the RHR signal (and the SKIP signal) is not active, the refresh address generator 539 can provide one of an auto-refresh address sequence as the refresh address RXADD. When the RHR signal is active (and the SKIP signal is not active), the refresh address generator 539 can provide a target refresh address, such as a victim address, as the refresh address RXADD.

[0080] The row decoder 508 can perform one or more operations on a memory array (not shown) based on the received signals and addresses. For example, in response to the activate signal ACT and the row address XADD (and the IREF, SKIP, and / or RHR signals being at a low logic level), the row decoder 508 can direct one or more access operations (e.g., read operations) to the specified row address XADD. In response to the RHR signal being active, the row decoder 508 can refresh the refresh address RXADD.

[0081] Figure 6 is a block diagram of a row decoder 600 according to embodiments of the present disclosure. In some embodiments of the present disclosure, the row decoder 600 can be included in Figure 1 of the row decoder 108. The row decoder 600 can determine whether to activate a word line of a bank of a memory array (e.g., the bank of the memory array 118) that corresponds to the row address XADD or the refresh address RXADD. Figure 1

[0082] As described above, the row decoder 600 can include a row address input 602, a refresh address input 604, a bank select input 606, an activate signal output 608, and a refresh signal output 610. The row address input 602 can receive a row address XADD. The refresh address input 604 can receive a refresh address RXADD. The bank select input 606 can receive a bank select signal BS. The activate signal output 608 can output an activate signal ACT. The refresh signal output 610 can output a refresh signal RFR. Figure 6 ​As shown, the row decoder 600 is provided with a row activation timing generator 642 that receives the internal refresh signal IREF and the row hammer refresh signal RHR, the activation signal ACT and the pre-charge signal Pre, and provides the state signal RefPD, the word line actuation signal wdEn, the sense amplifier actuation signal saEn and the bit line equalization signal BLEQ. In some embodiments, the signals IREF and RHR can be the auto-refresh signal AREF. The state signal RefPD is supplied to a multiplexer 640 that selects one of the row address XADD or the refresh address RXADD. The address XADDi selected by the multiplexer 640 is provided to a row redundancy control circuit 644. If the word line indicated by the address XADDi is replaced with a redundant word line, the activation hit signal RedMatch is asserted and the row address XADDdl is generated, which is the replacement target. The addresses XADDi and XADDdl are supplied to a multiplexer 646; where if the activation hit signal RedMatch is not asserted, the address XADDi is selected; and if the activation hit signal RedMatch is asserted, the address XADDdl is selected. The selected address XADD2 is supplied to an X address decoder 648. The X address decoder 648 controls the operation of the word line indicated by the address XADD2, its corresponding sense amplifier, equalization circuit, etc. based on the word line actuation signal wdEn, the sense amplifier actuation signal saEn and the bit line equalization signal BLEQ.

[0083] Figure 7 is an exemplary timing diagram of refresh operations in a memory device according to embodiments of the present disclosure. The timing diagram 700 illustrates refresh operations for memory banks BANKO-15 over time (along the x-axis). The memory banks can be the memory array 112 described with reference to Figure 1 or the memory banks 332(0)-(15) described with reference to Figure 3 The memory banks BANKO-15. The timing diagram 700 illustrates an example can in which the skip refresh operations can be interleaved among the memory banks BANKO-15. Other patterns of interleaving skip refresh operations among more or fewer memory banks can be used in other examples.

[0084] The timing diagram 700 illustrates an example embodiment in which four refresh operations are performed in response to each activation of the refresh signal AREF. Specifically, in response to each activation of AREF, there can be three pumps (e.g., activation of the pump signal in each refresh control circuit), and each of the pumps can be associated with either a skip refresh operation, an auto-refresh operation, or a target refresh operation. The pumps are represented by vertical lines in the timing diagram 700, where the line pattern identifies the type of refresh operation. The pumps are grouped in threes, representing the three pumps per AREF activation. Thus, each group of pumps activates AREF. The solid lines represent auto-refresh operations, the middle dashed lines represent skip refresh operations, and the longer dashed lines represent target refresh operations. As discussed herein, more word lines can be refreshed in a group simultaneously during an auto-refresh operation than during a target refresh operation, and thus auto-refresh operations can consume more power than target refresh operations. No word lines can be refreshed during a skip refresh operation.

[0085] Each group can perform a refresh operation in response to each of the pumps. Since the groups generate the pumps in response to a refresh signal (e.g., AREF) that they all receive, the pumps can generally be synchronized. Thus, each of the memory banks BANK0-15 can perform a first pump at the same time, then perform a second pump at the same time, etc. Each of the banks can generally perform one of a skip refresh operation, an auto-refresh operation, or a target refresh operation in response to each of the pumps. In the example depicted in the timing diagram 700, two different sequences of refresh operations are depicted for an AREF activation. In a first example sequence, an auto-refresh operation is performed in response to a first pump, a first target refresh operation is performed in response to a second pump, and a second target refresh operation is performed in response to a third pump. In a second example sequence, a skip refresh operation is performed in response to a first pump, a first target refresh operation is performed in response to a second pump, and a second target refresh operation is performed in response to a third pump.

[0086] In the example timing diagram 700, each of the memory banks BANKO-15 can alternate between the first example sequence and the second example sequence with each AREF activation. However, during a single AREF activation, among the memory banks BANKO-15, the skip and auto-refresh operations can be interleaved between banks such that a first group of memory banks among the memory banks BANKO-15 performs an auto-refresh operation while a second group of memory banks among the memory banks BANKO-15 performs a skip refresh operation. For example, during the AREF activation received at time TO, the memory banks BANKO-7 can perform the first example sequence (e.g., auto-refresh, first target refresh, second target refresh) while the memory banks BANK8-15 perform the second example sequence (e.g., skip refresh, first target refresh, second target refresh). During the AREF activation received at time Tl, the memory banks BANKO-7 can perform the second example sequence (e.g., skip refresh, first target refresh, second target refresh) while the memory banks BANK8-15 perform the first example sequence (e.g., auto-refresh, first target refresh, second target refresh). In the example timing diagram 700, this two-AREF-activation (e.g., starting at time T2, etc.) cycle or pattern can repeat. By performing an auto-refresh on only half of the memory banks BANKO-15 at a given time, peak current consumption can be reduced as compared to implementations in which all memory banks perform an auto-refresh operation at the same time.

[0087] Figure 7 The memory banks BANKO-15 of FIG. 1 are shown as having refresh cycles with the same number of pumps generated in response to each AREF. In some embodiments, the refresh cycles can be longer or shorter than the number of pumps generated in response to each AREF. Similarly, Figure 7 The example timing diagram 700 of FIG. 1 shows each group of pumps containing a mix of target refresh operations and either skip or auto-refresh operations. In some embodiments, a group can perform only one type of refresh operation in response to a given AREF. Figure 7 The first and second example sequences depicted in FIG. 1 and the repeating cycle of every two AREF activations are exemplary. It should be appreciated that more than two refresh operation sequences (e.g., any number, such as 3, 4, 6, 8, 16, 32, etc.) can be implemented for a given AREF activation, each AREF activation can contain more than three pumps (e.g., 4, 5, 6, etc.), and / or a repeating cycle can be implemented after more than two AREF activations (e.g., any number, such as 3, 4, 6, 8, 16, 32, etc.) without departing from the scope of the present disclosure.

[0088] Figure 8is an exemplary timing diagram 800 of refresh operations in a memory package according to embodiments of the present disclosure. The timing diagram 800 illustrates refresh operations of memory dies DIE0-7 over time (along the x-axis). The memory dies DIE0-7 can be the dies in the stack 125 described with reference to Figure 1 the semiconductor device 100, Figure 2 the master die 228 and / or the slave dies 229a-c of FIG. 2, and / or Figure 4 the memory dies in the memory packages 425(0)-(8) of the memory module 400 of FIG. 4. The timing diagram 800 illustrates an instance of how skip refresh operations can be interleaved among the memory dies DIE0-7. Other patterns of interleaving skip refresh operations among more or fewer memory dies can be used in other instances.

[0089] The timing diagram 800 illustrates an example embodiment in which three refresh operations are performed in response to each activation of the refresh signal AREF. Specifically, in response to each activation of AREF, there can be three pumps (e.g., activation of the pump signal in each refresh control circuit), and each of the pumps can be associated with any one of a skip refresh operation, an auto refresh operation, or a target refresh operation. The pumps are represented in the timing diagram 800 by vertical lines, with line patterns identifying the type of refresh operation. The pumps are in groups of three, representing the three pumps per AREF activation. Thus, each group of pumps activates AREF. Solid lines represent auto refresh operations, intermediate dashed lines represent skip refresh operations, and longer dashed lines represent target refresh operations. As discussed herein, more word lines can be refreshed simultaneously in a group during an auto refresh operation than during a target refresh operation, and thus auto refresh operations can consume more power than target refresh operations. No word lines can be refreshed during a skip refresh operation.

[0090] A given memory die of the memory dies DIE0-7 can perform a refresh operation in response to each of the pumps. Since the memory dies DIE0-7 generate the pumps in response to a refresh signal (e.g., AREF) that they all receive, the pumps can generally be synchronized. Thus, each of the memory dies DIE0-7 can perform a first pump simultaneously, then a second pump simultaneously, etc. In response to each of the pumps, each of the memory dies DIE0-7 can generally perform one of a skip refresh operation, an auto refresh operation, or a target refresh operation. In the example depicted in the timing diagram 800, two different sequences of refresh operations are depicted for an AREF activation. In a first example sequence, an auto refresh operation is performed in response to a first pump, a first target refresh operation is performed in response to a second pump, and a second target refresh operation is performed in response to a third pump. In a second example sequence, a skip refresh operation is performed in response to a first pump, a first target refresh operation is performed in response to a second pump, and a second target refresh operation is performed in response to a third pump.

[0091] In the example timing diagram 800, each of the memory dies DIE0-7 can alternate between the first example sequence and the second example sequence with each AREF activation. However, during a single AREF activation, among the memory dies DIE0-7, the skip and auto-refresh operations can be interleaved between the memory dies DIE0-7 such that a first group of memory dies among the memory dies DIE0-7 performs the auto-refresh operations while a second group of memory dies among the memory dies DIE0-7 performs the skip refresh operations. For example, during the AREF activation received at time TO, the memory dies DIE0-3 can perform the first example sequence (e.g., auto-refresh, first target refresh, second target refresh) while the memory dies DIE4-7 perform the second example sequence (e.g., skip refresh, first target refresh, second target refresh). During the AREF activation received at time Tl, the memory dies DIE0-3 can perform the second example sequence (e.g., skip refresh, first target refresh, second target refresh) while the memory dies DIE4-7 perform the first example sequence (e.g., auto-refresh, first target refresh, second target refresh). In the example timing diagram 800, this two-AREF-activation (e.g., starting at time T2, etc.) cycle or pattern can repeat. By performing the auto-refresh for only a subset of the memory dies DIE0-7 at a given time, peak current consumption can be reduced as compared to implementations in which all memory banks perform the auto-refresh operations at the same time.

[0092] Figure 8 The memory dies DIE0-7 of FIG. 8A are shown as having refresh cycles with the same number of pumps generated in response to each AREF. In some embodiments, the refresh cycles can be longer or shorter than the number of pumps generated in response to each AREF. Similarly, the memory dies DIE0-7 of FIG. 8B are shown as having refresh cycles with the same number of pumps generated in response to each AREF. In some embodiments, the refresh cycles can be longer or shorter than the number of pumps generated in response to each AREF. Figure 8 The example timing diagram 800 of FIG. 8A shows each group of pumps containing a mix of target refresh operations and either skip or auto-refresh operations. In some embodiments, the memory dies can perform only one type of refresh operation in response to a given AREF. Figure 8 The first and second example sequences depicted in FIGS. 8A and 8B, and the repeating cycle of every two AREF activations, are exemplary. It should be appreciated that more than two refresh operation sequences (e.g., any number, such as 3, 4, 6, 8, 16, 32, etc.) can be implemented for a given AREF activation, each AREF activation can contain more than three pumps (e.g., 4, 5, 6, etc.), and / or the repeating cycle can be implemented after more than two AREF activations (e.g., any number, such as 3, 4, 6, 8, 16, 32, etc.) without departing from the scope of the present disclosure.

[0093] While this application has described reducing peak current consumption during refresh operations within a non-volatile memory architecture, it should be understood that similar approaches can be implemented in other contexts and other types of semiconductor devices, including non-volatile memory devices. For example, the configuration of other types of periodic maintenance functions within a memory device / package / module can be interleaved in a similar manner to reduce peak power within each device or set of devices. Other types of periodic maintenance functions can include error correction code maintenance (e.g., ECC error checking and scrubbing), wear leveling, or other target recovery of data within a set of memory array containers after a destructive access other than a row hammer.

[0094] Figure 9 is a flowchart of a method 900 for interleaving refresh operations according to embodiments of the present disclosure. The method 900 can be performed by Figure 1 the semiconductor device 100 of FIG. 1, Figure 2 the memory package 200 of FIG. 2, Figure 3 the memory array 300 of FIG. 3, Figure 4 the memory module 400 of FIG. 4, Figure 5 the refresh interleaving circuit 535 and / or the refresh address control circuit 516 of FIG. 5, Figure 6 the row decoder 600 of FIG. 6, or a combination thereof. It should be noted that the method 900 can be performed to interleave automatic refresh operations across different memory dies (e.g., in a memory package or module), across different memory banks within a single memory die, or a combination thereof.

[0095] The method 900 can include receiving a refresh signal at a first memory die (or bank) and a second memory die (or bank) at 910. In some examples, the first and second memory dies include any of the memory dies in the stack 125 of FIG. 1, Figure 1 the master memory die 228 or any of the slave memory dies 229a-c of FIG. 2, Figure 2 the memory dies in any of the memory packages 425(0)-(8) of FIG. 4, or any combination thereof. In some examples, the first and second memory dies can be included in a memory package, such as the memory package 200 of FIG. 2. In some examples, the first and second memory dies can be included in a memory module, such as the memory module 400 of FIG. 4. In embodiment examples in which the method 900 is performed with first and second memory banks, the first and second memory banks can correspond to any of the memory banks BANK0-N (or corresponding groups of memory cells) of the memory array 118 of FIG. 1, Figure 4 Figure 2 Figure 4 Figure 1 Figure 2 ​​​​a respective bank of memory of a memory die of any one of the memory packages 425(0)-(8) of the memory system 400, or a combination thereof. Figure 3 any one of the banks of memory 332(0)-(15) of the memory system 300, Figure 4 a respective bank of memory of a memory die of any one of the memory packages 425(0)-(8) of the memory system 400, or a combination thereof.

[0096] In some examples, the method 900 can include determining, at the first memory die (or the second memory die), whether to perform an auto-refresh operation or to skip a refresh operation based on an internal setting in response to activation of the refresh signal. In examples, the internal setting is programmed in a fuse bank. In some examples, the determining can include determining a mode of the auto-refresh operation and the skip refresh operation based on the internal setting. The determining can be made via a refresh interleave circuit or a refresh address control circuit (e.g., the refresh interleave circuit 535 and / or the refresh address control circuit 516) of the memory system 500. Figure 5 the refresh interleave circuit 535 and / or the refresh address control circuit 516) of the memory system 500.

[0097] The method 900 can include performing an auto-refresh operation at the first memory die (or bank) and skipping an auto-refresh operation at the second memory die (or bank) in response to a first activation of the refresh signal at 920. In some examples, performing the auto-refresh operation at the first memory die includes performing the auto-refresh operation on a plurality of rows of memory cells.

[0098] The method 900 can include skipping an auto-refresh operation at the first memory die (or bank) and performing an auto-refresh operation at the second memory die (or bank) in response to a second activation of the refresh signal at 930. In some examples, performing the auto-refresh operation at the second memory die includes performing the auto-refresh operation on a plurality of rows of memory cells. In some examples, the method 900 can further include simultaneously performing a target refresh operation at both the first memory die and the second memory die in response to a third activation of the refresh signal. Figure 9 The method 900 depicted in the figure is exemplary only and can include additional steps, and the steps can be performed in a different order than depicted.

[0099] It should be appreciated that any of the examples, embodiments, or processes described herein can be combined or separated into additional examples, embodiments, and / or processes and / or executed in a different order than described.

[0100] The foregoing description of certain implementations of the present disclosure will be limited to illustrative embodiments and is not intended to be exhaustive or to limit the scope of the disclosure or its applications or usage to the specific embodiments described. In describing the implementations of the present system and method, reference is made to the drawings, which form a part thereof, and in which are shown by way of illustration specific embodiments in which the described system and method can be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the presently disclosed system and method, and it is to be understood that other embodiments can be utilized and that structural and logical changes can be made without departing from the spirit and scope of the present disclosure. Furthermore, to the extent that the terms "includes" and "including" are used in the detailed description and claims, these terms are intended to be inclusive in a manner similar to the term "comprising" as that term is interpreted in the appended claims. Furthermore, to the extent the term "or" is used in the detailed description and claims (including the case where "or" is used in the context of "at least one of A or B"), this term is intended to be interpreted as an inclusive OR, meaning either A or B or both A and B. Moreover, the use of the term "about" is intended to allow for variations, such as due to manufacturing tolerances, deviations, or imperfections, which do not materially alter the character of the described system and method. Therefore, the foregoing description and drawings are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present disclosure.

[0101] Finally, the above discussion is meant to be illustrative only of the presently disclosed system and should not be construed to limit the appended claims to any particular embodiment or group of embodiments. Thus, while the presently disclosed system has been described in detail with respect to exemplary embodiments, it will be apparent to those skilled in the art that numerous modifications and alternative embodiments can be devised without departing from the broader and intended spirit and scope of the presently disclosed system as set forth in the following claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense, and the scope of the appended claims should be limited only by the terms of the claims themselves.

Claims

1. An apparatus for memory operation, comprising: a first memory die configured to receive a refresh signal and to perform an auto-refresh operation in response to a first activation of the refresh signal and to skip the auto-refresh operation in response to a second activation of the refresh signal; as well as a second memory die configured to receive the refresh signal and to skip an auto-refresh operation in response to the first activation of the refresh signal and to perform an auto-refresh operation in response to the second activation of the refresh signal, wherein both the first memory die and the second memory die are configured to simultaneously perform a target refresh operation in response to a third activation of the refresh signal.

2. The apparatus of claim 1 , wherein the first memory die is configured to perform the auto-refresh operation on multiple rows of memory cells in response to the first activation of the refresh signal, and wherein the second memory die is configured to perform the auto-refresh operation on multiple rows of memory cells in response to the second activation of the refresh signal.

3. The apparatus of claim 1, further comprising a memory package including the first memory die and the second memory die.

4. The apparatus of claim 1, further comprising a memory module including the first memory die and the second memory die. 5 . The apparatus of claim 1 , wherein the first memory die is configured to determine whether to perform the auto-refresh operation or skip the auto-refresh operation based on an internal setting in response to activation of the refresh signal.

6. The apparatus of claim 5, wherein the internal setting is determined based on a value programmed in a fuse set. 7 . The apparatus of claim 5 , wherein the first memory die comprises a refresh address control circuit configured to determine a mode of auto-refresh operation and skip refresh operation based on the internal setting.

8. An apparatus for memory operation, comprising: a memory array having a first memory group and a second memory group; a refresh control circuit configured to receive a refresh signal, wherein in response to a first activation of the refresh signal, the refresh control circuit is configured to cause an auto-refresh operation to be performed on the group of memory cell rows of the first memory bank and to cause an auto-refresh operation to be skipped on the second memory bank, wherein in response to a second activation of the refresh signal, the refresh control circuit is configured to cause an auto-refresh operation to be skipped on the first memory bank and to cause an auto-refresh operation to be performed on the group of memory cell rows of the second memory bank, Wherein, in response to a third activation of the refresh signal, the refresh control circuit is configured to cause a targeted refresh operation to be performed on a row hammer attack victim row of memory cells of the first memory group and to cause a targeted refresh operation to be performed on a row hammer attack victim row of memory cells of the second memory group. 9 . The apparatus of claim 8 , wherein the refresh control circuit is configured such that auto-refresh operations are skipped for both the first memory group and the second memory group at the same frequency determined based on activation of a reset signal and at different phases.

10. The apparatus of claim 9 , wherein the refresh control circuit is configured such that an auto-refresh operation is skipped for the first memory group based on a first count value of a first counter having a predetermined value and is configured such that an auto-refresh operation is skipped for the second memory group based on a second count value of a second counter having the predetermined value, wherein each of the first counter and the second counter is adjustable in response to each activation of the refresh signal. 11 . The apparatus of claim 10 , wherein the refresh control circuit is configured to initialize the first counter to a count value different from that of the second counter.

12. The apparatus of claim 8 , wherein in response to a third activation of the refresh signal, the refresh control circuit is configured to cause an auto-refresh operation to be performed on a second memory cell row group of the first memory bank and to cause a target refresh operation to be performed on a second memory cell row group of the second memory bank.

13. A memory comprising: a plurality of memory cells; an interface configured to provide a refresh signal in response to a refresh command; a first refresh control circuit configured to receive the refresh signal, wherein in response to a first activation of the refresh signal, the first refresh control circuit is configured to cause an auto-refresh operation to be performed on a row of a first group of the plurality of memory cells, wherein in response to a second activation of the refresh signal, the first refresh control circuit is configured to cause all refresh operations to be skipped on the first group of the plurality of memory cells, wherein in response to a third activation of the refresh signal, the first refresh control circuit is configured to cause a target refresh operation to be performed on a second row of the first group of the plurality of memory cells; as well as a second refresh control circuit configured to receive the refresh signal, wherein in response to the first activation of the refresh signal, the second refresh control circuit is configured to cause all refresh operations to be skipped for a second group of the plurality of memory cells, wherein in response to a second activation of the refresh signal, the second refresh control circuit is configured to cause the auto-refresh operation to be performed on rows of the second group of the plurality of memory cells, Wherein in response to the third activation of the refresh signal, the second refresh control circuit is configured to cause the target refresh operation to be performed on a second row of the second group of the plurality of memory cells.

14. The memory of claim 13, further comprising a memory die comprising a first memory group and a second memory group, wherein the first memory group comprises the first group of the plurality of memory cells and the second memory group comprises the second group of the plurality of memory cells.

15. The memory of claim 13, further comprising a first memory die including the first group of the plurality of memory cells and a second memory die including the second group of the plurality of memory cells.

16. The memory of claim 13 , wherein the first refresh control circuit is configured such that all refresh operations are skipped for the first group of the plurality of memory cells at the same frequency relative to activation of the refresh signal as the second refresh control circuit is configured such that all refresh operations are skipped for the second group of the plurality of memory cells.

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