A chip detection method and system for semiconductor wafer surface

Abstract

The present invention belongs to the field of chip detection technology and discloses a chip detection method and system for semiconductor wafer surfaces. The method comprises: using electromagnetic feature vectors as positive sample instruction signals to construct a positive sample database; scanning the electromagnetic radiation signals of the chips on the surface of the semiconductor wafer to be tested, and outputting the electromagnetic radiation signals to be matched after performing windowing and framing processing on the electromagnetic radiation signals; uploading the electromagnetic radiation signals to be matched to the positive sample database for regional interception processing, measuring the distance between the interception results and any positive sample instruction signals in the positive sample database, and obtaining the chip electromagnetic state detection results; simulating chip impedance mismatch conditions and generating a reflection signal defect qualitative set based on the simulation results; matching the defects of the chips on the surface of the semiconductor wafer to be tested, and combining the defects with the chip electromagnetic state detection results to predict the lifespan of the chips on the surface of the semiconductor wafer to be tested. The present invention can detect non-surface and non-visible defects of chips based on electromagnetic reflection signals.

Description

Technical Field

[0001] The present invention relates to the field of chip detection technology, and in particular to a chip detection method and system for a semiconductor wafer surface. Background Art

[0002] Semiconductor wafers are thin slices made of single-crystal semiconductor materials (usually silicon, but also gallium arsenide, silicon carbide, etc.). As a carrier for manufacturing chips, nanoscale circuit structures can be processed on their surface through processes such as lithography, etching, and deposition. The chip on the surface of a semiconductor wafer refers to multiple chip (Chip / Die) units manufactured simultaneously on the surface of an uncut wafer (Wafer) through micro-nano technology.

[0003] However, during the inspection process, existing semiconductor wafer surface chips are unable to evaluate the corresponding state behavior based on the chip's electromagnetic vector and impedance conditions. When the chip is working, it will generate reflected electromagnetic waves. If these signals are not utilized, it is easy to miss important diagnostic basis, resulting in the inability to detect the chip's subtle structural damage behavior, and then miss the capture of potential defects, reducing the efficiency of chip inspection.

[0004] Therefore, how to provide a method and system for detecting chips on the surface of a semiconductor wafer is an urgent problem to be solved. Summary of the Invention

[0005] The embodiments of the present invention provide a method and system for detecting chips on the surface of a semiconductor wafer, so as to solve the problem in the prior art that subtle structural damage of chips cannot be detected.

[0006] To provide a basic understanding of some aspects of the disclosed embodiments, the following is a brief summary. This summary is not intended to be an extensive review, identify key or critical elements, or delineate the scope of these embodiments. Its sole purpose is to present some concepts in a simplified form as a prelude to the detailed description that follows.

[0007] According to a first aspect of an embodiment of the present invention, a method for detecting chips on the surface of a semiconductor wafer is provided.

[0008] In one embodiment, a method for detecting chips on a surface of a semiconductor wafer includes:

[0009] The electromagnetic feature vectors corresponding to the defect-free semiconductor wafer surface chips are obtained using a feature extraction algorithm, and the electromagnetic feature vectors are used as positive sample instruction signals to build a positive sample database;

[0010] The near-field probe technology is used to scan the electromagnetic radiation signal of the chip on the surface of the semiconductor wafer to be tested, and after the electromagnetic radiation signal is subjected to windowing and framing processing, the feature extraction algorithm is used to output the electromagnetic radiation signal to be matched;

[0011] The electromagnetic radiation signal to be matched is uploaded to the positive sample database for regional interception processing, and the distance between the interception result and any positive sample command signal in the positive sample database is measured to obtain the chip electromagnetic state detection result;

[0012] Processing multiple forms of defects on the surface of a defect-free semiconductor wafer chip, simulating chip impedance mismatch, and generating a qualitative set of reflection signal defects based on the simulation results;

[0013] The defects of the chip on the surface of the semiconductor wafer to be tested are matched according to the qualitative set of defects of the reflected signal, and the defect results are combined with the electromagnetic state detection results of the chip to predict the life of the chip on the surface of the semiconductor wafer to be tested.

[0014] In one embodiment, processing multiple defects on a defect-free semiconductor wafer surface chip, simulating chip impedance mismatch, and generating a reflection signal defect qualitative set based on the simulation results includes:

[0015] Generate modeling parameters based on the defect type of the chip on the semiconductor wafer surface, build a chip simulation model based on the modeling parameters and the chip structure on the semiconductor wafer surface, and add test signals in the simulation to observe the chip's reflected signal;

[0016] A feature extraction algorithm is used to extract a feature signal set containing peak amplitude and phase offset from the reflection signal, the feature signal set is associated with the defect type, and a mapping relationship set is constructed based on the association results;

[0017] The impedance mismatch performance of the chip on the surface of the semiconductor wafer is analyzed according to the mapping relationship set, and the defect emission coefficient and defect resonance offset of the chip on the surface of the semiconductor wafer are quantified based on the impedance mismatch performance to generate a qualitative set of reflection signal defects.

[0018] According to a second aspect of an embodiment of the present invention, a chip detection system for a semiconductor wafer surface is provided.

[0019] In one embodiment, a chip detection system for a semiconductor wafer surface includes:

[0020] A positive sample database construction module is used to obtain electromagnetic feature vectors corresponding to defect-free semiconductor wafer surface chips using a feature extraction algorithm, and use the electromagnetic feature vectors as positive sample instruction signals to construct a positive sample database;

[0021] The signal processing feature extraction module is used to scan the electromagnetic radiation signal of the chip on the surface of the semiconductor wafer to be tested using near-field probe technology, and after performing windowing and framing processing on the electromagnetic radiation signal, use the feature extraction algorithm to output the electromagnetic radiation signal to be matched;

[0022] The electromagnetic state detection and matching module is used to upload the electromagnetic radiation signal to be matched to the positive sample database for regional interception processing, measure the distance between the interception result and any positive sample command signal in the positive sample database, and obtain the chip electromagnetic state detection result;

[0023] The defect qualitative set generation module is used to process multiple forms of defects on the surface chip of a defect-free semiconductor wafer, simulate the chip impedance mismatch, and generate a reflection signal defect qualitative set based on the simulation results;

[0024] The chip life prediction and judgment module is used to match the defects of the chip on the surface of the semiconductor wafer to be tested according to the qualitative set of defects in the reflected signal, and combine the defect results with the chip electromagnetic state detection results to predict the life of the chip on the surface of the semiconductor wafer to be tested.

[0025] According to a third aspect of an embodiment of the present invention, a computer device is provided.

[0026] In one embodiment, the computer device includes a memory and a processor, the memory stores a computer program, and the processor implements the steps of the above method when executing the computer program.

[0027] According to a fourth aspect of embodiments of the present invention, a computer-readable storage medium is provided.

[0028] In one embodiment, the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the above method are implemented.

[0029] The technical solution provided by the embodiment of the present invention may have the following beneficial effects:

[0030] The present invention reflects the intrinsic electromagnetic behavior of the chip in a defect-free state by analyzing the electromagnetic eigenvector and uses the defect-free eigenvector as a standard template to quickly and accurately match the signals collected in the future, thereby realizing rapid detection of the chip. At the same time, based on the impedance mismatch and reflection signal changes caused by the defect, a recognizable physical pattern is constructed, and then according to the electromagnetic reflection signal, non-surface and non-visible defects of the chip can be detected.

[0031] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0033] Figure 1This is a flow chart showing a method for detecting chips on a surface of a semiconductor wafer according to an exemplary embodiment;

[0034] Figure 2 This is a principle block diagram of a chip detection system for a semiconductor wafer surface according to an exemplary embodiment;

[0035] Figure 3 The figure is a schematic diagram showing the structure of a computer device according to an exemplary embodiment. DETAILED DESCRIPTION

[0036] The following description and accompanying drawings sufficiently illustrate the specific embodiments herein to enable those skilled in the art to practice them. Portions and features of some embodiments may be included in or substituted for portions and features of other embodiments. The scope of the embodiments herein includes the entire scope of the claims, including all available equivalents thereof. Herein, the terms "first," "second," and the like are used solely to distinguish one element from another and do not require or imply any actual relationship or order between these elements. In practice, the first element can also be referred to as the second element, and vice versa. Furthermore, the terms "comprise," "comprising," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a structure, device, or apparatus comprising a list of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such structure, device, or apparatus. Without further limitation, an element defined by the phrase "comprising a..." does not preclude the presence of other identical elements in the structure, device, or apparatus comprising the element. The various embodiments herein are described in a progressive manner, with each embodiment focusing on its differences from the other embodiments. Similar or identical parts between the various embodiments can be referenced to each other.

[0037] The terms "longitudinal", "transverse", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like used herein to indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are intended only to facilitate the description of this document and simplify the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the present invention. In the description herein, unless otherwise specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, they can be mechanical or electrical connections, or they can be internal connections between two elements, they can be directly connected, or they can be indirectly connected through an intermediate medium. For those of ordinary skill in the art, the specific meanings of the above terms can be understood according to the specific circumstances.

[0038] As used herein, unless otherwise specified, the term "plurality" means two or more.

[0039] In this document, the character " / " indicates that the preceding and following objects are in an "or" relationship. For example, A / B means: A or B.

[0040] In this article, the term "and / or" is used to describe the association relationship between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or, A and B.

[0041] It should be understood that, although the various steps in the flowchart are shown in sequence as indicated by the arrows, these steps are not necessarily performed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps may be performed in other orders. Moreover, at least a portion of the steps in the figure may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily performed at the same time, but may be performed at different times. The execution order of these sub-steps or stages is not necessarily to be performed in sequence, but may be performed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

[0042] Each module in the device or system of the present application can be implemented in whole or in part by software, hardware, or a combination thereof. The above modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory of the computer device in the form of software so that the processor can call and execute the operations corresponding to the above modules.

[0043] In the absence of conflict, the embodiments of the present invention and the features thereof may be combined with each other.

[0044] Figure 1 An embodiment of a method for detecting chips on a surface of a semiconductor wafer according to the present invention is shown.

[0045] In this optional embodiment, the method for detecting chips on the surface of a semiconductor wafer includes:

[0046] Step S101, using a feature extraction algorithm to obtain electromagnetic feature vectors corresponding to defect-free semiconductor wafer surface chips, and using the electromagnetic feature vectors as positive sample instruction signals to construct a positive sample database;

[0047] Step S102, using a near-field probe technology to scan the electromagnetic radiation signal of the chip on the surface of the semiconductor wafer to be tested, and after performing windowing and framing processing on the electromagnetic radiation signal, using a feature extraction algorithm to output the electromagnetic radiation signal to be matched;

[0048] Step S103, uploading the electromagnetic radiation signal to be matched to the positive sample database for region interception processing, measuring the distance between the interception result and any positive sample instruction signal in the positive sample database, and obtaining the chip electromagnetic state detection result;

[0049] Step S104, processing multiple forms of defects on a chip on the surface of a defect-free semiconductor wafer, simulating chip impedance mismatch, and generating a qualitative set of reflection signal defects based on the simulation results;

[0050] Step S105 , matching defects of the chips on the surface of the semiconductor wafer to be tested according to the defect qualitative set of the reflected signal, and combining the defect results with the chip electromagnetic state detection results to predict the life of the chips on the surface of the semiconductor wafer to be tested.

[0051] In this optional embodiment, when using a feature extraction algorithm to obtain the electromagnetic feature vector corresponding to a defect-free semiconductor wafer surface chip, and using the electromagnetic feature vector as a positive sample instruction signal to construct a positive sample database, near-field probe technology can be used to scan the electromagnetic radiation signal of the defect-free semiconductor wafer surface chip, and obtain the scanning current frequency, scanning time sequence, signal time reception sequence and scanning duration; determine the correction frequency based on the scanning time sequence, signal time reception sequence and scanning current frequency, calculate the overall phase delay degree of the correction frequency within the scanning duration, and obtain the delay time of the electromagnetic radiation signal; compensate the received electromagnetic radiation signal according to the delay time, and resample the compensated electromagnetic radiation signal according to the original number of sampling points to obtain a corrected electromagnetic radiation signal; reconstruct the time domain signal based on the corrected electromagnetic radiation signal to obtain the true spectrum of the electromagnetic radiation signal as the electromagnetic feature vector, and use the electromagnetic feature vector as the positive sample instruction signal to construct a positive sample database.

[0052] It should be explained that the defect-free semiconductor wafer surface chip proposed in this embodiment is a chip with no scratches, no particle contamination, no cracks, no bubbles or residual photoresist on the surface, the metal interconnect line width or spacing is ≤±2% of the production standard value, the line edge roughness should be ≤1.5nm, the grain size should be ≤50nm, the resistivity should be ≤2.0μΩ·cm, and the leakage current in the crystal parameters should be less than 0.5μA / cm 2, under the test condition of 25°C; the static holding current SRAM is <10pA / cell, under the test condition of 25°C and the voltage is 0.8V; the refresh leakage current (DRAM) is <1fA / cell / ms, under the test condition of 85°C; and the wafer-level threshold voltage uniformity is ≤±30mV, the coupling coefficient of adjacent signal lines (spacing = 3×line width) is ≤-40dB, under the condition of an operating frequency of 5; at the same time, the radiation intensity difference is ≤±0.5dB (scanning step size 5μm), the deviation of the radiation intensity at the edge of the chip and the center area is ≤±1dB, and in order to ensure the quality of the positive sample database, the film thickness error controlled by the deposition or etching process of the defect-free semiconductor wafer surface chip is less than ±5%, and there is no deformation or electrical performance drift caused by thermal stress when operating in the temperature range of -40°C to 125°C, that is, the chip that meets the requirements of physical structure integrity, qualified electrical performance and process stability is the defect-free semiconductor wafer surface chip proposed in this embodiment.

[0053] It needs to be explained that in the process of using near-field probe technology to scan the electromagnetic radiation signal of the chip on the surface of a defect-free semiconductor wafer and obtain the scanning current frequency, scanning time series, signal time reception sequence and scanning time, it is necessary to build a scanning test platform, prepare the near-field probe (specifically, it can be an electric field or magnetic field type), scanning platform, signal acquisition equipment (such as a spectrum analyzer, a high-speed oscilloscope or an ADC acquisition card), amplifier, chip power supply and excitation system, and control and synchronization module, and at the same time fix the chip on the surface of the semiconductor wafer to be tested on the platform, configure its working state, ensure that the power supply, clock and input signal are normal, so that it can generate a stable electromagnetic radiation signal under normal functional state, set the scanning parameters, including the spatial boundary of the scanning area, step distance, probe scanning height, sampling time and sampling frequency of each point, to ensure spatial resolution and time precision. The scanning process is started through the control system. The probe moves to the predetermined scanning points on the two-dimensional plane in sequence, and electromagnetic signals are collected at each point. The collected signal is a time series, which records the position information of each sampling point, the sampling start and end time (used to generate the scanning time series), and the received original electromagnetic waveform (signal time reception sequence). The main frequency component is extracted as the scanning current frequency of the point. The high-speed circuit inside the chip inevitably generates high-frequency current / voltage changes when performing specific tasks. These changes are repeated continuously according to clear functional behavior laws, thus presenting stable and repeatable electromagnetic leakage characteristics in frequency and time. Under the premise of controlling the power supply, clock, environmental interference and excitation conditions, the signal can be stably captured and analyzed by the high-precision near-field probe to obtain the electromagnetic radiation signal of the defect-free chip on the surface of the semiconductor wafer.

[0054] The process of extracting the features of electromagnetic radiation signals to obtain electromagnetic vectors is to use the electromagnetic radiation signals as vector components to form a three-dimensional vector representation. It can be obtained by arranging multiple directional probes or rotating a single probe to sample in different directions in sequence. During the sampling process, each component signal needs to be collected synchronously to ensure time domain alignment. Then, after the collected signal is bandpass filtered and denoised, the short-time Fourier transform (STFT) or wavelet transform is applied to extract the time-frequency features of the signal in each direction, and the main frequency, energy, phase and other parameters in each direction are extracted, and then the amplitude vector and phase vector of the electric field or magnetic field are respectively constructed. Then, according to needs, complex vectors (complex forms representing amplitude and phase) can be further synthesized, and the electromagnetic vectors at each measuring point are spliced ​​to construct a spatial distribution map, and the electromagnetic vector field can be reconstructed.

[0055] In this optional embodiment, the calculation formula for the delay time of the electromagnetic radiation signal is:

[0056] ;

[0057] Where D shift Indicates the delay time of electromagnetic radiation signal, g measured represents the scanning current frequency, Δg represents the frequency error, T represents the sampling time, F T Indicates the total phase delay degree corresponding to the sampling time T correction frequency.

[0058] In this optional embodiment, when the electromagnetic radiation signal to be matched is uploaded to the positive sample database for regional interception processing, the distance between the interception result and any positive sample instruction signal in the positive sample database is measured, and the chip electromagnetic state detection result is obtained, the electromagnetic radiation signal to be matched can be obtained for amplification and correction processing, and regional interception processing is performed on the electromagnetic radiation signal to be matched according to the preset interception requirements, and morphological recognition is performed on the intercepted area; the morphological recognition result is compared with the positive sample database. If the morphological recognition result does not exist in the positive sample database, the regional interception processing is re-implemented until the regional interception exists in the positive sample database; if the morphological recognition result exists in the positive sample database, the electromagnetic radiation signal to be matched is directly matched from the positive sample database, and the shortest edit distance between the morphological recognition result and the matching result is determined; the difference between the shortest edit distance and the distance threshold is determined, and the chip electromagnetic state detection result of the electromagnetic radiation signal to be matched is identified according to the difference result.

[0059] It should be explained that in the process of obtaining the electromagnetic status detection results of the chip, near-field probe technology is used to scan the chip in a defect-free state, including scanning current frequency, scanning time sequence, signal time reception sequence and scanning duration, so as to obtain the stable electromagnetic response of the chip in a defect-free state, and provide high-quality original data for subsequent correction, modeling and comparison matching. By calculating the delay time of the electromagnetic radiation signal, the original received signal is compensated for the shift on the time axis, and the compensated signal is resampled according to the original number of sampling points to obtain a set of time domain reconstructed signals, which is convenient for eliminating signal misalignment problems caused by system delays or equipment errors.

[0060] Convert the corrected time domain signal to the frequency domain to obtain the spectrum feature vector, which is used as the positive sample instruction signal and stored in the positive sample database to obtain the characteristic standard of a defect-free chip, providing a reference for subsequent identification and comparison;

[0061] Obtain the electromagnetic radiation signal of the chip to be matched, amplify and correct it, perform regional interception processing according to the spatial window, perform morphological recognition (such as waveform pattern, feature distribution, etc.) on the intercepted area, select key feature areas for matching, improve accuracy and efficiency, and prepare for pattern matching for subsequent comparisons. If the morphological recognition result has no match in the positive sample library, re-intercept; if the morphological recognition result has a match: calculate the edit distance (such as the shortest edit distance); compare it with the set distance threshold to determine the degree of difference; derive the current electromagnetic state of the chip, and quantitatively compare the actual electromagnetic performance of the chip with the defect-free state. The edit distance represents the degree of matching. The larger the difference, the greater the difference, the more abnormal the state. Detect whether the chip is in normal, degraded, abnormal, etc.

[0062] In this optional embodiment, when processing multiple forms of defects on a defect-free semiconductor wafer surface chip, simulating chip impedance mismatch, and generating a qualitative set of reflection signal defects based on the simulation results, modeling parameters can be generated based on the defect type of the semiconductor wafer surface chip, a chip simulation model can be constructed based on the modeling parameters and the semiconductor wafer surface chip structure, and a test signal can be added in the simulation to observe the chip reflection signal; a feature extraction algorithm is used to extract a feature signal set containing peak amplitude and phase offset from the reflection signal, the feature signal set is associated with the defect type, and a mapping relationship set is constructed based on the association result; the impedance mismatch performance of the semiconductor wafer surface chip is analyzed based on the mapping relationship set, and the defect emission coefficient and defect resonance offset of the semiconductor wafer surface chip are quantified based on the impedance mismatch performance to generate a qualitative set of reflection signal defects.

[0063] In this optional embodiment, when using a feature extraction algorithm to extract a feature signal set including peak amplitude and phase offset from the reflected signal, associating the feature signal set with the defect type, and constructing a mapping relationship set based on the association result, the reflected signal can be decomposed to generate a number of vector signals, and the vector signal can be divided into intervals to calculate the signal fluctuation degree of the vector signal within the interval; based on the signal fluctuation degree, a fluctuation sequence of the vector signal is obtained, and based on the fluctuation sequence corresponding to each vector signal, a distribution characteristic value of the vector signal is obtained to obtain the phase offset degree of the vector signal; based on the phase offset degree, an adaptive threshold of the vector signal is analyzed, and the amplitude of the vector signal is extracted based on the adaptive threshold, and the peak amplitude of the vector signal is analyzed based on the extraction result; the peak amplitude and the phase offset degree are combined as the feature signal set of the reflected signal, and the feature signal set is associated with the defect type to construct a mapping relationship set.

[0064] In this optional embodiment, the calculation formula for the signal fluctuation degree is:

[0065] ;

[0066] Where H ab represents the signal fluctuation degree of the bth interval of the ath vector signal, c represents the total number of signals in the bth interval of the ath vector signal, y ab(d-1,d) represents the slope between the d-1th signal and the dth signal in the bth interval of the ath vector signal, y ab(d,d+1) represents the slope between the dth signal and the d+1th signal in the bth interval of the ath vector signal, y abd represents the dth signal in the bth interval of the ath vector signal, Represents the mean of all signals in the bth interval of the ath vector signal.

[0067] In this optional embodiment, when obtaining the fluctuation sequence of the vector signal based on the signal fluctuation degree, and obtaining the distribution characteristic value of the vector signal according to the fluctuation sequence corresponding to each vector signal, and obtaining the phase offset degree of the vector signal, the signal fluctuation degree can be sorted in ascending order, and the sorting result is used as the fluctuation sequence of the vector signal, and the possibility of each signal being a segmentation point is obtained according to the difference between the signals in the fluctuation sequence; the segmentation point is selected based on the feasibility result, and the segmentation point is used to divide the vector signal into two parts, the peak value and the phase, and the distribution characteristic values ​​of the peak value and the phase are judged based on the distribution state of the vector signal; the distribution characteristic value is used to obtain the offset part of the fluctuation sequence corresponding to each vector signal, and a reference sequence of the fluctuation sequence is generated according to the offset part, and the phase offset degree of the vector signal is obtained in combination with the interval corresponding to the fluctuation sequence.

[0068] It needs to be explained that in the process of generating a qualitative set of reflected signal defects, different defect types (such as scratches, etching residues, and uneven doping) are artificially simulated on the surface chip of a defect-free semiconductor wafer, and modeling parameters (such as depth, position, and dielectric changes) are generated based on the defect type. A simulation model is constructed, and electromagnetic test signals are injected into the model. The reflected signals are recorded, and a virtual experimental platform that can reproduce the changes in electromagnetic characteristics caused by defects can be created. At the same time, a feature extraction algorithm is used to extract the peak amplitude and phase offset from the reflected signal to construct a feature signal set, which represents the electromagnetic response behavior corresponding to different defects. Complex waveform data can be converted into comparable and classifiable vector features, and the extracted feature signal set is associated with the defect type to form a complete mapping set, indicating that a certain type of defect and a certain set of feature signals (such as a certain phase offset + peak amplitude) construct a defect recognition knowledge base to achieve the ability to infer the defect type from the electromagnetic response signal.

[0069] Decompose the reflected signal into multiple vector signals, partition each vector signal, calculate the signal fluctuation degree in each interval, and decompose the complex waveform into smaller data segments. The fluctuation degree reflects the activity level and disturbance characteristics of each signal segment, laying the foundation for peak / phase feature extraction. Arrange the fluctuation degree values ​​in ascending order to form a fluctuation sequence. Based on the signal difference, determine the segmentation point (specifically, the phase / peak boundary), divide the vector signal into the phase part and the peak part, analyze their distribution characteristic values ​​separately, calculate the phase offset degree, and use the distribution change to quantify the phase offset, which is an important signal dimension for defect identification.

[0070] An adaptive threshold is generated based on the fluctuation characteristics of the phase offset. Within each signal interval, the threshold is used to filter out areas of significant change (i.e., peak values). The peak amplitude and phase offset are used as a set of reflection signal feature vectors and bound to the defect type to form a qualitative set of reflection signal defects. This provides a reference library for reflection signals discovered during real-time detection and improves recognition accuracy.

[0071] Figure 2 An embodiment of a chip detection system for a semiconductor wafer surface according to the present invention is shown.

[0072] In this optional embodiment, the chip detection system for the surface of a semiconductor wafer includes:

[0073] The positive sample database construction module 201 is used to obtain electromagnetic feature vectors corresponding to defect-free semiconductor wafer surface chips using a feature extraction algorithm, and use the electromagnetic feature vectors as positive sample instruction signals to construct a positive sample database;

[0074] The signal processing feature extraction module 202 is used to use the near-field probe technology to scan the electromagnetic radiation signal of the chip on the surface of the semiconductor wafer to be tested, and after performing windowing and framing processing on the electromagnetic radiation signal, use the feature extraction algorithm to output the electromagnetic radiation signal to be matched;

[0075] The electromagnetic state detection and matching module 203 is used to upload the electromagnetic radiation signal to be matched to the positive sample database for region interception processing, measure the distance between the interception result and any positive sample command signal in the positive sample database, and obtain the chip electromagnetic state detection result;

[0076] The defect qualitative set generation module 204 is used to process multiple defects on a defect-free semiconductor wafer surface chip, simulate chip impedance mismatch, and generate a reflection signal defect qualitative set based on the simulation results;

[0077] The chip life prediction and judgment module 205 is used to match the defects of the chip on the surface of the semiconductor wafer to be tested according to the reflection signal defect qualitative set, and combine the defect results with the chip electromagnetic state detection results to predict the life of the chip on the surface of the semiconductor wafer to be tested.

[0078] In one embodiment, a computer device is provided. The computer device may be a server, and its internal structure diagram may be as follows: Figure 3 As shown. The computer device includes a processor, a memory, and a network interface connected via a system bus. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of the operating system and computer program in the non-volatile storage medium. The database of the computer device is used to store static information and dynamic information data. The network interface of the computer device is used to communicate with an external terminal via a network connection. When the computer program is executed by the processor, the steps of the above-mentioned method embodiment are implemented.

[0079] Those skilled in the art will understand that Figure 3 The structure shown in the figure is merely a block diagram of a portion of the structure related to the solution of the present invention and does not constitute a limitation on the computer device to which the solution of the present invention is applied. The specific computer device may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.

[0080] In addition, the present invention also provides a computer device, including a memory and a processor, wherein a computer program is stored in the memory, and the processor implements the steps in the above method embodiment when executing the computer program.

[0081] In addition, the present invention also provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the steps in the above method embodiment are implemented.

[0082] Those skilled in the art will appreciate that all or part of the processes in the above-described method embodiments can be implemented by instructing the relevant hardware using a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes in the above-described method embodiments. Any reference to memory, storage, database, or other media used in the various embodiments provided herein may include at least one of non-volatile and volatile memory. Non-volatile memory may include read-only memory (ROM), magnetic tape, floppy disk, flash memory, or optical storage. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM can take various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM).

[0083] The present invention is not limited to the structures described above and shown in the drawings, and various modifications and changes can be made without departing from the scope thereof. The scope of the present invention is limited only by the appended claims.

Claims

1. A method for detecting chips on the surface of a semiconductor wafer, characterized in that: include: The electromagnetic feature vectors corresponding to the defect-free semiconductor wafer surface chips are obtained using a feature extraction algorithm, and the electromagnetic feature vectors are used as positive sample instruction signals to build a positive sample database; The near-field probe technology is used to scan the electromagnetic radiation signal of the chip on the surface of the semiconductor wafer to be tested, and after the electromagnetic radiation signal is subjected to windowing and framing processing, the feature extraction algorithm is used to output the electromagnetic radiation signal to be matched; The electromagnetic radiation signal to be matched is uploaded to the positive sample database for regional interception processing, and the distance between the interception result and any positive sample command signal in the positive sample database is measured to obtain the chip electromagnetic state detection result; Processing multiple forms of defects on the surface of a defect-free semiconductor wafer chip, simulating chip impedance mismatch, and generating a qualitative set of reflection signal defects based on the simulation results; The defects of the chip on the surface of the semiconductor wafer to be tested are matched according to the qualitative set of defects of the reflected signal, and the defect results are combined with the electromagnetic state detection results of the chip to predict the life of the chip on the surface of the semiconductor wafer to be tested.

2. The method for detecting chips on the surface of a semiconductor wafer according to claim 1, wherein: The method of using a feature extraction algorithm to obtain electromagnetic feature vectors corresponding to defect-free semiconductor wafer surface chips and using the electromagnetic feature vectors as positive sample instruction signals to construct a positive sample database includes: Use near-field probe technology to scan the electromagnetic radiation signal of the chip on the surface of the defect-free semiconductor wafer, and obtain the scanning current frequency, scanning time sequence, signal time reception sequence and scanning duration; Determine the correction frequency according to the scanning time sequence, the signal time receiving sequence and the scanning current frequency, calculate the overall phase delay degree of the correction frequency within the scanning time, and obtain the delay time of the electromagnetic radiation signal; The received electromagnetic radiation signal is compensated according to the delay time, and the compensated electromagnetic radiation signal is resampled according to the number of original sampling points to obtain a corrected electromagnetic radiation signal; The time domain signal is reconstructed according to the corrected electromagnetic radiation signal to obtain the true spectrum of the electromagnetic radiation signal as the electromagnetic feature vector. The electromagnetic feature vector is used as the positive sample instruction signal to build a positive sample database.

3. The method for detecting chips on the surface of a semiconductor wafer according to claim 2, wherein: The calculation formula of the delay time of the electromagnetic radiation signal is: ； Where D shift Indicates the delay time of electromagnetic radiation signal, g measured represents the scanning current frequency, Δg represents the frequency error, T represents the sampling time, F T Indicates the total phase delay degree corresponding to the sampling time T correction frequency.

4. The method for detecting chips on the surface of a semiconductor wafer according to claim 3, wherein: The method of uploading the electromagnetic radiation signal to be matched to the positive sample database for region interception processing, measuring the distance between the interception result and any positive sample instruction signal in the positive sample database, and obtaining the chip electromagnetic state detection result includes: Obtain the electromagnetic radiation signal to be matched and uploaded, perform amplification and correction processing, and perform regional interception processing on the electromagnetic radiation signal to be matched according to preset interception requirements, and perform morphological recognition on the intercepted area; Compare the morphological recognition result with the positive sample database. If the morphological recognition result does not exist in the positive sample database, re-implement the region interception process until the region interception exists in the positive sample database. If there is a morphological recognition result in the positive sample database, the electromagnetic radiation signal to be matched is directly matched from the positive sample database, and the shortest edit distance between the morphological recognition result and the matching result is determined; The difference between the shortest edit distance and the distance threshold is determined, and the electromagnetic state detection result of the chip of the electromagnetic radiation signal to be matched is identified according to the difference result.

5. The method for detecting chips on the surface of a semiconductor wafer according to claim 1, wherein: The method of processing multiple defects on a defect-free semiconductor wafer surface chip, simulating chip impedance mismatch, and generating a qualitative set of reflection signal defects based on the simulation results includes: Generate modeling parameters based on the defect type of the chip on the semiconductor wafer surface, build a chip simulation model based on the modeling parameters and the chip structure on the semiconductor wafer surface, and add test signals in the simulation to observe the chip's reflected signal; A feature extraction algorithm is used to extract a feature signal set containing peak amplitude and phase offset from the reflection signal, the feature signal set is associated with the defect type, and a mapping relationship set is constructed based on the association results; The impedance mismatch performance of the chip on the surface of the semiconductor wafer is analyzed according to the mapping relationship set, and the defect emission coefficient and defect resonance offset of the chip on the surface of the semiconductor wafer are quantified based on the impedance mismatch performance to generate a qualitative set of reflection signal defects.

6. The method for detecting chips on the surface of a semiconductor wafer according to claim 5, wherein: The defect types of the semiconductor wafer surface chip include scratches, etching residues and uneven doping.

7. The method for detecting chips on the surface of a semiconductor wafer according to claim 6, wherein: The method of extracting a characteristic signal set including peak amplitude and phase shift from the reflection signal by using a feature extraction algorithm, associating the characteristic signal set with the defect type, and constructing a mapping relationship set based on the association result includes: Decompose the reflected signal to generate several vector signals, divide the vector signals into intervals, and calculate the signal fluctuation degree of the vector signals within the intervals; Obtaining a fluctuation sequence of the vector signal based on the signal fluctuation degree, and obtaining a distribution characteristic value of the vector signal according to the fluctuation sequence corresponding to each vector signal, thereby obtaining a phase shift degree of the vector signal; Analyzing the adaptive threshold of the vector signal according to the degree of phase shift, extracting the amplitude of the vector signal based on the adaptive threshold, and analyzing the peak amplitude of the vector signal based on the extraction result; The peak amplitude and the phase shift degree are combined as the characteristic signal set of the reflection signal, and the characteristic signal set is associated with the defect type to construct a mapping relationship set.

8. The method for detecting chips on the surface of a semiconductor wafer according to claim 7, wherein: The calculation formula for the signal fluctuation degree is: ； Where H ab represents the signal fluctuation degree of the bth interval of the ath vector signal, c represents the total number of signals in the bth interval of the ath vector signal, y ab(d-1,d) represents the slope between the d-1th signal and the dth signal in the bth interval of the ath vector signal, y ab(d,d+1) represents the slope between the dth signal and the d+1th signal in the bth interval of the ath vector signal, y abd represents the dth signal in the bth interval of the ath vector signal, Represents the mean of all signals in the bth interval of the ath vector signal.

9. The method for detecting chips on the surface of a semiconductor wafer according to claim 8, wherein: The step of obtaining a fluctuation sequence of a vector signal based on the signal fluctuation degree, obtaining a distribution characteristic value of the vector signal according to the fluctuation sequence corresponding to each vector signal, and obtaining a phase shift degree of the vector signal includes: Sort the signal fluctuation degrees from small to large, use the sorting results as the fluctuation sequence of the vector signal, and obtain the possibility of each signal being a segmentation point based on the differences between the signals in the fluctuation sequence; Select a split point based on the feasibility result, and use the split point to divide the vector signal into two parts: peak value and phase. Then, determine the distribution characteristic values ​​of the peak value and phase based on the distribution state of the vector signal. The distribution eigenvalue is used to obtain the offset part of the fluctuation sequence corresponding to each vector signal, and a reference sequence of the fluctuation sequence is generated according to the offset part. The phase offset degree of the vector signal is obtained by combining the interval corresponding to the fluctuation sequence.

10. A chip detection system for a semiconductor wafer surface, characterized in that: include: A positive sample database construction module is used to obtain electromagnetic feature vectors corresponding to defect-free semiconductor wafer surface chips using a feature extraction algorithm, and use the electromagnetic feature vectors as positive sample instruction signals to construct a positive sample database; The signal processing feature extraction module is used to scan the electromagnetic radiation signal of the chip on the surface of the semiconductor wafer to be tested using near-field probe technology, and after performing windowing and framing processing on the electromagnetic radiation signal, use the feature extraction algorithm to output the electromagnetic radiation signal to be matched; The electromagnetic state detection and matching module is used to upload the electromagnetic radiation signal to be matched to the positive sample database for regional interception processing, measure the distance between the interception result and any positive sample command signal in the positive sample database, and obtain the chip electromagnetic state detection result; The defect qualitative set generation module is used to process multiple forms of defects on the surface chip of a defect-free semiconductor wafer, simulate the chip impedance mismatch, and generate a reflection signal defect qualitative set based on the simulation results; The chip life prediction and judgment module is used to match the defects of the chip on the surface of the semiconductor wafer to be tested according to the qualitative set of defects in the reflected signal, and combine the defect results with the chip electromagnetic state detection results to predict the life of the chip on the surface of the semiconductor wafer to be tested.

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