Detection circuit and memory

Abstract

The invention relates to the technical field of semiconductors, and provides a detection circuit and a memory because a packaging substrate is easy to crack, the embodiment of the invention provides a detection circuit and a memory, and the detection circuit comprises a signal processing circuit and a detection line; the signal processing circuit is located in the chip, and the signal processing circuit is coupled to a detection output port and a result input port of the chip; the detection circuit is at least partially located in the packaging substrate, the detection circuit is a continuous loop, one end of the detection circuit is coupled to the detection output port, and the other end of the detection circuit is coupled to the result input port; a signal processing circuit configured to output a detection pulse signal to the detection output port; receiving a mark signal from the result input port, and generating a split mark signal based on the mark signal; the chip cracking mark signal indicates whether the packaging substrate is cracked or not. Therefore, countermeasures can be effectively taken according to the detection result, and safety risks in subsequent practical application are avoided.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a detection circuit and a memory. Background Art

[0002] With the rapid development of semiconductor technology, the size of semiconductor chips continues to shrink, and the thickness of semiconductor chips is also gradually decreasing. This trend makes it easier for semiconductor chips to crack during the manufacturing and packaging process, which not only affects the performance of semiconductor chips, but may also cause semiconductor chips to fail and reduce the yield of semiconductor chips. Summary of the invention

[0003] Embodiments of the present disclosure provide a detection circuit and a memory.

[0004] In a first aspect, an embodiment of the present disclosure provides a detection circuit, which is applied to an electronic device including a chip and a packaging substrate; the detection circuit includes a signal processing circuit and a detection circuit;

[0005] The signal processing circuit is located in the chip, and the signal processing circuit is coupled to the detection output port and the result input port of the chip;

[0006] The detection circuit is at least partially located inside the packaging substrate, the detection circuit is a continuous loop, one end of the detection circuit is coupled to the detection output port, and the other end of the detection circuit is coupled to the result input port;

[0007] The signal processing circuit is configured to output a detection pulse signal to the detection output port; and receive a flag signal from the result input port, and generate a crack flag signal based on the flag signal; the crack flag signal indicates whether the packaging substrate is cracked.

[0008] In some embodiments, the electronic device further comprises a printed circuit board, wherein the printed circuit board, the packaging substrate and the chip are stacked in sequence;

[0009] The detection circuit is alternately routed inside the printed circuit board and inside the packaging substrate, and passes through at least two non-enabled ball grids in the packaging substrate.

[0010] In some embodiments, the number of the detection circuits is 1 and the number of the signal processing circuits is 1;

[0011] In the case where one of the inactivated ball grids is distributed at each corner of the packaging substrate, the detection circuit passes through one of the inactivated ball grids in each corner in sequence;

[0012] When m unused ball grids are evenly distributed at the corners of the encapsulation substrate, the detection circuit sequentially passes through 1 to m of the unused ball grids in each of the corners; m is an integer greater than 0.

[0013] In some embodiments, the encapsulation substrate has 4 corners, and m unused ball grids are distributed at each of the corners, and the number of the detection circuits, the signal processing circuits, the detection output ports, and the result input ports is n;

[0014] The i-th detection circuit is respectively coupled to the i-th detection output port and the i-th result input port, and the i-th signal processing circuit is respectively coupled to the i-th detection output port and the i-th result input port;

[0015] The i-th detection circuit passes through at least 2 of the unused ball grids in the i-th corner; m is an integer greater than 0, n ≤ 4, and i ≤ n.

[0016] In some embodiments, the signal processing circuit includes: a first pulse generator and a latch circuit;

[0017] The first pulse generator is configured to receive a detection enable signal and output the detection pulse signal to the detection output port when the detection enable signal is in an enabled state;

[0018] The latch circuit is configured to, after receiving the flag signal, output the enabled die flag signal if the flag signal has a pulse; and output the disabled die flag signal if the flag signal does not have a pulse;

[0019] Wherein, the enabled die flag signal indicates that there is no crack in the encapsulation substrate, and the disabled die flag signal indicates that there is a crack.

[0020] In some embodiments, the latch circuit includes a first flip-flop and a first register;

[0021] The first flip-flop latches the high-level signal received at the input end based on the flag signal received at the clock terminal to output the die flag signal;

[0022] The first register receives and stores the die flag signal.

[0023] In some embodiments, the number of the detection circuits, the detection output ports, and the result input ports is 2, and the number of the signal processing circuits is 1; 3 unused ball grids are distributed at the corners of the encapsulation substrate;

[0024] The first detection circuit is respectively coupled to a first detection output port and a first result input port, and the first detection circuit sequentially passes through 1 unenabled ball grid out of the outermost ones among the four corners;

[0025] The second detection circuit is respectively coupled to a second detection output port and a second result input port, and the second detection circuit sequentially passes through at least 1 unenabled ball grid out of the inner ones among the four corners;

[0026] The first detection circuit surrounds the outside of the second detection circuit.

[0027] In some embodiments, the signal processing circuit includes a first processing circuit, a second processing circuit, and a logic output circuit, and the die separation flag signal includes a replacement flag signal and a repair flag signal;

[0028] The first processing circuit is configured to output a first detection pulse signal with pulses to the first detection output port when the detection enable signal is in an enabled state;

[0029] The second processing circuit is configured to output the second detection pulse signal with pulses to the second detection output port when the detection enable signal is in an enabled state and the first flag signal has no pulses;

[0030] The logic output circuit is configured to generate a disabled replacement flag signal and a disabled repair flag signal if both the first flag signal and the second flag signal have pulses; generate a disabled replacement flag signal and an enabled repair flag signal if the first flag signal has no pulses and the second flag signal has pulses; generate an enabled replacement flag signal and a disabled repair flag signal if both the first flag signal and the second flag signal have no pulses;

[0031] Wherein, the disabled replacement flag signal indicates that the area surrounded by the first detection circuit is not damaged, and the disabled repair flag signal indicates that the area surrounded by the second detection circuit is not damaged. In some embodiments, the first processing circuit includes a second pulse generator; the enable end of the second pulse generator receives the detection enable signal, and outputs the first detection pulse signal to the first detection output port when the detection enable signal is in an enabled state;

[0032] The second processing circuit includes an oscillator and a third pulse generator;

[0033] The oscillator is configured to receive the detection enable signal and the first flag signal, and the enabled first flag signal is used to control the oscillator to be disabled; when the detection enable signal is in the enabled state and the first flag signal has no pulse, an enabled first intermediate control signal is output; or, when the first detection enable signal is in the enabled state and the first flag signal has a pulse, the disabled first intermediate control signal is output;

[0034] The enable terminal of the third pulse generator receives the first intermediate control signal, and when the first intermediate control signal is in the enabled state, the second detection pulse signal is output to the second detection output port.

[0035] In some embodiments, the logic output circuit includes a second flip-flop, a third flip-flop, a NOT gate, and a NOR gate;

[0036] The second flip-flop latches the high-level signal received at the input terminal based on the first flag signal received at the clock terminal to output a second intermediate control signal;

[0037] The third flip-flop latches the high-level signal received at the input terminal based on the second flag signal received at the clock terminal to output a third intermediate control signal;

[0038] The NOT gate receives the third intermediate control signal and performs a NOT operation on the third intermediate control signal to output the replacement flag signal;

[0039] The NOR gate receives the second intermediate control signal and the replacement flag signal, and performs a NOR operation on the second intermediate control signal and the replacement flag signal to output the repair flag signal.

[0040] In some embodiments, the packaging substrate includes 4 corners, a first corner, a second corner, a third corner, and a fourth corner arranged in a clockwise order;

[0041] The chip includes 5 ports, and each port serves as the detection output port and / or the result input port;

[0042] Among them, the first port, the first corner, the second corner, the third corner, the fourth corner, and the fifth port are sequentially connected by a first connection line;

[0043] The third port is connected to the first connection line between the second corner and the third corner through a second connection line;

[0044] The second port is connected to the first connection line between the first corner and the second corner through a third connection line;

[0045] The fourth port is connected to the first connection line between the third corner and the fourth corner through a fourth connection line.

[0046] In some embodiments, the first connection line, the second connection line, the third connection line, and the fourth connection line form six detection lines;

[0047] The first detection line sequentially passes through the third port, at least one of the unactivated ball grids of the second corner, at least one of the unactivated ball grids of the first corner, and the first port;

[0048] The second detection line sequentially passes through the third port, at least one of the unactivated ball grids of the second corner, and the second port;

[0049] The third detection line sequentially passes through the third port, at least one of the unactivated ball grids of the third corner, at least one of the unactivated ball grids of the fourth corner, and the fifth port;

[0050] The fourth detection line sequentially passes through the third port, at least one of the unactivated ball grids of the third corner, and the fourth port;

[0051] The fifth detection line sequentially passes through the first port, at least one of the unactivated ball grids of the first corner, and the second port;

[0052] The sixth detection line sequentially passes through the fifth port, at least one of the unactivated ball grids of the fourth corner, and the fourth port.

[0053] In some embodiments, the signal processing circuit is configured to output a detection pulse signal to the third port; and receive a first flag signal from the first port, a second flag signal from the second port, a third flag signal from the fifth port, and a fourth flag signal from the fourth port;

[0054] Wherein, if there are pulses in all of the first flag signal to the fourth flag signal, the package substrate has no crack; if the first flag signal has no pulse and the second flag signal has a pulse, there is a crack in the area surrounded by the fifth detection line; if the third flag signal has no pulse and the fourth flag signal has a pulse, there is a crack in the area surrounded by the sixth detection line.

[0055] In some embodiments, when none of the first flag signal to the fourth flag signal has a pulse,

[0056] The signal processing circuit is further configured to output the detection pulse signal to the first port and the fifth port; and receive a fifth flag signal from the second port and a sixth flag signal from the fourth port;

[0057] If there is a pulse in the fifth flag signal, there is a break in the area surrounded by the second detection line; if there is a pulse in the sixth flag signal, there is a break in the area surrounded by the fourth detection line; if there is no pulse in both the fifth flag signal and the sixth flag signal, there is a break in the area surrounded by each detection line.

[0058] In a second aspect, an embodiment of the present disclosure provides a memory, which includes the detection circuit according to any one of the above embodiments.

[0059] An embodiment of the present disclosure provides a detection circuit and a memory. Since at least a part of the detection line is located inside the package substrate, and the detection line is a continuous loop, one end of the detection line is coupled to the detection output port, and the other end of the detection line is coupled to the result input port; thus, during detection, if the detection pulse signal can be output to the result input port through the detection line, the area surrounded by the detection line is intact; if the detection pulse signal cannot be output to the result input port through the detection line, it means that there is an open circuit in the detection line itself, and further indicates that the area surrounded by the detection line may or has already had a break, so that effective countermeasures can be taken to avoid safety risks in subsequent actual applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] Figure 1 is a schematic structural diagram of a detection circuit provided by an embodiment of the present disclosure;

[0061] Figure 2 is a schematic structural diagram of a detection line provided by an embodiment of the present disclosure Figure 1 ;

[0062] Figure 3 is a schematic structural diagram of a detection line provided by an embodiment of the present disclosure Figure 2 ;

[0063] Figure 4 is a schematic structural diagram of a detection line provided by an embodiment of the present disclosure Figure 3 ;

[0064] Figure 5 is a schematic structural diagram of a signal processing circuit provided by an embodiment of the present disclosure Figure 1 ;

[0065] Figure 6 is a schematic signal timing diagram of a detection circuit provided by an embodiment of the present disclosure;

[0066] Figure 7 Schematic diagram of the composition structure of a detection circuit provided by an embodiment of the present disclosure Figure 4 ;

[0067] Figure 8 Schematic diagram of the composition structure of a signal processing circuit provided by an embodiment of the present disclosure Figure 2 ;

[0068] Figure 9 Schematic diagram of the composition structure of a signal processing circuit provided by an embodiment of the present disclosure Figure 3 ;

[0069] Figure 10 Schematic diagram of the composition structure of a detection circuit provided by an embodiment of the present disclosure Figure 5 ;

[0070] Figure 11 Schematic diagram of the composition structure of a memory provided by an embodiment of the present disclosure. Detailed implementation manners

[0071] Next, the technical solutions in the embodiments of the present disclosure will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present disclosure. It can be understood that the specific embodiments described herein are only used to explain the relevant disclosure, rather than limiting the disclosure. In addition, it should be noted that for the convenience of description, only the parts related to the relevant disclosure are shown in the drawings.

[0072] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which this disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0073] In the following description, "some embodiments" are involved, which describe a subset of all possible embodiments. However, it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict.

[0074] It should be noted that the terms "first / second / third" involved in the embodiments of the present disclosure are only used to distinguish similar objects and do not represent a specific order for the objects. It can be understood that "first / second / third" can be interchanged with a specific order or sequence when allowed, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0075] At present, with the development of semiconductor processes, the number of internal packages in semiconductor chips is increasing, and semiconductor chips are becoming thinner and thinner. As a result, semiconductor chips are prone to cracks during the manufacturing process, seriously affecting the chip yield. Therefore, it is necessary to detect cracks in semiconductor chips. In addition, if there are cracks at the unactivated ball grids at the corners of the semiconductor chip, it indicates that there may currently be or may subsequently be problems with poor connection or signal transmission interruption in the internal circuit of the chip, which in turn affects the normal operation of the device. Therefore, the automotive market recommends detecting cracks (callcrack) in the unactivated ball grids at the four corners of the package substrate.

[0076] Based on this, embodiments of the present disclosure provide a detection circuit and a memory. The detection circuit is applied to an electronic device including a chip and a package substrate. The detection circuit includes a signal processing circuit and a detection line. The signal processing circuit is located in the chip and is coupled to the detection output port and the result input port of the chip. At least part of the detection line is located in the package substrate. The detection line is a continuous loop. One end of the detection line is coupled to the detection output port, and the other end of the detection line is coupled to the result input port. The signal processing circuit is configured to output a detection pulse signal to the detection output port, and receive a flag signal from the result input port and generate a chip breakage flag signal based on the flag signal. The chip breakage flag signal indicates whether the package substrate is broken. Since at least part of the detection line is located inside the package substrate and the detection line is a continuous loop, one end of the detection line is coupled to the detection output port, and the other end of the detection line is coupled to the result input port. In this way, during detection, if the detection pulse signal can be output to the result input port through the detection line, the area surrounded by the detection line is intact. If the detection pulse signal cannot be output to the result input port through the detection line, it means that there is a break in the detection line itself, indicating that there may be or already be a break in the area surrounded by the detection line, so that effective countermeasures can be taken to avoid safety risks in subsequent actual applications.

[0077] The following will describe each embodiment of the present disclosure in detail with reference to the accompanying drawings.

[0078] In one embodiment of the present disclosure, refer to Figure 1 , which shows a detection circuit. The detection circuit is applied to an electronic device 10 including a chip 11 and a package substrate 12. The detection circuit includes a signal processing circuit ( Figure 1not shown) and a detection circuit 120; the signal processing circuit is located in the chip 11, and the signal processing circuit is coupled to the detection output port 130 and the result input port 140 of the chip 11; at least a part of the detection circuit 120 is located inside the packaging substrate 12, the detection circuit 120 is a continuous loop, one end of the detection circuit 120 is coupled to the detection output port 130, and the other end of the detection circuit 120 is coupled to the result input port 140; the signal processing circuit is configured to output a detection pulse signal to the detection output port 130; and receive a flag signal from the result input port 140, and generate a die break flag signal based on the flag signal; the die break flag signal indicates whether the packaging substrate 12 is broken.

[0079] Figure 1 In the figure, a part of the detection circuit 120 located inside (relative to the surface) is marked with a dotted line. Since the detection circuit 120 usually surrounds the outside of the chip 11, and the crack usually extends from the outside to the inside. Therefore, when the chip is broken, the detection circuit 120 surrounding the chip 11 and inside the packaging substrate 12 usually also has an open circuit. In other words, it is possible to determine whether the chip has a risk of damage or malfunction by detecting whether the detection circuit 120 on the periphery is open (if it is open, it is considered that a crack has occurred). If there is a risk, a warning needs to be given in advance to avoid safety risks in actual applications.

[0080] In the embodiments of the present disclosure, the chip 11 may include a DRAM chip or other types of chips. Among them, for a DRAM chip, it can not only conform to memory specifications such as DDR, DDR2, DDR3, DDR4, DDR5, DDR6, etc., but also conform to memory specifications such as LPDDR, LPDDR2, LPDDR3, LPDDR4, LPDDR5, LPDDR6, etc. No specific limitation is made here.

[0081] In some embodiments, the electronic device 10 further includes a printed circuit board 13, and the printed circuit board 13, the packaging substrate 12, and the chip 11 are stacked in sequence; and the detection circuit alternates between the inside of the printed circuit board and the inside of the packaging substrate. For example, please continue to refer to Figure 1 , after the detection circuit 120 is coupled out from the detection output port 130, it alternately runs inside the packaging substrate 12 (as shown by the short dotted line in the figure) - inside the printed circuit board 13 (as shown by the long dotted line in the figure) in sequence, and finally is coupled to the result input port 140; in this way, it can be ensured that the detection circuit 120 can detect whether the connection between the printed circuit board 13 and the packaging substrate 12 is stable, and whether there is an open circuit between the printed circuit board 13 and the packaging substrate 12 due to the presence of cracks, so that the detection accuracy and reliability are relatively high.

[0082] In the embodiments of the present disclosure, one end of the detection line 120 is coupled to the detection output port 130: This means that one end of the detection line 120 can be directly connected to the detection output port 130 or indirectly connected. That is, "coupled" includes two ways: direct connection or indirect connection. For the "coupled" mentioned in the subsequent specification, the above explanation can be referred to for understanding. For example, please continue to refer to Figure 1 , one end of the detection line 120 is coupled to the detection output port 130, which means that one end of the detection line 120 is connected to the first intermediate port 131a, and the first intermediate port 131a is connected to the detection output port 130 through a bonding wire; similarly, the other end of the detection line 120 is coupled to the result input port 140, which means that the other end of the detection line 120 is connected to the second intermediate port 141a, and the second intermediate port 141a is connected to the result input port 140 through a bonding wire.

[0083] In addition, the detection line 120 being a continuous loop means that the detection line 120 is a continuous non-closed loop (as Figure 1 shown) or a closed loop; for example, when the detection output port and the result input port are the same port, the detection line 120 is a closed loop.

[0084] In the embodiments of the present disclosure, since at least a part of the detection line 120 is located in the package substrate, and the detection line 120 is a continuous loop, one end of the detection line 120 is coupled to the detection output port 130, and the other end of the detection line is coupled to the result input port 140; thus, during detection, if the detection pulse signal can be output through the detection line 120 to the result input port 140, the area surrounded by the detection line 120 is intact, so the flag signal is the same as the detection pulse signal, and the chip breakage flag signal generated by the signal processing circuit based on the flag signal indicates that the chip is not damaged; if the detection pulse signal cannot be output through the detection line to the result input port 140, there is a break in the area surrounded by the detection line 120, so the flag signal is a low-level signal, and the chip breakage flag signal generated by the signal processing circuit based on the received flag signal indicates that the chip is damaged; in this way, early warning can be provided to avoid safety risks in subsequent actual applications. It should be noted that the chip being damaged includes both the chip function itself being damaged and the signal transmission path between the package substrate and the printed circuit board being disconnected.

[0085] Next, the composition structure of the detection circuit in the embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0086] In some embodiments, the detection line 120 passes through at least two unused ball grids 150 in the package substrate 12.

[0087] In the embodiments of the present disclosure, a disabled ball grid 150 refers to a bump that is electrically connected to the printed circuit board 13 and the package substrate 12 but does not participate in signal transmission. Controlling the electrical connection between the disabled ball grid 150 and the printed circuit board 13 can strengthen the connection strength between the package substrate 12 and the printed circuit board 13, and increase the stability and reliability between the package substrate 12 and the printed circuit board 13.

[0088] It should be noted that the reason why the detection line 120 passes through at least 2 disabled ball grids 150 is as follows: The simplest detection line 120 is routed inside the package substrate 12 - inside the printed circuit board 13 - inside the package substrate 12. At this time, the number of disabled ball grids 150 passed through is 2. In this way, the minimum requirement for crack detection of the disabled ball grid 150 can be met. If only the disabled ball grid 150 at a single corner is detected, the probability of inaccurate detection results is relatively high.

[0089] In the embodiments of the present disclosure, the package substrate 12 includes 4 corners, namely the first corner A, the second corner B, the third corner C, and the fourth corner D, which are arranged in a clockwise order; for the chip 11 that conforms to the LPDDR4 memory specification, there is one disabled ball grid 150 corresponding to each of the four corners of the package substrate 12 (please refer to Figure 2 ); for the chip 11 that conforms to the LPDDR5 memory specification, there are three disabled ball grids 150 at each of the four corners of the package substrate 12 (please refer to Figure 3 ).

[0090] In the embodiments of the present disclosure, since the detection line 120 passes through at least 2 disabled ball grids 150, the connection performance of the disabled ball grid 150 can be detected. For example, when cracking occurs at the corner of the electronic device, resulting in poor connection of the disabled ball grid 150, the detection circuit can meet the detection requirements for the connection performance of the disabled ball grid 150, and the detection method is simple and the detection efficiency is relatively high.

[0091] Next, the detection line 120 provided by the present disclosure will be introduced in detail according to specific embodiments.

[0092] In some embodiments, the number of detection lines 120 is 1 and the number of signal processing circuits ( Figure 2 not shown in the figure) is 1; when there is 1 disabled ball grid 150 distributed at each corner of the package substrate 12, the detection line 120 sequentially passes through 1 disabled ball grid 150 in each corner.

[0093] For example, please refer to Figure 2, first, the detection output port 130 on the chip 11 is connected to the package substrate 12 through a connecting wire (shown as the short solid line in the figure); then, the detection line 120 successively routes inside the package substrate 12 (shown as the short dashed line in the figure) and is connected to the unactivated ball grid 150 at the first corner A, routes inside the printed circuit board 13 (shown as the long dashed line in the figure) and is connected to the unactivated ball grid 150 at the second corner B, routes inside the package substrate 12 and is connected to the unactivated ball grid 150 at the third corner C, and routes inside the printed circuit board 13 and is connected to the unactivated ball grid 150 at the fourth corner D; finally, after routing inside the package substrate 12, it is connected to the result input port 140 through a connecting wire. That is to say, the detection line 120 extends from the detection output port 130, alternately routes inside the package substrate 12 and the printed circuit board 13, and after passing through the unactivated ball grids 150 at the four corners of the package substrate 12, forms a non-closed loop and then returns to the result input port 140.

[0094] It should be noted that Figures 2 to 4 、 Figure 7 and Figure 10 do not show the first intermediate port 131a and the second intermediate port 141a on the surfaces of the chip 11 and the package substrate 12. For the connection positions of the chip 11 and the connecting wire, please refer to Figure 1 for understanding and will not be elaborated here.

[0095] In some embodiments, the number of detection lines 120 is 1 and the number of signal processing circuits is 1; when m unactivated ball grids 150 are evenly distributed at the corners of the package substrate 12, the detection line 120 successively passes through 1 to m unactivated ball grids 150 in each corner; m is an integer greater than 0.

[0096] For example, please refer to Figure 3, taking the example that 3 unactivated ball grids 150 are evenly distributed at the four corners of the packaging substrate 12, and the detection line 120 passes through 2 unactivated ball grids 150 in each corner in sequence. First, the detection output port 130 on the chip 11 is connected to the packaging substrate 12 through a connecting wire (shown as a short solid line in the figure); then, the detection line 120 sequentially routes inside the packaging substrate 12 (shown as a short dashed line in the figure) and is connected to an unactivated ball grid 150 at the first corner A, and routes inside the printed circuit board 13 (shown as a long dashed line in the figure) and is connected to another unactivated ball grid 150 at the first corner A. In this way, the detection line 120 is alternately arranged inside the packaging substrate 12 and the printed circuit board 13; finally, after routing inside the packaging substrate 12, it is connected to the result input port 140 through a connecting wire. That is to say, the detection line 120 comes out from the detection output port 130, sequentially routes inside the packaging substrate 12 and the printed circuit board 13, and after passing through 2 unactivated ball grids 150 in each corner of the packaging substrate 12, forms a loop and then returns to the result input port 140.

[0097] It should be noted that the number of unactivated ball grids 150 connected by the detection line 120 when passing through each corner can be equal (as Figure 3 shown), or can be unequal; for example, the detection line 120 can sequentially pass through 1 unactivated ball grid 150 at the first corner A, 2 unactivated ball grids 150 at the second corner B, 1 unactivated ball grid 150 at the third corner C, and 3 unactivated ball grids 150 at the fourth corner D.

[0098] In the embodiment of the present disclosure, since the detection line 120 not only routes inside the packaging substrate 12 and the printed circuit board 13, but also passes through the unactivated ball grids 150 at the corners of the packaging substrate 12, the detection circuit can not only detect cracks on the packaging substrate 12 and the printed circuit board 13, but also meet the detection requirements for the unactivated ball grids 150 at the same time. In this way, not only can cracks on the chip be detected, but also the detection requirements for the unactivated ball grids 150 at the corners in the automotive market can be met, thereby expanding the detection range of the detection circuit and providing more comprehensive guarantee for the stability and reliability of the electronic device 10.

[0099] In some embodiments, the encapsulation substrate 12 has four corners, and m unused ball grids 150 are distributed at each corner. The number of detection lines 120, signal processing circuits, detection output ports 130, and result input ports 140 is n. The i-th detection line 120 is respectively coupled to the i-th detection output port 130 and the i-th result input port 140, and the i-th signal processing circuit is respectively coupled to the i-th detection output port 130 and the i-th result input port 140. The i-th detection line 120 passes through at least two unused ball grids 150 in the i-th corner. m is an integer greater than 0, n ≤ 4, and i ≤ n.

[0100] For example, please refer to Figure 4 , three unused ball grids 150 are distributed at each of the four corners of the encapsulation substrate 12, and the number of detection lines 120, signal processing circuits, detection output ports 130, and result input ports 140 is 4. Specifically, taking the detection line 120 passing through the second corner B as an example, first, the detection output port 130 on the chip 11 is connected to the encapsulation substrate 12 through a connecting wire. Then, the detection line 120 sequentially routes inside the encapsulation substrate 12 (as shown by the short dashed line in the figure) and is connected to an unused ball grid 150 on the second corner B, and routes inside the printed circuit board 13 (as shown by the long dashed line in the figure) and is connected to another unused ball grid 150 on the second corner B. Finally, after routing inside the encapsulation substrate 12, it is connected to the result input port 140 through a connecting wire. That is to say, the detection line 120 comes out from the detection output port 130, sequentially routes inside the encapsulation substrate 12 and the printed circuit board 13, and after passing through two unused ball grids 150 on the second corner B, forms a loop and returns to the result input port 140. Additionally, please continue to refer to Figure 4 , the detection lines 120 passing through the first corner A, the third corner C, and the fourth corner D are similar to the detection line 120 passing through the second corner B, and will not be elaborated here.

[0101] In the embodiments of the present disclosure, since the four detection lines 120 are respectively connected to the unused ball grids 150 on the four corners, the connection effectiveness of the unused ball grids 150 connected to each corner can be accurately detected. In this way, the stability and reliability of the electronic device 10 can be ensured. Further, through the detection of the unused ball grids 150, problems such as possible poor connection or signal interruption in the internal circuit of the chip can be timely discovered, and corresponding maintenance measures can be effectively taken.

[0102] In some embodiments, please refer to Figure 5 , as above Figures 2 to 4The signal processing circuit 110 connected to the detection circuit 120 therein includes: a first pulse generator 111 and a latch circuit 112; the first pulse generator 111 is configured to receive a detection enable signal CrackEn, and when the detection enable signal is in an enabled state, output a detection pulse signal Crackout to the detection output port 130 ( Figure 5 not shown in, please refer to Figures 1 to 4 for understanding); the latch circuit 112 is configured to, after receiving a flag signal CrackIn, if the flag signal CrackIn has a pulse, output an enabled chip fracture flag signal Crackflag; if the flag signal CrackIn does not have a pulse, output a disabled chip fracture flag signal CrackFlag; wherein, the enabled chip fracture flag signal CrackFlag indicates that the packaging substrate 12 has no cracks, and the disabled chip fracture flag signal CrackFlag indicates that the packaging substrate 12 has cracks.

[0103] In an embodiment of the present disclosure, when detection is required, the chip 11 (such as a system-on-chip SOC) writes a detection enable signal of a specific chip (such as the chip corresponding to the low byte of CHANNEL A of RANK0) through a Mode Register Write (MRW) command. When the detection enable signal CrackEn changes from a low level state to a high level state, a detection pulse signal CrackOut is generated by the first pulse generator 111. The detection pulse signal CrackOut can be a high level pulse signal; the detection pulse signal CrackOut is output from the detection output port 130. After the detection pulse signal CrackOut is transmitted through the detection circuit 120 on the packaging substrate 12, a flag signal CrackIn is generated and input to the result input port 140. When there is no fracture phenomenon on the packaging substrate 12, the flag signal CrackIn is a high level pulse signal, and the latch circuit 112 will latch the received flag signal CrackIn as a high level, and the chip fracture flag signal CrackFlag becomes logic 1 (i.e., the chip fracture flag signal Crackflag without fracture phenomenon); when there is a fracture phenomenon on the packaging substrate 12, the flag signal CrackIn is a low level, and the chip fracture flag signal CrackFlag remains logic 0 (i.e., the disabled chip fracture flag signal).

[0104] In an embodiment of the present disclosure, please continue to refer to Figure 5, the signal processing circuit 110 further includes: a first driver 113; the input end of the first driver 113 is connected to the output end of the first pulse generator 111, and the output end of the first driver 113 is connected to the detection output port 130. The first driver 113 is used to amplify the detection pulse signal CrackOut to ensure the integrity and accuracy of the signal, so that the subsequent circuit can correctly identify and process the detection pulse signal CrackOut, and improve the stability and reliability of the detection circuit.

[0105] In some embodiments, refer to Figure 5 and Figure 6 , the latch circuit 112 includes a first flip-flop 112a; the reset terminal of the first flip-flop 112a receives the reset signal CheckEn. When the reset signal CheckEn is valid (i.e., logic 1), the first flip-flop 112a is reset, so that the output terminal of the first flip-flop 112a outputs a low potential, that is Figure 6 the first crack flag signal Crackflag first jumps from high level to low level; the first flip-flop 112a latches the high-level signal Vcc received at the input terminal based on the flag signal received at the clock terminal to output the crack flag signal. In this way, the crack flag signal can be directly sent out through the pad (pad), and whether the package substrate 12 is cracked can be directly judged according to the logic value transmitted by the pad.

[0106] In some embodiments, the latch circuit 112 further includes a first register 112b, and the first register 112b is used to receive and store the crack flag signal. In this way, when the crack flag signal is transmitted and stored in the first register 112b, the chip 11 can judge whether the package substrate 12 is cracked by reading the MRR value, so that the state of the package substrate 12 can be obtained in time when needed, and the response speed of the detection can be improved, and the requirements of multiple application scenarios can be better met.

[0107] In some embodiments, the number of the detection lines 120, the detection output ports 130 and the result input ports 140 is 2 each, and the number of the signal processing circuits (please refer to Figure 8 ) is 1; at least two unused ball grids 150 are distributed at the corners of the package substrate 12; the first detection line 120a is respectively coupled to the first detection output port 130a and the first result input port 140a, and the first detection line 120a sequentially passes through at least 1 unused ball grid 150 at the outermost side of the four corners; the second detection line 120b is respectively coupled to the second detection output port 130b and the second result input port 140b, and the second detection line 120b sequentially passes through at least 1 unused ball grid 150 at the inner side of the four corners; the first detection line 120a surrounds the outside of the second detection line 120b.

[0108] Here, the first detection line 120a and the second detection line 120b both belong to the detection line 120.

[0109] For example, please refer to Figure 7 , three unused ball grids 150 are evenly distributed at the corners of the package substrate 12; the first detection line 120a is connected from the first detection output port 130a to the package substrate 12 through a connection wire (shown as a short solid line in the figure); then, the first detection line 120a sequentially routes inside the package substrate 12 (shown as a short dashed line in the figure) to the outermost unused ball grid 150 on the first corner A, routes inside the printed circuit board 13 (shown as a long dashed line in the figure) to the outermost unused ball grid 150 on the second corner B, routes inside the package substrate 12 to the outermost unused ball grid 150 on the third corner C, and routes inside the printed circuit board 13 to the outermost unused ball grid 150 on the fourth corner D; finally, after routing inside the package substrate 12, it is connected to the first result input port 140a through a connection wire. That is to say, the first detection line 120a is connected from the first detection output port 130a, sequentially routes inside the package substrate 12 and the printed circuit board 13, and after passing through the outermost 1 unused ball grid 150 among the four corners in sequence, forms a non-closed loop and then returns to the first result input port 140a.

[0110] The second detection line 120b is connected from the second detection output port 130b to the package substrate 12 through a connection wire (shown as a short solid line in the figure); then, the second detection line 120b sequentially routes inside the package substrate 12 (shown as a short dashed line in the figure) to an unused ball grid 150 inside the first corner A, and routes inside the printed circuit board 13 (shown as a long dashed line in the figure) to another unused ball grid 150 inside the first corner A. In this way, the second detection line 120b is alternately arranged inside the package substrate 12 and the printed circuit board 13; finally, after routing inside the package substrate 12, it is connected to the second result input port 140b through a connection wire. That is to say, the second detection line 120b is connected from the second detection output port 130b, sequentially routes alternately inside the package substrate 12 and the printed circuit board 13, and after passing through at least 1 unused ball grid 150 inside the four corners in sequence, forms a non-closed loop and then returns to the second result input port 140b. The first detection line 120a surrounds the outside of the second detection line 120b.

[0111] In this way, the outer ring of the electronic device can be detected through the first detection circuit 120a. If there is no open circuit in the first detection circuit 120a, it indicates that the electronic device is intact. At this time, the detection can stop and continue to detect the inner ring. If there is an open circuit in the first detection circuit 120a, the inner ring of the electronic device is continuously detected through the second detection circuit 120b. If the inner ring is not broken, it indicates that the electronic device can still be used and can be repaired. If the inner ring is broken, it indicates that the electronic device is severely damaged. In this way, not only can the detection efficiency and accuracy be improved, but also unnecessary detection or operations on the already damaged electronic device can be avoided, reducing the test cost. At the same time, the electronic device that can be repaired is repaired to avoid waste.

[0112] In some embodiments, please refer to Figure 8 and Figure 9 , the signal processing circuit 110 connected to the detection circuit 120 in the above Figure 7 includes a first processing circuit 114, a second processing circuit 115, and a logic output circuit 116. The die separation flag signal includes a replacement flag signal and a repair flag signal. The first processing circuit 114 is configured to output a first detection pulse signal with pulses to the first detection output port 130a when the detection enable signal is in the enabled state. The second processing circuit 115 is configured to output a second detection pulse signal with pulses to the second detection output port 130b when the detection enable signal is in the enabled state and the first flag signal has no pulses. The logic output circuit 116 is configured to generate a disabled replacement flag signal and a disabled repair flag signal if both the first flag signal and the second flag signal have pulses (at this time, the second flag signal is equal to the first flag signal and the second flag signal is not independently generated); generate a disabled replacement flag signal and an enabled repair flag signal if the first flag signal has no pulses and the second flag signal has pulses; generate an enabled replacement flag signal and a disabled repair flag signal if both the first flag signal and the second flag signal have no pulses. Among them, the disabled replacement flag signal indicates that the area surrounded by the first detection circuit is not damaged, and the disabled repair flag signal indicates that the area surrounded by the second detection circuit is not damaged.

[0113] In the embodiments of the present disclosure, the disabled replacement flag signal and the disabled repair flag signal together indicate that the packaging substrate 12 has no breakage; the disabled replacement flag signal and the enabled repair flag signal together indicate that the packaging substrate 12 has local breakage (i.e., the outer ring has breakage) and has repair value; the enabled replacement flag signal and the disabled repair flag signal together indicate that the packaging substrate has breakage and has no repair value.

[0114] In some embodiments, the first processing circuit 114 includes a second pulse generator 114a; an enabling terminal of the second pulse generator 114a receives a detection enabling signal, and when the detection enabling signal is in an enabled state, a first detection pulse signal is output to the first detection output port 130a; the second processing circuit 115 includes an oscillator 115a and a third pulse generator 115b; the oscillator 115a is configured to receive the detection enabling signal and a first flag signal, and the enabled first flag signal is used to control the oscillator 115a to be disabled; when the detection enabling signal is in an enabled state and the first flag signal has no pulse, an enabled first intermediate control signal is output; alternatively, when the first detection enabling signal is in an enabled state and the first flag signal has a pulse, a disabled first intermediate control signal is output; an enabling terminal of the third pulse generator 115b receives the first intermediate control signal, and when the first intermediate control signal is in an enabled state, a second detection pulse signal is output to the second detection output port 130b.

[0115] In the embodiments of the present disclosure, the first processing circuit 114 further includes a second driver 114b, an input end of the second driver 114b is connected to an output end of the second pulse generator 114a, and an output end of the second driver 114b is connected to the first detection output port 130a; the second processing circuit 115 further includes a third driver 115c, an input end of the third driver 115c is connected to an output end of the third pulse generator 115b, and an output end of the third driver 115c is connected to the second detection output port 130b. In the embodiments of the present disclosure, the second driver 114b and the third driver 115c are used to respectively amplify the first detection enabling signal and the second detection enabling signal to ensure the integrity and accuracy of the signals, so that subsequent circuits can correctly identify and process the detection pulse signals, and the stability and reliability of the detection circuit are improved.

[0116] It should be noted that Figure 8 in, when the first detection line does not fail, both the first flag signal and the first detection pulse signal are pulse signals. At this time, the oscillator 115a is disabled, but the first flag signal can be unidirectionally transmitted to the line where the second flag signal is located, so that the second flag signal can be equal to the first flag signal, but the second flag signal will not affect the first flag signal. That is to say, as long as the first flag signal is a pulse signal, even if the oscillator 115a is disabled, the second flag signal is still a pulse signal. However, if the first flag signal is at a low level, the oscillator 115a is enabled, so that the second flag signal is a pulse signal, and the first flag signal will not change following the second flag signal, but will continue to be at a low level.

[0117] In some embodiments, the logic output circuit 116 includes a second flip-flop 116a, a third flip-flop 116b, a NOT gate 116c, and a NOR gate 116d; the reset terminal of the second flip-flop 116a receives a first reset signal, and when the first reset signal is valid (i.e., logic 1), the second flip-flop 116a is reset. The second flip-flop 116a latches the high-level signal received at the input terminal based on the first flag signal received at the clock terminal to output a second intermediate control signal. The reset terminal of the third flip-flop 116b receives a second reset signal, and when the second reset signal is valid (i.e., logic 1), the third flip-flop 116b is reset. The third flip-flop 116b latches the high-level signal received at the input terminal based on the second flag signal received at the clock terminal to output a third intermediate control signal; the NOT gate 116c receives the third intermediate control signal and performs a NOT operation on the third intermediate control signal to output a replacement flag signal; the NOR gate 116d receives the second intermediate control signal and the replacement flag signal, and performs a NOR operation on the second intermediate control signal and the replacement flag signal to output a repair flag signal.

[0118] In this way, the problem location of the packaging substrate 12 can be directly and accurately indicated according to the replacement flag signal and the repair flag signal, and the part that needs to be repaired or replaced can be found more quickly, thereby improving the repair efficiency and reducing the detection cost.

[0119] In some embodiments, please refer to Figure 10 , the chip 11 includes 5 ports, namely a first port 161, a second port 162, a third port 163, a fourth port 164, and a fifth port 165; each port is used as a detection output port and / or a result input port; wherein, the first port 161, the first corner A, the second corner B, the third corner C, the fourth corner D, and the fifth port 165 are sequentially connected through a first connection line 171; the third port 163 is connected to the first connection line 171 between the second corner B and the third corner C through a second connection line 172; the second port 162 is connected to the first connection line 171 between the first corner A and the second corner B through a third connection line 173; the fourth port 164 is connected to the first connection line 171 between the third corner C and the fourth corner D through a fourth connection line 174.

[0120] It should be noted that the connection of the first corner A through the first connection line 171 specifically means that at least one (for example, 1, 2, 3, etc.) of the unactivated ball grids 150 in the first corner A are connected through the first connection line 171; for example, as Figure 10 shown, 2 unactivated ball grids 150 in the first corner A are connected through the first connection line 171. The connection methods of the remaining corners are similar to that of the first corner A and will not be elaborated here.

[0121] In some embodiments, taking the case where seven detection lines are formed by a first connection line 171, a second connection line 172, a third connection line 173, and a fourth connection line 174 as an example for illustration; the first detection line sequentially passes through a third port 163, at least one unactivated ball grid 150 of a second corner B, at least one unactivated ball grid 150 of a first corner A, and a first port 161; the second detection line sequentially passes through the third port 163, at least one unactivated ball grid 150 of the second corner B, and a second port 162; the third detection line sequentially passes through the third port 163, at least one unactivated ball grid 150 of a third corner C, at least one unactivated ball grid 150 of a fourth corner D, and a fifth port 165; the fourth detection line sequentially passes through the third port 163, at least one unactivated ball grid 150 of the third corner C, and a fourth port 164; the fifth detection line sequentially passes through the first port 161, at least one unactivated ball grid 150 of the first corner A, and the second port 162; the sixth detection line sequentially passes through the fifth port 165, at least one unactivated ball grid 150 of the fourth corner D, and the fourth port 164. In other embodiments, a seventh detection line is further included, and the seventh detection line sequentially passes through the first port 161, at least one unactivated ball grid of the first corner A, at least one unactivated ball grid of the second corner B, at least one unactivated ball grid of the third corner B, at least one unactivated ball grid of the fourth corner D, and the fifth port 165.

[0122] In some embodiments, a signal processing circuit 110 is configured to output a detection pulse signal to the third port 163; and receive a first flag signal from the first port 161, a second flag signal from the second port 162, a third flag signal from the fifth port 165, and a fourth flag signal from the fourth port 164; wherein, if pulses exist in all of the first flag signal to the fourth flag signal, the packaging substrate 12 is not cracked; if the first flag signal has no pulse and the second flag signal has a pulse, it indicates that the first corner A is cracked; if the third flag signal has no pulse and the fourth flag signal has a pulse, it indicates that the fourth corner D is cracked.

[0123] That is to say, the third port 163 is used as a detection output port, and the first port 161, the second port 162, the fourth port 164, and the fifth port 165 are used as result input ports to detect the packaging substrate 12; in this way, the detection lines can be shared, the number of detection ports (i.e., solder pads) can be reduced, and the damaged position can be detected only through the detection circuit.

[0124] In some embodiments, when there are no pulses in the first to fourth flag signals, the signal processing circuit 110 is further configured to output a detection pulse signal to the first port 161 and the fifth port 165; and receive a fifth flag signal from the second port 162 and a sixth flag signal from the fourth port 164; if there is a pulse in the fifth flag signal, it indicates that the second corner B is cracked; if there is a pulse in the sixth flag signal, the third corner C is cracked; if there are no pulses in both the fifth flag signal and the sixth flag signal, there is a crack in the area surrounded by each detection line.

[0125] That is to say, the first port 161 and the fifth port 165 are used as detection output ports, and the second port 162 and the fifth port 165 are used as result input ports to detect the packaging substrate 12; in this way, by adjusting each port as a detection output port or a result input port, the detection area can be flexibly controlled, not only can the damaged position be determined more accurately, but also the flexibility of detection is increased, the detection lines are reduced, and thus the detection cost is reduced.

[0126] It should be noted that in the embodiments of the present disclosure, only some typical compositions of the detection line and the signal processing circuit are exemplarily listed, and the structures of the detection line and the signal processing circuit in the embodiments of the present disclosure are not limited thereto, and will not be listed one by one here.

[0127] In addition, please refer to Figure 11 , which shows a schematic diagram of the composition structure of a memory 20 provided by the embodiments of the present disclosure. As Figure 11 shown, the memory 20 includes any one of the detection circuits 100 in the foregoing embodiments.

[0128] In the embodiments of the present disclosure, for the memory 20, it can be, for example, a static random access memory (SRAM), a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate synchronous dynamic random access memory (DDR SDRAM), etc., and no specific limitation is made here.

[0129] It should be noted that the electronic device 10 in the above embodiments can be the memory 20 in the embodiments of the present disclosure.

[0130] In the embodiments of the present disclosure, for the memory 20, since it includes any of the detection circuits in the foregoing embodiments, the detection operation of the memory can be realized, so that corresponding measures can be effectively taken to avoid security risks in subsequent actual applications.

[0131] The above are only the preferred embodiments of the present disclosure and are not intended to limit the protection scope of the present disclosure.

[0132] It should be noted that in the present disclosure, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including a..." does not exclude the existence of additional identical elements in the process, method, article or device including the element.

[0133] The serial numbers of the embodiments of the present disclosure above are only for description and do not represent the superiority or inferiority of the embodiments.

[0134] The methods disclosed in several method embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0135] The features disclosed in several product embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

[0136] The features disclosed in several method or device embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0137] The above are only the specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should be covered by the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A detection circuit, characterized in that, Applied to an electronic device including a chip and a package substrate; the detection circuit includes a signal processing circuit and a detection line; The signal processing circuit is located in the chip, and the signal processing circuit is coupled to the detection output port and the result input port of the chip; At least a part of the detection line is located inside the package substrate. The detection line is a continuous loop. One end of the detection line is coupled to the detection output port, and the other end of the detection line is coupled to the result input port; The signal processing circuit is configured to output a detection pulse signal to the detection output port; And receive a flag signal from the result input port and generate a die separation flag signal based on the flag signal; The die separation flag signal indicates whether the package substrate is cracked.

2. The circuit according to claim 1, wherein The electronic device further includes a printed circuit board, and the printed circuit board, the package substrate and the chip are stacked in sequence; The detection line alternates in the interior of the printed circuit board and the interior of the package substrate and passes through at least two unused ball grids in the package substrate.

3. The circuit according to claim 2, wherein The number of the detection lines is 1 and the number of the signal processing circuits is 1; When one unused ball grid is evenly distributed at each corner of the package substrate, the detection line sequentially passes through one unused ball grid in each corner; When m unused ball grids are evenly distributed at each corner of the package substrate, the detection line sequentially passes through 1 to m unused ball grids in each corner; m is an integer greater than 0.

4. The circuit according to claim 2, wherein The package substrate has 4 corners, and m unused ball grids are evenly distributed at each corner. The number of the detection lines, the signal processing circuits, the detection output ports and the result input ports is all n; The i-th detection line is respectively coupled to the i-th detection output port and the i-th result input port, and the i-th signal processing circuit is respectively coupled to the i-th detection output port and the i-th result input port; The i-th detection line passes through at least two unused ball grids in the i-th corner; m is an integer greater than 0, n ≤ 4, i ≤ n.

5. The circuit according to any one of claims 2 to 4, characterized in that, The signal processing circuit includes: a first pulse generator and a latch circuit; The first pulse generator is configured to receive a detection enable signal and output the detection pulse signal to the detection output port when the detection enable signal is in an enabled state; The latch circuit is configured to, after receiving the flag signal, if the flag signal has a pulse, output the enabled die separation flag signal; if the flag signal does not have a pulse, output the disabled die separation flag signal; Wherein, the enabled die separation flag signal indicates that there is no crack in the package substrate, and the disabled die separation flag signal indicates that there is a crack.

6. The circuit according to claim 5, wherein The latch circuit includes a first flip-flop and a first register; The first flip-flop latches the high-level signal received at the input end based on the flag signal received at the clock terminal to output the die separation flag signal; The first register receives and stores the die flag signal.

7. The circuit according to claim 2, characterized in that, The number of the detection lines, the detection output ports, and the result input ports is 2 each, and the number of the signal processing circuits is 1; three unused ball grids are distributed at the corners of the packaging substrate. The first detection line is respectively coupled to the first detection output port and the first result input port, and the first detection line sequentially passes through one of the outermost unused ball grids among the four corners. The second detection line is respectively coupled to the second detection output port and the second result input port, and the second detection line sequentially passes through at least one of the inner unused ball grids among the four corners. The first detection line surrounds the outside of the second detection line.

8. The circuit according to claim 7, wherein, The signal processing circuit includes a first processing circuit, a second processing circuit, and a logic output circuit, and the die flag signal includes a replacement flag signal and a repair flag signal. The first processing circuit is configured to output a first detection pulse signal with pulses to the first detection output port when the detection enable signal is in the enabled state. The second processing circuit is configured to output the second detection pulse signal with pulses to the second detection output port when the detection enable signal is in the enabled state and the first flag signal has no pulses. The logic output circuit is configured to generate the disabled replacement flag signal and the disabled repair flag signal if both the first flag signal and the second flag signal have pulses; generate the disabled replacement flag signal and the enabled repair flag signal if the first flag signal has no pulses and the second flag signal has pulses; generate the enabled replacement flag signal and the disabled repair flag signal if both the first flag signal and the second flag signal have no pulses. Wherein, the disabled replacement flag signal indicates that the area surrounded by the first detection line is not damaged, and the disabled repair flag signal indicates that the area surrounded by the second detection line is not damaged.

9. The circuit according to claim 8, wherein The first processing circuit includes a second pulse generator; the enable terminal of the second pulse generator receives the detection enable signal, and outputs the first detection pulse signal to the first detection output port when the detection enable signal is in the enabled state. The second processing circuit includes an oscillator and a third pulse generator. The oscillator is configured to receive the detection enable signal and the first flag signal, and the enabled first flag signal is used to control the oscillator to be disabled. Output an enabled first intermediate control signal when the detection enable signal is in the enabled state and the first flag signal has no pulses; or output the disabled first intermediate control signal when the first detection enable signal is in the enabled state and the first flag signal has pulses. The enable terminal of the third pulse generator receives the first intermediate control signal, and outputs the second detection pulse signal to the second detection output port when the first intermediate control signal is in the enabled state.

10. The circuit according to claim 9, characterized in that, The logic output circuit includes a second flip-flop, a third flip-flop, a NOT gate, and a NOR gate; The second flip-flop latches the high-level signal received at the input end based on the first flag signal received at the clock terminal to output a second intermediate control signal; The third flip-flop latches the high-level signal received at the input end based on the second flag signal received at the clock terminal to output a third intermediate control signal; The NOT gate receives the third intermediate control signal and performs a NOT operation on the third intermediate control signal to output the replacement flag signal; The NOR gate receives the second intermediate control signal and the replacement flag signal, and performs a NOR operation on the second intermediate control signal and the replacement flag signal to output the repair flag signal.

11. The circuit according to claim 2, characterized in that, The packaging substrate includes 4 corners, namely a first corner, a second corner, a third corner, and a fourth corner, which are arranged in clockwise order; The chip includes 5 ports, and each of the ports serves as the detection output port and / or the result input port; Among them, the first port, the first corner, the second corner, the third corner, the fourth corner, and the fifth port are sequentially connected by a first connection line; The third port is connected to the first connection line between the second corner and the third corner through a second connection line; The second port is connected to the first connection line between the first corner and the second corner through a third connection line; The fourth port is connected to the first connection line between the third corner and the fourth corner through a fourth connection line.

12. The circuit according to claim 11, wherein, The first connection line, the second connection line, the third connection line, and the fourth connection line form 6 detection lines; The first detection line sequentially passes through the third port, at least 1 unactivated ball grid of the second corner, at least 1 unactivated ball grid of the first corner, and the first port; The second detection line sequentially passes through the third port and at least 1 unactivated ball grid of the second corner and the second port; The third detection line sequentially passes through the third port, at least 1 unactivated ball grid of the third corner, at least 1 unactivated ball grid of the fourth corner, and the fifth port; The fourth detection line sequentially passes through the third port and at least 1 unactivated ball grid of the third corner and the fourth port; The fifth detection line sequentially passes through the first port, at least 1 unactivated ball grid of the first corner, and the second port; The sixth detection line sequentially passes through the fifth port, at least 1 unactivated ball grid of the fourth corner, and the fourth port.

13. The circuit according to claim 12, wherein The signal processing circuit is configured to output a detection pulse signal to the third port; and receive a first flag signal from the first port, a second flag signal from the second port, a third flag signal from the fifth port, and a fourth flag signal from the fourth port; Among them, if there are pulses in the first to fourth flag signals, the packaging substrate is not cracked; if there is no pulse in the first flag signal and there is a pulse in the second flag signal, there is a crack in the area surrounded by the fifth detection line; if there is no pulse in the third flag signal and there is a pulse in the fourth flag signal, there is a crack in the area surrounded by the sixth detection line.

14. The circuit according to claim 13, characterized in that, In the case where there are no pulses in the first to fourth flag signals, the signal processing circuit is further configured to output the detection pulse signal to the first port and the fifth port; and receive a fifth flag signal from the second port and a sixth flag signal from the fourth port; if there is a pulse in the fifth flag signal, there is a crack in the area surrounded by the second detection line; if there is a pulse in the sixth flag signal, there is a crack in the area surrounded by the fourth detection line; if there are no pulses in both the fifth flag signal and the sixth flag signal, there are cracks in the area surrounded by each detection line.

15. A memory, characterized in that, The memory includes the detection circuit according to any one of claims 1 to 14.

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