Verification device, verification method, and program

Abstract

The invention provides a verification device, a verification method, and a program, which can ensure the accuracy of the operation verification of a circuit including a transistor and can reduce the man-hour required for the operation verification. A verification device according to an embodiment performs operation verification of a circuit including a transistor. The verification device according to an embodiment includes: a standard calculation unit that calculates an electrical standard of the transistor on the basis of information relating to a specification of the transistor; and a criterion determination unit that determines whether or not a verification data set including data for each time of a current value flowing through the transistor and a voltage value applied to the transistor within a predetermined time range satisfies the electrical criterion, and outputs data determined not to satisfy the electrical criterion in the verification data set.

Description

[0001] This application is based on Japanese Patent Application No. 2023-220508 (filing date: December 27, 2023) and claims the priority of this base application. This application includes all the contents of the base application by reference thereto. Technical Field

[0002] Embodiments of the present invention relate to a verification device, a verification method, and a program. Background Art

[0003] When designing a circuit including transistors, it is necessary to verify whether the circuit can operate without damaging or deteriorating the transistors. As such a verification method, for example, there is a method of comparing a double logarithmic curve graph of a safe operating area (SOA: Safe Operating Area) (electrical standard) described in a data sheet representing a transistor with each data of a current value flowing through the transistor and a voltage value applied to the transistor obtained by simulation or the like, and determining whether each data is included in the safe operating area. However, when the operator performing the verification manually performs this verification method, sometimes a large amount of man-hours is required. On the other hand, for example, it is also possible to consider that the operator inputs the conditions of the safe operating area into a computer or the like and automatically performs the above verification method. However, in this case, since the setting of the conditions of the safe operating area is entrusted to the operator, accurate verification may not be possible. Summary of the Invention

[0004] The problem to be solved by the present invention is to provide a verification device, a verification method, and a program that can ensure the accuracy of the operation verification of a circuit including transistors and can reduce the man-hours required for the operation verification.

[0005] The verification device according to an embodiment is a verification device that performs operation verification of a circuit including transistors. The verification device according to the embodiment includes: a standard calculation unit that calculates an electrical standard of the transistor based on information related to the specifications of the transistor; and a standard determination unit that determines whether a verification data set satisfies the electrical standard and outputs data in the verification data set that is determined not to satisfy the electrical standard, the verification data set including data of a current value flowing through the transistor and a voltage value applied to the transistor at each time within a specified time range. Brief Description of the Drawings

[0006] Figure 1 It is a block diagram showing the configuration of the verification device according to the embodiment.

[0007] Figure 2 It is a diagram showing an example of a circuit for which operation verification is performed by the verification device according to the embodiment.

[0008] Figure 3 It is a diagram showing an example of the verification data set of the embodiment as a time waveform.

[0009] Figure 4 It is a diagram showing an example of a double-logarithmic graph representing the safe operating region of a transistor.

[0010] Figure 5 It is a diagram showing an example of a graph representing the change in transient thermal resistance with respect to the pulse width of the pulse current applied to the transistor.

[0011] Figure 6 It is a diagram showing an example of a double-logarithmic graph representing the safe operating region corresponding to the first partition created by the standard calculation unit of the embodiment.

[0012] Figure 7 It is a diagram showing an example of a double-logarithmic graph representing the safe operating region corresponding to the second partition created by the standard calculation unit of the embodiment.

[0013] Figure 8 It is a diagram showing an example of a double-logarithmic graph representing the safe operating region corresponding to the third partition created by the standard calculation unit of the embodiment.

[0014] Figure 9 It is a diagram showing an example of a graph representing the change in allowable loss with respect to the case temperature of the transistor.

[0015] Figure 10 It is a diagram showing an example in the case of adjusting the double-logarithmic graph of the safe operating region corresponding to the second partition of the embodiment.

[0016] Figure 11 It is a diagram showing an example of plotting the sampled data determined to be in the first partition on the double-logarithmic graph of the safe operating region of the first partition of the embodiment.

[0017] Figure 12 It is a diagram showing an example of plotting the sampled data determined to be in the second partition on the double-logarithmic graph of the safe operating region of the second partition of the embodiment.

[0018] Figure 13 It is a diagram showing an example of plotting the sampled data determined to be in the third partition on the double-logarithmic graph of the safe operating region of the third partition of the embodiment.

[0019] Figure 14 It is a diagram showing an example of plotting the sampled data determined to be in the second partition on the double-logarithmic graph of the adjusted safe operating region of the second partition of the embodiment.

[0020] Figure 15This is a diagram showing an example of the time waveform generated by the waveform generation unit of the embodiment.

[0021] Figure 16 This is a flowchart showing an example of the operation order of the arithmetic unit of the embodiment.

[0022] Figure 17 This is a flowchart showing an example of the processing order of the data determination unit of the embodiment.

[0023] Figure 18 This is a flowchart showing an example of the processing order of the standard calculation unit of the embodiment.

[0024] Figure 19 This is a flowchart showing an example of the processing order of the standard determination unit of the embodiment.

[0025] Figure 20 This is a flowchart showing an example of the processing order of the waveform generation unit of the embodiment.

[0026] Symbol Explanation:

[0027] 12: Data determination unit; 13: Standard calculation unit; 14: Standard determination unit; 15: Waveform generation unit; 40: Circuit; 50: Transistor; 100: Verification device; CL: Partition; DG: Verification data group; dI d / dt: Slope; I d : Drain current (current); V ds : Drain-source voltage (voltage); Pd, Pd1, Pd2: Allowable loss; TR: Time range; W, Wd, Wi: Time waveform. Detailed Embodiment

[0028] Hereinafter, the verification device, verification method, and program of the embodiment will be described with reference to the drawings.

[0029] Figure 1 This is a block diagram showing the configuration of the verification device 100 of the present embodiment. Figure 1 The verification device 100 of the present embodiment shown is a device for verifying the operation of the circuit 40 including the transistor 50. Figure 2 This is a diagram showing an example of the circuit 40 whose operation is verified by the verification device 100. As Figure 2 shown, the circuit 40 includes the transistor 50. In Figure 2In the example, transistor 50 is a field effect transistor (FET: Field Effect Transistor) having a gate 51, a drain 52, and a source 53. In circuit 40, a resistor 61 is connected to gate 51. A gate voltage is applied to gate 51 via resistor 61. In circuit 40, a resistor 62 connecting gate 51 and source 53 is provided. In circuit 40, source 53 is grounded.

[0030] Verification device 100 is, for example, a computer. A program for causing verification device 100, which is a computer, to execute the verification method of the present embodiment is installed in verification device 100. As Figure 1 shown, verification device 100 includes an arithmetic unit 10, an operation unit 20, and a display unit 30. Operation unit 20 is a part for an operator to operate verification device 100. Operation unit 20 is, for example, a keyboard and a mouse, etc. By operating operation unit 20, the operator can input various data to arithmetic unit 10 and cause arithmetic unit 10 to start arithmetic operations, etc. Display unit 30 is a part capable of displaying the arithmetic result of arithmetic unit 10. Display unit 30 is, for example, a display, etc. In addition, when verification device 100 is a smart device such as a smart phone or a tablet terminal, the screen of the smart device may also be operation unit 20 and display unit 30.

[0031] Arithmetic unit 10 is, for example, a processor such as a CPU (Central Processing Unit) installed with a program capable of executing the verification method of the present embodiment. Arithmetic unit 10 executes the verification method of the present embodiment for performing operation verification of circuit 40. Arithmetic unit 10 includes a storage unit 11, a data determination unit 12, a standard calculation unit 13, a standard determination unit 14, and a waveform generation unit 15.

[0032] Storage unit 11 is a part for storing various data. Storage unit 11 is implemented by storage media such as a RAM (Random Access Memory), a ROM (Read Only Memory), an HDD (Hard Disk Drive), and a flash memory, etc. Data input by the operator via operation unit 20 and data of files read by the operator via operation unit 20 are stored in storage unit 11.

[0033] The storage unit 11 includes a verification data storage unit 11a and a specification data storage unit 11b. The verification data storage unit 11a is the part that stores the verification data group DG, which contains data at each time of the current value flowing through the transistor 50 within a specified time range TR when driving the circuit 40 and the voltage value applied to the transistor 50. In the present embodiment, the verification data group DG is a data group obtained by simulation. In addition, the method for obtaining the verification data group DG by simulation is not particularly limited, and all known methods can be adopted. The multiple data included in the verification data group DG are sampled data Sd obtained at a specified sampling period. The sampling period is, for example, 0.1 microsecond or more. In the present embodiment, the voltage value of the sampling data Sd is the voltage applied between the drain 52 and the source 53, that is, the drain-source voltage V ds value. In the present embodiment, the current value of the sampling data Sd is the current flowing from the drain 52 to the source 53, that is, the drain current I d value.

[0034] Figure 3 is a diagram showing an example of the verification data group DG as a time waveform. In Figure 3 example, it shows the verification data group DG including the value of the drain current I d of the transistor 50 and the value of the drain-source voltage V ds within a specified time range TR from time t1 to time t6. Figure 3 The upper curve graph in d is a curve graph showing the change of the drain current I Figure 3 with respect to time t. ds The lower curve graph in Figure 3 is a curve graph showing the change of the drain-source voltage V d with respect to time t. In Figure 3 the upper curve graph, the horizontal axis is time t, and the vertical axis is the drain current I ds . In

[0035] In Figure 3In the example of the verification data group DG shown, the time range TR has a first interval P1, a second interval P2, a third interval P3, a fourth interval P4, and a fifth interval P5. The first interval P1, the second interval P2, the third interval P3, the fourth interval P4, and the fifth interval P5 are sequentially set continuously in time. The first interval P1 and the fifth interval P5 are cutoff intervals in which the transistor 50 is in the cutoff state. The second interval P2 is a conduction interval in which the transistor 50 switches from the cutoff state to the on state. The third interval P3 is an on interval in which the transistor 50 is in the on state. The fourth interval P4 is a disconnection interval in which the transistor 50 switches from the on state to the cutoff state. The first interval P1 is an interval between time t1 and time t2. The second interval P2 is an interval between time t2 and time t3. The third interval P3 is an interval between time t3 and time t4. The fourth interval P4 is an interval between time t4 and time t5. The fifth interval P5 is an interval between time t5 and time t6. The time width in the second interval P2 as the conduction interval is greater than the time width in the fourth interval P4 as the disconnection interval.

[0036] The specification data storage unit 11b is a part that stores information related to the specifications of the transistor 50. The information related to the specifications of the transistor 50 includes values in a specification table that records various values representing the specifications of the transistor 50, values read from a graph representing the specifications of the transistor 50, and the like. The graph representing the specifications of the transistor 50 includes a graph representing the safe operating area (SOA) 70 of the transistor 50 and a graph representing the transient thermal resistance r th A graph of the change in the pulse width tw of the pulse current applied to the transistor 50, etc.

[0037] Figure 4 is a diagram that is an example of a double logarithmic graph representing the safe operating area 70 of the transistor 50. In Figure 4 it, the horizontal axis represents the drain-source voltage V ds , and the vertical axis represents the drain current I d . The safe operating area 70 is an electrical standard of the transistor 50 that represents the range of the drain current I d and the range of the drain-source voltage V ds in which the transistor 50 can be safely used without being damaged or deteriorated. The double logarithmic graph representing the safe operating area 70 is recorded in the data sheet representing the specifications of the transistor 50. Figure 4 The safe operating area 70 shown is a region surrounded by a current limit region 71, a voltage limit region 72, a on-resistance limit region 73, a thermal limit region 74, and a second breakdown region 75, that is, Figure 4 the region shaded in Figure 4Plot the drain current I of transistor 50 when circuit 40 operates on the curve graph d and the point determined by the value of the drain-source voltage V ds When the plotted point is within the safe operating region 70, circuit 40 can operate without damaging or deteriorating transistor 50.

[0038] The current limit region 71 is the region determined by the rated value of the drain current I d . That is, Figure 4 the value of the drain current I shown by the region line of the current limit region 71 in d is the rated value of the drain current I d . The voltage limit region 72 is the region determined by the rated value of the drain-source voltage V ds . That is, Figure 4 the value of the drain-source voltage V shown by the region line of the voltage limit region 72 in ds is the rated value of the drain-source voltage V ds .

[0039] The on-resistance limit region 73 is the region determined by the maximum value of the on-resistance of transistor 50. The on-resistance of transistor 50 is the resistance value between drain 52 and source 53 when a voltage above the threshold is applied to gate 51 of transistor 50 to make transistor 50 in the on state. The thermal limit region 74 is the region determined by the allowable power loss P d of transistor 50. The allowable power loss P d is the maximum power consumption that does not exceed the temperature at which the performance of transistor 50 can be maintained, and is equivalent to the rated power of transistor 50. The thermal limit region 74 is set within a range that can prevent transistor 50 from being damaged by heat.

[0040] The second breakdown region 75 is the region determined based on the second breakdown generated in transistor 50. The second breakdown generated in transistor 50 is a phenomenon in which current concentrates in the channel of transistor 50 due to the decrease in channel resistance accompanying the temperature rise of transistor 50. More specifically, when the temperature of transistor 50 rises, the threshold voltage of gate 51 decreases, resulting in a decrease in channel resistance, and current concentrates in the channel where the resistance has decreased, causing second breakdown. If second breakdown occurs and current concentrates in the channel, the temperature of transistor 50 further rises, and the threshold voltage of gate 51 further decreases. As a result, current further concentrates in the channel, and transistor 50 may be damaged.

[0041] Figure 4Each of the area lines indicated by the solid lines, for example, represents the lines of the respective areas when a direct current flows through the transistor 50. The safe operating area 70 varies depending on whether the current flowing through the transistor 50 is a direct current or a pulsed current. In addition, the safe operating area 70 also varies depending on the pulse width tw of the pulsed current flowing through the transistor 50. Figure 4 Each of the area lines of the current limiting area 71, the thermal limiting area 74, and the second breakdown area 75 indicated by the dashed lines in the figure represents the lines of the areas when a pulsed current flows through the transistor 50. In Figure 4 In this case, the safe operating area 70 when a pulsed current flows through the transistor 50 is the area surrounded by the current limiting area 71, the thermal limiting area 74, and the second breakdown area 75 indicated by the dashed lines, and the voltage limiting area 72 and the on-resistance limiting area 73 indicated by the solid lines. From Figure 4 It can be confirmed that the range of the safe operating area 70 changes between the case where a direct current flows through the transistor 50 and the case where a pulsed current flows through the transistor 50. The safe operating area 70 when a direct current flows through the transistor 50 is narrower than the safe operating area 70 when a pulsed current flows through the transistor 50. The voltage limiting area 72 and the on-resistance limiting area 73 do not change, for example, depending on the current flowing through the transistor 50.

[0042] In the double logarithmic graph showing the safe operating area 70 recorded in the data sheet representing the specifications of the transistor 50, the safe operating area 70 when a direct current flows through the transistor 50 and the safe operating area 70 when a pulsed current flows through the transistor 50 are shown. For the safe operating area 70 when a pulsed current flows through the transistor 50, multiple safe operating areas 70 with different pulse widths tw are shown in the double logarithmic graph showing the safe operating area 70 of the transistor 50. The multiple safe operating areas 70 when a pulsed current flows through the transistor 50 include, for example, the safe operating areas 70 when the pulse width tw is 10 milliseconds, 1 millisecond, 100 microseconds, and 10 microseconds.

[0043] Figure 5 is a graph showing an example of a graph of the change of the transient thermal resistance r th with respect to the pulse width tw of the pulsed current applied to the transistor 50. Figure 5 The graph of is a double logarithmic graph. In Figure 5 this graph, the horizontal axis represents the pulse width tw [seconds], and the vertical axis represents the transient thermal resistance r th [℃ / W]. The transient thermal resistance r th is the thermal resistance in the time range affected by the thermal capacitance. The change of the transient thermal resistance r th varies, for example, depending on the duty ratio of the pulsed current applied to the transistor 50.

[0044] In the specification data storage unit 11b, the rated value of the drain current I flowing through the transistor 50, the rated value of the drain-source voltage V applied to the transistor 50, the maximum value of the on-resistance of the transistor 50, the channel temperature T of the transistor 50 d and the case temperature T of the transistor 50 ds are stored as information related to the specifications of the transistor 50. The rated value of the drain current I flowing through the transistor 50, the rated value of the drain-source voltage V applied to the transistor 50, the maximum value of the on-resistance of the transistor 50, the channel temperature T of the transistor 50 ch and the case temperature T of the transistor 50 c are, for example, values read from the specification table of the transistor 50. d ds ch c d d d d

[0045] The rated value of the drain current I stored in the specification data storage unit 11b includes the rated value when the drain current I flowing through the transistor 50 is a direct current, and the rated value when the drain current I flowing through the transistor 50 is a pulse current. The rated value when the drain current I flowing through the transistor 50 is a pulse current can also be set for each pulse current of multiple pulse widths tw. In addition, for example, when the rated value of the drain current I d is not described in the specification table, etc., the rated value can also be read from the double logarithmic curve graph showing the safe operating region 70 of the transistor 50 as shown in d d d d c c c1 c Figure 4 . The case temperature T c is the temperature of the case of the transistor 50. As the case temperature T c , for example, the standard case temperature T c1 described in the specification of the transistor 50, etc., and the maximum value of the case temperature T c assumed to be reached with the temperature rise of the transistor 50 are stored in the specification data storage unit 11b. The case temperature T c1 is, for example, 25 °C. In addition, in the specification data storage unit 11b, the ambient temperature T c of the transistor 50 can be stored instead of the case temperature T a .

[0046] In the specification data storage unit 11b, the values of the transient thermal resistance r corresponding to the respective pulse widths tw are stored. From the th double logarithmic curve graph showing the transient thermal resistance r Figure 5 as shown in thThe transient thermal resistance r is read from the graph relative to the change in pulse width tw. th For example, in Figure 5 In the case where a pulse current with a pulse width tw of 0.001 seconds flows through transistor 50, the transient thermal resistance r th The transient thermal resistance r corresponding to the DC current is stored in the specification data storage unit 11b. th The value of . Figure 5 The transient thermal resistance r th The transient thermal resistance r corresponding to the DC current is read from the graph relative to the change in pulse width tw. th Specifically, the pulse width tw can be set to a certain value or more, and the transient thermal resistance r th The transient thermal resistance r th The value of the transient thermal resistance r corresponding to the DC current th The value of Figure 5 When the pulse width tw is greater than 0.1 seconds, the transient thermal resistance r th becomes constant. For example, Figure 5 Transient thermal resistance r when the pulse width tw is 10 seconds th The value of r2 is set to the transient thermal resistance r corresponding to the DC current th The value r2 is, for example, a value greater than the value r1.

[0047] The specification data storage unit 11 b stores the drain currents I at any two points on the region line representing the secondary breakdown region 75. d The value of each drain-source voltage V ds From Figure 4 The double logarithmic graph showing the safe operation range 70 of the transistor 50 is shown in FIG. Figure 4 The drain current I at point 75a is shown d The value of drain-source voltage V ds The value of Figure 4 The drain current I at point 75b is shown d The value of drain-source voltage V ds The value of .

[0048] The data determination unit 12 is a part that determines to which of the plurality of partitions CL each sample data Sd included in the verification data group DG belongs. The plurality of partitions CL are partitions corresponding to the plurality of safe operation regions 70 corresponding to the pulse application time, that is, the pulse width tw, of the pulse current applied to the transistor 50. In the present embodiment, the plurality of partitions CL are based on the drain current I in the verification data group DG. dis determined by the magnitude of the slope that changes over time. Specifically, in the Figure 3 example shown, the multiple partitions CL include a first partition CL1, a second partition CL2, and a third partition CL3.

[0049] The first partition CL1 is a partition where the slope of the drain current I d changing over time is greater than or equal to a value α and less than or equal to a value β. The value α is a negative value, and the value β is a positive value. The absolute value of the value α and the absolute value of the value β may be the same as each other or different from each other. The second partition CL2 is a partition where the slope of the drain current I d changing over time is greater than the value β. The third partition CL3 is a partition where the slope of the drain current I d changing over time is less than the value α. In the Figure 3 example, the first interval P1, the third interval P3, and the fifth interval P5 are included in the first partition CL1. The second interval P2 is included in the second partition CL2. The fourth interval P4 is included in the third partition CL3. That is, the second partition CL2 is the partition CL of the sampled data Sd included in the conduction interval. The third partition CL3 is the partition CL of the sampled data Sd included in the disconnection interval. The first partition CL1 is the partition CL of the sampled data Sd included in the interval other than the conduction interval and the disconnection interval. The absolute value of the slope of the drain current I d changing over time in the first partition CL1 is less than the absolute value of the slope of the drain current I d changing over time in the second partition CL2 and the third partition CL3. The value α is the determination value of the slope at the time of disconnection (when decreasing). The value β is the determination value of the slope at the time of conduction (when increasing).

[0050] In addition, for example, when the time width of the second interval P2, which is the conduction interval, is large to a certain extent, the second interval P2 may be regarded as an interval corresponding to the case where a direct current flows through the transistor 50 and classified into the first partition CL1.

[0051] In intervals where the drain current I d and the drain-source voltage V ds change, such as in the second interval P2 and the fourth interval P4, the time width of each interval can be regarded as the pulse width tw of the pulse current applied to the transistor 50. Here, in the intervals where the drain current I d and the drain-source voltage V ds change, the larger the absolute value of the slope of the drain current I d , the smaller the time width of the interval, and the smaller the absolute value of the slope of the drain current I d , the larger the time width of the interval. Therefore, by calculating the drain current I dThe magnitude of the slope can determine the drain current I applied to the transistor 50 in each interval within the specified time range TR d which corresponds to the case of a pulse current with a pulse width tw applied

[0052] The data determination unit 12 calculates the slope of the drain current I in the verification data group DG d changing with time. In the present embodiment, the data determination unit 12 calculates this slope for each sampling data Sd included in the verification data group DG. Specifically, the data determination unit 12 calculates, for example, using the sampling data Sd before and after the sampling data Sd for calculating this slope, the differential value obtained by differentiating the drain current I d for this sampling data Sd, that is, I d / dt as the slope of this sampling data Sd. Based on the calculated value of this slope, the data determination unit 12 determines which of the multiple partitions CL each sampling data Sd included in the verification data group DG belongs to. In the following description, sometimes the slope of the drain current I d changing with time in the verification data group DG is referred to as the slope dI d / dt

[0053] The standard calculation unit 13 is a part that calculates the electrical standard of the transistor 50 based on information related to the specifications of the transistor 50. In the present embodiment, the standard calculation unit 13 calculates the safe operating region 70 of the transistor 50 as the electrical standard of the transistor 50. Specifically, the standard calculation unit 13 derives functions representing the current limit region 71, the voltage limit region 72, the on-resistance limit region 73, the thermal limit region 74, and the second breakdown region 75 respectively based on the values related to the specifications of the transistor 50, and calculates the safe operating region 70 as the electrical standard. In the present embodiment, the standard calculation unit 13 calculates the electrical standard, that is, the safe operating region 70, based on the rated current value of the transistor 50, that is, the rated value of the drain current I d , the rated voltage value of the transistor 50, that is, the rated value of the drain-source voltage V ds , the maximum value of the on-resistance of the transistor 50, the allowable loss P d of the transistor 50, the value of the drain current I d related to the second breakdown of the transistor 50, and the value of the drain-source voltage V ds . In the following description, the safe operating region 70 calculated by the standard calculation unit 13 is referred to as the safe operating region 70S

[0054] In the present embodiment, the standard calculation unit 13 can calculate electrical standards corresponding to a plurality of partitions CL, that is, the safe operation regions 70S. In the present embodiment, the standard calculation unit 13 calculates the safe operation region 70A corresponding to the first partition CL1, the safe operation region 70B corresponding to the second partition CL2, and the safe operation region 70C corresponding to the third partition CL3. The safe operation region 70A in the first partition CL1 corresponds to the safe operation region when a direct current flows through the transistor 50. The safe operation regions 70B and 70C in the second partition CL2 and the third partition CL3 correspond to the safe operation region when a pulse current flows through the transistor 50. The safe operation region 70B in the second partition CL2 corresponds to the safe operation region when the pulse width tw of the pulse current flowing through the transistor 50 is larger than that of the safe operation region 70C in the third partition CL3. In addition, since the plurality of safe operation regions 70S calculated by the standard calculation unit 13 are divided based on the time (pulse width tw) when a current flows through the transistor 50, it can be said that the time standard of the transistor 50 is included in the plurality of electrical standards calculated by the standard calculation unit 13.

[0055] When the drain current is set to I d , and the rated value of the drain current I d is set to I r , the current limit region 71 is represented by I d = I r . The standard calculation unit 13 can derive a function representing the current limit region 71 by substituting the rated value of the drain current I r stored in the specification data storage unit 11b into I d in this formula.

[0056] When the drain-source voltage is set to V ds , and the rated value of the drain-source voltage V ds is set to V r , the voltage limit region 72 is represented by V ds = V r . The standard calculation unit 13 can derive a function representing the voltage limit region 72 by substituting the rated value of the drain-source voltage V r stored in the specification data storage unit 11b into V ds in this formula.

[0057] When the drain current is set to I d , the drain-source voltage is set to V ds , and the maximum value of the on-resistance is set to R ds , the on-resistance limit region 73 is represented by I d = V ds / (R ds) is represented. By substituting the maximum value of the on-resistance stored in the specification data storage unit 11b into R in this formula, the standard calculation unit 13 can derive a function representing the on-resistance limit region 73. ds When the drain current is set to I

[0058] and the drain-source voltage is set to V d , and the allowable loss is set to P ds , the thermal limit region 74 is represented by I d = P d / V d . When the channel temperature is set to T ds and the case temperature is set to T ch , and the transient thermal resistance is set to r c , the allowable loss P th is represented by P d = (T d - T ch ) / r c . The standard calculation unit 13 can derive a function representing the thermal limit region 74 by substituting the values of the channel temperature T th , the case temperature T ch , and the transient thermal resistance r c stored in the specification data storage unit 11b into these formulas. Additionally, when the allowable loss P th is described in the specification table of the transistor 50, the value of the allowable loss P d described in the specification table can also be stored in the specification data storage unit 11b, and the stored value can be used as the value of the allowable loss P d . d

[0059] When the drain current is set to I d and the drain-source voltage is set to V ds , the second breakdown region 75 is represented by the following formula (1).

[0060]

Mathematical formula 1

[0061]

[0062] where I d1 is the value of the drain current I d at any point on the region line of the second breakdown region 75 in the double logarithmic curve graph of the safe operating region 70 described in the data sheet of the transistor 50, and V ds1 is the value of the drain-source voltage V ds at this arbitrary point. I d2The drain current I at any other point on the region line of the secondary breakdown region 75 in the double-logarithmic curve graph of the safe operating region 70 recorded in the data sheet of the transistor 50 d value, and V ds2 is the drain-source voltage V ds value at this any other point.

[0063] The standard calculation unit 13 substitutes the drain currents I at any two points on the region line of the secondary breakdown region 75 stored in the specification data storage unit 11b into the above formula (1) d values and the drain-source voltages V ds values at these points, and can derive a function representing the secondary breakdown region 75. In this embodiment, in I d1 substitute the drain current I Figure 4 value of the point 75a shown, and in V d substitute the drain-source voltage V ds1 value of the point 75a. In I ds substitute the drain current I d2 value of the point 75b shown in Figure 4 and in V d substitute the drain-source voltage V ds2 value of the point 75b. ds value.

[0064] The standard calculation unit 13 creates a data table based on each function defining the safe operating region 70S and according to each sampling data Sd included in the verification data group DG. The standard calculation unit 13 creates a data group of the drain current I ds value in the current limit region 71 corresponding to the drain-source voltage V d value of each sampling data Sd, that is, the rated value of the drain current I d stored in the specification data storage unit 11b, and creates a data table of the current limit region 71. The standard calculation unit 13 creates a data group of the drain-source voltage V d value in the voltage limit region 72 corresponding to the drain current I ds value of each sampling data Sd, that is, the rated value of the drain-source voltage V ds stored in the specification data storage unit 11b, and creates a data table of the voltage limit region 72.

[0065] In the functions defining the safe operating region 70S, the standard calculation unit 13 has a function with I d and V ds as variables, that is, the function representing the on-resistance limit region 73, the function representing the thermal limit region 74, and the function representing the secondary breakdown region 75, and for V dsSubstitute the drain-source voltage V of each sampling data Sd included in the verification data group DG into the formula respectively ds and create data tables for the on-resistance limit region 73, thermal limit region 74, and second breakdown region 75 corresponding to each sampling data Sd respectively.

[0066] The standard calculation unit 13 plots the values of the created data tables on a double logarithmic graph to create a double logarithmic graph of the safe operating region 70S corresponding to the safe operating region 70 recorded in the data sheet of the transistor 50. In the present embodiment, the standard calculation unit 13 creates double logarithmic graphs of the safe operating region 70S corresponding to the respective partitions CL.

[0067] Figure 6 FIG. is an example of a double logarithmic graph of the safe operating region 70A corresponding to the first partition CL1 created by the standard calculation unit 13. Figure 7 FIG. is an example of a double logarithmic graph of the safe operating region 70B corresponding to the second partition CL2 created by the standard calculation unit 13. Figure 8 FIG. is an example of a double logarithmic graph of the safe operating region 70C corresponding to the third partition CL3 created by the standard calculation unit 13. In Figures 6 to 8 the horizontal axis is the drain-source voltage V ds and the vertical axis is the drain current I d . In addition, in Figures 6 to 8 the region lines of the current limit region 71, voltage limit region 72, on-resistance limit region 73, thermal limit region 74, and second breakdown region 75 are schematically represented by straight lines, but in reality, the region lines representing each region are created based on the values of the created data tables. As Figures 6 to 8 shown, the voltage limit region 72 and the on-resistance limit region 73 are the same in the safe operating region 70S of any partition CL.

[0068] The standard calculation unit 13 is based on the temperature adjustment electrical standard related to the transistor 50. The temperature related to the transistor 50 may be any temperature related to the transistor 50, which may be the temperature at any position of the transistor 50 or the temperature around the transistor 50. In the present embodiment, the standard calculation unit 13 is based on the case temperature T c as the temperature related to the transistor 50 and adjusts the thermal limit region 74 and the second breakdown region 75 in each region defining the safe operating region 70S. Specifically, the standard calculation unit 13 adjusts the thermal limit region 74 and the second breakdown region 75 by adjusting the value of the allowable loss P d .

[0069] Figure 9 FIG. shows the allowable loss Pd Graph showing the change in the case temperature T of the transistor 50 c An example of a graph. In Figure 9 , the horizontal axis represents the case temperature T c , and the vertical axis represents the allowable loss P d . In Figure 9 's example, in the region where the case temperature T c is equal to or higher than the standard case temperature T c1 , the allowable loss P d decreases linearly as the case temperature T c increases. According to this relationship, when the allowable loss calculated with the case temperature T c equal to the standard case temperature T c1 is set as P d1 , and the channel temperature is set as T ch , the allowable loss P c calculated with the case temperature T c1 higher than the case temperature T c2 is expressed as P d2 = P d2 × (T d1 - T ch ) / (T c2 - T ch ). The case temperature T c1 is, for example, the maximum value of the case temperature T c2 assumed to be reached with the temperature rise of the transistor 50. As an example, the case temperature T c is 120 °C or the like. c2

[0070] The standard calculation unit 13 can adjust the thermal limit region 74 in the case where the case temperature T d is the case temperature T d1 to the thermal limit region 74 in the case where the case temperature T d2 is the case temperature T c by changing the allowable loss P c1 in the function representing the thermal limit region 74 to the allowable loss P c . c2

[0071] The standard calculation unit 13 can adjust the second breakdown region 75 in the case where the case temperature T d2 is the case temperature T d1 to the second breakdown region 75 in the case where the case temperature T c is the case temperature T c1 by multiplying the right side of the above formula (1) representing the second breakdown region 75 by the ratio of the allowable loss P c to the allowable loss P c2 ​​The secondary breakdown region 75 in the case of. Specifically, the standard calculation unit 13 obtains the function of the adjusted secondary breakdown region 75 through the following formula (2).

[0072]

Mathematical formula 2

[0073]

[0074] Among them, C1 and C2 are the same as formula (1).

[0075] Figure 10 is a diagram showing an example in the case of a double logarithmic curve graph for adjusting the safe operating region 70B corresponding to the second partition CL2. In Figure 10 , the horizontal axis is the drain-source voltage V ds , and the vertical axis is the drain current I d . As Figure 10 shown, when the case temperature T c changes from the case temperature T c1 to a case temperature T c1 higher than the case temperature T c2 , the values of the drain current I d in the thermal limit region 74 and the secondary breakdown region 75 become lower, and the safe operating region 70B becomes narrower. In this way, the standard calculation unit 13 can perform temperature derating on the safe operating region 70S.

[0076] The standard determination unit 14 determines whether the verification data group DG satisfies the electrical standard calculated in the standard calculation unit 13. In the present embodiment, the standard determination unit 14 determines whether each sampling data Sd of the verification data group DG is included in the safe operating region 70S calculated in the standard calculation unit 13. More specifically, the standard determination unit 14 plots the sampling data Sd classified into multiple partitions CL on the double logarithmic curve graph of the safe operating region 70S produced by the standard calculation unit 13 for each of the multiple partitions CL, and determines whether each sampling data Sd is included in the safe operating region 70S of the plotted double logarithmic curve graph. That is, in the present embodiment, the standard determination unit 14 uses the safe operating region 70S corresponding to each partition CL to determine the sampling data Sd according to which partition CL the determined sampling data Sd is included in. In other words, the standard determination unit 14 automatically changes the electrical standard for the verification data group DG according to the partition CL determined by the data determination unit 12.

[0077] When the standard determination unit 14 includes the sampled data Sd in all of the current limit region 71, voltage limit region 72, on-resistance limit region 73, thermal limit region 74, and second breakdown region 75 of the specified safe operation region 70S, it determines that the sampled data Sd is included in the safe operation region 70S, and the sampled data Sd meets the electrical standard of the transistor 50. When the standard determination unit 14 does not include the sampled data Sd in one or more of the current limit region 71, voltage limit region 72, on-resistance limit region 73, thermal limit region 74, and second breakdown region 75, it determines that the sampled data Sd is not included in the safe operation region 70S, and the sampled data Sd does not meet the electrical standard of the transistor 50. The standard determination unit 14 outputs the sampled data Sd determined not to meet the electrical standard in the verification data group DG to the waveform generation unit 15.

[0078] The fact that the sampled data Sd is included in the current limit region 71 means that the drain current I of the sampled data Sd d is less than the drain current I of the region line of the current limit region 71 d , that is, the rated value of the drain current I d . The fact that the sampled data Sd is included in the voltage limit region 72 means that the drain-source voltage V of the sampled data Sd ds is less than the drain-source voltage V of the region line of the voltage limit region 72 ds , that is, the rated value of the drain-source voltage V ds . The fact that the sampled data Sd is included in the on-resistance limit region 73, thermal limit region 74, and second breakdown region 75 means that in the drain-source voltage V of the sampled data Sd ds , the value of the drain current I of the sampled data Sd d is less than the value of the drain current I in each of the region lines of the on-resistance limit region 73, thermal limit region 74, and second breakdown region 75 d .

[0079] Figure 11 is a diagram showing an example of the sampled data Sd determined to be in the first partition CL1 plotted on the double logarithmic graph of the safe operation region 70A of the first partition CL1. Figure 12 is a diagram showing an example of the sampled data Sd determined to be in the second partition CL2 plotted on the double logarithmic graph of the safe operation region 70B of the second partition CL2. Figure 13 is a diagram showing an example of the sampled data Sd determined to be in the third partition CL3 plotted on the double logarithmic graph of the safe operation region 70C of the third partition CL3. Figure 14This is a diagram showing an example of the sampled data Sd determined to be in the second partition CL2 plotted on a double-logarithmic graph of the safety operation region 70B of the adjusted second partition CL2.

[0080] In Figures 11 to 14 , the horizontal axis is the drain-source voltage V ds , and the vertical axis is the drain current I d . Additionally, in Figures 11 to 14 , the region lines of the current limit region 71, voltage limit region 72, on-resistance limit region 73, thermal limit region 74, and secondary breakdown region 75 are schematically represented by straight lines. However, in reality, the region lines representing each region are created based on the values in the data table being plotted.

[0081] In Figures 11 to 14 , the sampled data Sd that satisfies each safety operation region 70S, i.e., each electrical standard, is represented by white circles, and the sampled data Sd that does not satisfy each electrical standard is represented by black circles. The standard determination unit 14 outputs the sampled data Sd determined to not satisfy the electrical standard to the waveform generation unit 15. Additionally, the standard determination unit 14 can also output each double-logarithmic graph on which the sampled data Sd is plotted to the display unit 30 and display it on the display unit 30. Furthermore, the standard determination unit 14 can also represent all the sampled data Sd by plotting in the same color in each double-logarithmic graph displayed on the display unit 30.

[0082] The waveform generation unit 15 generates the time waveform W of the drain current I d and the drain-source voltage V ds in the verification data group DG. Specifically, the waveform generation unit 15 plots each sampled data Sd included in the verification data group DG stored in the verification data storage unit 11a on the time axis and generates the time waveform W of the drain current I d and the drain-source voltage V ds . The waveform generation unit 15 displays the sampled data Sd in the verification data group DG that does not satisfy the electrical standard output from the standard determination unit 14 on the generated time waveform W.

[0083] Figure 15 This is a diagram showing an example of the time waveform W generated by the waveform generation unit 15. Figure 15 The upper graph in d is a graph showing the time waveform Wi of the drain current I Figure 15 The lower graph in ds is a graph showing the time waveform Wd of the drain-source voltage V Figure 15 In the upper graph of d , the horizontal axis is the time t, and the vertical axis is the drain current I Figure 15In the graph on the lower side, the horizontal axis is time t and the vertical axis is the drain-source voltage V ds . As Figure 15 shown, the waveform generation unit 15 highlights the sampled data Sd that does not meet the electrical standard on each of the time waveforms Wi and Wd. In Figure 15 the example, the sampled data Sd that meets the electrical standard is represented by a white circle, and the sampled data Sd that does not meet the electrical standard is represented by a black circle. The waveform generation unit 15 outputs the produced time waveform W to the display unit 30 and displays it on the display unit 30. Thus, the operator can confirm which part of the verification data set DG does not meet the safe operating area 70S of the transistor 50, that is, the electrical standard.

[0084] Next, a verification method using the verification device 100 will be described. Figure 16 is a flowchart showing an example of the operation order of the operation unit 10. Figure 17 is a flowchart showing an example of the processing order of the data determination unit 12. Figure 18 is a flowchart showing an example of the processing order of the standard calculation unit 13. Figure 19 is a flowchart showing an example of the processing order of the standard determination unit 14. Figure 20 is a flowchart showing an example of the processing order of the waveform generation unit 15.

[0085] As Figure 16 shown, when the operation unit 10 is input with information related to the specifications of the transistor 50 and the verification data set DG via the operation unit 20 (step S11), it determines whether each sampled data Sd of the verification data set DG belongs to one of the multiple partitions CL (step S12), and calculates the safe operating area 70S, that is, the electrical standard, for each of the multiple partitions CL (step S13).

[0086] In addition, the operation unit 10 can perform step S12 and step S13 in sequence. In this case, either step S12 or step S13 can also be performed first. Furthermore, in the case where a determination of a transistor 50 with the same specifications was made before this verification, and in the case where information related to the specifications of the transistor 50 input last time is stored in the storage unit 11, the input of information related to the specifications of the transistor 50 can also be omitted in step S11.

[0087] Step S12 is performed in the data determination unit 12. As Figure 17 shown, the data determination unit 12 creates a time waveform of the drain current I d in the verification data set DG (step S21). This time waveform is, for example, the same waveform as the time waveform shown in the upper graph of Figure 3 . The data determination unit 12 calculates this drain current I for each sampled data Sdd Differentiate the time waveform of d to calculate the slope dI of the change with time d / dt (step S22). In this way, the verification method of the present embodiment includes calculating the slope dI of the change with time of the current value in the verification data group DG

[0088] The data determination unit 12 determines whether the calculated slope dI d / dt satisfies the first specified condition (step S23). The first specified condition is that the slope dI d / dt of the sampled data Sd is less than the above value α or greater than the above value β. When the calculated slope dI d / dt does not satisfy the first specified condition (step S23: No), the data determination unit 12 determines that the sampled data Sd belongs to the first partition CL1 (step S25).

[0089] On the other hand, when the calculated slope dI d / dt satisfies the first specified condition (step S23: Yes), the data determination unit 12 determines whether the calculated slope dI d / dt satisfies the second specified condition (step S24). The second specified condition is that the slope dI d / dt of the sampled data Sd is greater than the above value β. When the calculated slope dI d / dt satisfies the second specified condition (step S24: Yes), the data determination unit 12 determines that the sampled data Sd belongs to the second partition CL2 (step S26). On the other hand, when the calculated slope dI d / dt does not satisfy the second specified condition (step S24: No), the data determination unit 12 determines that the sampled data Sd belongs to the third partition CL3 (step S27). The data determination unit 12 performs the above determination on all the sampled data Sd included in the verification data group DG, and determines whether each sampled data Sd belongs to a certain partition CL. In this way, the verification method of the present embodiment includes determining which partition CL among the multiple partitions CL divided based on the magnitude of the slope dI d / dt each sampled data Sd included in the verification data group DG belongs to.

[0090] Step S13 is performed in the standard calculation unit 13. As Figure 18As shown, the standard calculation unit 13 derives a function representing the safe operating area 70S, i.e., the electrical standard, based on information related to the specifications of the transistor 50 (step S31). In the present embodiment, the standard calculation unit 13 derives a function representing the safe operating area 70S for each of the plurality of partitions CL. Specifically, the standard calculation unit 13 derives functions representing the current limit region 71, the voltage limit region 72, the on-resistance limit region 73, the thermal limit region 74, and the second breakdown region 75 as described above. That is, the verification method of the present embodiment includes calculating the electrical standard based on the rated current value of the transistor 50, the rated voltage value of the transistor 50, the maximum value of the on-resistance of the transistor 50, the allowable loss P d of the transistor, the current value and voltage value related to the second breakdown of the transistor 50.

[0091] Based on the derived functions, the standard calculation unit 13 creates a data table of the safe operating area 70S according to each sampling data Sd of the verification data group DG (step S32). In the present embodiment, the standard calculation unit 13 creates a data table of the safe operating area 70S for each of the plurality of partitions CL. The standard calculation unit 13 creates a double logarithmic curve graph of the safe operating area 70S according to the created data table (step S33). In the present embodiment, the standard calculation unit 13 creates a double logarithmic curve graph of the safe operating area 70S for each of the plurality of partitions CL. The double logarithmic curve graph of the safe operating area 70S created by the standard calculation unit 13 in step S33 is, for example, the one shown above Figures 6 to 8 and so on.

[0092] In addition, for example, when an operator inputs an instruction indicating temperature derating to the verification device 100, in step S13, the standard calculation unit 13, as described above Figure 10 adjusts the electrical standard based on the case temperature T c of the transistor 50.

[0093] As described above, the verification method of the present embodiment includes: calculating the electrical standard of the transistor 50 based on information related to the specifications of the transistor 50; calculating the electrical standards corresponding to the plurality of partitions CL respectively; and adjusting the electrical standard based on the temperature related to the transistor 50.

[0094] As Figure 16 shown, after performing steps S12 and S13, the arithmetic unit 10 determines for each of the plurality of partitions CL whether each sampling data Sd is included in the safe operating area 70S (step S14). Step S14 is performed in the standard determination unit 14. As Figure 19As shown, in step S14, the standard determination unit 14 reads the double logarithmic curve graph of the safe operation area 70S created by the standard calculation unit 13 according to the partition CL determined by the data determination unit 12 (step S41). As the standard determination unit 14 does Figures 11 to 14 shown, it plots the sampling data Sd included in the partition CL determined in the data determination unit 12 on the double logarithmic curve graph (step S42). The standard determination unit 14 determines whether the plotted sampling data Sd is included in the safe operation area 70S (step S43). When the sampling data Sd is included in the safe operation area 70S, the standard determination unit 14 similarly determines the next sampling data Sd (step S45). On the other hand, when the sampling data Sd is not included in the safe operation area 70S, the standard determination unit 14 outputs the sampling data Sd to the waveform generation unit 15 (step S44) and similarly determines the next sampling data Sd (step S45).

[0095] The standard determination unit 14 performs step S14 until the determination of all the sampling data Sd included in the verification data group DG is completed. As long as the standard determination unit 14 determines all the sampling data Sd, it may determine the sampling data Sd in any order. The standard determination unit 14 may determine the sampling data Sd for each of multiple partitions CL, or may sequentially determine the sampling data Sd included in the verification data group DG in chronological order.

[0096] As described above, the verification method of the present embodiment includes: determining whether the verification data group DG of the sampling data Sd at each time of the current value flowing through the transistor 50 and the voltage value applied to the transistor 50 included within a specified time range TR satisfies the electrical standard; outputting the sampling data Sd determined not to satisfy the electrical standard in the verification data group DG; and automatically changing the electrical standard for determining the verification data group DG according to the determined partition CL.

[0097] As Figure 16 shown, after performing step S14, the arithmetic unit 10 generates a time waveform W showing the sampling data Sd not included in the safe operation area 70S and displays it on the display unit 30 (step S15). Step S15 is performed in the waveform generation unit 15. As Figure 20 shown, in step S15, the waveform generation unit 15 is as described above Figure 15In this way, the time waveform W of the verification data group DG is generated and displayed on the display unit 30 (step S51). The waveform generation unit 15 emphasizes and displays the sampled data Sd that is not included in the safe operation region 70S on the time waveform W (step S52). In step S52, the waveform generation unit 15, for example, changes the color of the sampled data Sd that is not included in the safe operation region 70S with respect to the sampled data Sd included in the safe operation region 70S and plots it on the time waveform W, thereby emphasizing and displaying the sampled data Sd that is not included in the safe operation region 70S on the time waveform W. In this way, the verification method of the present embodiment includes: generating the time waveform W of the current value and voltage value in the verification data group DG; and displaying the sampled data Sd that does not meet the electrical standard in the verification data group DG on the time waveform W.

[0098] According to the above, the operation verification of the verification device 100 is completed. By observing the time waveform W displayed on the display unit 30, the operator can easily confirm which part of the verification data group DG plotted on the time axis is not included in the safe operation region 70S, that is, does not meet the electrical standard.

[0099] At least a part of the functions of the respective components of the arithmetic unit 10 described above is realized, for example, by a processor such as a CPU executing a program stored in the storage unit 11, that is, software. In addition, at least a part of the functions of the respective components of the arithmetic unit 10 can be realized by hardware including circuit units such as LSI (Large Scale Integration), ASIC (Application Specific Integrated Circuit), FPGA (Field-Programmable Gate Array), and GPU (Graphics Processing Unit), or can be realized by the cooperation of software and hardware.

[0100] According to the present embodiment, the verification device 100 performs the operation verification of the circuit 40 including the transistor 50, and includes: a standard calculation unit 13 that calculates the electrical standard (safe operation region 70S) of the transistor 50 based on information related to the specifications of the transistor 50; and a standard determination unit 14 that determines the current value (drain current I d value) flowing through the transistor 50 and the voltage value (drain-source voltage V dsVerify whether the verification data group DG of the sampled data Sd at each time of the value) meets the electrical standard, and output the sampled data Sd in the verification data group DG that is determined not to meet the electrical standard. Therefore, by only inputting information related to the specifications of the transistor 50 into the verification device 100, the operator can automatically calculate the electrical standard of the transistor 50 and output the sampled data Sd in the verification data group DG that does not meet this electrical standard. Thus, without the operator personally inputting the electrical standard of the transistor 50 into the verification device 100, by only inputting a few necessary minimum values that can be easily read from a specification table or the like into the verification device 100, the operator can easily verify whether each sampled data Sd of the verification data group DG meets the electrical standard of the transistor 50. Therefore, different from the case where the operator himself inputs the electrical standard of the transistor 50, the accuracy of the electrical standard for determining the verification data group DG can be guaranteed. Thus, the accuracy of the operation verification of the circuit 40 including the transistor 50 can be guaranteed, and the man-hours required for this operation verification can be reduced.

[0101] In addition, the verification data group DG includes the sampled data Sd at each time of the current value flowing through the transistor 50 and the voltage value applied to the transistor 50 within a specified time range TR. Therefore, by knowing which sampled data Sd of the verification data group DG does not meet the electrical standard of the transistor 50, the operator can easily grasp at which position on the time axis the current value flowing through the transistor 50 and the voltage value applied to the transistor 50 do not meet the electrical standard when the circuit 40 operates within the specified time range TR. Thus, the operator can easily identify the reason why the operation of the circuit 40 does not meet the electrical standard of the transistor 50 and easily take countermeasures to make the operation of the circuit 40 meet the electrical standard of the transistor 50. Therefore, the circuit 40 including the transistor 50 can be easily designed.

[0102] In addition, according to the present embodiment, the verification device 100 includes a data determination unit 12 that calculates the drain current I in the verification data group DG d The slope dI of the value changing with time d / dt, and determines which partition CL among the multiple partitions CL divided based on the magnitude of the slope dI d / dt the respective sampled data Sd included in the verification data group DG belongs to. The standard calculation unit 13 can calculate the electrical standards corresponding to the multiple partitions CL respectively. The standard determination unit 14 automatically changes the electrical standard for determining the verification data group DG according to the partition CL determined by the data determination unit 12. As described above, when the drain current I d changes, the greater the absolute value of the slope dI d of the value of the drain current I changing with time d / dt, the greater the drain current I dThe shorter the length of the varying period, the smaller the absolute value of the slope dI d of the value of the drain current I d with respect to time dt, the longer the length of the period during which the drain current I d varies. Therefore, by dividing each sampled data Sd into a plurality of partitions CL according to the slope dI d / dt and determining each sampled data Sd using electrical criteria corresponding to each partition CL, it is possible to determine whether each sampled data Sd satisfies the electrical criteria based on the pulse application time applied to the transistor 50. Thus, it is possible to more accurately and appropriately perform the determination of the verification data group DG.

[0103] In addition, according to the present embodiment, based on the rated current value of the transistor 50, the rated voltage value of the transistor 50, the maximum value of the on-resistance of the transistor 50, the allowable loss P d of the transistor 50, the current value and voltage value related to the second breakdown of the transistor 50, the electrical criteria are calculated. Therefore, it is possible to easily and appropriately calculate the safe operating region 70S as the electrical criteria by the standard calculation unit 13.

[0104] In addition, according to the present embodiment, the standard calculation unit 13 adjusts the electrical criteria based on the case temperature T c which is the temperature related to the transistor 50. Therefore, for example, in a case where it is expected that the temperature of the transistor 50 becomes higher than normal during the operation of the circuit 40, by inputting the expected temperature into the verification device 100, it is possible to adjust the electrical criteria according to the expected temperature, that is, perform temperature derating. Thereby, it is possible to more accurately perform the operation verification of the circuit 40 including the transistor 50.

[0105] In addition, according to the present embodiment, the verification device 100 includes a waveform generation unit 15 that generates a time waveform W of the current value and voltage value in the verification data group DG. The waveform generation unit 15 displays the sampled data Sd that does not satisfy the electrical criteria in the verification data group DG on the time waveform W. Therefore, by observing the time waveform W displayed on the display unit 30, the operator can more appropriately grasp which part of the verification data group DG on the time axis does not satisfy the electrical criteria of the transistor 50.

[0106] Each of the above effects of the verification device 100 is also an effect that can be obtained by a verification method including a method corresponding to each configuration of the verification device 100.

[0107] According to at least one of the embodiments described above, the verification device is a verification device that verifies the operation of a circuit including a transistor. The verification device includes: a standard calculation unit that calculates the electrical standard of the transistor based on information related to the specifications of the transistor; and a standard determination unit that determines whether a verification data set including data of the current value flowing through the transistor and the voltage value applied to the transistor at each time within a specified time range satisfies the electrical standard, and outputs the data in the verification data set that is determined not to satisfy the electrical standard. Thereby, it is possible to ensure the accuracy of the operation verification of the circuit including the transistor and reduce the man-hours required for the operation verification.

[0108] The standard calculation unit can be of any configuration as long as it calculates the electrical standard of the transistor based on information related to the specifications of the transistor. The electrical standard can also be a standard other than the safe operating area as long as it can be used for the operation verification of the circuit including the transistor. The standard calculation unit can also calculate the electrical standard of the transistor based on information related to the specifications of the transistor by a method other than the above-described embodiments. The standard calculation unit can also calculate the electrical standard without using any one or more of the rated current value of the transistor, the rated voltage value of the transistor, the maximum value of the on-resistance of the transistor, the allowable loss of the transistor, the current value and voltage value related to the second breakdown of the transistor.

[0109] The data determination unit can also calculate the slope of the voltage value in the verification data set over time and determine which of the multiple partitions each data belongs to. The number of partitions divided based on the magnitude of the slope of the current value or voltage value over time is not particularly limited as long as it is two or more. The multiple partitions can also be divided based on the magnitude of the slope of the current value or voltage value over time and the length of the period during which the magnitude of the slope continuously persists. For example, when the transistor is in the on state, the magnitude of the slope is a value approximately close to zero, but when the length of the period during which such a slope continuously persists is small to a certain extent or more, the period during which the transistor is in the on state can be divided into a period corresponding to the case where a pulse current flows through the transistor. The multiple partitions may not be provided. The waveform generation unit can also generate a time waveform of only one of the current value and voltage value in the verification data set. The method by which the waveform generation unit displays the data that does not satisfy the electrical standard on the time waveform is not particularly limited.

[0110] The verification device may not include a storage unit. In this case, the verification device can also read in information related to the specifications of the transistor and the verification data set from a storage unit such as a server separately provided from the verification device via network communication or the like. The type of transistor whose operation is verified by the verification device and verification method of the embodiment is not particularly limited. The transistor can also be a transistor other than a field effect transistor such as a bipolar transistor.

[0111] Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and the scope equivalent thereto.

Claims

1. A verification device for verifying the operation of a circuit including a transistor, comprising: a standard calculation unit that calculates an electrical standard of the transistor based on information related to a specification of the transistor; and The standard determination unit determines whether the verification data group satisfies the electrical standard and outputs data in the verification data group that is determined not to satisfy the electrical standard. The verification data group includes data at each time of the current value flowing through the transistor and the voltage value applied to the transistor within a specified time range.

2. The verification device according to claim 1, wherein: The verification device includes a data determination unit that calculates the slope of the current value or the voltage value in the verification data group over time, and determines which partition of the plurality of partitions divided based on the size of the slope each data included in the verification data group belongs to. The standard calculation unit is capable of calculating the electrical standards corresponding to the plurality of partitions, respectively. The standard determination unit automatically changes the electrical standard used for determination of the verification data group according to the partition determined by the data determination unit.

3. The verification device according to claim 1, wherein: The standard calculation unit calculates the electrical standard based on a rated current value of the transistor, a rated voltage value of the transistor, a maximum value of on-resistance of the transistor, an allowable loss of the transistor, and at least one of the current value and the voltage value associated with a secondary breakdown of the transistor.

4. The verification device according to claim 1, wherein: The standard calculation unit adjusts the electrical standard based on a temperature associated with the transistor.

5. The verification device according to any one of claims 1 to 4, wherein: The verification device includes a waveform generating unit that generates a time waveform of at least one of the current value and the voltage value in the verification data group. The waveform generating unit displays data that does not satisfy the electrical standard in the verification data group on the time waveform.

6. A verification method for verifying the operation of a circuit including a transistor, comprising: calculating an electrical standard of the transistor based on information related to specifications of the transistor; determining whether a verification data set satisfies the electrical standard, the verification data set including data of each time of a current value flowing through the transistor and a voltage value applied to the transistor within a prescribed time range; and The data determined not to satisfy the electrical standard in the verification data group is output.

7. The verification method according to claim 6, wherein: include: Calculating the slope of the current value or the voltage value in the verification data group over time; Determine to which partition each data included in the verification data group belongs among the plurality of partitions divided based on the size of the slope; Calculating the electrical standards corresponding to the plurality of zones respectively; and The electrical standard used for judging the verification data group is automatically changed according to the judged partition.

8. The verification method according to claim 6, wherein: The verification method includes calculating the electrical standard based on the rated current value of the transistor, the rated voltage value of the transistor, the maximum value of the on-resistance of the transistor, the allowable loss of the transistor, and at least one of the current value and the voltage value related to the secondary breakdown of the transistor.

9. The verification method according to claim 6, wherein: The verification method includes adjusting the electrical standard based on a temperature associated with the transistor.

10. The verification method according to any one of claims 6 to 9, wherein: include: generating a time waveform of at least one of the current value and the voltage value in the verification data group; as well as The data that does not satisfy the electrical standard in the verification data group is displayed on the time waveform.

11. A program, wherein: A computer is caused to execute the verification method according to any one of claims 6 to 9.

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