A power management chip test analysis system

Abstract

The application relates to the technical field of chip testing, and discloses a power management chip test analysis system, which comprises a data acquisition unit, a data processing unit, a feature extraction unit, a performance analysis unit, a fault diagnosis unit and a result display unit. Comprehensive chip voltage, current and temperature data are acquired, unique preprocessing methods are used, interference is effectively filtered out, and the data accuracy is greatly improved. Through a scientific performance index extraction method, multiple performance indexes of the chip can be accurately obtained. In the performance evaluation link, the chip output voltage stability, current efficiency and overheating risk can be directly judged by comparison with a preset threshold. In the fault diagnosis aspect, based on a database constructed by a large number of known fault chip tests, combined with matching analysis, the chip fault can be efficiently judged and accurately positioned. The result display unit directly presents various analysis results, helps relevant personnel quickly understand the chip condition, and timely takes improvement, maintenance or replacement measures.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip testing, and in particular to a power management chip testing and analyzing system. BACKGROUND

[0002] In the complex system of modern electronic devices, the power management chip is the core hub, and its performance directly affects the overall performance of the device. From smartphones, tablets to industrial control devices, new energy vehicles, etc., various electronic devices are highly dependent on power management chips to achieve efficient power conversion and distribution, to ensure stable operation of the device, reduce energy consumption and prolong battery life. With the continuous expansion of electronic device functions and the continuous improvement of performance, the performance requirements for power management chips are becoming increasingly demanding. Not only must the voltage and current output be accurate and stable under various working conditions, but also high conversion efficiency must be achieved to reduce energy loss, and the chip temperature must be effectively controlled to avoid overheating and performance degradation or even failure. To meet these needs, it is essential to comprehensively and accurately test and analyze the performance of power management chips.

[0003] However, the current power management chip testing and analyzing technology has many shortcomings. In the traditional data collection process, it is difficult to capture voltage, current and temperature data from different parts of the chip in a comprehensive and high-precision manner, resulting in data loss or deviation, which affects the accuracy of subsequent analysis. In terms of performance index extraction, previous methods are mostly limited to simple calculations, and cannot deeply explore key performance characteristics under complex operating conditions of the chip. Evaluation and analysis methods are often not comprehensive enough, and can only make rough judgments on chip performance from a single dimension, and cannot comprehensively consider the correlation and influence between multiple performance indicators. Fault diagnosis is also a challenge, as there is a lack of systematic fault feature library and accurate matching algorithm, making it difficult to quickly and accurately locate the chip fault type and location. These problems seriously hinder the development of power management chips, restricting the improvement of product performance and reliability.

[0004] Therefore, it is an urgent need to develop a system that can comprehensively and accurately test and analyze power management chips to improve the quality and reliability of electronic devices. SUMMARY

[0005] The present application relates to the technical field of chip testing, and in particular to a power management chip testing and analyzing system.

[0006] The present application relates to the technical field of chip testing, and in particular to a power management chip testing and analyzing system.

[0007] A power management chip testing and analyzing system, comprising:

[0008] A data acquisition unit is configured to acquire various operation data from different parts of the power management chip to be tested, including voltage data, current data and temperature data of the power management chip;

[0009] A data processing unit is configured to pre-process the acquired operation data, remove interference and unify formats;

[0010] A feature extraction unit is configured to extract various performance indicators of the chip based on the pre-processed various operation data;

[0011] A performance analysis unit is configured to evaluate and analyze the power management chip according to the extracted performance indicators;

[0012] A fault diagnosis unit is configured to determine whether the power management chip has a fault and locate the fault position according to the extracted performance indicators;

[0013] A result display unit is configured to display the results obtained by the feature extraction unit, the performance analysis unit and the fault diagnosis unit to relevant personnel.

[0014] As a further scheme of the present application, the pre-processing manner is as follows:

[0015] Step C1, the voltage data, current data and temperature data of the power management chip are respectively marked as Vt, Lt and Tt, t = 1, 2, …, e, e represents the number of collection time nodes in a predetermined observation period, Vt, Lt and Tt respectively represent the voltage value, current value and temperature value of the power management chip at the tth collection time node; t t t t t t

[0016] Step C2, the voltage data of the power management chip is selected;

[0017] Then, the voltage data of the power management chip is filtered through the following formula:

[0018] The filtered voltage value V1t at the tth collection time node is calculated;

[0019] In the formula, t-1 is the previous collection time node of the tth collection time node, t+1 is the next collection time node of the tth collection time node, and the value range of t in the formula is 2, 3, …, e-1;

[0020] Step C3, the filtered current value and temperature value at each collection time node are calculated in the manner of Step C2.

[0021] As a further scheme of the present application, the performance indicator extraction manner is as follows:​​​​​​

[0022] Step G1, stability analysis:

[0023] Obtain the pre-processed voltage data V1 in the observation period t , and calculate the average value of the voltage data, and mark it as V1 p ;

[0024] Then combine the voltage data with its average value, calculate the standard deviation of the voltage data, and mark it as V1 b ;

[0025] Where,

[0026] Step G2, efficiency analysis:

[0027] First, at the same collection time node, obtain the input voltage and input current of the power management chip, and mark them as V in and L in , respectively;

[0028] Then calculate the input power P in of the power management chip by P in = V in × L in ;

[0029] Then, at the same collection time node, obtain the output voltage and output current of each output port of the power management chip, and mark them as V out，i and L out，i , respectively;

[0030] Where, i = 1, 2, … n, representing the number of all output ports of the power management chip;

[0031] Then calculate the output power P out of the power management chip by ;

[0032] Then calculate the current efficiency PX of the power management chip by ;

[0033] Step G3, performance analysis:

[0034] Obtain the pre-processed temperature data T1 in the observation period t , and calculate the average value of the temperature data, and mark it as T1 p ;

[0035] Where,

[0036] Then calculate the temperature efficiency TX of the power management chip by: Calculate the temperature change rate TC of the power management chip;

[0037] In the formula, s represents the interval length between two adjacent collection time nodes, and the interval length between each adjacent collection time node is the same.

[0038] As a further scheme of the application, the evaluation analysis method is as follows:

[0039] Step K1, calculate the standard deviation V1 of the voltage data corresponding to the power management chip to be tested b Compare with the preset voltage stability threshold value Vy:

[0040] If V1 b > Vy, it indicates that the output voltage of the power management chip is in an unstable state;

[0041] If V1 b ≤ Vy, it indicates that the stability of the output voltage of the power management chip is good;

[0042] Step K2, compare the current efficiency PX corresponding to the power management chip to be tested with the preset current efficiency threshold value Xy:

[0043] When PX≥Xy, it is determined that the current efficiency of the power management chip is high;

[0044] When PX<Xy, it is determined that the current efficiency of the power management chip is low;

[0045] Step K3, calculate the average value T1 of the temperature data corresponding to the power management chip to be tested p And compare the temperature change rate TC with the corresponding preset temperature threshold value Ty and temperature change threshold value TCy respectively:

[0046] When T1 p > Ty and TC>TCy, either of which is true, it is determined that the power management chip has an overheating risk;

[0047] When T1 p ≤ Ty and TC≤TCy are all true, it is determined that the power management chip does not have an overheating risk.

[0048] As a further scheme of the application, the fault judgment method is as follows:

[0049] Step D1, extract the pre-established fault database, wherein the fault database stores known fault types, corresponding fault feature vectors and fault occurrence position information;

[0050] Step D2: Obtain the performance indicators of the power management chip under test, then match and analyze them with the fault feature vectors in the fault database, and determine the diagnostic results of the power management chip under test.

[0051] As a further aspect of the present invention, the matching analysis method is as follows:

[0052] Step D2.1: Mark the various performance indicators of the power management chip under test as test feature vectors Fj, where j = 1, 2, ..., m, and m represents the number of performance indicators;

[0053] Step D2.2: Mark the performance indicators of the fault feature vectors corresponding to the same known fault type and known fault location in the fault database as [Fmin]. j，k Fmax j，k ], where k = 1, 2, ... g, and g represents the index of the fault feature vector corresponding to the same known fault type and known fault location in the fault database;

[0054] Step D2.3, Pass:

[0055]

[0056] Calculate the matching degree Rk between the test feature vector of the power management chip under test and the fault feature vectors corresponding to each known fault type and known fault location;

[0057] The matching degree Rk is then compared with the preset matching degree threshold Ry, and the known fault type and known fault location corresponding to Rk with the largest value of Rk > Ry are selected from the fault database as the diagnostic result.

[0058] As a further aspect of the present invention, the fault database is established as follows:

[0059] First, select several power management chips with known fault types and known fault locations, and conduct multiple tests and analyses on each of them:

[0060] The test and analysis method is as follows: First, the data acquisition unit acquires various operating data from the power management chip with known fault type and known fault location. Then, the data processing unit preprocesses the acquired operating data. Subsequently, the feature extraction unit extracts various performance indicators of the power management chip with known fault type and known fault location based on the preprocessed operating data.

[0061] Then, the multiple test analysis results of the power management chip of the related known fault type and known fault position are extracted, and the multiple test analysis results corresponding to the same known fault type and known fault position of the power management chip are extracted, and the extracted test analysis results are sorted and analyzed.

[0062] As a further scheme of the application, the fault database comprises fields corresponding to fault types, fault positions and fault feature vectors.

[0063] As a further scheme of the application, the sorting and analyzing mode is as follows:

[0064] The fault type of the related power management chip is imported into the field corresponding to the fault type in the fault database.

[0065] The fault position of the related power management chip is imported into the field corresponding to the fault position in the fault database.

[0066] From the extracted test analysis results, the maximum value and the minimum value corresponding to each performance index are extracted, and the corresponding fault performance index range is formed, and then the fault performance index range corresponding to each performance index is imported into the field corresponding to the fault feature vector as the fault feature vector.

[0067] The application has the following beneficial effects:

[0068] The application collects voltage, current and temperature data of different parts of the chip through the data acquisition unit, and provides rich information for chip state monitoring. The unique data preprocessing method filters the data at each time node through a specific formula, effectively removes interference, unifies the format, greatly improves the data accuracy and reliability, and lays a solid foundation for subsequent analysis.

[0069] The application accurately extracts voltage average, standard deviation, current efficiency, temperature average and change rate and other performance indicators from the preprocessed data through a series of steps such as stability analysis, efficiency analysis and performance analysis. These indicators comprehensively and accurately reflect the performance characteristics of the chip, and provide rich and accurate basis for chip performance evaluation.

[0070] The application compares the extracted performance indicators with the preset threshold value, which can scientifically and intuitively evaluate the key performance of the chip output voltage stability, current efficiency and overheating risk. The clear judgment standard enables the staff to quickly and accurately judge whether the chip performance meets the standard, and helps to control product quality.

[0071] The application can efficiently judge whether the chip is faulty and accurately locate the fault type and position by establishing a fault database and matching and analyzing the performance indicators of the chip to be tested with the fault feature vectors in the library. The fault database is based on a large number of known fault chip test analysis and construction, and has high reliability. The unique matching analysis method further improves the accuracy and efficiency of fault diagnosis by comparing the matching degree with the threshold value, and saves the time and labor cost of troubleshooting.

[0072] The application can intuitively present the feature extraction, performance analysis and fault diagnosis results to relevant personnel through the result display unit, facilitate timely understanding of the chip performance and fault conditions, and then take corresponding measures, such as improving the performance of the chip, repairing or replacing the faulty chip, improving product quality and production efficiency, and has important application value in actual production. BRIEF DESCRIPTION OF DRAWINGS

[0073] The application will be further described below with reference to the accompanying drawings.

[0074] Figure 1 is a system block diagram of a power management chip test analysis system of the application.

[0075] Figure 2 is a flowchart of a feature extraction unit in a power management chip test analysis system of the application. DETAILED DESCRIPTION

[0076] The technical solutions in the embodiments of the application will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the application. Obviously, the described embodiments are only part of the embodiments of the application, rather than all the embodiments. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the application.

[0077] Embodiment one

[0078] Please refer to Figure 1 and Figure 2 The application is a power management chip test analysis system, which comprises:

[0079] A data acquisition unit is configured to acquire various types of operation data from different parts of the power management chip to be tested.

[0080] The various types of operation data include voltage data, current data and temperature data of the power management chip.

[0081] In this embodiment, the voltage data is the voltage value of the chip in different working states collected in real time by connecting the voltage sensor to the input and output pins of the power management chip; the current data is the current sensor connected in series on the current transmission path of the power management chip; the temperature data is the temperature sensor installed on the surface and internal key heating area of the power management chip, and the working temperature of the chip is obtained;

[0082] The feature extraction unit is used to extract various performance indicators of the chip based on the collected various types of operation data.

[0083] The performance indicator extraction method is as follows:

[0084] Step G1, stability analysis:

[0085] The voltage data V1 collected in the observation period is obtained t , and the average value of the voltage data is calculated and marked as V1 p .

[0086] Then the standard deviation of the voltage data is calculated by combining the voltage data with its average value, and is marked as V1 b .

[0087] Among them,

[0088] Step G2, efficiency analysis:

[0089] First, the input voltage and input current of the power management chip are obtained at the same collection time node, and are marked as V in and L in respectively.

[0090] Then the input power P in of the power management chip is calculated by P in =V in ×L in .

[0091] Then the output voltage and output current of each output port of the power management chip are obtained at the same collection time node, and are marked as V out，i and L out，i respectively.

[0092] Among them, i=1, 2, ……n, indicating the number of all output ports of the power management chip.

[0093] Then the output power P of the power management chip is calculated by P out .

[0094] Then the current efficiency PX of the power management chip is calculated by PX .

[0095] Step G3, performance analysis:

[0096] Obtain the temperature data T1 collected in the observation period t , and calculate the average value of the temperature data, and mark it as T1 p ;

[0097] Wherein,

[0098] Then calculate the temperature change rate TC of the power management chip;

[0099] In the formula, s represents the interval length between two adjacent collection time nodes, and the interval length between each adjacent collection time node is the same;

[0100] The fault diagnosis unit is used to determine whether the power management chip has a fault and locate the fault position according to the extracted performance indicators;

[0101] The fault judgment mode is as follows:

[0102] Step D1, extract the pre-established fault database, wherein the fault database stores known fault types, corresponding fault feature vectors and fault position information;

[0103] Step D2, obtain each performance indicator corresponding to the power management chip to be tested, and then match and analyze it with the fault feature vector in the fault database, and the matching and analyzing mode is as follows:

[0104] Step D2.1, mark each performance indicator corresponding to the power management chip to be tested as a test feature vector Fj, wherein j=1, 2, …, m, and m represents the number of performance indicators;

[0105] In this embodiment, F1 represents the standard deviation of the voltage data corresponding to the power management chip to be tested, F2 represents the average value of the voltage data corresponding to the power management chip to be tested, F3 represents the current efficiency corresponding to the power management chip to be tested, F4 represents the average value of the temperature data corresponding to the power management chip to be tested, and F5 represents the temperature change rate corresponding to the power management chip to be tested;

[0106] Step D2.2, mark each performance indicator of the fault feature vector corresponding to the same known fault type and known fault position in the fault database as [Fmin j，k , Fmax j，k ], wherein k=1, 2, …, g, and g represents the serial number of the fault feature vector corresponding to the same known fault type and known fault position in the fault database; ​

[0107] StepD2.3、by:

[0108]

[0109] Calculate the matching degree Rk between the test feature vector of the power management chip to be tested and the fault feature vector corresponding to each same known fault type and known fault position;

[0110] Then compare the matching degree Rk with the preset matching degree threshold Ry, and select Rk> Ry from the fault database, and the known fault type and known fault position corresponding to the maximum Rk value as the diagnostic result;

[0111] Embodiment one constructs a power management chip test analysis system, which obtains voltage, current and temperature and other running data from different parts of the chip through the data acquisition unit, providing a basis for subsequent analysis. The feature extraction unit calculates the performance indicators of the chip based on the collected data, such as voltage stability, current efficiency and temperature change rate, etc., which comprehensively reflects the performance of the chip. The fault diagnosis unit uses the pre-established fault database to match and analyze the performance indicators and fault feature vectors, which can accurately judge whether the chip has a fault and locate the fault position, providing an effective means for chip quality detection and problem troubleshooting, which helps to improve the accuracy and efficiency of chip testing.

[0112] Embodiment two

[0113] Please refer to Figure 1 and Figure 2 As shown in the embodiment two of the present application, compared with embodiment one, the technical solution of the present embodiment is only different from that of embodiment one in that the present embodiment further comprises:

[0114] The performance analysis unit is used for evaluating and analyzing the power management chip according to the extracted performance indicators, and the evaluation and analysis method is as follows:

[0115] StepK1, the standard deviation V1 of the voltage data corresponding to the power management chip to be tested b is compared with the preset voltage stability threshold value Vy:

[0116] If V1 b > Vy, it indicates that the output voltage of the power management chip is in an unstable state;

[0117] If V1 b ≤ Vy, it indicates that the stability of the output voltage of the power management chip is good;

[0118] StepK2, compare the current efficiency PX of the power management chip to be tested with the pre-set current efficiency threshold value Xy:

[0119] When PX≥Xy, it is determined that the current efficiency of the power management chip is high;

[0120] When PX<Xy, it is determined that the current efficiency of the power management chip is low;

[0121] Step K3, the average value T1 of the temperature data corresponding to the power management chip to be tested p and the temperature change rate TC are compared with the corresponding preset temperature threshold Ty and temperature change threshold TCy respectively:

[0122] When T1 p >Ty and TC>TCy, it is determined that the power management chip has an overheating risk;

[0123] When T1 p ≤Ty and TC≤TCy, it is determined that the power management chip does not have an overheating risk;

[0124] Example two is based on example one, and a performance analysis unit is added. The unit compares the voltage standard deviation of the chip with the preset voltage stability threshold to judge the output voltage stability; compares the current efficiency with the current efficiency threshold to evaluate the current efficiency; compares the temperature average value and the temperature change rate with the corresponding threshold respectively to judge whether there is an overheating risk. This makes the system not only able to detect faults, but also to evaluate the performance state of the chip in multiple dimensions, helping users to better understand the performance of the chip, so as to reasonably select and use the chip in different application scenarios, and improve the reliability and adaptability of chip application.

[0125] Example three

[0126] Please refer to Figure 1 and Figure 2 As example three of the present application, compared with example one and example two, the technical solution of the present embodiment is to combine the above-mentioned example one and example two, the difference between the technical solution of the present embodiment and example one and example two is only that the present embodiment further includes:

[0127] A result display unit for displaying the results obtained by the feature extraction unit, the performance analysis unit and the fault diagnosis unit to relevant personnel.

[0128] Embodiment three integrates the schemes of embodiment one and embodiment two, and adds a result display unit. This unit visually displays the results obtained by the feature extraction unit, performance analysis unit and fault diagnosis unit to the relevant personnel, making the test analysis results easier to obtain and understand. Whether it is chip performance index data, performance evaluation conclusion or fault diagnosis information, it can be presented in time and clearly, greatly improving the information transmission efficiency, facilitating technical personnel to make decisions based on these results, such as chip improvement direction, use scene adjustment, etc., improving the practicability and convenience of the whole chip test analysis process.

[0129] Embodiment four

[0130] Please refer to Figure 1 and Figure 2 As embodiment four of the present application, compared with embodiment one, embodiment two and embodiment three, the difference between this embodiment and embodiment one, embodiment two and embodiment three is that this embodiment further includes:

[0131] A data processing unit for pre-processing the collected running data, removing interference and unifying format;

[0132] The pre-processing method is as follows:

[0133] Step C1, the voltage data, current data and temperature data of the power management chip are respectively marked as V t , L t and T t , t = 1, 2, ……e, e represents the number of collection time nodes in a predetermined observation period, V t , L t and T t respectively refer to the voltage value, current value and temperature value of the power management chip at the tth collection time node;

[0134] Step C2, select the voltage data of the power management chip;

[0135] Then pass through;

[0136] Calculate the filtered voltage value V1t at the tth collection time node;

[0137] In the formula, t-1 is the previous collection time node of the tth collection time node, t+1 is the next collection time node of the tth collection time node, and in the formula, the value range of t is 2, 3, ……e-1;

[0138] Step C3, according to the method of Step C2, calculate the filtered current value and temperature value at each collection time node;

[0139] The feature extraction unit extracts performance indicators of the chip based on the preprocessed various types of operation data.

[0140] Embodiment four is based on the previous embodiments, and a data processing unit is added. This unit preprocesses the collected voltage, current and temperature data, removes interference through a specific algorithm and unifies the format to obtain filtered data. This process effectively improves the data quality, so that the performance indicators extracted by the feature extraction unit based on the preprocessed data are more accurate and reliable, reducing the influence of data noise and inconsistent formats on the analysis results, thereby improving the stability of the entire test analysis system and the credibility of the analysis results, providing a more solid data foundation for chip performance evaluation and fault diagnosis.

[0141] Embodiment five

[0142] Please refer to Figure 1 and Figure 2 As embodiment five of the present application, compared with embodiment one, embodiment two, embodiment three and embodiment four, the technical solution of the present embodiment is to combine the above-mentioned embodiment one, embodiment two, embodiment three and embodiment four, the difference between the technical solution of the present embodiment and embodiment one, embodiment two, embodiment three and embodiment four is only that the establishment method of the fault database is proposed in the present embodiment, which is as follows:

[0143] First, select a number of power management chips with known fault types and known fault locations, and test and analyze them multiple times respectively:

[0144] The test and analysis method is to first acquire various types of operation data on the power management chips with known fault types and known fault locations through the data acquisition unit, then preprocess the collected operation data through the data processing unit, and then extract performance indicators of the power management chips with known fault types and known fault locations based on the preprocessed various types of operation data through the feature extraction unit;

[0145] Among them, the fault database contains fields corresponding to fault types, fault locations and fault feature vectors.

[0146] Then, extract the multiple test and analysis results of the related power management chips with known fault types and known fault locations, and extract the corresponding multiple test and analysis results of the same power management chips with known fault types and known fault locations, and then arrange and analyze the extracted test and analysis results, the arrangement and analysis method is as follows:

[0147] The fault types of the related power management chips are imported into the fault type corresponding field in the fault database;

[0148] The fault position of the related power management chip is introduced into the fault database in a field corresponding to the fault position.

[0149] From the extracted test analysis results, the corresponding maximum and minimum values of each performance indicator are extracted, and they are combined to form the corresponding fault performance indicator range. Then, the fault performance indicator range corresponding to each performance indicator is introduced into the field corresponding to the fault feature vector as the fault feature vector.

[0150] Embodiment five proposes a method for establishing a fault database. By selecting a plurality of power management chips with known fault types and positions for multiple tests and analysis, the running data is obtained and processed and features are extracted after processing and feature extraction, and the test results are analyzed. The fault type, fault position and fault performance indicator range extracted from the test results, i.e. the fault feature vector, are introduced into the corresponding fields of the fault database. This establishment method makes the fault database have rich and accurate data support, can more accurately match the chip performance indicators, improve the accuracy of the fault diagnosis unit in judging and positioning the fault, and provide strong guarantee for the reliability of the chip test and analysis system.

[0151] Embodiment six

[0152] Please refer to Figure 1 and Figure 2 As embodiment six of the present application, compared with embodiment one, embodiment two, embodiment three, embodiment four and embodiment five, the technical solution of the present embodiment is to combine the above-mentioned embodiment one, embodiment two, embodiment three, embodiment four and embodiment five.

[0153] Embodiment six integrates the schemes of the previous five embodiments and has the advantages of each embodiment. Through data acquisition to obtain comprehensive running data, the data processing unit improves the data quality, the feature extraction unit accurately calculates the performance indicators, the performance analysis unit multi-dimensionally evaluates the chip performance, the fault diagnosis unit accurately judges the fault, the result display unit intuitively presents the results, and the perfect fault database establishment method. The whole system forms a complete, efficient and accurate power management chip test and analysis system, from data acquisition to result application, which fully guarantees the smooth development of chip test and analysis work, greatly improves the efficiency, accuracy and practicability of chip test and analysis, and meets the needs of different users for chip performance detection and fault troubleshooting.

[0154] The above formulas are dimensionless values, and the formulas are obtained by software simulation of a large amount of data to obtain the most real situation. The preset parameters and threshold values in the formula are set by the person skilled in the art according to the actual situation.

[0155] The above merely provides the specific implementation of the present application, but the protection scope of the present application is not limited to this. Any person skilled in the art can easily think of the changes or replacements within the technical range disclosed by the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A power management chip test analysis system, characterized by, Comprise: Data acquisition unit, for obtaining various types of running data from different parts of the power management chip to be tested, including voltage data, current data and temperature data of the power management chip; Feature extraction unit, for extracting various performance indicators of the chip in the various types of running data obtained from different parts of the power management chip to be tested; the mode is to calculate the standard deviation of the voltage data in the observation period; at the same time, the input voltage, input current, output voltage and output current of the power management chip to be tested are calculated to obtain the input power and output power, and then the current efficiency is calculated; also by calculating the average value of the temperature data in the observation period, and combining the adjacent collection time interval length to calculate the temperature change rate; Fault diagnosis unit, the performance indicators of the power management chip to be tested are marked as test feature vectors, the matching degree of the test feature vectors and each fault feature vector in the pre-established fault database is calculated, and then the matching degree and the corresponding preset matching degree threshold are used to determine the fault type and fault position corresponding to the power management chip to be tested; wherein, the fault database contains known fault type, corresponding fault feature vector and fault position information; The matching analysis mode is as follows: StepD2.1, mark the various performance indicators of the power management chip to be tested as test feature vectors Fj, wherein j=1, 2, ……m, m represents the number of performance indicators; StepD2.2, mark each performance index of the fault feature vector corresponding to the same known fault type and known fault location in the fault database as [Fmin j，k , Fmax j，k ], wherein k = 1, 2, …, g, and g represents the serial number of the fault feature vector corresponding to the same known fault type and known fault location in the fault database; StepD2.3, by: Calculate the matching degree Rk between the test feature vector of the power management chip to be tested and each fault feature vector corresponding to the same known fault type and known fault position; Then compare the matching degree Rk with the preset matching degree threshold Ry, and select the known fault type and known fault position corresponding to the maximum Rk from the fault database as the diagnosis result.

2. The power management chip test analysis system of claim 1, wherein, The extraction mode of performance indicators is as follows: StepG1, stability analysis: Obtaining the pre-processed voltage data V1 in the observation period t and calculating the average value of the voltage data, and marking it as V1 p ; The voltage data is then combined with its average value, the standard deviation of the voltage data is calculated and is labeled as VI b ; StepG2, efficiency analysis: First, at the same acquisition time node, the input voltage and input current of the power management chip are acquired, and are marked as V in and L in , respectively. Next, the input power P of the power management chip is calculated in ; Then at the same acquisition time node, the output voltage and output current of each output port of the power management chip are acquired, and are marked as V out，i and L out，i ; Wherein, i=1, 2, ……n, represents the number of all output ports of the power management chip; Thereby passing , the output power P of the power management chip is calculated out ; Afterwards, the current efficiency PX of the power management chip is calculated by ​ StepG3, performance analysis: Obtaining pre-processed temperature data T1 in an observation period t and calculating the average value of the temperature data and marking it as T1 p ; Then, the temperature change rate TC of the power management chip is calculated by: ​ Wherein, s represents the interval length between two adjacent collection time nodes, and the interval length between each adjacent collection time node is the same, and e represents the number of collection time nodes in the predetermined observation period.

3. The power management chip test analysis system of claim 2, wherein, The fault judgment mode is as follows: StepD1, extract the pre-established fault database, wherein the fault database stores the known fault type, corresponding fault feature vector and fault position information; StepD2, obtain the various performance indicators of the power management chip to be tested, and then match them with the fault feature vectors in the fault database, and determine the diagnosis result of the power management chip to be tested.

4. The power management chip test analysis system of claim 1, wherein, Also includes: Data processing unit, for pre-processing the collected running data, the pre-processing mode is as follows: Step C1: Label the voltage, current, and temperature data of the power management chip as V. t L t and T t t=1, 2, ..., e, where e represents the number of data collection points within the predetermined observation period, V t L t and T t These refer to the voltage, current, and temperature values ​​of the power management chip at the t-th acquisition time node, respectively. StepC2, select the voltage data of the power management chip; followed by; ; Calculate the filtered voltage value V1t at the tth collection time node; In the formula, t-1 is a preceding collection time node of the tth collection time node, t+1 is a following collection time node of the tth collection time node, and the value range of t is 2, 3, …, e-1; Step C3, in the manner of Step C2, the filtered current value and temperature value at each collection time node are calculated; The feature extraction unit extracts various performance indicators of the power management chip from the preprocessed various types of operation data.

5. The power management chip test analysis system of claim 1, wherein, Further comprising: The performance analysis unit is configured to evaluate and analyze the power management chip according to the extracted performance indicators; the evaluation and analysis manner is as follows: Step K1, comparing the standard deviation of the voltage data corresponding to the to-be-tested power management chip with a preset voltage stability threshold value, and determining whether the voltage of the power management chip is stable according to the comparison result: Step K2, comparing the current efficiency corresponding to the to-be-tested power management chip with a preset current efficiency threshold value, and determining the current efficiency of the power management chip according to the comparison result: Step K3, comparing the average value of the temperature data corresponding to the to-be-tested power management chip and the temperature change rate with the corresponding preset temperature threshold value and temperature change threshold value, respectively, and determining whether the power management chip has an overheating risk according to the comparison result.

6. The power management chip test analysis system of claim 5, wherein, In Step K1: If the standard deviation of the voltage data exceeds the voltage stability threshold value, it indicates that the output voltage of the power management chip is in an unstable state; otherwise, it indicates that the stability of the output voltage of the power management chip is good.

7. The power management chip test analysis system of claim 5, wherein, In Step K2: When the current efficiency is greater than or equal to the current efficiency threshold value, it is determined that the current efficiency of the power management chip is high; otherwise, it is determined that the current efficiency of the power management chip is low.

8. The power management chip test analysis system of claim 5, wherein, In Step K3: When the average value of the temperature data does not exceed the temperature threshold value, and the temperature change rate does not exceed the temperature change threshold value, it is determined that the power management chip does not have an overheating risk; otherwise, it is determined that the power management chip has an overheating risk.

9. The power management chip test analysis system of claim 5, wherein, Further comprising: The result display unit is configured to display the results obtained by the feature extraction unit, the performance analysis unit and the fault diagnosis unit to relevant personnel.

Images