Test vector generation method, system and computer-readable storage medium

Abstract

The present invention provides a test vector generation method, comprising: obtaining a chip functional test instruction, and parsing the task content and task input parameters contained in the functional test instruction; selecting a corresponding instruction template based on the task content, calling the instruction template, assigning an instruction register value, and obtaining a TDI data sequence and TDO data based on the corresponding address parameters and write / read data in the task input parameters; the instruction template is created based on a jtag protocol, an ADI protocol, and a data transmission protocol of a chip test circuit, and the instruction template is associated with a jtag test driver function; calling the jtag test driver function based on the instruction register value, the TDI data sequence, and the TDO data, and outputting the functional test instruction content as a combination of a TDI signal, a TCK signal, a TMS signal, and a TDO signal at different times. The present invention also provides a test vector generation system and a computer-readable storage medium.

Description

Technical Field

[0001] The present invention belongs to the technical field of chip testing, and in particular relates to a test vector generation method, system and computer-readable storage medium. Background Art

[0002] When performing functional testing on a chip on ATE (Automatic Test Equipment), a corresponding function pattern (functional test vector) is required. Typically, the verification department develops a testbench and test cases, then simulates to generate waveform files (such as Value Change Dump files, also known as VCD files, which are standard waveform files). These simulated waveform files are then converted into WGL files (WGL: Wave Generation Language, a format used to describe functional test patterns in automatic test equipment) or STILFIL (Standard Test Interface Language). However, the waveform files also record glitches. Furthermore, during ATE testing, if you want to temporarily modify the function pattern, you need to re-modify the test cases and regenerate the waveform file, a time-consuming process.

[0003] ARM (Advanced RISC Machine) is a family of processors designed based on the Reduced Instruction Set (RISC) principle. ARM architecture SoC chips (System on Chip) are a solution that integrates the core functions of a computer into a single chip. These chips are widely used in smartphones, tablets, embedded systems, and other electronic devices that require a balance between high performance and low power consumption.

[0004] The ARM debug system consists of components such as the debug interface, debug access port (DAP), cross trigger interface (CTI), embedded trace macrocell (ETM), trace funnel (a component of the CoreSight architecture used to manage and merge trace data streams from multiple sources), and TPIU (trace port interface unit), along with the ARM and DSP (Digital Signal Processing) processors. The debugger connects to the target system through the JTAG (Joint Test Action Group) interface, an international standard test protocol, and then sends debug commands to the DAP through the JTAG interface.

[0005] In order to simplify the process of generating functional test vectors for SoC chips based on ARM architecture and to facilitate the modification of functional test vectors, it is necessary to design a method based on ARM debugging system that can quickly generate functional test vectors. Summary of the Invention

[0006] The present invention provides a test vector generation method and system, which directly converts chip function test instructions into function test vectors based on the JTAG protocol.

[0007] The present invention also provides a computer-readable storage medium for executing the test vector generation method.

[0008] Other purposes and advantages of the present invention can be further understood from the technical features disclosed in the present invention.

[0009] To achieve one or part or all of the above-mentioned purposes or other purposes, a technical solution of the present invention provides a test vector generation method, the method comprising: obtaining a chip functional test instruction and parsing the task content and task input parameters contained in the functional test instruction; selecting a corresponding instruction template based on the task content, calling the instruction template, assigning a value to an instruction register, and obtaining a TDI data (input data) sequence and TDO data (output data) based on the corresponding address parameters and write / read data in the task input parameters; the instruction template is created based on the jtag protocol, the ADI protocol (ARM Debug Interface, a standardized debug interface protocol defined by ARM, which provides hardware-level debugging support for the processor, usually implemented through the JTAG or SWD protocol, and is a bridge between the debugging tool and the processor core) and the data transmission protocol of the chip test circuit, and the instruction template is associated with a jtag test driver function; calling the jtag test driver function based on the instruction register value, the TDI data sequence and the TDO data, and outputting the functional test instruction content as a combination of a TDI signal, a TCK signal (clock signal), a TMS signal (mode selection signal) and a TDO signal at different times.

[0010] According to the basic tasks that need to be performed when the chip to be tested is tested based on the test protocol, multiple basic instruction templates are created. Each basic instruction template performs an instruction task. Multiple different basic instruction templates are combined to realize different test functions of the chip.

[0011] The basic instruction template includes at least a write instruction to a DP port (Debug Port), a read instruction to a DP port, a write instruction to an AP port (Access Port), and a read instruction to an AP port.

[0012] The basic instruction template includes a write instruction to the AP port on the ahb bus (one of the AMBA bus protocols) and a read instruction to the AP port on the ahb bus; as well as a write instruction to the DP port on the ahb bus and a read instruction to the DP port on the ahb bus; the write instruction to the AP port on the ahb bus and the read instruction to the AP port on the ahb bus are further converted into a read instruction and a write instruction to the AP port, and the write instruction to the DP port on the ahb bus and the read instruction to the DP port on the ahb bus are further converted into a read instruction and a write instruction to the DP port.

[0013] Based on the task content contained in the functional test instruction, the corresponding basic instruction template is selected, and the functional test instruction is converted into a read and write instruction for the AP port and DP port on the chip according to the basic instruction template; the converted read and write instruction for the AP port and DP port on the chip is further associated with the jtag test driver function. Alliance .

[0014] According to the instruction task executed by the basic instruction template, the instruction register value is assigned; according to the jtag protocol, ADI protocol and the data transmission protocol of the chip test circuit, the intermediate variables are set and the intermediate variables are assigned to the TDI data sequence or TDO data; the intermediate variables are connected to the read instruction and write instruction of the AP port created as well as The address parameters required for the read and write instructions of the DP port are related to the write / read data.

[0015] The jtag test driver function inputs the TMS signal and controls the state machine to sequentially enter the IR register scanning state, the Capture-IR state (the system captures or loads a predefined fixed value into the instruction register) and the Shift-IR state (the system shifts the new instruction into the instruction register bit by bit through the TDI pin, and removes the old data bit by bit through the TDO pin). The IR register is jointly operated through the input TMS signal and the TCK signal. In the Shift-IR state, the assigned instruction register value is filled bit by bit starting from the low bit according to the TDI data sequence format to output the TDI signal, thereby obtaining the combination of the TDI signal, the TMS signal, the TCK signal and the TDO signal at different times.

[0016] The instruction template adds a tail identifier to the data expected to be read in the functional test instruction and outputs it as TDO data. The jtag test driver function simply fills the TDO data generated by the instruction template and then outputs it.

[0017] When the basic instruction template is used to execute the task of accessing the DP port, the instruction register is assigned the value 0b1010; when the basic instruction template is used to execute the task of accessing the AP port, the instruction register is assigned the value 0b1011; the jtag test driver function obtains the instruction register value assigned by the instruction template, and fills the assigned instruction register value bit by bit starting from the low bit according to the TDI data sequence format to output the TDI signal.

[0018] The data transmission protocol of the chip test circuit includes the AMBA bus protocol, and the DAP debugger accesses the system resources on the chip based on the AMBA bus protocol.

[0019] Another technical solution of the present invention provides a test vector generation system, including: a test instruction parsing module, which parses the input functional test instruction and outputs the task content and task input parameters contained in the functional test instruction; a test vector generation module, which selects a corresponding instruction template based on the task content, calls the instruction template, assigns the instruction register value, and obtains the TDI data sequence and TDO data according to the corresponding address parameters and write / read data in the task input parameters; the instruction template is created based on the jtag protocol, the ADI protocol and the data transmission protocol of the chip test circuit, and the instruction template is associated with the jtag test driver function; the jtag test driver function is called according to the instruction register value, the TDI data sequence and the TDO data, and the functional test instruction content is output as a combination of TDI signal, TCK signal, TMS signal and TDO signal at different times.

[0020] Another technical solution of the present invention provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, the steps of the test vector generation method described above are implemented.

[0021] Compared with the prior art, the present invention has the following advantages: the present invention parses the task content and write / read data included in the functional test instruction to obtain the instruction register value, TDI data sequence, and TDO data, and calls the JTAG test driver function in the instruction template based on the instruction register value, TDI data sequence, and TDO data, and uses the instruction template to convert the functional test instruction into a test vector output. The present invention does not require simulation to generate a waveform file and then convert it into a test vector, and has the advantage of high test vector generation efficiency. It also solves the problem of inaccurate acquisition clock affecting test vector output during the VCD generation process of the simulation file when generating test vectors.

[0022] In order to make the above and other objects, features and advantages of the present invention more clearly understood, preferred embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0024] Figure 1 This is a flow chart of the test vector generation method of the present invention.

[0025] Figure 2 This is a schematic diagram of the debugger of the present invention implementing system debugging and control on hardware.

[0026] Figure 3 This is a schematic diagram of the hardware connection between the JTAG-DP of the present invention and an external debugger.

[0027] Figure 4 This is an architecture diagram of an ARM debugging system of the present invention.

[0028] Figure 5 This is a schematic diagram of the working state of the DBGTAPSM state machine of the present invention.

[0029] Figure 6 This is a diagram of the calling relationship of the created instruction template. DETAILED DESCRIPTION

[0030] The foregoing and other technical aspects, features, and functions of the present invention are clearly presented in the following detailed description of a preferred embodiment with reference to the accompanying drawings. Directional terms such as up, down, left, right, front, and back, used in the following embodiments, are intended solely to refer to the directions in the accompanying drawings. Therefore, the directional terms used are for illustrative purposes only and are not intended to limit the present invention.

[0031] Example 1

[0032] Embodiment 1 provides a test vector generation method, which includes: obtaining a chip functional test instruction, and parsing the task content and task input parameters contained in the functional test instruction; selecting a corresponding instruction template based on the task content, calling the instruction template, assigning an instruction register value, and obtaining a TDI data sequence and TDO data based on the corresponding address parameters and write / read data in the task input parameters; the instruction template is created based on the jtag protocol, the ADI protocol and the data transmission protocol of the chip test circuit, and the instruction template is associated with a jtag test driver function; calling the jtag test driver function based on the instruction register value, the TDI data sequence and the TDO data, and outputting the functional test instruction content as a combination of TDI signal, TCK signal, TMS signal and TDO signal at different times.

[0033] Among them, the obtained functional test instructions (also called functional test outputs) are developed by technical developers based on the functions to be implemented by the chip. The functional test instructions drive the tested chip to perform specific operations and output the corresponding instruction execution results to verify whether the chip's functions meet the requirements.

[0034] A test vector generation method of the first embodiment is explained in detail below with reference to the accompanying drawings.

[0035] The test vector generation method of the present invention is used for outputting functional test vectors of SoC chips of ARM architecture, and outputs functional test instructions as external interface test vectors of jtag interface according to the jtag protocol in the ARM debugging system architecture.

[0036] Specifically, if Figure 1 As shown, the following steps are included:

[0037] Step 1: Create instruction templates based on the JTAG protocol, ADI protocol, and the data transmission protocol of the chip test circuit.

[0038] See also Figure 4An architecture diagram of an ARM debugging system. The ARM debugging system includes CoreSight components (an on-chip debugging and tracing system developed by ARM) such as the debug interface (JTAG port), DAP debugger, CTI (Cross Trigger Interface), ETM (Embedded Trace Macrocell), Trance Funnel (trace funnel, which merges or distributes trace data from multiple sources), and TPIU (Trace Port Interface Unit, which is responsible for outputting trace data from inside the chip to external devices). The debugger is connected to the target board through the JTAG interface, and then sends debugging commands to the DAP through the interface. After receiving the command, the DAP will process it according to whether it is a DP command or an AP command: 1) If it is a DP command, the DAP will directly process it and return the result. For example, it can be used to obtain DAP information, set the AP address, terminate transaction access, etc. 2) If it is an AP command, the command will be sent to the designated AP access port (memory access port MEM-AP or JTAG access port JTAG-AP). Taking the AP access port MEM-AP as an example, it will access the corresponding debug bus or system bus according to the AMBA bus protocol, and then implement operations on coresight components, CPU and other related registers, or read and write memory values. Figure 4 For example, Figure 4 The DAP debugger accesses the CoreSight component through the Debug APB protocol. The Debug APB protocol is a debugging bus protocol in the ARM architecture and is part of the ARM AMBA (Advanced Microcontroller Bus Architecture) bus family. It is mainly used to communicate with the debug logic inside the processor (such as debug registers, debug interfaces, etc.) and is one of the core components of the ARM processor debugging function.

[0039] In actual chip design, the data transmission protocol may also be other bus protocols, such as Ahb protocol.

[0040] The above functions are implemented through a series of components and specifications, including:

[0041] 1) The debugger and chip connection port use the JTAG protocol or SWD protocol (Serial Wire Debug, serial debugging protocol);

[0042] 2) ADI specification (ARM Debug Interface), which specifies how the debugger accesses the DP layer and AP layer. Figure 2 A diagram illustrating how a debugger implements system debugging and control in hardware, including a display controller (DP), multiple access points (APs) connected to the DP, and system resources connected to the APs. The debugger connects to the DP via a physical interface (typically a JTAG or SWD interface) and can directly access DP information or select a connected AP through DP registers, thereby accessing the corresponding system resources through the AP.

[0043] The debugger in the first embodiment is connected to the DP via jtag in hardware, see Figure 3 The debugger of the ARM architecture debugging system connects to the target board via the JTAG interface, through which debug commands are sent to the debugger. After receiving a command, the debugger processes it separately, depending on whether it is sent to the DP (Debug port, the main entry point for communication between the debugger and the target hardware, responsible for managing the debug connection and providing a mechanism for resetting the system, controlling execution, and communicating with one or more Access ports. DP can be implemented through the JTAG physical interface) port or the AP (Access port, allowing the debugger to access different components on the chip, such as system memory and peripherals). If it is a DP command, the debugger processes it directly and returns the result. If it is an AP command, the command is sent to JTAG-DP and then sent to the AP via JTAG-DP.

[0044] The ADI protocol specifies a layered system consisting of the following layers: I. jtag or SWD physical layer; II. jtag protocol or SWD protocol layer, which is used to manage the jtag or SWD state machine; III. jtag or SWD data link layer, which is used to perform DP register and AP register access; IV. AP layer, which is used to access one or more subsystems in the SOC.

[0045] 3) The coresight component includes definitions of various on-chip debugging components, such as DP, APB-AP (APB protocol access AP port), AXI-AP (AXI protocol access AP port), etc.

[0046] 4) The CPU architecture defines the CPU core's support for debugging capabilities, such as halting processor execution and single-step debugging.

[0047] Combine Figure 2 As can be seen from the above analysis, whether it is the CoreSight component, CPU or system memory, they are all bus resources for the AP (accessing system resources through the ARM AMBA bus). The debugger can debug and control the system by simply controlling the resource address corresponding to the AP operation.

[0048] When designing the JTAG test circuit on the periphery of the chip, the corresponding peripheral test circuit will be designed based on the requirements of the JTAG protocol, the ADI protocol, and the AMBA bus protocol (other data transmission protocols can also be used according to the actual circuit design requirements. Example 1 uses the AMBA bus protocol as an example for explanation). The instruction template is created based on the JTAG protocol, the ADI protocol, and the AMBA bus protocol. Among them, not all peripheral test circuits involve the AMBA bus structure. For example, in the design of chip peripheral circuits, only the DAP debugger accesses chip resources through the AMBA bus. In this case, the instruction template is created based on the requirements of the AMBA bus protocol. The purpose of creating the instruction template is to reversely deduce and calculate the combination of data and signals input to the JTAG based on the tasks to be implemented by the functional test instructions and the relevant parameters, including a set of data sequences including TDI, TMS, TCK, and RST interface signals and the expected TDO output results, so as to realize chip automation testing or simulation testing on ATE equipment.

[0049] When creating instruction templates, multiple basic instruction templates need to be created based on the basic functions that need to be executed during the test of the chip to be tested. Each basic instruction template performs an instruction task. Multiple different basic instruction templates are combined to implement different chip test functions. Based on the above explanation of the debugging process of ARM architecture debugging, the debugger needs to send corresponding commands to the DP port or the AP port when performing different debugging tasks. Therefore, the created basic instruction templates must at least include write instructions to the DP port, read instructions from the DP port, write instructions to the AP port, and read instructions from the AP port.

[0050] If there is an ahb bus in the ARM architecture (one of the AMBA buses, used for high-performance, high-clock frequency system structures, the amb bus is designed based on design requirements and performance requirements), the created basic instruction template also needs to include write instructions to the AP port on the ahb bus and read instructions to the AP port on the ahb bus; as well as write instructions to the DP port on the ahb bus and read instructions to the DP port on the ahb bus; at the same time, the write instructions to the AP port on the ahb bus and the read instructions to the AP port on the ahb bus need to be further converted into read instructions and write instructions to the AP port, and the write instructions to the DP port on the ahb bus and the read instructions to the DP port on the ahb bus need to be further converted into read instructions and write instructions to the DP port.

[0051] The following uses code as an example (for the protocol mentioned above, a specific circuit structure is designed, corresponding to a specific instruction template code. Here, only the instruction template corresponding to a specific circuit structure is described. In practice, a specific circuit can be designed according to the protocol requirements, and then a specific instruction template can be created) to illustrate the basic instruction template. The code is before "#", and the meaning of the code is after "#".

[0052] Read instruction for AP port on ahb bus:

[0053] jtag_ahb_ap_read(addr, data); #Read instruction for AP port on ahb bus;

[0054] jtag_write_ap("32'h04", addr); # Pass the values ​​of 32'h04 and bits 31 to 0 of the addr address as parameters to the jtag_write_ap function;

[0055] jtag_read_ap("32'h0c", data); # Pass 32'h0c and data as parameters to the jtag_read_ap function.

[0056] Write instructions to the AP port on the ahb bus:

[0057] jtag_ahb_ap_write_data(addr, data); #Write instruction to the AP port on the ahb bus;

[0058] jtag_write_ap("32'h04", addr); # Pass the values ​​of 32'h04 and bits 31 to 0 of the addr address as parameters to the jtag_write_ap function;

[0059] jtag_read_ap("32'h0c", data); # Pass 32'h0c and data as parameters to the jtag_read_ap function.

[0060] Write instructions for AP port:

[0061] jtag_write_ap(addr, data); #Write instruction to ap port, #Pass addr address and data as parameters to jtag_write_ap function;

[0062] delay_time:5000ns; #Set delay time;

[0063] value=int(addr)&int(32'hffff_fff0); #The specific operation of the above function: perform an AND operation on the addr parameter and 32'hffff_fff0, retain the high 28 bits and assign them to the intermediate variable value;

[0064] jtag_dp_wr(2'd2, value, "35'bx100"); #pass the three parameters 2'd2, value, "35'bx100" to another dp write function;

[0065] delay_time:3000ns; #Set delay time;

[0066] value=addr[3:2]; assign the result of the addr address slicing operation to the intermediate variable value;

[0067] jtag_ap_wr(value, data, 35'bx100); #The following are the specific operations of the above jtag_ap_wr function.

[0068] jtag_ap_wr(addr, data, tdo_data);

[0069] tdi_data=data+addr+"1'b0";#tdi_data assignment;

[0070] ir_data="4'b1011"; #tdi_data is assigned a fixed value based on the AP port being accessed;

[0071] tdo_data=tdo_data;

[0072] jtag_process(ir_data, tdi_data, tdo_data); #Pass the three parameters ir_data, tdi_data, and tdo_data to the jtag_process function, and output the TDI, TMS, TCK, and TDO vectors corresponding to the jtag interface; the TDO value here is the theoretical output value, which is used to compare with the output results of simulation or ATE test.

[0073] Read instructions for the AP port:

[0074] jtag_read_ap(addr, data);

[0075] delay_time: 3000ns;

[0076] value=int(addr)&int(32'hffff_fff0);

[0077] jtag_dp_wr(2'd2, value, "35'bx100");

[0078] delay_time: 3060ns;

[0079] value = addr[3:2];

[0080] jtag_ap_rd(value, "35'bx100");

[0081] delay_time = 3000ns;

[0082] value = data + "3'b100";

[0083] jtag_dp_rd(2'd3, value);

[0084] jtag_dp_rd(addr, data);

[0085] value = "32'b0" + addr + "1'b1";

[0086] ir_data = 4'b1010;

[0087] tdi_data = value;

[0088] tdo_data = data;

[0089] jtag_process(ir_data, tdi_data, tdo_data).

[0090] Write instruction for DP port:

[0091] tag_write_dp(addr, banksel, data);

[0092] delay_time: 2000ns;

[0093] jtag_dp_wr(2'd2, banksel, "35'hx100");

[0094] delay_time: 2000ns;

[0095] value = addr[1:0];

[0096] jtag_dp_wr(value, data, "35'hx100");

[0097] jtag_dp_wr(addr, data, tdo_data);

[0098] value = data + addr + "1'b0";

[0099] ir_data = "4'b1010";

[0100] tdi_data = value;

[0101] tdo_data = tdo_data;

[0102] jtag_process(ir_data, tdi_data, tdo_data).

[0103] Read instruction for DP port:

[0104] jtag_read_dp(addr, banksel, data);

[0105] delay_time: 2000ns;

[0106] jtag_dp_wr(2'd2, banksel, "35'hx100");

[0107] delay_time: 2000ns;

[0108] value = addr[1:0];

[0109] jtag_dp_rd(value, "35'hx100");

[0110] delay_time = 2000ns;

[0111] value = data + "3'b100";

[0112] jtag_dp_rd(2'd3, value);

[0113] jtag_dp_rd(addr, data); <U+

[0114] value = "32'b0" + addr + "1'b1";

[0115] ir_data = 4'b1010;

[0116] tdi_data = value;

[0117] tdo_data = data; <U+

[0118] jtag_process(ir_data, tdi_data, tdo_data).

[0119] The parameter passing process in the aforementioned instruction templates, namely the setting of intermediate variables (for example, "value="32'b0"+addr+"1'b1""), the passing of intermediate variables to the TDI data sequence or TDO data, and the calling process between instruction templates are configured accordingly based on the JTAG protocol, the ADI protocol, and the AMBA bus protocol. Specifically, the JTAG protocol specifies the connection method between the debugger and the chip port, and the ADI specification (ARM Debug Interface) specifies how the debugger accesses the DP layer and the AP layer. Therefore, the chip peripheral test circuitry should be configured based on the aforementioned protocols. The parameter passing process mentioned above is also the reverse derivation process corresponding to the functions implemented by the chip peripheral test circuitry (during normal circuit testing, the layer-by-layer data transfer process corresponds to the functions achievable by the chip test circuitry, while the reverse derivation of the instruction template is based on the functions of the chip peripheral test circuitry). If the chip debug architecture uses the AMBA bus protocol, the corresponding chip external test circuitry should also be configured based on the AMBA bus protocol, and the parameter passing process in the instruction templates should also refer to the AMBA bus protocol. The calling process between instruction templates is also configured according to the three protocols described above. The above code merely illustrates the framework of the instruction template. The design concept behind the instruction template is to determine how to access system resources via JTAG, given the functional test instructions and their corresponding address and register parameters. The instruction template calculates the TDI data sequence input to the JTAG interface and the theoretically correct TDO data by reverse engineering (from system resources to the JTAG interface).

[0120] The above instruction templates are a layered parsing process. For example, the AP port write instruction jtag_write_ap requires calling the jtag_dp_wr and jtag_ap_wr instructions to complete the jtag_write_ap instruction. Each of these instructions has a corresponding template. The corresponding instruction template code is provided in the above code, so this article will not repeat it here. The combination of the three basic instruction templates above forms the write instruction for the AP port.

[0121] The calling relationship between the basic instruction templates of this application can be found in Figure 6 , each basic instruction template can be set according to the jtag protocol, ADI protocol and AMBA bus protocol, see Figure 6, where the jtag_process function uses the state machine to output the TDI, TMS, TCK, and TDO vectors of the jtag interface based on the ir_data, tdi_data, and tdo_data generated by the instruction template. The jtag_process function is explained in detail in step 2. Figure 6 For example, if you need to read and write chip resources (Coresight components) through the AHB bus, you can use the jtag_write_ap and jtag_read_ap instructions to achieve this. The jtag_write_ap and jtag_read_ap instructions are formed by combining the basic instruction templates of the next level.

[0122] Step 2: Associate the basic instruction template with the jtag test driver function.

[0123] Step 2-1: Based on the called instruction template, ir_data, tdi_data, and tdo_data are obtained, and the jtag test driver function is called based on the obtained ir_data, tdi_data, and tdo_data.

[0124] The value of ir_data is selectively set according to whether the DP port or AP port is accessed. Among the IR instructions, the DPACC (DP port access) and APACC (AP port access) instructions are more commonly used. That is, the IR instruction value is equal to 0b1010 (when the basic instruction template is executed to access the DP port) or 0b1011 (when the basic instruction template is executed to access the AP port). Therefore, in script development, only these two IR instruction values ​​need to be met.

[0125] Step 2-2: The jtag test driver function is based on the jtag protocol state machine. It uses the state machine to select the corresponding operating state under the TMS signal, and operates the IR register in conjunction with the TCK signal and TMS signal to output the combination of TDI signal, TMS signal, TCK signal, and TDO signal at different times.

[0126] See also Figure 5This diagram illustrates the operating state of the DBGTAPSM state machine (an extended state machine for debugging). The state machine shifts IR and DR data into and out of the JTAG-DP via the DBGTDI (test data input) and DBGTDO (test data output) signals. This invention utilizes the state machine protocol and its operating principles to reverse engineer the TDI signal. The invention selects the state machine state based on the value of the DBGTMS (test state select) signal, controlling the state machine to sequentially enter the IR register scan state, the Capture-IR state, and the Shift-IR state. The IR register is manipulated using the input TMS and TCK signals. In the Shift-IR state, the assigned instruction register value is padded bit by bit, starting from the lowest bit, according to the TDI data sequence format (the tdi_data obtained from the instruction template represents the TDI data format, which is then padded using the JTAG process function). This padded function then outputs the TDI signal, resulting in the combination of the TDI, TMS, TCK, and TDO signals at different times.

[0127] The operation process of the jtag state machine is common knowledge in this field and will not be repeated here in this application. This application uses the state machine to fill the tdi_data data of the instruction template bit by bit under the control of the TCK signal and the TMS signal.

[0128] The following code snippet illustrates how the jtag test driver function jtag_process controls the state transition of the TAP controller, executes the data shift operation of the jtag instruction register, and implements the bit-by-bit filling output of the TDI signal.

[0129] The code is before "#", and the code explanation is after "#".

[0130] #First, set the intermediate IR instruction value ir_data_tmp and the intermediate TDI data value wr_tdi_data_tmp according to the instruction type. DPACC (DP access command) and APACC (AP access command) are the most commonly used IR instructions. This means the IR instruction value is equal to 0b1010 or 0b1011 (the TR instruction value is assigned when the instruction template is called to process the functional test instruction). Therefore, in script development, only these two IR instruction values ​​are required. The assignment of TDI data values ​​and IR instruction values ​​is based on the specific circuit structure and implemented function.

[0131] # Initialize input parameters:

[0132] if(tr.Type=JTAG_DP_WR)begin; #The instruction type is JTAG_DP_WR, which is a write operation on DP;

[0133] ir_data_tmp= 4'bxxxx; #ir_data_tmp value is 4'bxxxx, ir_data_tmp here is the initial value;

[0134] wr_tdi_data_tmp={tr.data_in, tr.addr_in, 1'b0}; #wr_tdi_data_tmp value is a simple combination of data_in, addr_in, 1'b0. This step assigns a value to wr_tdi_data_tmp. wr_tdi_data_tmp is the initial value written to tdi_data.

[0135] End. #The writing operation to DP is completed.

[0136] else if(tr.Type == JTAG_DP_RD) begin #The instruction type is a read instruction for DP;

[0137] ir_data_tmp=4'bxxxx; #The initial value of ir_data is 4'bxxxx;

[0138] wr_tdi_data_tmp={32'b0, tr.addr in, 1'b1}; #wr_tdi_data_tmp value is a simple combination of 32'b0, tr.addr in, 1'b1;

[0139] End. #The read operation assignment to DP is completed.

[0140] else if(tr.Type == JTAG_AP_WR) begin;#The instruction is the write instruction to AP;

[0141] ir_data_tmp=4'bxxxx;

[0142] wr_tdi_data_tmp ={tr.data_in, tr.addr_in, l'b0};

[0143] End.

[0144] else if(tr.Type == JTAG_AP_RD) begin;#The instruction is the read instruction for AP;

[0145] ir_data_tmp=4'bxxxx;

[0146] wr_tdi_data_tmp ={32'b, tr.addr in, 1'b1};

[0147] End.

[0148] # jtag_process code implementation example (IR operation, TAP controller to Exit1-IR state):

[0149] #First, assign values ​​to ir_data_tmp and wr_tdi_data_tmp according to the instruction template type;

[0150] if(tr.Type==JTAG_DP_WR)begin; #If the instruction template is JTAG_DP_WR;

[0151] ir_data_tmp=4'b1010; #Assign the IR register value 4'b1010 copied in the instruction template to ir_data_tmp;

[0152] wr_tdi_data_tmp={tr.data_in, tr.addr_in, 1'b0);

[0153] End.

[0154] else if(tr.Type==JTAG_DP_RD) begin;

[0155] ir_data_tmp=4'b1010;

[0156] wr_tdi_data_tmp={32'b0,tr.addr_in,1'b1},

[0157] End.

[0158] else if(tr.Type==JTAG_AP_WR) begin;

[0159] ir_data_tmp=4'b1011;

[0160] wr_tdi_data_tmp={tr.data_in, tr.addr_in, l'b0};

[0161] End.

[0162] else if(tr.Type==JTAG_AP_RD) begin;

[0163] ir_data_tmp==4'b1011;

[0164] wr tdi data tmp ={32'b,tr.addr_in,1'b1},

[0165] End.

[0166] virtual task jtag_process(ref jtag_items tr); #Execute the jtag_process task again;

[0167] / / Get IR=DPACC / APACC instruction through ir_data;

[0168] ir_data=ir_data_tmp; # ir_data_tmp (initial value) is assigned to ir_data, and then the instruction is obtained through the ir_data value;

[0169] wr_tdi_data = wr_tdi_data_tmp; #The tdi_data written is wr_tdi_data_tmp (initial value);

[0170] rd_tdo_data=0; #The initial tdo_data read is 0.

[0171] / / ********Enter IR-shift process********; #Enter IR-shift operation state;

[0172] / / From run-test / idel ->àselect–IR-Scan process, the corresponding TMS changes from 0 value state to 1'b1 for two consecutive beats; #The state machine enters the IR-Scan state from the run-test / idel state, and the corresponding TMS signal is set to high level for two consecutive clock cycles;

[0173] for (int i=0;i<2;i++) begin;#Execute logical loop operation;

[0174] @(posedge jtag_intf.clk); #wait for the rising edge of clk signal;

[0175] Jtag_intf.tms = 1'b1; #Drive the TMS signal high for two clock cycles;

[0176] End.

[0177] / / capture-IR, tms beat is 0, enter capture-IR state; #tms beat is 0, the current operation enters capture-IR state;

[0178] @(posedge jtag_intf.clk); #wait for the rising edge of clk signal;

[0179] Jtag_intf.tms=1'b0; #drive the TMS signal to low level;

[0180] / / shift-IR, tms beat is 0, enter the shift-IR state; #tms beat is 0, the current operation enters the shift-IR state;

[0181] @(posedge jtag_intf.clk); #wait for the rising edge of clk signal;

[0182] Jtag_intf.tms=1'b0; #drive the tms signal to low level;

[0183] / / Assign tdi;

[0184] for(int i =0; i<4; i++) begin; #Loop the following operation 4 times;

[0185] @(posedge jtag_intf.clk); #wait for the rising edge of clk signal;

[0186] / / jtag_intf.tms=1'b0, keep the tms signal at 0;

[0187] Jtag_intf, tdi=ir_data[0]; / / Write ir_data into tdi after 4 beats; #Assign the lowest bit of ir_data to TDI signal;

[0188] Ir_data=ir_data>>1; # Shift ir_data right by one bit so that the next bit of data is the lowest bit and perform the assignment operation;

[0189] / / exit1-IR; #The current operation enters the exit1-IR state;

[0190] if(i==3) / / On the 4th beat, set tms to 1 and enter the exit1-IR state; #When the loop variable i is equal to 3, the tms signal is set to 1 and exit the shift-IR state;

[0191] jtag_intf.tms=1'b1; drive the TMS signal to high level;

[0192] End.

[0193] The above code shows how to drive the state machine into the shift-IR state under the joint drive of the TMS signal and the clk signal, and complete the assignment operation of tdi_data in the shift-IR state to output the combination of the TMS signal, TCK signal, TDI signal and TDO signal at different times (the clock signal TCK is output after the CLK signal is output).

[0194] At the same time, when outputting TDO data, the instruction template first adds the tail identifier to the data expected to be read (expect_rdata) in the functional test instruction and outputs it as TDO data (for example, "value=data+"3'b100"" in the instruction templates "jtag_read_ap" and "jtag_read_dp" is the data data in the functional test instruction plus the tail identifier "3'b100"). The jtag test driver function simply fills in the TDO data generated by the instruction template and outputs it (that is, the TDO data in the instruction template is directly filled in according to the format of the output TDO data and then outputted). The output TDO data is theoretically correct TDO data, and the test results can be compared with the theoretically correct TDO data after the jtag_process function generates a functional test vector for testing.

[0195] Let's take a piece of code as an example, for example:

[0196] Functional test instructions: #comment-->test PV_SDR__REG1; #test PV_SDR__REG1;

[0197] delay_time: 2000ns;

[0198] task_name:jtag_ahb_ap_write_data, addr:32'h200100c4, wr_data:32'h5a5a5a5a;

[0199] task_name:jtag_ahb_ap_read_data,addr:32'h200100c4,expect_rdata:32'h5a5a5a5a.

[0200] The above function test instruction includes writing data to the AP port on the AHB bus and reading the data, wherein the expected read data is 32'h5a5a5a5a. Figure 6, jtag_ahb_ap_read_data will call jtag_read_ap, and the instruction template jtag_read_ap will add the identifier "3'b100" to the data expected to be read.

[0201] Step 3: Get the chip functional test instructions and pin information (the final generated wgl file must contain pin information), and parse the task content and task input parameters contained in the functional test instructions. The task input content refers to the task type that the functional test instruction needs to execute, and the task input parameters include address parameters and register parameters.

[0202] Step 4: Select the corresponding instruction template based on the task content, call the instruction template, assign the instruction register value, and obtain the TDI data sequence and TDO data based on the corresponding address parameters and write / read data in the task input parameters; the instruction template is created based on the jtag protocol, ADI protocol and AMBA bus protocol, and the instruction template is associated with the jtag test driver function; call the jtag test driver function based on the instruction register value, TDI data sequence and TDO data, and output the functional test instruction content as a combination of TDI signal, TCK signal, TMS signal and TDO signal at different times.

[0203] The following takes a functional test instruction as an example to illustrate how to parse the functional test instruction to parse the task name and how to call the corresponding instruction template.

[0204] #comment-->reset fsm running, reset state machine;

[0205] delay_time: 100000ns;

[0206] #comment-->jtag power up, jtag power on, direct access to dp;

[0207] task_name:jtag_read_dp, addr:2'b01, banksel:4'b0, expect_rdata:32'h0;

[0208] task_name:jtag_write_dp, addr:2'b01, banksel:4'b0, wr_data:32'h10000000;

[0209] delay_time: 1000ns;

[0210] task_name: jtag_read_ap, addr: 32'hfc, expect_rdata: 32'h84770001;

[0211] #comment-->Test PV_SDR__REG1; Test PV_SDR__REG1;

[0212] delay_time: 2000ns;

[0213] task_name: jtag_ahb_ap_write_data, addr: 32'h200100c4, wr_data: 32'h5a5a5a5a;

[0214] task_name: jtag_ahb_ap_read_data, addr: 32'h200100c4, expect_rdata: 32'h5a5a5a5a;

[0215] #comment-->Test s4 sram1; Test s4 sram1;

[0216] delay_time: 2000ns;

[0217] task_name: jtag_ahb_ap_write_data, addr: 32'h30040000, wr_data: 32'h6a6a6a6a;

[0218] task_name: jtag_ahb_ap_read_data, addr: 32'h30040000, expect_rdata: 32'h6a6a6a6a;

[0219] #comment-->Test s9 sram1; Test s9 sram1;

[0220] delay_time: 2000ns;

[0221] task_name: jtag_ahb_ap_write_data, addr: 32'h30080000, wr_data: 32'h7a7a7a7a;

[0222] task_name: jtag_ahb_ap_read_data, addr: 32'h30080000, expect_rdata: 32'h7a7a7a7a;

[0223] #comment-->test s4 i2c;test s4 i2c;

[0224] delay_time: 2000ns;

[0225] task_name:jtag_ahb_ap_write_data, addr:32'h40000014, wr_data:32'h8a8a8a8a;

[0226] task_name:jtag_ahb_ap_read_data,addr:32'h40000014,expect_rdata:32'h8a8a8a8a.

[0227] The functional test instruction set described above includes multiple functional test instructions (comment). For example, "comment-->jtagpower-up" contains two tasks (task_name). For example, task_name: jtag_read_dp takes as its parameters: address parameter addr: 2'b01, instruction mnemonic banksel: 4'b0, and expected read value expect_rdata: 32'h0. This task_name requires the execution of the jtag_read_dp instruction, with the corresponding parameters addr, banksel, and expect_rdata. Therefore, the jtag_read_dp instruction template (described above) can be directly called. Based on the parameters addr (address parameter), banksel (instruction mnemonic), and expect_rdata (expected read value), the instruction template is used to calculate tdi_data and tdo_data. The jtag test driver function is then called to generate the required test vectors.

[0228] The above describes in detail a test vector generation method of the present invention. The functional test instructions written by developers can be converted into jtag interface test vectors through the instruction template of the present invention, which is efficient and easy to modify.

[0229] Example 2:

[0230] Embodiment 2 provides a test vector generation system, which includes at least the following modules:

[0231] The test instruction parsing module parses the input functional test instruction and outputs the task content and task input parameters contained in the functional test instruction;

[0232] A test vector generation module selects a corresponding instruction template based on the task content, calls the instruction template, assigns a value to the instruction register, and obtains a TDI data sequence and TDO data based on the corresponding address parameters and write / read data in the task input parameters; the instruction template is created based on the jtag protocol, the ADI protocol and the data transmission protocol of the chip test circuit, and the instruction template is associated with a jtag test driver function; the jtag test driver function is called based on the instruction register value, the TDI data sequence and the TDO data, and the functional test instruction content is output as a combination of TDI signal, TCK signal, TMS signal and TDO signal at different times.

[0233] The test vector generation system in the second embodiment is used to execute the steps of the test vector generation method in the first embodiment.

[0234] Example 3

[0235] Embodiment 3 provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the steps of the test vector generation method described in embodiment 1 are implemented.

[0236] The above is a detailed introduction to the test vector generation method, system, and computer-readable storage medium provided by the present invention. Specific examples are used herein to illustrate the structure and working principle of the present invention. The description of the above embodiments is only intended to help understand the method and core concept of the present invention. It should be noted that, for those skilled in the art, without departing from the principles of the present invention, several improvements and modifications may be made to the present invention, and such improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. A test vector generation method, characterized in that: The method comprises: Obtain chip functional test instructions and parse out the task content and task input parameters contained in the functional test instructions; Select a corresponding instruction template based on the task content, call the instruction template, assign the instruction register value, and obtain the TDI data sequence and TDO data based on the corresponding address parameters and write / read data in the task input parameters; the instruction template is created based on the jtag protocol, the ADI protocol and the data transmission protocol of the chip test circuit, and the instruction template is associated with the jtag test driver function; wherein, the corresponding peripheral test circuit is designed according to the jtag protocol, the ADI protocol and the data transmission protocol of the chip test circuit, and the parameter transfer process is designed according to the corresponding reverse deduction process of the function implemented by the chip peripheral test circuit, and then a specific instruction template is created; The jtag test driver function is called according to the instruction register value, TDI data sequence and TDO data, and the functional test instruction content is output as a combination of TDI signal, TCK signal, TMS signal and TDO signal at different times.

2. A test vector generation method according to claim 1, characterized in that: According to the basic tasks that need to be performed when the chip to be tested is tested based on the test protocol, multiple basic instruction templates are created. Each basic instruction template performs an instruction task. Multiple different basic instruction templates are combined to realize different test functions of the chip.

3. A test vector generation method according to claim 2, characterized in that: The basic instruction template includes at least a write instruction for the DP port, a read instruction for the DP port, a write instruction for the AP port, and a read instruction for the AP port.

4. A test vector generation method according to claim 3, characterized in that: The basic instruction template includes a write instruction to the AP port on the ahb bus, a read instruction to the AP port on the ahb bus, a write instruction to the DP port on the ahb bus, and a read instruction to the DP port on the ahb bus; The write instruction to the AP port on the ahb bus and the read instruction to the AP port on the ahb bus are further converted into the read instruction and write instruction to the AP port, and the write instruction to the DP port on the ahb bus and the read instruction to the DP port on the ahb bus are further converted into the read instruction and write instruction to the DP port.

5. A test vector generation method according to any one of claims 3 or 4, characterized in that: Based on the task content contained in the functional test instruction, a corresponding basic instruction template is selected, and the functional test instruction is converted into a read instruction and a write instruction for the AP port on the chip and a read instruction and a write instruction for the DP port according to the basic instruction template; The converted read instructions and write instructions to the AP port on the chip and the read instructions and write instructions to the DP port are further associated with the jtag test driver function.

6. A test vector generation method according to claim 5, characterized in that: Assigning a value to the instruction register according to the instruction task executed by the basic instruction template; According to the JTAG protocol, ADI protocol and the data transmission protocol of the chip test circuit, set the intermediate variables and assign the intermediate variables to the TDI data sequence or TDO data; The intermediate variables are related to the address parameters and write / read data required for the created read instructions and write instructions to the AP port and the created read instructions and write instructions to the DP port.

7. A test vector generation method according to claim 6, characterized in that: The jtag test driver function inputs the TMS signal, controls the state machine to enter the IR register scanning state, Capture-IR state and Shift-IR state in sequence, and operates the IR register through the input TMS signal and TCK signal. In the Shift-IR state, the assigned instruction register value is filled bit by bit starting from the low bit according to the TDI data sequence format to output the TDI signal, and obtains the combination of TDI signal, TMS signal, TCK signal and TDO signal at different times.

8. A test vector generation method according to claim 6, characterized in that: The instruction template adds a tail identifier to the data expected to be read in the functional test instruction and outputs it as TDO data. The jtag test driver function simply fills the TDO data generated by the instruction template and then outputs it.

9. A test vector generation method according to claim 6, characterized in that: When the basic instruction template is used to execute the task of accessing the DP port, the instruction register is assigned a value of 0b1010; when the basic instruction template is used to execute the task of accessing the AP port, the instruction register is assigned a value of 0b1011; The jtag test driver function obtains the instruction register value assigned by the instruction template, and fills the assigned instruction register value bit by bit starting from the low bit according to the TDI data sequence format to output the TDI signal.

10. A test vector generation method according to claim 1, characterized in that: The data transmission protocol of the chip test circuit includes the AMBA bus protocol, and the DAP debugger accesses the system resources on the chip based on the AMBA bus protocol.

11. A test vector generation system, characterized in that: include: The test instruction parsing module parses the input functional test instruction and outputs the task content and task input parameters contained in the functional test instruction; A test vector generation module selects a corresponding instruction template based on the task content, calls the instruction template, assigns a value to the instruction register, and obtains a TDI data sequence and TDO data according to the corresponding address parameters and write / read data in the task input parameters; The instruction template is created based on the jtag protocol, the ADI protocol and the data transmission protocol of the chip test circuit, and the instruction template is associated with the jtag test driver function; wherein, the corresponding peripheral test circuit is designed according to the jtag protocol, the ADI protocol and the data transmission protocol of the chip test circuit, and the parameter transfer process is designed according to the corresponding reverse deduction process of the function implemented by the peripheral test circuit of the chip, and then a specific instruction template is created; the jtag test driver function is called according to the instruction register value, the TDI data sequence and the TDO data, and the functional test instruction content is output as a combination of TDI signal, TCK signal, TMS signal and TDO signal at different times.

12. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the test vector generation method according to any one of claims 1 to 10 are implemented.

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