High-speed serial signal jitter injection system and method, electronic equipment and storage medium

Abstract

The invention relates to the technical field of integrated circuits, and provides a high-speed serial signal jitter injection system and method, electronic equipment and a storage medium, and the system comprises a controller, a parallel shift register unit, a parallel-serial conversion unit, a data delay line and a high-speed digital-to-analog converter; the parallel shift register unit obtains multiple paths of parallel pseudo-random sequences based on pseudo-random seeds, the parallel-serial conversion unit converts the multiple paths of parallel pseudo-random sequences into high-speed serial data streams, and the high-speed digital-to-analog converter converts control signals of the controller into analog voltage and inputs the analog voltage to the data delay line; the data delay line determines a jitter mode based on a change in the analog voltage, and determines a high-speed serial signal of the high-speed serial data stream based on the jitter mode. In the system, the parallel shift register unit performs shift summation parallel processing on a pseudo-random seed, and time delay regulation and control are realized through a data delay line controlled by analog voltage, so that the flexibility of a jitter injection mechanism is improved, and the anti-interference capability and the time sequence precision are improved.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and in particular, to a high-speed serial signal jitter injection system, method, electronic device, and storage medium. Background Art

[0002] In high-speed digital communication, test and measurement, and radio frequency systems, pseudo-random pattern generators are widely used to generate test signals and evaluate the anti-interference ability of the system. Traditional pseudo-random pattern generators mostly adopt a fixed generation mode, with high signal stability. However, in some application scenarios, such as simulating clock jitter, signal interference, and timing errors in an actual channel, they lack a flexible jitter injection function and cannot comprehensively evaluate the anti-interference ability of the receiving end and the fault tolerance performance of the system.

[0003] The pure digital jitter generation scheme uses a Digital Signal Processor (DSP) to directly perform random delay processing on the digital sequence to achieve jitter injection. Although the scheme is simple to implement, it is difficult to meet the requirements of resolution and stability of digital delay in high-speed applications, and it has a large dependence on the system clock accuracy. Summary of the Invention

[0004] The present invention provides a high-speed serial signal jitter injection system, method, electronic device, and storage medium to solve the defects existing in the prior art.

[0005] The present invention provides a high-speed serial signal jitter injection system, including a controller, a parallel shift register unit, a parallel-to-serial conversion unit, a data delay line, and a high-speed digital-to-analog converter; The controller generates a pseudo-random seed; The parallel shift register unit performs shift summation parallel processing on the pseudo-random seed to obtain a multi-channel parallel pseudo-random sequence; The parallel-to-serial conversion unit converts the multi-channel parallel pseudo-random sequence into a high-speed serial data stream; The high-speed digital-to-analog converter converts the control signal of the controller into an analog voltage and inputs the analog voltage to the data delay line; The data delay line is used to determine a jitter mode based on the change of the analog voltage, and determine a high-speed serial signal of the high-speed serial data stream based on the jitter mode.

[0006] According to the high-speed serial signal jitter injection system provided by the present invention, the system further includes a data splitter and an error code detector; The data splitter is used to perform signal splitting on the delay signal output by the data delay line to obtain a first-channel signal; The error detector is used to detect errors in the first channel signal and obtain an error detection result.

[0007] According to a high-speed serial signal jitter injection system provided by the present invention, the data splitter is further configured to split the delayed signal output by the data delay line to obtain a second channel signal; the second channel signal is a high-speed serial signal of the high-speed serial data stream.

[0008] According to a high-speed serial signal jitter injection system provided by the present invention, the system further includes a phase detector and a high-speed analog-to-digital converter; The data splitter is further configured to split the delayed signal output by the data delay line to obtain a third channel signal; The phase detector is configured to detect the phase difference between the third channel signal and the analog voltage to obtain a phase detection voltage; The high-speed analog-to-digital converter converts the phase detection voltage into a digital signal and inputs the digital signal to the controller.

[0009] According to a high-speed serial signal jitter injection system provided by the present invention, the data delay line is configured to determine a jitter pattern based on the change of the analog voltage, including: When the analog voltage is at a fixed level, the data delay line determines that the jitter pattern is no jitter; When the analog voltage is a sine signal, the data delay line determines that the jitter pattern is sine jitter.

[0010] According to a high-speed serial signal jitter injection system provided by the present invention, the data delay line is a voltage-controlled delay line.

[0011] According to a high-speed serial signal jitter injection system provided by the present invention, when the analog voltage is a sine signal, the data delay line determines that the jitter pattern is sine jitter, including: When the analog voltage is a sine signal, the voltage-controlled delay line determines that the jitter pattern is the sine jitter by adjusting the frequency and amplitude of the sine signal.

[0012] The present invention also provides a high-speed serial signal jitter injection method, including the following steps: Obtain a pseudo-random seed and a control signal; Perform a shift-sum parallel process on the pseudo-random seed to obtain a multi-channel parallel pseudo-random sequence; Convert the multi-channel parallel pseudo-random sequence into a high-speed serial data stream, convert the control signal into an analog voltage, and determine a jitter pattern based on the change of the analog voltage; Based on the dithering pattern, determine the high-speed serial signal of the high-speed serial data stream.

[0013] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the program, the high-speed serial signal dithering injection method as described in any one of the above is implemented.

[0014] The present invention also provides a non-transitory computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the high-speed serial signal dithering injection method as described in any one of the above is implemented.

[0015] The present invention also provides a computer program product, including a computer program. When the computer program is executed by a processor, the high-speed serial signal dithering injection method as described in any one of the above is implemented.

[0016] The high-speed serial signal dithering injection system, method, electronic device, and storage medium provided by the present invention include a controller, a parallel shift register unit, a parallel-to-serial conversion unit, a data delay line, and a high-speed digital-to-analog converter. The controller generates a pseudo-random seed. The parallel shift register unit performs shift summation parallel processing on the pseudo-random seed to obtain a plurality of parallel pseudo-random sequences. The parallel-to-serial conversion unit converts the plurality of parallel pseudo-random sequences into a high-speed serial data stream. The high-speed digital-to-analog converter converts the control signal of the controller into an analog voltage and inputs the analog voltage to the data delay line. The data delay line is used to determine the dithering pattern based on the change of the analog voltage, and determine the high-speed serial signal of the high-speed serial data stream based on the dithering pattern. On the one hand, the parallel shift register unit performs shift summation parallel processing on the pseudo-random seed to obtain a plurality of parallel pseudo-random sequences, which not only improves the generation rate of the sequence, but also takes into account the randomness and balance of the sequence. On the other hand, the data delay line controlled by the analog voltage is used to realize the time delay regulation, which improves the flexibility of the dithering injection mechanism, and enhances the anti-interference ability and timing accuracy. Description of the Drawings

[0017] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0018] Figure 1 is one of the schematic diagrams of the high-speed serial signal dithering injection system provided by the present invention.

[0019] Figure 2 is the second schematic diagram of the high-speed serial signal dithering injection system provided by the present invention.

[0020] Figure 3 It is a schematic flowchart of the high-speed serial signal jitter injection method provided by the present invention.

[0021] Figure 4 It is a schematic structural diagram of the electronic device provided by the present invention. Detailed implementation manners

[0022] To make the objectives, technical solutions and advantages of the present invention clearer, the technical solutions in the present invention will be clearly and completely described below with reference to the accompanying drawings in the present invention. Apparently, the described embodiments are some but not all of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present invention without making creative efforts shall fall within the protection scope of the present invention.

[0023] In the related art, there are: 1) Insufficient pseudo-randomness: The traditional pseudo-random sequence generation method has bottlenecks in parallel processing and high-speed conversion, and it is difficult to meet the requirements for timing accuracy at high data rates.

[0024] 2) Weak real-time regulation ability: In actual tests, there is a lack of flexibility in real-time online adjusting the jitter characteristics, and it is impossible to simulate the dynamic interference situations under various channel environments.

[0025] Figure 1 It is one of the schematic diagrams of the high-speed serial signal jitter injection system provided by the present invention. As Figure 1 shown, the system includes a controller 1, a parallel shift register unit 2, a parallel-to-serial conversion unit 3, a data delay line 4, and a high-speed digital-to-analog converter 5; The controller 1 generates a pseudo-random seed; The parallel shift register unit 2 performs shift summation parallel processing on the pseudo-random seed to obtain a multiplex parallel pseudo-random sequence; The parallel-to-serial conversion unit 3 converts the multiplex parallel pseudo-random sequence into a high-speed serial data stream; The high-speed digital-to-analog converter 5 converts the control signal of the controller 1 into an analog voltage and inputs the analog voltage to the data delay line 4; The data delay line 4 is used to determine a jitter pattern based on the change of the analog voltage, and determine the high-speed serial signal of the high-speed serial data stream based on the jitter pattern.

[0026] Specifically, the controller 1 generates a pseudo-random seed, which is loaded into the parallel shift register unit 2 as an initial value, determining the starting state of the generated multi-channel parallel pseudo-random sequence. Here, the parallel shift register unit 2 can be a Linear Feedback Shift Register (LFSR), or a Parallel-in Serial-out (PISO) register, or a Serial-in Parallel-out (SIPO) register, or a Serial-in Serial-out (SISO) register, etc. The embodiments of the present invention do not make specific limitations thereto.

[0027] It can be understood that since the operation of the parallel shift register unit 2 is deterministic, different seed values will generate different pseudo-random sequences. Therefore, the selection of the pseudo-random seed is crucial for generating a pseudo-random sequence with specific characteristics.

[0028] Here, the parallel shift register unit 2 uses a shift-summation parallel processing technique, which performs shift-summation parallel processing on the pseudo-random seed, not only improving the sequence generation speed, but also improving the statistical characteristics of the sequence, reducing the correlation, and thus ensuring that the signal has better randomness.

[0029] The parallel-to-serial conversion unit 3 converts the multi-channel parallel pseudo-random sequence into a high-speed serial data stream. The High-Speed Digital-to-Analog Converter (DAC) converts the control signal of the controller 1 into an analog voltage and inputs the analog voltage to the data delay line 4.

[0030] The high-speed DAC 5 is an electronic device that can quickly convert digital signals into analog signals.

[0031] It should be noted that the generated multi-channel parallel pseudo-random sequence is converted into a high-speed serial data stream through the parallel-to-serial conversion unit 3. During the conversion process, high-precision timing control is adopted to ensure that there is no error in the signal timing, meeting the requirements of high-speed communication testing.

[0032] It can be understood that by using the parallel-to-serial conversion unit 3 to convert the multi-channel parallel pseudo-random sequence into a high-speed serial data stream, and at the same time, realizing delay control through the data delay line 4 controlled by an analog voltage, a jitter injection mechanism that closely combines digital and analog is formed.

[0033] Here, the data delay line 4 is used to determine the jitter pattern based on the change of the analog voltage, and based on the jitter pattern, determine the high-speed serial signal of the high-speed serial data stream.

[0034] Here, the data delay line 4 can be a voltage-controlled delay line (VCDL), a tapped delay line (TDL), a digitally controlled delay line, etc. The embodiments of the present invention do not make specific limitations thereto.

[0035] It should be noted that the delay duration of the data delay line 4 is determined by an external analog voltage.

[0036] The system provided by the embodiments of the present invention has a flexible jitter control mode. For example, when the analog voltage is at a fixed level, the data delay line has a constant delay, thereby achieving jitter shutdown; when the analog voltage is a sine signal, sine jitter can be injected into the data path. By adjusting the frequency and amplitude of the sine signal, the frequency and amplitude of the jitter can be controlled respectively to meet the requirements of various test scenarios.

[0037] In addition, the high-speed serial signal jitter injection system can be embedded with a temperature compensation, clock jitter suppression, and feedback regulation module to achieve environmental adaptive correction and ensure stable output of high-quality jitter signals under different working conditions.

[0038] The system provided by the embodiments of the present invention includes a controller, a parallel shift register unit, a parallel-to-serial conversion unit, a data delay line, and a high-speed digital-to-analog converter; the controller generates a pseudo-random seed, the parallel shift register unit performs shift summation parallel processing on the pseudo-random seed to obtain a plurality of parallel pseudo-random sequences, the parallel-to-serial conversion unit converts the plurality of parallel pseudo-random sequences into a high-speed serial data stream, the high-speed digital-to-analog converter converts the control signal of the controller into an analog voltage and inputs the analog voltage to the data delay line; the data delay line is used to determine a jitter mode based on the change of the analog voltage and determine a high-speed serial signal of the high-speed serial data stream based on the jitter mode. On the one hand, the parallel shift register unit performs shift summation parallel processing on the pseudo-random seed to obtain a plurality of parallel pseudo-random sequences, which not only improves the sequence generation rate but also takes into account the randomness and balance of the sequences; on the other hand, at the same time, delay regulation is achieved through the data delay line controlled by the analog voltage, forming a jitter injection mechanism that closely combines digital and analog, improving the anti-interference ability and timing accuracy.

[0039] Based on the above embodiments, the system further includes a data splitter 6 and an error detector 7; The data splitter 6 is used to split the delay signal output by the data delay line 4 to obtain a first channel signal; The error detector 7 is used to perform error detection on the first channel signal to obtain an error detection result.

[0040] Specifically, to further enhance the system stability, an embodiment of the present invention may set up a real-time monitoring module to detect the timing and bit error rate of the output signal, and adjust the delay signal of the data delay line 4 through feedback regulation to achieve closed-loop adaptive correction. Correspondingly, the system may further include a data splitter 6 and a bit error detector 7. The data splitter 6 is used to split the delay signal output by the data delay line 4 to obtain a first channel signal.

[0041] Here, the bit error detector 7 is used to detect bit errors in the first channel signal to obtain a bit error detection result. For example, when bit errors occur or the bit error rate threshold is exceeded, the jitter at this time exceeds the expected jitter.

[0042] Among them, the bit error detector 7 may be a traditional bit error meter or a high-performance bit error rate tester, etc. The embodiments of the present invention do not make specific limitations on this.

[0043] In addition, temperature sensors may be set for the controller 1, the parallel shift register unit 2, the serial-to-parallel conversion unit 3, the data delay line 4, the high-speed digital-to-analog converter 5, the data splitter 6, and the bit error detector 7, so as to obtain their respective temperature sensor information based on the temperature sensors, and then automatically compensate for the delay drift caused by environmental changes to improve the long-term stability of the system.

[0044] It can be understood that by monitoring the temperature, the controller 1 can adjust the working parameters of the controller 1 to ensure its stable operation under different environmental conditions; temperature changes may affect the delay characteristics of the parallel shift register unit 2. Through temperature compensation, the processing speed can be adjusted to ensure the accuracy of data processing; temperature changes may affect the delay and synchronization during the conversion process. Through temperature compensation, the accuracy of the data delay line 4 in regulating the time delay can be ensured, constituting a jitter injection mechanism that closely combines digital and analog, further improving the anti-interference ability and timing accuracy.

[0045] Based on the above embodiment, the data splitter is further used to split the delay signal output by the data delay line to obtain a second channel signal; the second channel signal is the high-speed serial signal of the high-speed serial data stream.

[0046] Specifically, the data splitter 6 is further used to split the delay signal output by the data delay line 4 to obtain a second channel signal. Among them, the second channel signal is the high-speed serial signal of the high-speed serial data stream. The high-speed serial signal here is a high-speed serial signal with jitter, so that the anti-interference evaluation can be carried out based on the high-speed serial signal with jitter, and then the anti-interference ability and system fault tolerance performance of the receiving end can be comprehensively evaluated.

[0047] Based on the above embodiment, the system further includes a phase discriminator 8 and a high-speed analog-to-digital converter 9; The data splitter 6 is further configured to split the delayed signal output by the data delay line to obtain a third-channel signal; The phase detector 8 is configured to perform phase detection on the third-channel signal and the analog voltage to obtain a phase-detected voltage; The high-speed analog-to-digital converter 9 converts the phase-detected voltage into a digital signal and inputs the digital signal to the controller 1.

[0048] Specifically, the system further includes a phase detector 8 and a high-speed analog-to-digital converter 9. The data splitter 6 is further configured to split the delayed signal output by the data delay line 4 to obtain a third-channel signal.

[0049] The phase detector 8 is configured to perform phase detection on the third-channel signal and the analog voltage to obtain a phase-detected voltage, ensuring the correctness of the jitter frequency and amplitude.

[0050] A high-speed analog-to-digital converter (ADC) is an electronic device that can quickly convert an analog signal into a digital signal. The high-speed analog-to-digital converter 9 converts the phase-detected voltage into a digital signal and inputs the digital signal to the controller 1.

[0051] It can be understood that the phase detector 8 can improve the synchronization accuracy. Specifically, in a multi-channel system with high-speed serial signal jitter injection, the phase detector 8 can be used to calibrate the phase difference between different channels. By measuring the phase difference between each channel and the reference channel and performing corresponding compensation, high-precision multi-channel synchronization can be achieved; the closed-loop feedback mechanism adjusts the system parameters according to the phase difference signal output by the phase detector 8 to minimize the phase error. This feedback adjustment can dynamically compensate for the phase drift and noise in the system, ensure the phase synchronization of the signal, and then significantly reduce the phase difference between multiple channels to achieve high-precision synchronous output.

[0052] In the related art, for the multi-clock source mixing scheme: multiple slightly offset independent clock sources are mixed to generate jitter, and the jitter effect is achieved through the phase interference of different frequency clocks. However, this scheme has a complex design, is difficult to accurately control the jitter amplitude and frequency, and has a high system cost at the same time.

[0053] Based on the above embodiments, the data delay line 4 is configured to determine the jitter mode based on the change of the analog voltage, including: When the analog voltage is at a fixed level, the data delay line 4 determines that the jitter mode is no jitter; When the analog voltage is a sine signal, the data delay line 4 determines that the jitter mode is sine jitter.

[0054] Specifically, when the analog voltage is at a fixed level, the data delay line 4 determines that the jitter mode is no jitter. When the analog voltage is a sine signal, the data delay line 4 determines that the jitter mode is sinusoidal jitter.

[0055] Here, the data delay line 4 can be a voltage-controlled delay line. For example, when the analog voltage is a sine signal, the voltage-controlled delay line determines that the jitter mode is sinusoidal jitter by adjusting the frequency and amplitude of the sine signal. When the analog voltage is a fixed value, the delay of the voltage-controlled delay line is constant, and the output signal is stable without jitter. When the analog voltage is a sine wave, the delay time changes periodically, injecting sinusoidal jitter. By finely adjusting the frequency and amplitude of the sine signal, the frequency and magnitude of the jitter can be independently adjusted, so as to simulate the signal jitter conditions in various actual working environments.

[0056] Based on any of the above embodiments, Figure 2 is the second schematic diagram of the high-speed serial signal jitter injection system provided by the present invention. As Figure 2 shown, the system includes a controller 1, a parallel shift register unit 2, a parallel-to-serial conversion unit 3, a data delay line 4, a high-speed digital-to-analog converter 5, a data splitter 6, an error detector 7, and a high-speed analog-to-digital converter 9.

[0057] Among them, the controller 1 generates a pseudo-random seed. The parallel shift register unit 2 performs shift summation parallel processing on the pseudo-random seed to obtain a multi-channel parallel pseudo-random sequence. The parallel-to-serial conversion unit 3 converts the multi-channel parallel pseudo-random sequence into a high-speed serial data stream. The high-speed digital-to-analog converter 5 converts the control signal of the controller 1 into an analog voltage and inputs the analog voltage to the data delay line 4.

[0058] The data splitter 6 is used to split the delay signal output by the data delay line 4 to obtain a first channel signal. The error detector 7 is used to detect errors in the first channel signal to obtain an error detection result.

[0059] The data splitter 6 is also used to split the delay signal output by the data delay line 4 to obtain a second channel signal. The second channel signal is the high-speed serial signal of the high-speed serial data stream.

[0060] The data splitter 6 is also used to split the delay signal output by the data delay line to obtain a third channel signal. The phase discriminator 8 is used to perform phase discrimination on the third channel signal and the analog voltage to obtain a phase discrimination voltage. The high-speed analog-to-digital converter 9 converts the phase discrimination voltage into a digital signal and inputs the digital signal to the controller 1.

[0061] The system provided by the embodiments of the present invention: 1) adopts a scheme of generating two channels by replicating one signal: the data splitter 6 splits the delayed signal output by the data delay line 4 to generate multiple signals (such as the first channel signal, the second channel signal, and the third channel signal). This method reduces the number of independent pattern generators because there is no need to configure a pattern generator for each channel separately.

[0062] 2) Reduce system complexity and cost: By reducing the number of independent components, the overall design of the system is simplified and the hardware cost is reduced. For example, a parallel shift register unit 2 and a parallel-to-serial conversion unit 3 are used to generate multiple parallel pseudo-random sequences and convert them into high-speed serial data streams, instead of configuring these components for each channel separately.

[0063] 3) Enhance system stability: 1. Real-time detection and feedback mechanism: The controller 1 generates a pseudo-random seed and generates a high-speed serial data stream through the parallel shift register unit 2 and the parallel-to-serial conversion unit 3. The data delay line 4 adjusts the delay according to the analog voltage provided by the high-speed digital-to-analog converter 5. The error detector 7 real-time detects the error condition of the first channel signal, the phase discriminator 8 real-time detects the phase difference of the third channel signal, and converts the phase discrimination voltage into a digital signal through the high-speed analog-to-digital converter 9 and feeds it back to the controller 1.

[0064] 2. Adapt to changes in the external environment: Through real-time detection and feedback control, the system can automatically correct the delay drift and phase error caused by external environmental factors such as temperature fluctuations and voltage changes. For example, the data delay line 4 can dynamically adjust the delay according to the change of the analog voltage to ensure the stability and consistency of the signal.

[0065] 3. Robustness: This real-time detection and automatic correction mechanism enables the system to have strong adaptability and robustness to changes in the external environment, improving the overall performance and reliability of the system.

[0066] 4) By adjusting the configuration of the data splitter 6, the delayed signal output by the data delay line 4 can be flexibly split into more channels. For example, more splitting channels can be added to generate more signal channels to meet the requirements of different application scenarios.

[0067] The following describes the high-speed serial signal jitter injection method provided by the present invention. The high-speed serial signal jitter injection method described below can be mutually corresponding and referred to with the high-speed serial signal jitter injection system described above.

[0068] Based on any of the above embodiments, the present invention provides a high-speed serial signal jitter injection method. Figure 3 It is a schematic flow chart of the high-speed serial signal jitter injection method provided by the present invention, as Figure 3As shown, the method includes steps 310, 320, 330, and 340: Step 310, obtaining a pseudo-random seed and a control signal; Step 320, performing a shift-sum parallel processing on the pseudo-random seed to obtain a multi-channel parallel pseudo-random sequence; Step 330, converting the multi-channel parallel pseudo-random sequence into a high-speed serial data stream, converting the control signal into an analog voltage, and determining a jitter pattern based on the change of the analog voltage; Step 340, determining a high-speed serial signal of the high-speed serial data stream based on the jitter pattern.

[0069] Specifically, first, obtain a pseudo-random seed and a control signal, and then perform a shift-sum parallel processing on the pseudo-random seed to obtain a multi-channel parallel pseudo-random sequence.

[0070] The controller 1 can generate a pseudo-random seed, which is loaded into the parallel shift register unit 2 as an initial value, determining the starting state of the generated multi-channel parallel pseudo-random sequence. Here, the parallel shift register unit 2 can be a linear feedback shift register, or a parallel-in serial-out shift register, or a serial-in parallel-out shift register and a serial-in serial-out shift register, etc. The embodiments of the present invention do not make specific limitations on this.

[0071] It can be understood that since the operation of the parallel shift register unit 2 is deterministic, different seed values will generate different pseudo-random sequences. Therefore, the selection of the pseudo-random seed is crucial for generating a pseudo-random sequence with specific characteristics.

[0072] Here, the parallel shift register unit 2 uses a shift-sum parallel processing technique, which performs a shift-sum parallel processing on the pseudo-random seed, not only improving the sequence generation speed, but also improving the statistical characteristics of the sequence, reducing the correlation, so as to ensure that the signal has better randomness.

[0073] Furthermore, the multi-channel parallel pseudo-random sequence can be converted into a high-speed serial data stream, the control signal can be converted into an analog voltage, and the jitter pattern can be determined based on the change of the analog voltage. Here, the data delay line can be used to determine the jitter pattern based on the change of the analog voltage, and determine the high-speed serial signal of the high-speed serial data stream based on the jitter pattern.

[0074] Here, the data delay line 4 can be a voltage-controlled delay line, or a multi-tap delay line, or a digitally controlled delay line, etc. The embodiments of the present invention do not make specific limitations on this.

[0075] For example, when the analog voltage is at a fixed level, the data delay line has a constant delay, thereby achieving jitter shutdown; when the analog voltage is a sine signal, sinusoidal jitter can be injected into the data path. By adjusting the frequency and amplitude of the sine signal, the frequency and amplitude of the jitter can be controlled respectively to meet the requirements of various test scenarios.

[0076] Finally, based on the jitter mode, the high-speed serial signal of the high-speed serial data stream is determined.

[0077] The method provided by the embodiment of the present invention obtains a pseudo-random seed and a control signal, then performs shift summation parallel processing on the pseudo-random seed to obtain a multi-channel parallel pseudo-random sequence. Then, the multi-channel parallel pseudo-random sequence is converted into a high-speed serial data stream, the control signal is converted into an analog voltage, and based on the change of the analog voltage, the jitter mode is determined. Finally, based on the jitter mode, the high-speed serial signal of the high-speed serial data stream is determined. On the one hand, performing shift summation parallel processing on the pseudo-random seed to obtain a multi-channel parallel pseudo-random sequence not only improves the sequence generation rate, but also takes into account the randomness and balance of the sequence; on the other hand, based on the change of the analog voltage, the jitter mode is determined, and finally, based on the jitter mode, the high-speed serial signal of the high-speed serial data stream is determined, forming a jitter injection mechanism that closely combines digital and analog, thereby improving the anti-interference ability and timing accuracy.

[0078] Figure 4 is a schematic structural diagram of an electronic device provided by the present invention, as Figure 4 shown, the electronic device may include: a processor 410, a communication interface 420, a memory 430, and a communication bus 440. Among them, the processor 410, the communication interface 420, and the memory 430 complete communication with each other through the communication bus 440. The processor 410 can call the logical instructions in the memory 430 to execute the high-speed serial signal jitter injection method, and the method includes: obtaining a pseudo-random seed and a control signal; performing shift summation parallel processing on the pseudo-random seed to obtain a multi-channel parallel pseudo-random sequence; converting the multi-channel parallel pseudo-random sequence into a high-speed serial data stream, converting the control signal into an analog voltage, and based on the change of the analog voltage, determining the jitter mode; based on the jitter mode, determining the high-speed serial signal of the high-speed serial data stream.

[0079] In addition, when the logical instructions in the above-mentioned memory 430 are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as USB flash drives, mobile hard disks, read-only memories (ROM, Read-Only Memory), random access memories (RAM, Random Access Memory), magnetic disks, or optical discs.

[0080] On the other hand, the present invention also provides a computer program product. The computer program product includes a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the high-speed serial signal jitter injection method provided by the above-mentioned various methods. The method includes: obtaining a pseudo-random seed and a control signal; performing a shift-sum parallel process on the pseudo-random seed to obtain a multi-channel parallel pseudo-random sequence; converting the multi-channel parallel pseudo-random sequence into a high-speed serial data stream, converting the control signal into an analog voltage, and determining a jitter pattern based on the change of the analog voltage; and determining the high-speed serial signal of the high-speed serial data stream based on the jitter pattern.

[0081] In yet another aspect, the present invention also provides a non-transitory computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, it is implemented to execute the high-speed serial signal jitter injection method provided by the above-mentioned various methods. The method includes: obtaining a pseudo-random seed and a control signal; performing a shift-sum parallel process on the pseudo-random seed to obtain a multi-channel parallel pseudo-random sequence; converting the multi-channel parallel pseudo-random sequence into a high-speed serial data stream, converting the control signal into an analog voltage, and determining a jitter pattern based on the change of the analog voltage; and determining the high-speed serial signal of the high-speed serial data stream based on the jitter pattern.

[0082] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art can understand and implement it without creative efforts.

[0083] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on this understanding, the essence of the above technical solution, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0084] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A high-speed serial signal jitter injection system, characterized in that, It includes a controller, a parallel shift register unit, a parallel-to-serial conversion unit, a data delay line, and a high-speed digital-to-analog converter; The controller generates a pseudo-random seed; The parallel shift register unit performs shift summation parallel processing on the pseudo-random seed to obtain a multi-channel parallel pseudo-random sequence; The parallel-to-serial conversion unit converts the multi-channel parallel pseudo-random sequence into a high-speed serial data stream; The high-speed digital-to-analog converter converts the control signal of the controller into an analog voltage and inputs the analog voltage to the data delay line; The data delay line is used to determine a jitter pattern based on the change of the analog voltage, and determine the high-speed serial signal of the high-speed serial data stream based on the jitter pattern.

2. The high-speed serial signal jitter injection system according to claim 1, wherein The system further includes a data splitter and an error detector; The data splitter is used to split the delay signal output by the data delay line to obtain a first channel signal; The error detector is used to perform error detection on the first channel signal to obtain an error detection result.

3. The high-speed serial signal jitter injection system according to claim 2, wherein The data splitter is further used to split the delay signal output by the data delay line to obtain a second channel signal; the second channel signal is the high-speed serial signal of the high-speed serial data stream.

4. The high-speed serial signal jitter injection system according to claim 3, characterized in that The system further includes a phase detector and a high-speed analog-to-digital converter; The data splitter is further used to split the delay signal output by the data delay line to obtain a third channel signal; The phase detector is used to perform phase detection on the third channel signal and the analog voltage to obtain a phase detection voltage; The high-speed analog-to-digital converter converts the phase detection voltage into a digital signal and inputs the digital signal to the controller.

5. The high-speed serial signal jitter injection system according to any one of claims 1 to 4, characterized in that The data delay line is used to determine a jitter pattern based on the change of the analog voltage, including: When the analog voltage is at a fixed level, the data delay line determines that the jitter pattern is no jitter; When the analog voltage is a sine signal, the data delay line determines that the jitter pattern is sine jitter.

6. The high-speed serial signal jitter injection system according to claim 5, characterized in that, The data delay line is a voltage-controlled delay line.

7. The high-speed serial signal jitter injection system according to claim 6, wherein When the analog voltage is a sine signal, the data delay line determines that the jitter pattern is sine jitter, including: When the analog voltage is a sine signal, the voltage-controlled delay line determines that the jitter pattern is the sine jitter by adjusting the frequency and amplitude of the sine signal.

8. A high-speed serial signal jitter injection method, characterized in that It includes: Obtain a pseudo-random seed and a control signal; Perform shift summation parallel processing on the pseudo-random seed to obtain a multi-channel parallel pseudo-random sequence; Convert the multi-channel parallel pseudo-random sequence into a high-speed serial data stream, convert the control signal into an analog voltage, and determine a jitter pattern based on the change of the analog voltage; Determine the high-speed serial signal of the high-speed serial data stream based on the jitter pattern.

9. An electronic device, comprising a memory, a processor, and a computer program stored on the memory and running on the processor, characterized in that, When the processor executes the computer program, it implements the high-speed serial signal jitter injection method as described in claim 8.

10. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the high-speed serial signal jitter injection method as described in claim 8.

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