Processor instruction transmitting method and device

Abstract

The invention discloses a processor instruction transmitting method and device. The method comprises the steps that an instruction ID is distributed to each instruction; setting a register state information table, wherein each table item comprises a first data bit and a second data bit; the first data bit represents whether the current register is ready or not, and the second data bit records an instruction ID of an instruction depended by the non-ready register; when an instruction is transmitted and submitted, the register state information table is updated in real time according to an instruction ID and a target register number of the instruction; before an instruction is transmitted, the state of a source register is obtained and recorded by inquiring a register state information table; in the instruction transmitting process, the state of the source operand is updated in real time by monitoring the instruction ID and the write-back data of the write-back instruction. On the premise that the instruction source operand state is accurately recorded, speculative emission can be carried out under the condition that instruction data is not ready, efficient forwarding of data from an execution unit to an execution unit is achieved in the speculative emission process, and the instruction execution efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and particularly to a method and apparatus for processor instruction issue. Background Art

[0002] With the continuous development of computer technology, the performance requirements for processors are getting higher and higher. The instruction issue mechanism is one of the key factors affecting processor performance. However, during the instruction issue process, data dependencies can cause delays in instruction execution, thereby reducing the overall performance of the processor.

[0003] Therefore, it is necessary to provide a method and apparatus for processor instruction issue to solve the above problems. Summary of the Invention

[0004] In view of the problems and deficiencies existing in the prior art, the present invention provides a method and apparatus for processor instruction issue, which improve the instruction execution efficiency by allocating instruction IDs and setting a register status information table.

[0005] The technical solution adopted by the present invention to solve the above technical problems is to provide a method for processor instruction issue, including the following steps:

[0006] Before instruction issue after instruction decoding, assign an instruction ID to each instruction;

[0007] Set a register status information table, each entry of which includes a first data bit and a second data bit;

[0008] The first data bit is used to indicate whether the current register is ready, and the second data bit is used to record the instruction ID of the instruction on which the unready register depends; the register status information table is updated in real time according to the instruction ID and the destination register number of the instruction during instruction issue and commit;

[0009] Before instruction issue, query the register status information table to obtain and record the status of the source register;

[0010] During the instruction issue process, listen to the instruction ID and write-back data of the write-back instruction to update the status of the source operand in real time.

[0011] Preferably, when the first data bit is 1, it indicates that the register data corresponding to this entry is ready and the data can be directly read from the corresponding register; when the first data bit is 0, it indicates that the register corresponding to this entry is waiting for write-back;

[0012] When an instruction is issued, set the first data bit of the register status information table corresponding to the destination register of this instruction to 0, and assign the second data bit to the instruction ID of the current instruction;

[0013] When an instruction is submitted, query the register status information table corresponding to the destination register of the instruction. If the second data bit of the register status information table corresponds to the instruction ID of the instruction, set the first data bit of the register status information table to 1.

[0014] Preferably, the register status information table implements 64 entries, and the 64 entries correspond to the status information of 32 fixed-point registers and 32 floating-point registers.

[0015] Preferably, when there are source operands in the instruction to be issued, mark the data dependency relationship of the instruction to be issued by querying the register status information table.

[0016] Preferably, when all source operands are ready, the instruction to be issued can be directly issued successfully.

[0017] Preferably, when a source operand is not ready, listen for the write-back result of the execution unit with the dependency information of the source operand during the instruction issue process;

[0018] If there is an instruction in the write-back instruction whose instruction ID is the same as the instruction ID on which the source operand depends, forward the write-back result of the instruction, regard the source operand as ready, and the instruction is issued successfully;

[0019] If there is no instruction in the write-back instruction whose instruction ID is the same as the instruction ID on which the source operand depends, the source operand is not ready, the instruction issue fails, and it returns to the issue cycle to be re-issued.

[0020] Preferably, when multiple source operands are not ready, listen for the write-back results of the execution unit with the dependency information of multiple source operands simultaneously during the instruction issue process;

[0021] If all the multiple source operands are ready, the instruction is issued successfully;

[0022] If not all of the multiple source operands are ready, the instruction issue fails, update the information of the ready source operands into the instruction information, and return to the issue cycle to be re-issued.

[0023] Preferably, the bit width of the instruction ID is set according to the size of the execution unit.

[0024] Preferably, the instruction ID is released after the instruction is submitted, and the released instruction is cyclically allocated to a new instruction to be issued;

[0025] When all instruction IDs have been allocated and no new instruction ID is released, the subsequent decoded instructions are blocked. When a new instruction ID is released, continue to allocate the instruction ID and enter the next pipeline stage.

[0026] The present invention also provides a processor instruction issuing device, which comprises:

[0027] An instruction ID allocation module, which is configured to allocate an instruction ID to each instruction after instruction decoding and before issuing;

[0028] A register status information table, each entry of the register status information table includes a first data bit and a second data bit; the first data bit is used to indicate whether the current register is ready, and the second data bit is used to record the instruction ID of the instruction on which the unready register depends;

[0029] A source operand information recording module, which is configured to, before instruction issuing, obtain and record the status of the source operand by querying the register status information table;

[0030] A source operand status update and judgment module, which is configured to, during instruction issuing, update the status of the source operand in real time by listening to the instruction ID and the write-back data of the write-back instruction, and judge whether all the source operands of the instruction are ready, and use this as the basis for successful instruction issuing.

[0031] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0032] A processor instruction issuing method and device provided by the present invention, the method comprising the following steps: after instruction decoding and before issuing, allocate an instruction ID to each instruction; set a register status information table, each entry of the register status information table includes a first data bit and a second data bit; the first data bit is used to indicate whether the current register is ready, and the second data bit is used to record the instruction ID of the instruction on which the unready register depends; the register status information table is updated in real time according to the instruction ID and the destination register number of the instruction during instruction issuing and submission; before instruction issuing, obtain and record the status of the source register by querying the register status information table; during instruction issuing, update the status of the source operand in real time by listening to the instruction ID and the write-back data of the write-back instruction, and on the premise of accurately recording the status of the instruction source operand, speculative issuing can be performed when the instruction data is not ready, and efficient forwarding of data from execution unit to execution unit can be achieved during the speculative issuing process, thereby improving the instruction execution efficiency.

[0033] Further, when there are source operands in the instruction to be issued, by querying the register status information table, the data readiness and data dependency relationships of the instruction to be issued are marked. When all source operands are ready, the instruction to be issued can be directly issued successfully; when one source operand is not ready, during the instruction issuance process, the write-back results of the execution unit are monitored using the dependency information of this source operand; if among the written-back instructions, there is an instruction with the same instruction ID as the instruction on which this source operand depends, then the write-back result of this instruction is forwarded, regarding this source operand as ready, and the instruction is issued successfully; if among the written-back instructions, no instruction with the same instruction ID as the instruction on which this source operand depends is matched, then this source operand is not ready, the instruction issuance fails, and it returns to the issue cycle for re-issuance; when multiple source operands are not ready, during the instruction issuance process, the write-back results of the execution unit are simultaneously monitored using the dependency information of multiple source operands; if all of the multiple source operands are ready, the instruction is issued successfully; if not all of the multiple source operands are ready, the instruction issuance fails, the information of the ready source operands is updated into the instruction information, and it returns to the issue cycle for re-issuance. Brief Description of the Drawings

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention, rather than all embodiments. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0035] Figure 1 It is a flowchart of the processor instruction issuance method of a preferred embodiment of the present invention.

[0036] Figure 2 It is a schematic diagram of the architecture of the register status information table in the processor instruction issuance method of a preferred embodiment of the present invention.

[0037] Figure 3 It is a schematic diagram of the structure of the processor instruction issuance device of a preferred embodiment of the present invention. Detailed Embodiments

[0038] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are some, rather than all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0039] The following will detail the technical solutions of the present invention with specific embodiments.

[0040] Based on the problems existing in the prior art, an embodiment of the present invention provides a method and device for processor instruction issuance, which improve the instruction execution efficiency by allocating instruction IDs (Identifications) and setting a register status information table.

[0041] Now refer to Figure 1 - Figure 2 , an embodiment of the present invention provides a method for processor instruction issuance, including the following steps:

[0042] Step S1: After instruction decoding and before issuance, assign an instruction ID to each instruction;

[0043] Step S2: Set a register status information table, and each entry of the register status information table includes a first data bit and a second data bit;

[0044] Step S3: The first data bit is used to indicate whether the current register is ready, and the second data bit is used to record the instruction ID of the instruction on which the unready register depends; the register status information table is updated in real time according to the instruction ID and the destination register number of the instruction during instruction issuance and submission;

[0045] Step S4: Before instruction issuance, query the register status information table to obtain and record the status of the source register;

[0046] Step S5: During instruction issuance, listen to the instruction ID and the written-back data of the write-back instruction to update the status of the source operand in real time.

[0047] Specifically, in step S1, the instruction IDs are allocated in sequence. The instruction ID serves as the identifier of the instruction and is the main basis for data forwarding.

[0048] In step S2, the first data bit is a 1-bit ready bit, and the second data bit is an instruction ID bit. The second data bit, that is, the instruction ID bit, records the instruction ID of the instruction that will be written back to this register.

[0049] In steps S4 and S5, it is preset that each instruction has at most one destination register. Before each instruction is issued, at most one entry of the register status information table is updated. After each instruction is submitted, at most one entry of the register status information table is updated.

[0050] Specifically, the update of the register status information table is based on the destination register of the data. The destination register is the result register of an instruction. After the instruction calculation is completed, the result needs to be written back to the result register. The status of the source operand comes from the register status information table. After the instruction queries the register status information table, the register status information is saved to the source operand status information. The content of the source operand status information is the same as the register status information. When the instruction is issued, it is necessary to determine whether the source operand is ready and the dependent instructions, etc.

[0051] For example, Instruction 1 and Instruction 2 are data-dependent instructions. Among them, Instruction 1: x1 + x2 = x3; Instruction 2: x3 + x4 = x5.

[0052] When Instruction 1 is issued, the status information table of the destination register x3 will be updated to not ready, and the instruction ID of Instruction 1 will be recorded. When Instruction 1 is committed, the result will be written back to the x3 register, and at the same time, the status information table of x3 will be updated to ready. Instruction 2 is issued after Instruction 1. When Instruction 2 is issued, Instruction 1 may be in two situations: The first situation is that Instruction 1 has been committed, and at this time, the status of x3 is ready. At this time, Instruction 2 directly obtains the source operand from the x3 register. The second situation is that Instruction 1 has not been committed, and the status of x3 is not ready. At this time, Instruction 2 saves the status information of x3 as the status information of the source operand, that is, not ready, and the dependent instruction is Instruction 1. Then wait for Instruction 1 to write back and use the write-back result of Instruction 1.

[0053] In a specific implementation, when the first data bit is 1, it indicates that the register data corresponding to the table entry is ready and the data can be directly read from the corresponding register; when the first data bit is 0, it indicates that the register corresponding to the table entry is waiting for write-back.

[0054] When an instruction is issued, the first data bit of the register status information table corresponding to the destination register of the instruction is set to 0, and the second data bit is assigned the instruction ID of the current instruction.

[0055] When an instruction is committed, query the register status information table corresponding to the destination register of the instruction. If the second data bit of the register status information table corresponds to the instruction ID of the instruction, set the first data bit of the register status information table to 1.

[0056] In a specific implementation, the register status information table has 64 entries, and the 64 entries correspond to the status information of 32 fixed-point registers and 32 floating-point registers.

[0057] In a specific implementation, when there are source operands in the instruction to be issued, the data dependency relationship of the instruction to be issued is marked by querying the register status information table.

[0058] Specifically, a Ready bit is added to each source operand, and an instruction ID bit is added to each source operand. When the Ready bit is 1, it indicates that the current operand of the current instruction is ready. When the Ready bit is 0, it means that the current operand of the current instruction requires the result forwarding of other instructions. The instruction ID bit is the instruction ID of the dependent instruction. In the specific implementation, since the dependent instruction ID of the source operand and the data of the source operand are mutually exclusive, that is, if the source operand is ready, only the source operand needs to be saved in the instruction information, and there is no dependent instruction. If the source operand is not ready, the dependent instruction ID of the source operand needs to be saved in the instruction information, and there is no source operand data to be saved at this time. Therefore, in the instruction information, the dependent instruction ID bit of the source operand can reuse the source operand data bit. When the Ready bit is 0, this group of signals saves the dependent instruction ID of the source operand. When the Ready bit is 1, this group of signals saves the source operand data.

[0059] In the specific implementation, when all source operands are ready, the instruction to be issued can be directly issued successfully.

[0060] In the specific implementation, when a source operand is not ready, the write-back result of the execution unit is monitored by using the dependency information of the source operand during the instruction issue process;

[0061] If there is an instruction in the write-back instruction with the same instruction ID as the instruction on which the source operand depends, then forward the write-back result of this instruction, consider the source operand as ready, and the instruction is issued successfully;

[0062] If there is no instruction in the write-back instruction that matches the instruction ID on which the source operand depends, then the source operand is not ready, the instruction issue fails, and it returns to the issue cycle to be re-issued.

[0063] In the specific implementation, when multiple source operands are not ready, the write-back results of the execution unit are simultaneously monitored by using the dependency information of multiple source operands during the instruction issue process;

[0064] If all of the multiple source operands are ready, the instruction is issued successfully;

[0065] If not all of the multiple source operands are ready, the instruction issue fails, updates the information of the ready source operands to the instruction information, and returns to the issue cycle to be re-issued.

[0066] Specifically, the number of multiple source operands may be one, two, or three. The source operands need to be read from the general-purpose registers. After decoding, each source operand corresponds to a general-purpose register number. Before the instruction is issued, each source operand needs to query the corresponding register status information entry, and the query index is the general-purpose register number of the source operand.

[0067] According to the query result, if the Ready bit of the register status information table entry corresponding to the register number of a source operand is 1, it indicates that the register is not in the waiting write-back state. At this time, the read value of the corresponding general register can be directly assigned to the corresponding source operand, and the current source operand is marked as ready in the instruction information. If the Ready bit of the register status information table entry corresponding to the register number of a source operand is 0, it indicates that the register is in the waiting write-back state. At this time, the current source operand needs to be marked as not ready in the instruction information, and the instruction ID of the instruction waiting to write back this source operand is recorded simultaneously.

[0068] In the instruction information with multiple source operands, the information of each source operand needs to be recorded separately.

[0069] Specifically, after recording the source operand information of the instruction, the instruction can be speculatively issued without waiting for the source operand to be ready. During the instruction issue process, monitor the write-back information of each execution unit. If the write-back instruction ID matches the source operand dependent instruction ID, the write-back data is directly forwarded to the source operand channel of the current instruction. After forwarding, if all source operands are ready, the current instruction's speculative issue is successful; otherwise, if there are still source operands not ready, the speculatively issued instruction needs to be retreated to the speculative issue cycle and speculatively issued again.

[0070] Each time the speculatively issued instruction is retreated to the speculative issue cycle, the source operands that have been successfully forwarded need to be saved together, and the status of the successfully forwarded source operands is set to Ready. When speculatively issuing next time, there is no need to monitor the write-back of the execution unit with the currently ready source operands, and only the not-yet-ready source operands need to be used to monitor the write-back of the forwarding execution unit.

[0071] In a specific implementation, the bit width of the instruction ID is set according to the size of the execution unit. For example, an instruction ID width of 3 bits means that the execution unit can accommodate 8 instructions simultaneously, and a 4-bit instruction ID width means that the execution unit can accommodate 16 instructions simultaneously.

[0072] In a specific implementation, the instruction ID is released after the instruction is committed, and the released instruction is cyclically assigned to new instructions to be issued. In this way, in the entire execution pipeline, each instruction corresponds to a unique instruction ID. When all instruction IDs have been assigned and no new instruction ID is released, the subsequent decoded instructions are blocked. When a new instruction ID is released, the instruction ID is continued to be assigned and enters the next pipeline stage. Once the instruction ID is assigned, it is bound to the current instruction, saved in the instruction information, and passed through the pipeline with the instruction until the instruction submission is completed and the instruction ID is released.

[0073] The following is an example description of the processor instruction emission method:

[0074] The decoding module 21 decodes the instruction information. The decoded instruction information includes information such as the instruction type, instruction register number, and instruction immediate value. The instruction register number accesses the register status information table 22, updates the instruction information according to the result of accessing the register status information table 22, and records the status of each source operand in the instruction information. The result of the speculative emission of the previous instruction can be used as the selection basis of the multiplexer 23. If the speculative emission fails, the multiplexer 23 selects the instruction information with speculative emission failure as the instruction for the next speculative emission to enter the instruction emission register 24. At the same time, it blocks the instruction information sent by the decoding module 21 from entering the instruction emission register 24 and holds the instruction in the decoding module 21. If there is no instruction in the emission cycle for speculative emission, or there is an instruction for speculative emission and the speculative emission is successful, the multiplexer 23 selects the instruction sent by the decoding module 21 as the instruction for the next speculative emission to enter the instruction emission register. The selection result of the multiplexer 23 enters the channel of the instruction emission register 24. After the instruction is output from the instruction emission register 24, speculative emission is performed. During the speculative emission process, the source operand information in the instruction information is transmitted to the source bypass module 25. The source bypass module 25 mainly focuses on the unready source operand information and obtains the write-back information through the execution unit 26 at the same time. If the instruction ID corresponding to the instruction being written back by the execution unit 26 is the same as the dependent instruction ID of the unready source operand, the write-back data is forwarded to the instruction being emitted through the source bypass module 25, and at the same time, the status of the corresponding source operand in the instruction information being emitted is updated to ready. After the arbitration of the source bypass module 25 ends, if there are still source operands in the instruction that are ready, the source bypass module 25 outputs an instruction emission failure signal, and at the same time transmits it to the selection end and the instruction emission end of the multiplexer 23. The selection end of the multiplexer 23 is mainly used to select the instruction with speculative emission failure for re-emission, and the speculative emission failure signal at the instruction emission end is used to prevent the unready instruction from being emitted to the execution unit 26.

[0075] An embodiment of the present invention further provides a processor instruction emission device, and the device includes:

[0076] An instruction ID allocation module 31, which is used to allocate an instruction ID to each instruction after instruction decoding and before emission;

[0077] A register status information table 32, each entry of the register status information table includes a first data bit and a second data bit; the first data bit is used to indicate whether the current register is ready, and the second data bit is used to record the instruction ID of the instruction on which the unready register depends;

[0078] A source operand information recording module 33, which is used to obtain and record the status of the source operand by querying the register status information table before instruction issuance;

[0079] A source operand status update and determination module 34, which is used to update the status of the source operand in real time by listening to the instruction ID and the write-back data of the write-back instruction during the instruction issuance process, and determine whether all the source operands of the instruction are ready, and use this as the basis for successful instruction issuance.

[0080] In summary, a processor instruction issuance method and device provided by the present invention, the method includes the following steps: before instruction issuance after instruction decoding, assign an instruction ID to each instruction; set a register status information table, each entry of the register status information table includes a first data bit and a second data bit; the first data bit is used to indicate whether the current register is ready, and the second data bit is used to record the instruction ID of the instruction on which the unready register depends; the register status information table is updated in real time according to the instruction ID and the destination register number of the instruction during instruction issuance and submission; before instruction issuance, obtain and record the status of the source register by querying the register status information table; during the instruction issuance process, update the status of the source operand in real time by listening to the instruction ID and the write-back data of the write-back instruction. On the premise of ensuring accurate recording of the status of the instruction source operand, speculative issuance can be performed when the instruction data is not ready, and efficient forwarding of data from execution unit to execution unit can be achieved during the speculative issuance process, thereby improving the instruction execution efficiency.

[0081] Further, when there are source operands in the instruction to be issued, query the register status information table to mark the data readiness and data dependency of the instruction to be issued. When all source operands are ready, the instruction to be issued can be directly issued successfully; when a source operand is not ready, listen to the write-back result of the execution unit with the dependency information of the source operand during the instruction issuance process; if there is an instruction in the write-back instruction with the same instruction ID as the instruction on which the source operand depends, forward the write-back result of the instruction, regard the source operand as ready, and the instruction is issued successfully; if there is no instruction in the write-back instruction that matches the same instruction ID as the instruction on which the source operand depends, the source operand is not ready, the instruction issuance fails, and the instruction returns to the issue stage for re-issuance; when multiple source operands are not ready, listen to the write-back results of the execution unit with the dependency information of multiple source operands at the same time during the instruction issuance process; if all the multiple source operands are ready, the instruction is issued successfully; if not all the multiple source operands are ready, the instruction issuance fails, update the information of the ready source operands to the instruction information, and return to the issue stage for re-issuance.

[0082] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A processor instruction transmission method, characterized in that: The following steps are involved: After the instruction is decoded but before it is issued, an instruction ID is assigned to each instruction; Setting a register status information table, wherein each table entry of the register status information table includes a first data bit and a second data bit; The first data bit is used to indicate whether the current register is ready, and the second data bit is used to record the instruction ID of the instruction on which the unready register depends; the register status information table is updated in real time according to the instruction ID and the destination register number of the instruction when the instruction is issued and submitted; Before the instruction is issued, the state of the source register is obtained and recorded by querying the register state information table; During the instruction issuance process, the state of the source operand is updated in real time by monitoring the instruction ID and write-back data of the write-back instruction.

2. The processor instruction issuing method according to claim 1, characterized in that: When the first data bit is 1, it indicates that the register data corresponding to the table entry is ready, and data can be directly read from the corresponding register; when the first data bit is 0, it indicates that the register corresponding to the table entry is waiting for write-back; When an instruction is issued, the first data bit of the register state information table corresponding to the destination register of the instruction is set to 0, and the second data bit is assigned the instruction ID of the current instruction; When an instruction is submitted, the register status information table corresponding to the destination register of the instruction is queried. If the second data bit of the register status information table corresponds to the instruction ID of the instruction, the first data bit of the register status information table is set to 1.

3. The processor instruction issuing method according to claim 1, characterized in that: The register status information table implements 64 entries, and the 64 entries correspond to status information of 32 fixed-point registers and 32 floating-point registers.

4. The processor instruction issuing method according to claim 1, characterized in that: When there is a source operand in the instruction to be issued, the data dependency of the instruction to be issued is marked by querying the register status information table.

5. The processor instruction issuing method according to claim 4, characterized in that: When all source operands are ready, the instruction to be issued can be directly issued successfully.

6. The processor instruction issuing method according to claim 4, characterized in that: When a source operand is not ready, the dependency information of the source operand is used to monitor the write-back result of the execution unit during instruction issuance; If there is an instruction with the same instruction ID as the instruction that the source operand depends on among the instructions written back, the write-back result of the instruction is forwarded, the source operand is considered ready, and the instruction is successfully issued; If the instruction written back does not match the instruction with the same instruction ID as the source operand depends on, the source operand is not ready, the instruction issuance fails, and the issuance is returned to re-issue.

7. The processor instruction issuing method according to claim 6, characterized in that: When multiple source operands are not ready, the write-back results of the execution units are monitored simultaneously using dependency information of the multiple source operands during instruction issuance; If the plurality of source operands are all ready, the instruction is issued successfully; If the plurality of source operands are not all ready, the instruction issuance fails, the information of the ready source operands is updated into the instruction information, and the issuance is returned to be reissued.

8. The processor instruction issuing method according to claim 1, characterized in that: The bit width of the instruction ID is set according to the size of the execution unit.

9. The processor instruction issuing method according to claim 1, characterized in that: The instruction ID is released after the instruction is submitted, and the released instruction is cyclically assigned to a new instruction to be issued; When all instruction IDs have been allocated and no new instruction IDs are released, the subsequent decoded instructions are blocked. When new instruction IDs are released, instruction IDs continue to be allocated and enter the next level of the pipeline.

10. A processor instruction transmitting device, characterized in that: The device comprises: An instruction ID allocation module, which is used to allocate an instruction ID to each instruction after the instruction is decoded but before it is transmitted; A register status information table, each table entry of the register status information table includes a first data bit and a second data bit; the first data bit is used to indicate whether the current register is ready, and the second data bit is used to record the instruction ID of the instruction on which the unready register depends; A source operand information recording module, which is used to obtain and record the state of the source operand by querying the register state information table before the instruction is issued; The source operand status update and judgment module is used to update the status of the source operands in real time during the instruction issuance process by monitoring the instruction ID and write-back data of the write-back instruction, and to judge whether all the source operands of the instruction are ready, which serves as the basis for successful instruction issuance.

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