System and method for dynamically combining memory resources and allocating multi-level switches

Abstract

The present invention discloses a system and method for dynamically combining memory resources for multi-level switches, relating to the field of computer technology. The system comprises: dynamically acquiring and analyzing type data of a target configuration space when a server is started; an identification engine identifying a first hardware resource connected to a current peripheral interconnection link according to the type data; and, when the first hardware resource includes a multi-level switch, identifying a second hardware resource connected to the multi-level switch; determining which devices require resource reservation according to the identification result of the second hardware resource without checking each possible connection situation one by one; and allocating the first memory resource to the multi-level switch and the second hardware resource based on the second identification result, thereby avoiding consuming too much time for resource allocation when the server is started when there are too many switches in the peripheral interconnection link, thereby reducing the time consumption when the server is started, improving the startup efficiency of the server, and further ensuring the stability and stability of the memory resource allocation.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a system and method for dynamically combining memory resources of a multi-level switch. Background Art

[0002] Smart NICs contain numerous devices, including physical or virtual devices such as network ports, virtual network adapters, and storage devices. These devices require memory resources, and some memory resources are prioritized. For example, 32-bit memory resources require high priority. However, some Data Processing Units (DPUs) also contain switch chips, which connect to other PCI devices and thus require memory allocation. Furthermore, in servers, not only do DPUs contain switch chips, but the server motherboard or PCI device cards also contain similar switch chips. These switch chips and the PCI devices underlying them also require resources. However, 32-bit memory resources are limited to a maximum of 4GB. Exceeding 4GB will render some devices unusable, such as display interfaces (DPU display interface or onboard VGA interface) unavailable.

[0003] Related technologies reserve resources when the server starts up. However, the Switch chip can contain multiple levels, and some levels require memory resource reservation while others do not. Whether to reserve resources depends on the purpose and device of the port. At this time, since the server may involve many Switch chips and the Switch chip level cannot be fixed and it is impossible to predict which specific Switch chip requires resource reservation, the server startup time is significantly extended. Summary of the Invention

[0004] The present invention provides a memory resource allocation method, electronic device, storage medium and program product, which at least solve the problem that the memory resource allocation method in the related art causes a long server startup time.

[0005] The present invention provides a system for dynamically combining memory resources and allocating them using a multi-level switch, comprising: at least one processing circuit of a server, the at least one processing circuit being connected to at least one peripheral interconnection link, the at least one processing circuit being used to: execute a read engine to read type data of a target configuration space of the engine when the server is started; propagate the type data to an identification engine, the identification engine identifying a first hardware resource connected to the current peripheral interconnection link based on the type data, and if the first hardware resource includes a multi-level switch, identifying a second hardware resource connected to the multi-level switch; propagating an identification result of the identification engine to an allocation engine, the allocation engine determining, based on a first identification result of the first hardware resource, that the current peripheral interconnection link is connected to a multi-level switch, and then, based on a second identification result of the second hardware resource, allocating a first memory resource to the multi-level switch and the second hardware resource.

[0006] The present invention also provides a server comprising the above-mentioned multi-level switch dynamic combination memory resource allocation system.

[0007] The present invention also provides a method for dynamically combining memory resources of a multi-level switch, using at least one processing circuit connected to at least one peripheral interconnection link, wherein the at least one processing circuit is used to: execute a reading engine to read type data of a target configuration space of the engine when the server is started; propagate the type data to an identification engine, the identification engine identifies a first hardware resource connected to the current peripheral interconnection link based on the type data, and if the first hardware resource includes a multi-level switch, identifies a second hardware resource connected to the multi-level switch; propagate the identification result of the identification engine to an allocation engine, the allocation engine determines that the current peripheral interconnection link is connected to a multi-level switch based on a first identification result of the first hardware resource, and allocates memory resources to the multi-level switch and the second hardware resource based on a second identification result of the second hardware resource.

[0008] The present invention also provides a computer-readable storage medium storing a computer program, wherein when the computer program is executed by a processor, the steps of any of the above-mentioned methods for dynamically combining memory resources of a multi-layer switch are implemented.

[0009] The present invention also provides a computer program product, comprising a computer program, which implements the steps of any of the above-mentioned methods for dynamically combining memory resources of a multi-level switch when executed by a processor.

[0010] The present invention dynamically obtains and analyzes the type data of the target configuration space when the server is started. The recognition engine identifies the first hardware resource connected to the current peripheral interconnection link based on the type data, and when the first hardware resource includes a multi-level switch, identifies the second hardware resource connected to the multi-level switch. Based on the second recognition result of the second hardware resource, it is determined which devices need to reserve resources, without having to check each possible connection situation one by one. Based on the second recognition result, the first memory resource is allocated to the multi-level switch and the second hardware resource, avoiding the situation where there are too many switches in the peripheral interconnection link, resulting in excessive time spent on resource allocation when the server is started, thereby reducing the time consumption when the server is started, improving the startup efficiency of the server, and thus ensuring the stability and stability of memory resource allocation. Therefore, it can solve the technical problem in the related art that the memory resource allocation method causes a long server startup time. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the embodiments of the present invention, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0012] Figure 1 A schematic diagram of a system for dynamically combining memory resources and allocating multi-level switches provided by an embodiment of the present invention;

[0013] Figure 2 A schematic diagram of a link of a Switch chip provided in one embodiment of the present invention;

[0014] Figure 3 This is an example diagram of a link of a multi-level switch chip provided by another embodiment of the present invention;

[0015] Figure 4 A schematic diagram of the physical connection of a server motherboard provided by one embodiment of the present invention;

[0016] Figure 5 A schematic diagram of the structure of a DPU device provided in one embodiment of the present invention;

[0017] Figure 6 A flowchart of a method for dynamically combining memory resources of a multi-level switch provided according to an embodiment of the present invention;

[0018] Figure 7 A diagram showing component execution connection relationships of a multi-level switch combined memory resource allocation system during a server startup phase according to an embodiment of the present invention;

[0019] Figure 8An example diagram of memory resource allocation of a server during the startup phase provided by one embodiment of the present invention;

[0020] Figure 9 An example diagram of memory resource allocation of a server during the startup phase provided by another embodiment of the present invention;

[0021] Figure 10 A diagram illustrating a component execution connection relationship of a multi-level switch combined memory resource allocation system when a server enters an operating system stage according to an embodiment of the present invention;

[0022] Figure 11 This is an example diagram of memory resource allocation for a server entering an operating system, provided by one embodiment of the present invention. DETAILED DESCRIPTION

[0023] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0024] It should be noted that, in the description of the present invention, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. The terms "first," "second," etc., in the present invention are used to distinguish similar objects, and are not used to describe a particular order or precedence.

[0025] In order to enable those skilled in the art to better understand the solutions of the present invention, the present invention is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0026] An embodiment of the present invention provides a system for dynamically combining memory resources and allocating them to a hierarchical switch.

[0027] like Figure 1 As shown, the system 10 for dynamically combining memory resource allocation using a hierarchical switch includes:

[0028] The server has at least one processing circuit 11, and at least one processing circuit 11 is connected to at least one peripheral interconnection link. The at least one processing circuit 11 is used to: execute a reading engine to read the type data of the target configuration space of the reading engine when the server is started; propagate the type data to the recognition engine, and the recognition engine identifies the first hardware resource connected to the current peripheral interconnection link according to the type data, and if the first hardware resource includes a multi-level switch, identifies the second hardware resource connected to the multi-level switch; propagate the recognition result of the recognition engine to the allocation engine, and the allocation engine determines that the current peripheral interconnection link is connected to a multi-level switch based on the first recognition result of the first hardware resource, and allocates the first memory resource to the multi-level switch and the second hardware resource based on the second recognition result of the second hardware resource.

[0029] Among them, the target configuration space can be a PCI configuration space. When the server starts, the BIOS (Basic Input / Output System) of the embodiment of the present invention reads the type and subtype of the PCI configuration space during the PCI (Peripheral Component Interconnect) enumeration phase of the DXE phase. The peripheral interconnection link of the embodiment of the present invention can be a PCI link; the first hardware resource can include peripheral interconnection devices (PCI devices), switches, etc. The switch can be a Switch chip; a single-layer switch is connected to other devices without connecting to a switch; a multi-layer switch is a switch connected to at least another switch, which is a hierarchical structure; the second hardware resource can include PCI devices, peripheral interconnection ports (PCI ports), etc. The link connection of a single-layer switch is as follows: Figure 2 As shown, the link connections of the multi-level switches are as follows Figure 3 shown.

[0030] In an embodiment of the present invention, if there are too many devices when the current device starts, some device resources will not be effectively allocated, that is, the 32-bit resources of 4G cannot meet the total demand of the devices exceeding the limit of 4G, which will cause some devices to be unusable. If the PCI link devices of the current server are all directly connected to the PCI end bridge port of the CPU (Central Processing Unit), there is no need to worry about insufficient 4G resources. However, if the PCI link passes through multiple levels of Switch chips or multiple PCI root bridges connect multiple PCI Switches, there will be a problem of insufficient Switch resource reservation, which will cause the devices under the system to fail to work normally. Therefore, the embodiment of the present invention first needs to determine the hardware resource data on the current PCI link according to the type and subtype of the PCI configuration space to facilitate the subsequent memory resource allocation for all devices on the server. Resource allocation includes both resource reservation allocation and currently identified device resource allocation. The physical link of the server motherboard is as follows Figure 4 As shown, these hardware resources all require reserved memory resources, so it takes too much time to allocate resources when the server starts, resulting in extended server startup time and low startup efficiency.

[0031] Specifically, an embodiment of the present invention can read the type data of the PCI configuration space of the engine when the server is started, and the identification engine identifies the first hardware resource connected to the current peripheral interconnection link based on the type data, and determines whether the current PCI link contains a multi-layer Switch chip. When there are too many Switch chips in the PCI link, the BIOS will spend too much time on resource allocation due to the excessive number of Switch chips when the server is started. Therefore, in order to optimize the startup time of the server and ensure that the resource allocation of a specific Switch chip is fixed, an embodiment of the present invention can identify the second hardware resource connected to the multi-level switch, determine which devices need to reserve resources based on the second identification result of the second hardware resource, without having to check each possible connection situation one by one, and allocate the first memory resource to the multi-level switch and the second hardware resource to reduce the time consumption when the server is started and improve the startup efficiency of the server.

[0032] In the embodiment of the present invention, the allocation engine is configured to allocate the first memory resource to the peripheral interconnection device when it is determined that the peripheral interconnection link is connected to the peripheral interconnection device according to the first identification result of the first hardware resource.

[0033] It can be understood that, in an embodiment of the present invention, when it is determined, based on the first identification result of the first hardware resource, that a peripheral interconnection device is connected to the current peripheral interconnection link, the allocation engine allocates the first memory resource to the peripheral interconnection device, and normally allocates 32-bit resources to the peripheral interconnection device.

[0034] In an embodiment of the present invention, the allocation engine is configured to: before allocating the first memory resource to the peripheral interconnect device, if the peripheral interconnect device is a data processor, allocate the first memory resource according to the resource size of the data processor.

[0035] Because a DPU (Data Processing Unit) typically has specific memory resource requirements, embodiments of the present invention can read the identifier of a peripheral interconnect device and use the identifier to identify whether the peripheral interconnect device is a DPU, so as to adopt different memory allocation strategies for the peripheral interconnect device. If the peripheral interconnect device is not a DPU, memory resources are allocated normally to it. If it is a DPU device, memory resources are allocated to the peripheral interconnect device based on the resource size of the DPU to ensure the normal operation of the DPU device.

[0036] It should be noted that DPU is a dedicated processor that provides data center infrastructure virtualization services such as network, storage, security, and management around data processing. It is a computing architecture composed of CPUs based on ARM / X86 architectures and dedicated hardware acceleration engines such as ASIC (Application Specific Integrated Circuit) / NP (Network Processor) / FPGA (Field Programmable Gate Array). It forms an entity that provides virtualization functions and requires sufficient resources to support complex service operations. Therefore, resources need to be reserved. The structure of DPU is as follows: Figure 5 As shown, DPU products have been widely used in various architecture servers in data centers (often in the form of smart network cards), including but not limited to X86 architecture and ARM architecture. However, no matter what architecture server, when using the smart network card, it is necessary to reserve resources for the smart network card in advance. This is because the smart network card contains many devices, such as network port devices, virtual network cards, storage devices SSD and other physical or virtual devices. These devices all need to use memory resources and some memory resources are prioritized. For example, 32-bit memory resources need to be highly prioritized. Therefore, it is necessary to reserve resources for the DPU in advance to ensure that various devices can obtain the required memory resources and operate normally.

[0037] Among them, whether it is a data processor is judged based on the identification, specifically, the DID and VID of the peripheral interconnection device can be identified. If the DID and VID exist in the pre-set data processor identification information list, the peripheral interconnection device is judged to be a data processor, otherwise it is not a data processor.

[0038] Specifically, when the server starts, the BIOS determines whether the current PCI link contains a switch chip by reading the type and subtype of the PCI configuration space during the PCI enumeration phase of the DXE stage. If not, the BIOS continues to confirm whether the current device is a DPU device by reading the DID and VID of each PCI device. If not, 32-bit memory resources are allocated normally. If it is a DPU device, 32-bit resources are reserved based on the known 32-bit resource size of the DPU. At the same time, when counting the 32-bit resources required by other PCI devices, the PCI link physically connected to the current DPU accumulates the MMIO 32-bit resources reserved by the DPU. At the same time, the BIOS enables (turns on) the hot-swap function (hotplug function) of the PCI configuration space of the bridge of the PCI link physically connected to the DPU.

[0039] For example, the server's CPU has multiple PCI links, among which PCI link A is connected to a DPU device and several other common PCI devices (including PCI device A and PCI device B). PCI link A has a PCI link bridge for connecting the CPU and the devices on PCI link A. Based on the existing 32-bit memory resource size of the DPU device, for example, 200MB of MIMO32 resources are reserved for it. At the same time, the 32-bit memory resources required by PCI device A and PCI device B on PCI link A are also counted. For example, PCI device A requires 30MB and PCI device B requires 15MB. Therefore, the total 32-bit memory resources required by PCI link A are 200+30+15=245MB.

[0040] In an embodiment of the present invention, the allocation engine is configured to: when determining, based on a first identification result of the first hardware resource, that a current peripheral interconnection link is connected to a peripheral interconnection port and a switch, allocate the first memory resource to the peripheral interconnection port and the switch if the peripheral interconnection port is a target port.

[0041] It is understood that during the PCI enumeration phase, the BIOS of the present invention confirms whether the current PCI link has a switch chip and whether it is a specific PCI port (target port) by reading the type and subtype of the PCI configuration space. If it is a specific PCI port, 32-bit memory resources are reserved and the hotplug function is enabled in the PCI configuration space of the switch chip's upstream and downstream ports and the PCI link bridge where the switch chip is located. If it is not a specific PCI port and a PCI switch chip is present, the BIOS does not enable the hotplug function for the switch chip's upstream and downstream ports or reserve PCI port resources. Thus, by reserving resources and enabling the hotplug function only for specific PCI ports, critical devices can be ensured to receive the necessary support while reducing resource allocation to non-essential ports. If it is not a specific PCI port and a PCI switch chip is present, the BIOS does not enable the hotplug function for the switch chip's upstream and downstream ports or reserve PCI port resources, thereby avoiding unnecessary resource usage and simplifying resource management.

[0042] In an embodiment of the present invention, the allocation engine is configured to: if a peripheral interconnection device is connected to a downstream port of a current-level switch, allocate a first memory resource to the upstream port, downstream port, and peripheral interconnection device of the current-level switch; and if the downstream port of the current-level switch is idle, not allocate memory resources to the upstream port and downstream port of the current-level switch.

[0043] It's understandable that when a switch chip detects a PCI device connected to a downstream port, it allocates the required memory resources to those devices and ensures that the relevant hotplug function is enabled. If a downstream port at a certain level is not connected to any device (i.e., idle), no memory resources are allocated to that port and the hotplug function is disabled to conserve resources.

[0044] Specifically, when there is still a Switch chip on the downstream port of the Switch chip, that is, when there is a physical multi-level Switch chip in the PCI link, it is necessary to reserve resources for the PCI device of the downstream port of the multi-level Switch chip and the upstream and downstream ports of the Switch layer through which the entire PCI link passes, and set the hotplug function for the PCI configuration space of the PCI link. By reserving resources only where they are actually needed, unnecessary resource waste can be avoided. If there is no PCI device on the terminal PCI port of the multi-level Switch chip, there is no need to reserve resources and the hotplug function of the entire PCI link and the upstream and downstream ports of the Switch chips at each level will be turned off. If the above two situations intersect, the Switch port that reserves memory resources will be used to reserve memory resources.

[0045] In an embodiment of the present invention, at least one processing circuit 11 is configured to execute a read engine that reads an identifier of a peripheral interconnect device; and an allocation engine that determines a first memory resource allocation requirement based on the identifier of the peripheral interconnect device. If it is determined that the peripheral interconnect device has a first memory resource allocation requirement, the first memory resource is allocated to the upstream port, the downstream port, and the peripheral interconnect device of the current-level switch.

[0046] The identifier is used to identify the type of the peripheral interconnect device and can be a DID (Device ID) and a VID (Vendor ID). In actual implementation, the BIOS of this embodiment of the present invention reads the DID and VID of each PCI device during the PCI enumeration phase of the DXE phase.

[0047] In this embodiment of the present invention, based on the identification information obtained by the reading engine, the allocation engine analyzes this information to determine whether the first memory resource needs to be reserved for the peripheral interconnect device. If the device identification information determines that the device does require the first memory resource, the allocation engine allocates the required memory resources to the upstream and downstream ports of the current-level switch (switch chip) and the peripheral interconnect device itself.

[0048] In an embodiment of the present invention, the allocation engine is configured to allocate non-memory resources to a downstream port of a current-level switch if it is determined that the peripheral interconnection device does not have an allocation demand for the first memory resource.

[0049] Specifically, the BIOS of the embodiment of the present invention will judge the PCI device of the multi-level Switch chip. When it is confirmed through VID and DID, type, subtype, etc. that it is a PCI device that requires memory resource reservation, the BIOS will reserve resources and enable the hotplug function of the PCI configuration space of the Switch link and PCI bridge link where the terminal PCI device is located. If not, the BIOS will reserve non-memory resources for the downstream port of the Switch where the PCI terminal device is located and disable the hotplug function of this downstream port. For the upstream port of this Switch, it is necessary to determine whether there are other devices on the downstream port of the current Switch chip. If not, the upstream port will be disabled and polling will be continued until the hotplug function of this PCI link bridge is disabled. If there are other downstream ports and resources need to be reserved, the hotplug function of the upstream port of this Switch chip cannot be disabled.

[0050] Therefore, the embodiment of the present invention scans all downstream ports of the PCI device switch chip to check whether other devices are connected. If no device is connected to the downstream port of a switch chip, it is considered that the switch chip is not currently carrying any actual workload. The upstream port can be closed and polled repeatedly until the hotplug function of this PCI link bridge is disabled. If other devices are connected to the downstream port of the current switch chip, the upstream port of the switch chip must remain enabled, and memory resources must be reserved for these devices, and the hotplug function must be enabled. Therefore, the embodiment of the present invention can avoid unnecessary resource waste by dynamically determining the connection status of the downstream port of the switch chip.

[0051] In the embodiment of the present invention, at least one processing circuit 11 is configured to execute a setting engine, wherein the setting engine sets a hot-swap function for a peripheral interconnection link where the hardware resource to which the first memory resource has been allocated is located.

[0052] In the above embodiment, the present invention can enable a hot plug function for the peripheral interconnect link (e.g., PCI link) to which the hardware resource to which the first memory resource is allocated resides. By enabling the hot plug function, the required memory resources are automatically allocated to the device when it is plugged in and automatically reclaimed when it is unplugged. This enables dynamic resource management, improves resource utilization, and avoids resource waste.

[0053] In the embodiment of the present invention, at least one processing circuit 11 is configured to execute a startup engine when the identification engine polls all peripheral interconnection links, the first hardware resource, and the second hardware resource, and the startup engine starts the operating system of the server.

[0054] It is understandable that, in the embodiment of the present invention, when the identification engine has polled all peripheral interconnection links, the first hardware resources and the second hardware resources, it executes the startup engine, starts the server's operating system, and enters the next stage of memory resource allocation, namely the server's operating system stage.

[0055] In summary, the process of allocating the first memory resource when the server is started, ie, in the startup phase, in the embodiment of the present invention is as follows.

[0056] (1) When the server starts, the BIOS determines whether the current PCI link contains a switch chip by reading the type and subtype of the PCI configuration space during the PCI enumeration phase of the DXE phase. If not, the BIOS continues to confirm whether the current device is a DPU device by reading the DID and VID of each PCI device. If not, the 32-bit memory resources are allocated normally. If it is a DPU device, 32-bit resources are reserved based on the known 32-bit resource size of the DPU. At the same time, the PCI link physically connected to the current DPU accumulates the MMIO 32-bit resources reserved by the DPU when counting the 32-bit resources required by other PCI devices. At the same time, the BIOS enables the hot-plug function of the PCI configuration space of the bridge of the PCI link physically connected to the DPU, that is, the hotplug function.

[0057] (2) During the PCI enumeration stage, the BIOS confirms whether there is a Switch chip on the current PCI link and whether it is a specific PCI port by reading the type and subtype of the PCI configuration space. If it is a specific PCI port, the BIOS reserves 32-bit memory resources, sets the upstream and downstream ports of the Switch chip, and enables the hotplug function for the PCI configuration space of the PCI link bridge where the Switch chip is located. If it is not a specific PCI port and there is a PCI Switch chip, the BIOS does not enable the hotplug function for the upstream and downstream ports of the Switch chip and does not reserve PCI port resources. When there is still a Switch chip on the downstream port of the Switch chip, that is, when there are physical multi-level Switch chips on the PCI link, it is necessary to reserve resources for the PCI devices on the downstream port of the multi-level Switch chip and the upstream and downstream ports of the Switch levels passed by the entire PCI link, and set the hotplug function for the PCI configuration space of the PCI link where it is located. If there is no PCI device on the terminal PCI port of the multi-level Switch chip, there is no need to reserve resources, and the hotplug function for this entire PCI link and the upstream and downstream ports of each level of Switch chip is turned off. If the above two situations overlap, the Switch port that reserves memory resources will be used to reserve memory resources. At the same time, the BIOS will judge the terminal device of the multi-level Switch chip. If it is determined that the PCI device requires reserved memory resources through VID, DID, type, subtype, etc., the BIOS will reserve resources for the PCI configuration space of the Switch link and the PCI bridge link where this terminal PCI device is located and enable the hotplug function. If not, non-memory resources will be reserved for the downstream port of the Switch where this PCI terminal device is located, and the hotplug function of this downstream port will be turned off. For the upstream port of this Switch, it is necessary to judge whether there are other devices on the downstream port of the current Switch chip. If not, this upstream port will be closed and polled in turn until the hotplug function of this PCI link bridge is turned off. If there are other downstream ports and resource reservation is required, the hotplug function of the upstream port of this Switch chip cannot be turned off;

[0058] (3) Poll all PCI link bridges and the Switch chips and their devices under the corresponding PCI link bridges in sequence according to steps 1 and 2. After polling all the PCI links and Switch chips of all CPUs, continue to start and enter the operating system;

[0059] In summary, the embodiments of the present invention can flexibly adapt to the memory resource requirements of different types of peripheral interconnection devices, switches, and peripheral interconnection ports, avoiding insufficient memory resource allocation for the device, which may cause the device to be unable to be used normally. At the same time, it improves the utilization rate of memory resources, avoids waste of memory resources, and thus improves the overall performance and stability of the server.

[0060] In one embodiment of the present invention, at least one processing circuit is used to: after the server enters the operating system, execute a reading engine, the reading engine reads the memory allocation function of the server; and an allocation engine reallocates the first memory resource of the server according to the memory allocation function.

[0061] The memory allocation function is used to determine whether resources need to be reallocated. The memory allocation function can be identified through the Grub parameter of the operating system, which is PCI=realloc.

[0062] Since resource requirements of a server may change when it enters the operating system, the embodiment of the present invention reads the memory allocation function of the server after the server enters the operating system to determine whether the first memory resource needs to be reallocated.

[0063] In one embodiment of the present invention, at least one processing circuit is used to: execute a reading engine before reallocating the first memory resource of the server according to the memory allocation function, wherein the reading engine reads the reallocation requirement of the server; and an allocation engine reallocates the first memory resource of the server according to the reallocation requirement and the memory allocation function.

[0064] It is understandable that the embodiment of the present invention can determine whether the first memory resource of the server needs to be reallocated based on the reallocation requirement and the memory allocation function.

[0065] In an embodiment of the present invention, if the reading engine does not read the reallocation requirement of the server, the allocation engine deletes the memory allocation function and retains the allocation parameters of the first memory resource in the server startup phase.

[0066] It is understandable that the embodiment of the present invention deletes the memory allocation function when no reallocation request from the server is read, so that memory resources are not reallocated when the server enters the operating system, and the allocation parameters of the first memory resource in the server startup phase are retained.

[0067] Specifically, when the server enters the operating system, the Grub interface of the operating system adds the PCI=realloc parameter to the Grub parameters by default. If the system does not need to reallocate the memory resources allocated by the BIOS at this time, the PCI=realloc parameter will be removed from the Grub file; if the system needs to reallocate the memory resources allocated by the BIOS at this time, the PCI=realloc parameter will be retained. At this time, the operating system will reallocate all PCI resources of the server to ensure the reasonable allocation and utilization of memory resources.

[0068] In an embodiment of the present invention, at least one processing circuit 11 is used to: execute a scanning engine, the scanning engine scans all peripheral interconnection links of the server; propagate the scanning data of the scanning engine to the recognition engine, the recognition engine recognizes the scanning data, and if the current peripheral interconnection link, the first hardware resource connected to the current peripheral interconnection link, and the switch connected to the current peripheral interconnection link are recognized, the hot plug function is enabled, and the first memory resource allocated to the current peripheral interconnection link during the server startup phase is reserved.

[0069] It can be understood that the embodiment of the present invention can execute a scanning engine, propagate the scanning data of the scanning engine to the recognition engine, the recognition engine recognizes the scanning data, and when it recognizes the current peripheral interconnection link, the first hardware resource connected to the current peripheral interconnection link, and the switch connected to the current peripheral interconnection link, turns on the hot plug function, indicating that the device may change dynamically, then retains the first memory resource allocated by the current peripheral interconnection link during the server startup phase to ensure that the device can work normally when it is connected or removed, and reasonably allocates memory resources.

[0070] In an embodiment of the present invention, the identification engine is used to: if the current peripheral interconnection link, the first hardware resource connected to the current peripheral interconnection link, and the switch connected to the current peripheral interconnection link are identified, turn off the hot plug function, and allocate the engine to reallocate the first memory resource of the server according to the memory allocation function.

[0071] It can be understood that when the embodiment of the present invention identifies that the hot-swap function of the current peripheral interconnection link, the first hardware resource connected to the current peripheral interconnection link, or the switch connected to the current peripheral interconnection link is turned off, the first memory resource that has been allocated when the server is started or the device to which the first memory resource cannot be allocated is reallocated to achieve flexible allocation of memory resources to adapt to new memory resource allocation requirements.

[0072] In the embodiment of the present invention, the identification engine is configured to stop allocating the first memory resource of the server if it is identified that the current peripheral interconnection link is idle, or the switch connected to the current peripheral interconnection link is idle.

[0073] It can be understood that, in the embodiment of the present invention, when the current peripheral interconnection link space or the switch connected to the current peripheral interconnection link is idle, the first memory resources of the server are stopped from being allocated, and these resources are reserved for other more needed tasks or processes, thereby improving the overall utilization of memory resources and enabling the server to run more efficiently.

[0074] In an embodiment of the present invention, at least one processing circuit 11 is used to: execute a scanning engine, the scanning engine scans the current peripheral interconnection link level; propagate the scanning data of the scanning engine to the recognition engine, the recognition engine recognizes the scanning data, if the current peripheral interconnection link level is N, then the number of reallocations of the first memory resource is N+1; the allocation engine allocates the first memory resource according to the number of reallocations.

[0075] Since the server's peripheral interconnection link may have a multi-layer structure, the embodiment of the present invention can scan the current peripheral interconnection link layer. If a data switch is physically connected during the scanning process, the scanning continues until all layers of data switches are scanned and the final number of layers is counted. If the number of layers is N, the number of times resources are reallocated is counted as N + 1. After the scanning of the layers is completed, resources are reallocated for the scanned layers. The statistics of the number of layers and the number of reallocations can provide a basis for subsequent resource reallocation to ensure the accuracy of resource reallocation.

[0076] In an embodiment of the present invention, at least one processing circuit is used to: execute a read engine, the read engine reads the second memory resources of the server; propagate the remaining resources of the second memory resources to the recognition engine, the recognition engine identifies whether the remaining resources are less than a resource threshold; propagate the recognition result of the recognition engine to the allocation engine, and when the remaining resources are less than the resource threshold, the allocation engine stops allocating the first memory resources of the server and reallocates the first memory resources that have been allocated to the hardware resources that do not support the hot-swap function and the peripheral interconnection links.

[0077] The resource threshold may be set according to specific circumstances, such as 4G.

[0078] It can be understood that the embodiment of the present invention can identify the second memory resource to optimize the allocation of the first memory resource. When the remaining resources of the second memory resource are less than the resource threshold, it indicates that the current memory resources are insufficient, and the allocation of the first memory resource of the hardware resources of the current level or the next level is stopped to improve the rationality and effectiveness of the memory resource allocation.

[0079] In an embodiment of the present invention, the allocation engine is further used to: if any switch of the multi-level switch does not support the hot-swap function, reallocate the first memory resource of the peripheral interconnection link where the switch that does not support the hot-swap function is located; if all switches of the multi-level switch support the hot-swap function, retain the allocation parameters of the first memory resource in the server startup phase.

[0080] It can be understood that, in the embodiment of the present invention, if any one of the multi-level switches does not support the hot-swap function, the first memory resource of the peripheral interconnection link where the switch that does not support the hot-swap function is located is reallocated, so that the memory resources are better adapted to the link that does not support hot-swap, avoiding problems caused by the mismatch between the hot-swap-related resource allocation and the actual hardware capabilities, and making the memory resource allocation more reasonable, releasing part of the memory resources originally reserved for the hot-swap function and using them for other places that are more needed, thereby improving the overall utilization efficiency of the memory resources; when all switches of the multi-level switch support the hot-swap function, the allocation parameters of the first memory resource in the server startup phase are retained to more flexibly adapt to the dynamic changes of the device, and avoid system performance fluctuations or configuration errors that may be caused by frequent adjustments to memory allocation, thereby maintaining the overall performance and stability of the server.

[0081] Specifically, the current PCI link level is scanned. If a switch physical connection is detected during the scanning process, the scanning continues until all levels of switch chips are scanned and the final number of levels is counted. If the number of levels is N, the number of resource reallocations is counted as N+1. After the scanning level is completed, the system reallocates resources for the scanned level. Thus, the embodiment of the present invention can perform detailed resource reallocation based on the device status and hot-swap function status of each level, improve the rationality and effectiveness of resource allocation, and avoid resource conflicts and uneven resource allocation among multiple levels of devices. Specifically:

[0082] The purpose of resource allocation is to provide memory resources for connected peripheral interconnection devices to support their operation. Therefore, if there is no peripheral interconnection device under the peripheral interconnection link of the current level, it is meaningless to allocate memory resources to the peripheral interconnection link, which will cause resource waste. Therefore, no resource allocation is performed on the bridge of the current level, or the hot plug function of the data switch is turned off, indicating that there will be no device insertion or removal operation of the current data switch. The first memory resources reserved in the startup phase will not be used due to the connection or removal of the device. Therefore, the reserved first memory resources are released for subsequent allocation to other devices to improve resource utilization.

[0083] If there are peripheral interconnection devices under the peripheral interconnection link of the current level, resources will be allocated to the peripheral interconnection devices to ensure the normal operation of these devices. If the hot plug function of the data switch bridge is enabled, it indicates that devices may be connected or removed. Therefore, resources will not be allocated to the peripheral interconnection devices. The resources set at the server startup stage will be used to avoid device failure or data loss caused by reallocation of resources.

[0084] If there are peripheral interconnection devices and devices at the next level under the peripheral interconnection link of the current level, resources are allocated to the peripheral interconnection devices to ensure normal operation of the devices. It is also determined whether there are peripheral interconnection devices on the peripheral interconnection link of the next level to further determine whether resources need to be allocated to the devices at the next level, thereby achieving reasonable resource allocation for the entire hierarchical structure.

[0085] If the peripheral interconnection link of the next level is not connected to a peripheral interconnection device and the hot plug function is turned off, it means that no new device will be connected or removed, so there is no need to allocate resources for the bridge to avoid resource waste. If the peripheral interconnection link of the next level has peripheral interconnection devices, in order to ensure the normal operation of these devices, memory resources need to be allocated to them to meet the operation requirements of the devices. Or if the hot plug function of the next level is turned on, it indicates that there may be a device insertion or removal operation, so there is no need to reallocate the first memory resources.

[0086] After allocating and judging resources for peripheral interconnection links and devices at all levels, when the resource reallocation of the N+1 layer is completed, it indicates that the resource allocation work of the entire server system has been completed. Ending resource allocation can allow the system to enter a stable operating state, avoid unnecessary resource allocation operations, and improve system efficiency and stability.

[0087] Specifically, the specific operations of the embodiment of the present invention after the server enters the operating system are as follows:

[0088] (1) When the server enters the operating system, the Grub interface of the operating system adds the PCI=realloc parameter to the Grub parameter by default. If the system does not need to reallocate the memory resources allocated by the BIOS, remove this parameter from the Grub file. If the system needs to reallocate the memory resources allocated by the BIOS, retain this parameter. At this time, the operating system will reallocate all PCI resources of the server. When the system driver scans the PCI bridge and the Switch chip under the PCI bridge and the PCI configuration space hotplug function of the downstream port of the Switch chip is turned on, This device reserves resources during BIOS startup. If the hotplug function of the PCI configuration space of the PCI bridge, the switch chip under the PCI bridge, and the downstream ports of the switch chip is disabled, the operating system will reallocate the resources that the BIOS has allocated during the DXE phase or the devices to which 32-bit memory resources cannot be allocated. If there are no devices on the PCI bridge or the switch chip and the downstream ports of the switch chip in the PCI link and the hotplug function is disabled, no 32-bit memory resources need to be allocated. This ensures that the PCI devices under the system can normally obtain 32-bit memory resources and meet the conditions for use under special requirements.

[0089] (2) When reallocating resources under the system, it is necessary to scan the PCI bridge device of each PCI link. Here, only one PCI link is used as an example to illustrate; first scan the level of the current PCI link. If a switch physical connection appears during the scanning process, continue scanning until all levels of the switch chip are scanned and the final level number is counted. If the level number is N, the number of reallocated resources is counted as N+1; after the scanning level is completed, the system will reallocate resources to the scanned level. If there is no PCI terminal device under the bridge of the first level, no resources will be allocated to this bridge or Hot If the Hotplug function is not enabled, the reserved resources will be released; if there is a PCI terminal device under the first-level bridge, resources will be allocated to this terminal device. If the Hotplug function of the Switch chip bridge is enabled, the operating system will not allocate resources to this PCI device, and it can be used according to the resource size set when the BIOS is started; if there is a PCI terminal device under the first-level bridge and a lower-level bridge device, resources need to be allocated to the PCI terminal device and whether there is a PCI terminal device on the next-level bridge. If there is no terminal device on the next-level bridge and the hotplug function of the PCI configuration space of the next-level bridge is enabled, the operating system will not allocate resources to this PCI device. If the g function is closed, this bridge does not need to allocate resources. If there is a PCI terminal device under the next-level bridge, resources will be allocated to the next-level bridge. If the Hotplug function of the lower-level bridge is enabled, there is no need for the system to reallocate resources for this Switch. It can be used according to the memory resources allocated when the BIOS is started. In this way, N+1 layer resource allocation is performed until 32-bit resource allocation is completed; when all PCI device resources of the server are allocated, if 4G memory resources meet all current PCI devices, there is no problem. If 4G memory resources are insufficient, the PCI devices identified at the current level will be allocated 32-bit memory resources and there is no memory left. If resources can be allocated, no resources will be allocated to the remaining PCI devices in the current layer or the Switch bridge chips and PCI devices in the next layer. If the Switch chip of any node in the multi-layer Switch chip of the PCI link does not support the Hotplug function, the system layer will reallocate resources for this PCI link. If each Switch chip layer in the multi-layer Switch chip of the PCI link supports the Hotplug function, resources will be reserved according to the resource size allocated by the BIOS when the server is started, and no resource reallocation will be performed.

[0090] According to the multi-level switch dynamic combination memory resource allocation system proposed in an embodiment of the present invention, by dynamically obtaining and analyzing the type data of the target configuration space when the server is started, the recognition engine identifies the first hardware resource connected to the current peripheral interconnection link based on the type data, and when the first hardware resource includes a multi-level switch, identifies the second hardware resource connected to the multi-level switch, and determines which devices need to reserve resources based on the second recognition result of the second hardware resource, without having to check each possible connection situation one by one, and allocates the first memory resource to the multi-level switch and the second hardware resource based on the second recognition result, avoiding the situation where there are too many switches in the peripheral interconnection link, resulting in excessive time spent on resource allocation when the server is started, thereby reducing the time consumption when the server is started, improving the server startup efficiency, and thus ensuring the fixity and stability of memory resource allocation. Therefore, it can solve the technical problem in the related art that the memory resource allocation method causes a long server startup time.

[0091] An embodiment of the present invention further provides a server comprising the above-mentioned multi-level switch combined memory resource allocation system.

[0092] An embodiment of the present invention also provides a method for dynamically combining memory resources of a multi-level switch.

[0093] like Figure 6 As shown, the method for dynamically combining memory resources and allocating resources of a multi-level switch includes the following steps:

[0094] In step S101, at least one processing circuit connected to at least one peripheral interconnect link is used, wherein the at least one processing circuit is used to execute a read engine to read type data of a target configuration space when the server is started.

[0095] It can be understood that the embodiment of the present invention can use at least one processing circuit connected to at least one peripheral interconnection link, and the at least one processing circuit is used to execute a read engine. The read engine reads the type data of the target configuration space when the server starts when the server starts. The target configuration space can be a PCI configuration space. When the server starts, the BIOS of the embodiment of the present invention reads the type and subtype of the PCI configuration space in the PCI enumeration stage of the DXE stage.

[0096] In step S102, the type data is propagated to the identification engine, which identifies the first hardware resource connected to the current peripheral interconnect link according to the type data. If the first hardware resource includes a multi-level switch, the identification engine identifies the second hardware resource connected to the multi-level switch.

[0097] It is understandable that the embodiment of the present invention can propagate the type data of the PCI configuration space to the recognition engine, and the recognition engine identifies the first hardware resource connected to the current peripheral interconnect link to facilitate subsequent memory resource allocation.

[0098] In step S103, the identification result of the identification engine is propagated to the allocation engine. The allocation engine determines, based on the first identification result of the first hardware resource, that a multi-level switch is connected to the current peripheral interconnection link. Then, based on the second identification result of the second hardware resource, the allocation engine allocates memory resources to the multi-level switch and the second hardware resource.

[0099] It should be noted that the description of the features in the embodiment corresponding to the method for dynamically combining memory resources allocation in a multi-level switch can be found in the relevant description of the embodiment corresponding to the system for dynamically combining memory resources allocation in a multi-level switch, and will not be repeated here.

[0100] According to the method for dynamically combining memory resources allocated by multi-level switches proposed in an embodiment of the present invention, by dynamically acquiring and analyzing the type data of the target configuration space when the server is started, the recognition engine identifies the first hardware resource connected to the current peripheral interconnection link based on the type data, and when the first hardware resource includes a multi-level switch, identifies the second hardware resource connected to the multi-level switch, and determines which devices need to reserve resources based on the second recognition result of the second hardware resource, without having to check each possible connection situation one by one, and allocates the first memory resource to the multi-level switch and the second hardware resource based on the second recognition result, thereby avoiding the situation where there are too many switches in the peripheral interconnection link, resulting in excessive time spent on resource allocation when the server is started, thereby reducing the time consumption when the server is started, improving the server startup efficiency, and thus ensuring the stability and stability of memory resource allocation. Therefore, the technical problem that the memory resource allocation method in the related art causes a long server startup time can be solved.

[0101] The following describes a process of dynamically combining memory resources in a multi-level switch according to an embodiment of the present invention through a specific embodiment, specifically including:

[0102] During the server startup phase, the multi-level switches dynamically combine the execution connection relationships between the various components of the memory resource allocation system. Figure 7As shown, the BIOS controls the processing circuit during the server startup phase, which is equivalent to the BIOS performing memory resource allocation operations during the server startup phase. Specifically, the execution engine reads the type data of the target configuration space at server startup and transmits the type data to the identification engine. The identification engine identifies a first hardware resource (peripheral interconnect device, switch, etc.). If the first hardware resource includes a multi-level switch, it is necessary to identify a second hardware resource (including a peripheral interconnect port, peripheral interconnect device, etc.) connected to the multi-level switch, generate an identification result, and transmit the identification result to the allocation engine. Based on the first identification result of the first hardware resource, the allocation engine determines that the current peripheral interconnect link is connected to a multi-level switch. Based on the second identification result of the second hardware resource, the allocation engine allocates the first memory resource to the multi-level switch and the second hardware resource. After the first memory resource allocation is completed, the configuration engine sets the hot plug function for the peripheral interconnect link to which the hardware resource to which the first memory resource has been allocated. Then, the startup engine starts the server's operating system.

[0103] The following combination Figure 7 The execution connection relationship diagram between the various components in the startup phase is used to describe the specific execution process of memory resource allocation in the server startup phase. The specific process is shown in Figure 8.

[0104] 1. During server startup, the DXE phase determines whether a switch chip exists in the PCI link by reading the PCI type and subtype. If no switch chip exists in the PCI link, the DID and VID of the PCI device in the PCI link are read directly to determine whether it is a DPU or PCI-specific device. If so, 32-bit memory resources are reserved and the hotplug feature of the PCI link bridge is enabled. If no device exists, the BIOS evaluates whether it is a specific PCI port that requires memory resource reservation and supports hotplugging. If no device exists and it is not a PCI port requiring resource reservation, no memory resources are allocated. If a device exists and is not a DPU or a specific device, normal memory resource allocation is performed. It should be noted that the PCI link physically connected to the current DPU adds the DPU's reserved MMIO 32-bit resources to the 32-bit resource count of other PCI devices. Simultaneously, the BIOS enables the hotplug feature in the PCI configuration space of the bridge that physically connects to the DPU.

[0105] 2. During the PCI enumeration phase, the BIOS confirms whether the current PCI link has a switch chip and whether it is a specific PCI port by reading the type and subtype of the PCI configuration space. If it is a specific PCI port, the BIOS reserves 32-bit memory resources and sets the hotplug function of the upstream and downstream ports of the switch chip and the PCI link bridge where the switch chip is located. If it is not a specific PCI port and a PCI switch chip exists, the BIOS does not enable the hotplug function for the upstream and downstream ports of the switch chip or reserve PCI port resources.

[0106] 3. When there are multiple layers of PCI link switch chips, such as Figure 9 As shown, the BIOS first scans the depth of the PCI link, that is, the switch level. Assuming the switch level is N, the BIOS determines whether a PCI device at level N exists. If not, the hotplug function of the downstream port of the switch corresponding to port N is disabled and no memory resources are allocated. If resource reservation is required, the hotplug function of the downstream port corresponding to switch N is enabled. If a PCI device exists for the downstream port of the switch corresponding to port N, memory resources are allocated. If the system requires memory resource reallocation for this port, the hotplug function is disabled. If the system does not allocate memory resources, the hotplug function is disabled. After the N-level scan is completed, the same operation is performed on the previous level, switch N-1. At this time, if the hotplug function of the downstream port N+1 at level N is enabled, the corresponding upstream port also needs to be enabled. The hotplug functions of the downstream port at level N-1 and the upstream port at level N need to be enabled. This method is continued until all switch levels are executed, and the hotplug function of the PCI link bridge where the switch level is located is enabled.

[0107] 4. According to steps 1-3, all PCI link bridges and the switch chips and their devices under the corresponding PCI link bridges are polled in sequence. After polling all the CPU PCI links and switch chips, continue to boot and enter the operating system.

[0108] 2. The server enters the operating system stage.

[0109] The server enters the operating system stage. The multi-level switch dynamically combines the execution connection relationship between the various components of the memory resource allocation system. Figure 10As shown, the operating system control processing circuit of the server is equivalent to the server entering the operating system stage and the operating system performs the reallocation of the first memory resources, specifically: the execution reading engine reads the memory allocation function of the server and reads whether there is a memory resource reallocation demand; the allocation engine reads the result according to the memory resource reallocation demand transmitted by the reading engine, executes the deletion operation of the memory allocation function (that is, does not reallocate memory resources) or reallocates the first memory resource; after identifying the reallocation first memory resource instruction, executes the scanning engine, the scanning engine is used for the hierarchical structure of the peripheral interconnection link, hardware resources, hot plug function settings, etc., and transmits the scan data to the recognition engine; the recognition engine is used to identify the scan data and transmit it to the allocation engine; the allocation engine reallocates the first memory resource.

[0110] The following combination Figure 10 The execution connection relationship diagram between the various components in the startup phase is used to describe the specific execution process of memory resource allocation when the server enters the operating system phase. The process is as follows Figure 11 Shown, including:

[0111] 1. When the server enters the operating system, the operating system's Grub interface adds the PCI=realloc parameter to the Grub parameters by default. If the system does not need to reallocate the memory resources allocated by the BIOS, remove this parameter from the Grub file. If the system needs to reallocate the memory resources allocated by the BIOS, retain this parameter. The operating system will reallocate all PCI resources of the server. When the system driver scans the PCI bridge and the Switch chip under the PCI bridge and the PCI configuration space of the downstream port of the Switch chip, the Hotplug function is turned on. The resources reserved for this device during BIOS startup are retained. If the Hotplug function of the PCI configuration space of the PCI bridge, the Switch chip under the PCI bridge, and the downstream ports of the Switch chip is disabled, the operating system will reallocate the resources that the BIOS has allocated during the DXE phase or the devices to which 32-bit memory resources cannot be allocated. If there are no devices on the PCI bridge or Switch chip and the downstream ports of the Switch chip in the PCI link and the Hotplug function is disabled, there is no need to allocate 32-bit memory resources. This ensures that the PCI devices under the system can normally obtain 32-bit memory resources and meet the conditions for use under special requirements.

[0112] 2. When reallocating resources under the operating system, it is necessary to scan the PCI bridge device of each PCI link. If there are N-level Switch chips, the Switch chip will be reallocated N+1 times, and the upstream and downstream ports of each Switch chip and the bridge of the PCI link where the Switch chip is located must enable the hotplug function. If the Hotplug function of any node in the entire link is not turned on, resources will be reallocated. If all are turned on, the memory resources allocated when the BIIOS is started will be used for allocation. Therefore, when the BIOS is started and there is no Switch chip in the PCI link, we need to turn on the hotplug function in the bridge configuration space of the PCI link where the DPU is located, and enable the hotplug function in the PCI configuration space of the PCI link bridge of the identified PCI device, enable the hotplug function in the PCI configuration space of the PCI bridge that needs to support hot plugging under the system, and use the memory resources allocated by the BIOS by default. At the same time, when the PCI link contains a Switch, it is necessary to set the PCI of the downstream port of the Switch or reserve resources for the PCI port that needs to reserve resources. , turn on the hotplug function of the PCI configuration space of the upstream and downstream ports of the Switch chip and turn on the hotplug function of the PCI configuration space of the PCI link bridge where the Switch chip is located; the above-mentioned solution of whether the PCI link has or does not have the Switch chip tells the operating system when the Hotplug function is turned on that there is no need to allocate 32-bit memory resources to the DPU, the detected PCI devices or the PCI link ports that need to support hot plug function. At the same time, the operating system will allocate resources for all other PCI bridges and PCI devices under the system To allocate memory, you first need to scan the Switch level, add 1 to the value obtained at the level, reallocate memory resources, and reserve them. If the hotplug function of the PCI bridge is turned on and there is no device, 2M 32-bit memory resources are allocated by default for reservation. If the PCI bridge does not have the hotplug function and there is no device, no 32-bit memory resource reservation is required. If the PCI bridge does not have the hotplug function and there is a device, allocation is made based on the remaining capacity of the allocated 32-bit 4G memory resources. If the resources required by the current device are met, allocation is made. If not, no allocation is made and memory resources are isolated.

[0113] In summary, the multi-level switch of the embodiment of the present invention dynamically combines memory resources in a manner that uses BIOS to determine whether the Switch chip of the PCI link exists when the server starts. If not, the PCI device of the PCI link is directly determined, especially the DPU or a specific PCI device is actively identified, and the Hotplug function is set to be turned on for the PCI configuration space of the bridge of the PCI link where the DPU and the specific device are located. For the normally identified PCI device, resources are allocated in a normal mode and the Hotplug function of the PCI link is turned off. However, for the specific port of the PCI link, resources are reserved and the Hotplug function of the PCI link is turned off. If the hotplug function is turned on, and other PCI links do not allocate resources and turn off the Hotplug function of the corresponding PCI link; when there is a PCI link Switch chip, the downstream port of the Switch chip is judged to see whether it is necessary to reserve resources to support the hot plug function in the system and there is no PCI device, or there is a PCI device in the downstream port. When the above two situations occur, the hotplug function of the upstream and downstream ports of the Switch chip and the PCI configuration space of the PCI link bridge is enabled. If there is no special requirement, the Hotplug function of the Switch chip is turned off to facilitate the reallocation of resources in the system. If there is a PCI The BIOS of the switch chip first scans the depth of the PCI link, namely the switch level. Assuming the switch level is N, it determines whether the PCI device at level N exists. If not, the hotplug function of the downstream port of the switch corresponding to port N is disabled and no memory resources are allocated. If a PCI device exists for the downstream port of the switch corresponding to port N, memory resources are allocated. If this port requires memory resource reallocation by the system, the hotplug function is disabled. If no memory resource allocation is required by the system, the hotplug function is disabled. After the N-level scan is completed, the same operation is performed on the previous level, switch level N-1. At this time, if the hotplug function of the downstream port at level N is enabled, the corresponding upstream port also needs to be enabled. The hotplug function of the downstream port at level N-1 and the upstream port at level N needs to be enabled. This method is continued until all switch levels are executed, and the hotplug function of the PCI link bridge where the switch level is located is enabled. This new solution is convenient and fast, and can reduce resource reservation for unimportant PCI devices or unused PCI ports.

[0114] When the server enters the operating system, because the PCI=Realloc parameter already exists by default and the operating system will reallocate the system's memory resources, even if the BIOS has completed memory resource allocation, such as 32-bit memory resource allocation, the system will still reallocate memory resources. Because memory resources are limited and the location information of the DPU and specific PCI devices cannot be fixed, according to the function of the parameter, the PCI device identified later will have no resources to allocate because the memory resources have been allocated. However, the PCI link with the Hotplug function turned on does not need to reallocate memory resources. At the same time, the system will scan the Switch level. If there are N-level Switch chips, the Switch chip will be reallocated N+1 times, and the upstream and downstream ports of each Switch chip and the bridge of the PCI link where the Switch chip is located must have hotplug enabled. The Hotplug function is enabled. If the Hotplug function of any node in the entire link is not enabled, resources will be reallocated. If all are enabled, the memory resources allocated when the BIIOS is started will be used for allocation. When reallocating memory resources, the level of the scan switch is N, the number of scans is N+1, and 32-bit memory resources are allocated to PCI devices starting from N+1. When the N+1 memory resource allocation is completed, resources are allocated to PCI devices at the Nth level until all devices in the PCI link bridge have completed resource allocation. If there is insufficient 32-bit memory resources, Memory resource allocation for the switch chips and PCI devices at the lower levels is abandoned. Therefore, the BIOS must enable the Hotplug function of the PCI links where the DPU and specific PCI devices are located, and the Hotplug function of the upstream and downstream ports of the PCI link switch chip and the PCI link bridge by default. This prevents the system from reallocating memory resources and causing the DPU and specific PCI devices to be unable to function normally. If the Hotplug function of the DPU and specific PCI devices is disabled and the DPU device's 32-bit memory resources are exhausted, the resources of the DPU and specific PCI devices will be released and unable to meet memory resource requests during normal use. This may cause the DPU to fail to display or the DPU or specific PCI device functions to malfunction. The above settings ensure that the DPU and specific PCI devices can be used normally at all times, eliminating the need to worry about resource issues causing the DPU to be unusable. If system memory reallocation is not required, remove the PCI=realloc parameter in the Grub file during server startup. The memory resources allocated by the BIOS during server startup will be used by default without the need for system reallocation.

[0115] It should be noted that when there are too many Switch chips in the PCI link, the BIOS will spend too much time allocating resources when the server starts because of the excessive number of Switch chips. At this time, in order to optimize the server startup time and ensure that the resource allocation of a specific Switch chip is fixed, the resources and hotplug function of the Switch chip can be set during BIOS enumeration through the device VID or DID or through the hierarchical relationship, the device's BUS, dev, and FUN numbers to reserve resources to reduce the time consumption during server startup and improve the server startup efficiency. At the same time, resources are reserved and the hotplug function is enabled for the specific Switch chip and the PCI ports of the upstream and downstream ports, and the PCI link where the Switch chip is located.

[0116] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0117] An embodiment of the present invention further provides a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps of any of the above-mentioned multi-layer switch dynamic combination memory resource allocation method embodiments when running.

[0118] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0119] An embodiment of the present invention further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, it implements the steps of any of the above-mentioned methods for dynamically combining memory resources for multi-level switches.

[0120] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present invention.

[0121] The above is a detailed introduction to a memory resource allocation method provided by the present invention. This article uses specific examples to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core ideas. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. A system for dynamically combining memory resources and allocating multi-level switches, characterized in that: include: At least one processing circuit of the server, the at least one processing circuit being connected to at least one peripheral interconnect link, the at least one processing circuit being configured to: executing a reading engine, wherein the reading engine reads type data of a target configuration space when the server is started; Propagating the type data to an identification engine, the identification engine identifying a first hardware resource connected to the current peripheral interconnect link based on the type data, and if the first hardware resource includes a multi-level switch, identifying a second hardware resource connected to the multi-level switch; The identification result of the identification engine is propagated to the allocation engine. The allocation engine determines, based on the first identification result of the first hardware resource, that a multi-level switch is connected to the current peripheral interconnection link. Then, based on the second identification result of the second hardware resource, the allocation engine allocates the first memory resource to the multi-level switch and the second hardware resource.

2. The system for dynamically combining memory resources and allocating multi-layer switches according to claim 1, wherein: The allocation engine is used to: If a downstream port of the current level switch is connected to a peripheral interconnection device, allocating a first memory resource to the upstream port, the downstream port, and the peripheral interconnection device of the current level switch; If the downlink port of the current-level switch is idle, no memory resources are allocated to the uplink port and the downlink port of the current-level switch.

3. The system for dynamically combining memory resources of a multi-layer switch according to claim 2, characterized in that: The at least one processing circuit is configured to: executing a reading engine, wherein the reading engine reads an identification of the peripheral interconnection device; The allocation engine is used to: determine a first memory resource allocation requirement based on the identifier of the peripheral interconnection device; if it is determined that the peripheral interconnection device has the first memory resource allocation requirement, allocate the first memory resource to the upstream port, the downstream port and the peripheral interconnection device of the current level switch.

4. The system for dynamically combining memory resources and allocating multi-layer switches according to claim 3, wherein: The allocation engine is used to: If it is determined that the peripheral interconnection device does not have an allocation demand for the first memory resource, non-memory resources are allocated to the downstream port of the current-level switch.

5. The system for dynamically combining memory resources and allocating multi-layer switches according to claim 1, wherein: The allocation engine is used to: When it is determined, based on the first identification result of the first hardware resource, that a peripheral interconnection device is connected to the current peripheral interconnection link, a first memory resource is allocated to the peripheral interconnection device.

6. The system for dynamically combining memory resources and allocating multi-layer switches according to claim 5, characterized in that: The allocation engine is used to: Before allocating the first memory resource to the peripheral interconnection device, if the peripheral interconnection device is a data processor, the first memory resource is allocated according to the resource size of the data processor.

7. The system for dynamically combining memory resources and allocating multi-layer switches according to claim 1, wherein: The allocation engine is used to: When it is determined according to the first identification result of the first hardware resource that the current peripheral interconnection link is connected to a peripheral interconnection port and a switch, if the peripheral interconnection port is a target port, a first memory resource is allocated to the peripheral interconnection port and the switch.

8. The system for dynamically combining memory resources of a multi-layer switch according to any one of claims 1 to 7, characterized in that: The at least one processing circuit is configured to: A setting engine is executed, wherein the setting engine sets a hot-swap function for a peripheral interconnection link of the hardware resource to which the first memory resource has been allocated.

9. The system for dynamically combining memory resources and allocating multi-layer switches according to claim 1, wherein: The at least one processing circuit is configured to: When the identification engine polls all peripheral interconnection links, the first hardware resource, and the second hardware resource, a startup engine is executed, and the startup engine starts the operating system of the server.

10. The system for dynamically combining memory resources and allocating multi-layer switches according to claim 9, wherein: The at least one processing circuit is configured to: After the server enters the operating system, the reading engine is executed, and the reading engine reads the memory allocation function of the server; The allocation engine reallocates the first memory resource of the server according to the memory allocation function.

11. The system for dynamically combining memory resources and allocating multi-layer switches according to claim 9, wherein: The at least one processing circuit is configured to: Before reallocating the first memory resource of the server according to the memory allocation function, executing the reading engine, wherein the reading engine reads the reallocation requirement of the server; The allocation engine reallocates the first memory resource of the server according to the reallocation requirement and the memory allocation function.

12. The system for dynamically combining memory resources and allocating multi-layer switches according to claim 10, wherein: If the reading engine does not read the reallocation requirement of the server, the allocation engine deletes the memory allocation function and retains the allocation parameters of the first memory resource in the server startup phase.

13. The system for dynamically combining memory resources and allocating multi-layer switches according to claim 10, characterized in that: The at least one processing circuit is configured to: executing a scanning engine, wherein the scanning engine scans all peripheral interconnection links of the server; The scanning data of the scanning engine is propagated to the recognition engine. The recognition engine recognizes the scanning data. If the current peripheral interconnection link, the first hardware resource connected to the current peripheral interconnection link, and the switch connected to the current peripheral interconnection link are recognized, the hot plug function is enabled, and the first memory resource allocated to the current peripheral interconnection link during the server startup phase is reserved.

14. The system for dynamically combining memory resources and allocating multi-layer switches according to claim 13, wherein: The recognition engine is used to: If the current peripheral interconnection link, the first hardware resource connected to the current peripheral interconnection link, and the switch connected to the current peripheral interconnection link are identified, the hot plug function is turned off, and the allocation engine reallocates the first memory resource of the server according to the memory allocation function.

15. The system for dynamically combining memory resources and allocating multi-layer switches according to claim 13, wherein: The recognition engine is used to: If it is identified that the current peripheral interconnection link is idle, or the switch connected to the current peripheral interconnection link is idle, allocating the first memory resource of the server is stopped.

16. The system for dynamically combining memory resources of a multi-layer switch according to any one of claims 10 to 15, characterized in that: The at least one processing circuit is configured to: executing a scanning engine, wherein the scanning engine scans a current peripheral interconnection link level; Propagating the scan data of the scan engine to the recognition engine, the recognition engine recognizing the scan data, and if the current peripheral interconnection link level is N, the number of times the first memory resource is reallocated is N+1; The allocation engine performs first memory resource allocation according to the number of reallocations.

17. The system for dynamically combining memory resources and allocating multi-layer switches according to claim 16, wherein: The at least one processing circuit is configured to: executing a reading engine, wherein the reading engine reads a second memory resource of the server; propagating the remaining resource of the second memory resource to the recognition engine, the recognition engine identifying whether the remaining resource is less than a resource threshold; The identification result of the identification engine is propagated to the allocation engine. When the remaining resources are less than the resource threshold, the allocation engine stops allocating the first memory resources of the server and reallocates the first memory resources that have been allocated to the hardware resources that do not support the hot-swap function and the peripheral interconnection links.

18. The system for dynamically combining memory resources and allocating multi-layer switches according to claim 17, wherein: The allocation engine is further configured to: If any one of the multi-level switches does not support the hot-swap function, reallocating the first memory resource of the peripheral interconnection link where the switch that does not support the hot-swap function is located; If all switches of the multi-layer switch support the hot plug function, the allocation parameter of the first memory resource in the server startup phase is retained.

19. A server, characterized in that: include: A system for dynamically combining memory resources and allocating multi-layer switches as claimed in any one of claims 1 to 18.

20. A method for dynamically combining memory resources of a multi-level switch, characterized in that: include: At least one processing circuit connected using at least one peripheral interconnect link, wherein the at least one processing circuit is configured to: executing a reading engine, wherein the reading engine reads type data of a target configuration space when the server is started; Propagating the type data to an identification engine, the identification engine identifying a first hardware resource connected to the current peripheral interconnect link based on the type data, and if the first hardware resource includes a multi-level switch, identifying a second hardware resource connected to the multi-level switch; The identification result of the identification engine is propagated to the allocation engine. The allocation engine determines, based on the first identification result of the first hardware resource, that a multi-level switch is connected to the current peripheral interconnection link. Then, based on the second identification result of the second hardware resource, the allocation engine allocates memory resources to the multi-level switch and the second hardware resource.

21. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, the steps of the method for dynamically combining memory resources of a multi-layer switch according to claim 20 are implemented.

22. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method for dynamically combining memory resources of a multi-layer switch according to claim 20 are implemented.

Images