Chip debugging system and method based on OTP storage medium

Abstract

The invention discloses a chip debugging system and method based on an OTP storage medium. The chip debugging system comprises an FPGA debugging board and a chip end. Wherein to-be-debugged firmware used for debugging a chip end is stored in the FPGA debugging board, and reading operation and / or writing operation on data of the chip end are / is realized by transmitting a communication instruction to the chip end in the process of running the to-be-debugged firmware; and the chip end internally comprises an OTP storage medium, communication instruction analysis firmware is stored in the OTP storage medium, the communication instruction transmitted by the FPGA debugging board is analyzed through operation of the communication instruction analysis firmware, and corresponding read operation and / or write operation are / is executed based on the analyzed communication instruction. Based on the characteristic that the FPGA debugging board can be repeatedly burnt, debugging of different firmware on the same chip end adopting the OTP storage medium is achieved. The OTP storage medium at the chip end only stores the communication instruction analysis firmware, so that the analysis of the communication instruction under different firmware debugging is realized, and the firmware debugging cost of the chip adopting the OTP storage medium is effectively reduced.

Description

Technical Field

[0001] This application relates to the field of chip debugging, and specifically relates to a chip debugging system and method based on an OTP storage medium. Background Art

[0002] Currently, for the chip debugging method using an OTP storage medium, the firmware to be debugged is usually directly burned into the chip for debugging. Due to the one-time programmable characteristic of the OTP storage medium, when the firmware stored in the chip needs to be changed after debugging, a new chip needs to be used for burning, resulting in a large loss of chips and high costs during the firmware debugging stage. Summary of the Invention

[0003] This application provides a chip debugging system and method based on an OTP storage medium. The specific technical solutions are as follows: A chip debugging system based on an OTP storage medium, characterized in that the chip debugging system includes: an FPGA debugging board and a chip end; wherein, the FPGA debugging board internally stores the firmware to be debugged for debugging the chip end, and realizes the read operation and / or write operation of the chip end data by transmitting communication instructions to the chip end during the operation of the firmware to be debugged; the chip end internally includes an OTP storage medium, and the OTP storage medium internally stores communication instruction parsing firmware, and parses the communication instructions transmitted by the FPGA debugging board through the operation of the communication instruction parsing firmware, and executes corresponding read operations and / or write operations based on the parsed communication instructions.

[0004] Further, the FPGA debugging board specifically includes: a debugging firmware memory for storing the firmware to be debugged for debugging the chip end; a debugging board central processing unit for running the firmware to be debugged stored in the debugging firmware memory, and outputting corresponding chip end read instructions and / or chip end write instructions during the operation of the firmware to be debugged; a communication host module for sending communication instructions to the chip end based on the chip end read instructions and / or chip end write instructions output by the debugging board central processing unit during the operation of the firmware to be debugged.

[0005] Further, the FPGA debugging board further includes: a conversion control module for controlling the operation and stop of the debugging board central processing unit for the firmware to be debugged, receiving the chip end read instructions and / or chip end write instructions output by the debugging board central processing unit, and controlling the communication host module to output corresponding communication instructions based on the received chip end read instructions and / or chip end write instructions.

[0006] Further, the chip side specifically includes: a communication slave module, configured to receive communication instructions sent by the communication host module of the FPGA debug board and transmit them to the central processing unit of the chip side, and further configured to send target read information obtained by the central processing unit of the chip side from the peripheral module based on the parsed communication instructions to the communication host module of the FPGA debug board; a central processing unit of the chip side, configured to run communication instruction parsing firmware stored inside the OTP storage medium to parse the communication instructions transmitted by the communication slave module, and perform read operations and / or write operations on the peripheral module based on the parsed communication instructions; a peripheral module, controlled by the central processing unit of the chip side to perform write operations and / or read operations.

[0007] Further, the chip debugging system further includes: inside the FPGA debug board, there are a debug board random access memory and a debug board non-volatile memory; the debug board random access memory is used to store debug intermediate data generated during the operation of the to-be-debugged firmware by the central processing unit of the debug board; the debug board non-volatile memory is used to store the to-be-debugged firmware; inside the chip side, there is a chip side random access memory, used to store parsing intermediate data generated during the operation of the communication instruction parsing firmware by the central processing unit of the chip side.

[0008] Further, the chip side further includes: a chip side interrupt port, connected to the FPGA debug board, configured to transmit the chip side total interrupt signal output by the central processor of the chip side to the FPGA debug board.

[0009] Further, the FPGA debug board further includes: a debug board interrupt port, connected to the chip side interrupt port of the chip side, configured to receive the chip side total interrupt signal transmitted by the chip side and transmit the received chip side total interrupt signal to the central processing unit of the debug board.

[0010] Further, the central processing unit of the debug board is further configured to run the to-be-debugged firmware based on the received chip side total interrupt signal to output corresponding chip side read instructions and / or chip side write instructions.

[0011] Further, the peripheral module is further configured to output a peripheral interrupt signal and transmit it to the central processing unit of the chip side, so that the central processing unit of the chip side generates a chip side total interrupt signal based on the received peripheral interrupt signal.

[0012] The present application also discloses a chip debugging method based on an OTP storage medium. The chip debugging method based on an OTP storage medium is implemented based on the chip debugging system based on an OTP storage medium described in any of the preceding items, and specifically includes the following steps: The central processor of the debug board runs the firmware to be debugged stored in the debug firmware memory, and outputs corresponding chip-side read and write instructions to the conversion control module during the running of the firmware to be debugged; the conversion control module controls the communication host module to convert the chip-side read and write instructions into corresponding communication instructions according to the adopted communication protocol and transmit them to the communication slave module; the communication slave module receives the communication instructions transmitted by the communication host module and transmits the received communication instructions to the chip-side central processing unit; the chip-side central processing unit parses the communication instructions transmitted by the communication slave module through the communication instruction parsing firmware stored in the OTP storage medium, and performs read operations and / or write operations on the peripheral module based on the parsed communication instructions.

[0013] Further, the chip debugging method further includes: when the central processor of the debug board outputs chip-side read and write instructions to the conversion control module, the conversion control module controls the central processor of the debug board to stop running the firmware to be debugged based on the received chip-side read and write instructions, until the chip-side central processing unit completes the read operation and / or write operation on the peripheral module based on the parsed communication instructions, and then outputs a chip-side read and write instruction completion signal to be transmitted to the communication host module through the communication slave module. The communication host module transmits the chip-side read and write instruction completion signal to the conversion control module, and the conversion control module controls the central processor of the debug board to resume running the firmware to be debugged based on the chip-side read and write instruction completion signal.

[0014] Further, the chip debugging method further includes: the peripheral module generates a peripheral interrupt signal based on a new event occurring in the peripheral component and transmits the peripheral interrupt signal to the chip-side central processing unit; the chip-side central processing unit generates a chip-side total interrupt signal based on the received peripheral interrupt signal and transmits the chip-side total interrupt signal to the debug board through the chip-side interrupt port; the debug board receives the chip-side total interrupt signal transmitted by the chip-side based on the debug board interrupt interface and transmits the received chip-side total interrupt signal to the central processor of the debug board; the central processor of the debug board executes the debug board interrupt response process based on the received chip-side total interrupt signal.

[0015] Further, the central processing unit of the debug board executes a debug board interrupt response process based on the received chip - side total interrupt signal, which specifically includes: The central processing unit of the debug board outputs a first chip - side read instruction to the conversion control module based on the chip - side total interrupt signal. The conversion control module controls the communication host module to convert the first chip - side read instruction into a corresponding first communication instruction according to the adopted communication protocol and transmit it to the communication slave module. The communication slave module receives the first communication instruction transmitted by the communication host module and transmits the received first communication instruction to the chip - side central processing unit. The chip - side central processing unit parses the first communication instruction transmitted by the communication slave module by running the communication instruction parsing firmware stored in the OTP storage medium, performs a read operation on the chip - side total interrupt status register of the chip - side central processing unit based on the parsed first communication instruction to determine the peripheral component that issues the peripheral interrupt signal at the chip - side, and transmits the information of the read chip - side total interrupt status register to the debug board via the communication slave module. The debug board determines the peripheral component that issues the peripheral interrupt signal at the chip - side based on the information of the chip - side total interrupt status register received by the communication host module and transmitted to the central processing unit of the debug board, outputs a second chip - side read instruction to the conversion control module, the conversion control module controls the communication host module to convert the second chip - side read instruction into a corresponding second communication instruction according to the adopted communication protocol and transmit it to the communication slave module. The communication slave module receives the second communication instruction transmitted by the communication host module and transmits the received second communication instruction to the chip - side central processing unit. The chip - side central processing unit parses the second communication instruction transmitted by the communication slave module by running the communication instruction parsing firmware stored in the OTP storage medium, performs a read operation on the interrupt status register of the peripheral component that issues the peripheral interrupt signal based on the parsed second communication instruction to determine the reason for the peripheral component to issue the peripheral interrupt signal, and transmits the information of the read peripheral component interrupt status register to the debug board via the communication slave module. The debug board determines the reason for the peripheral component to issue the peripheral interrupt signal based on the information of the read peripheral component interrupt status register received by the communication host module and transmitted to the central processing unit of the debug board.

[0016] Further, the central processing unit of the debug board executing the debug board interrupt response process based on the received chip - side total interrupt signal further includes: When the debugger central processing unit determines the reason for the peripheral component to issue the peripheral interrupt signal, the debugger central processing unit executes a first chip - side write instruction based on the peripheral component that issues the peripheral interrupt signal to clear the peripheral component interrupt status register; when the clearing of the peripheral component interrupt status register is completed, the debugger central processing unit executes a second chip - side write instruction to clear the chip - side total interrupt status register.

[0017] The chip debugging system and method based on an OTP storage medium described in this application store the firmware to be debugged for the chip side in an FPGA debugging board outside the chip side, and realize the debugging of different firmwares for the same chip side using an OTP storage medium based on the repeatedly burnable characteristic of the FPGA debugging board. The OTP storage medium of the chip side is only used to store the communication instruction parsing firmware, and based on the communication parsing firmware, the communication instructions under different firmware debuggings are parsed, improving the stability of the stored content in the OTP storage medium of the chip side during the firmware debugging stage, and effectively reducing the firmware debugging cost of the chip using the OTP storage medium. Brief Description of the Drawings

[0018] Figure 1 It is a schematic diagram of the modules of the chip debugging system based on an OTP storage medium according to an embodiment of this application. Embodiment

[0019] Next, the embodiments of this application will be described in detail in conjunction with the drawings. It should be understood that the specific embodiments described below are only used to explain this application and are not used to limit this application.

[0020] This application provides a chip debugging system based on an OTP storage medium, as Figure 1 shown, including: an FPGA debugging board and a chip side; wherein, the FPGA debugging board internally stores the firmware to be debugged for the chip side, and realizes the read operation and / or write operation of the data on the chip side by transmitting communication instructions to the chip side during the running of the firmware to be debugged; the chip side internally includes an OTP storage medium, and the OTP storage medium internally stores the communication instruction parsing firmware, and parses the communication instructions transmitted by the FPGA debugging board through the running of the communication instruction parsing firmware, and executes the corresponding read operation and / or write operation based on the parsed communication instructions. Among them, the communication instruction parsing firmware refers to the firmware used to parse the communication instructions transmitted by the FPGA debugging board, and the parsing method thereof is based on the communication protocol adopted by the communication instructions.

[0021] Among them, the full name of the FPGA in the FPGA debug board is Field-Programmable Gate Array, that is, a programmable gate array, which is a chip whose internal structure can be changed through programming. In this application, the FPGA debug board is adopted, which has the advantages of being reusable and eliminating the need for repeated manual configuration. Therefore, it is possible to implement firmware debugging for the chip end using the OTP storage medium based on a variety of different firmware to be debugged. In this embodiment, the firmware to be debugged for debugging the chip end is stored in the FPGA debug board outside the chip end, so as to realize the debugging of different firmwares for the same chip end using the OTP storage medium based on the repeatedly burnable characteristics of the FPGA debug board. The OTP storage medium of the chip end is only used to store the communication instruction parsing firmware, so as to realize the parsing of communication instructions under different firmware debugging, improve the stability of the stored content in the OTP storage medium of the chip end during the firmware debugging stage, and effectively reduce the firmware debugging cost of the chip using the OTP storage medium.

[0022] As a preferred embodiment of this application, the FPGA debug board specifically includes: a debug firmware memory, a debug board central processing unit, and a communication host module. Among them, The debug firmware memory is used to store the firmware to be debugged for debugging the chip end; among them, the debug firmware memory uses an erasable memory, so that the FPGA debug board can update and erase the stored firmware to be debugged by repeatedly erasing the debug firmware memory.

[0023] The debug board central processing unit is used to run the firmware to be debugged stored in the debug firmware memory, and output corresponding chip end read instructions and / or chip end write instructions during the running of the firmware to be debugged; among them, the chip end read instruction is generated based on the chip end communication slave address, the target read register address combined with the read flag; the chip end write instruction is generated based on the chip end communication slave address, the target write register address, the target write data combined with the write mark; A communication host module is used to send communication instructions to the chip end based on the chip - end read instruction and / or chip - end write instruction output by the central processing unit of the debug board during the operation of the firmware to be debugged. Among them, the communication host module sending communication instructions to the chip end based on the chip read instruction and / or chip - end write instruction means that the communication host module converts the chip read instruction and / or chip write instruction into corresponding communication instructions according to the communication protocol it adopts, and transmits the converted communication instructions to the chip end. In this embodiment, the FPGA debug board adopted converts the chip read instruction and / or chip write instruction into corresponding communication instructions according to the communication protocol based on the communication host module, so that the central processor of the debug board can convert different chip read instructions and / or chip write instructions output by different firmwares to be debugged into communication instructions using the same communication protocol, effectively standardizing the instruction unity, and enabling the chip end to parse different chip read instructions and / or chip write instructions transmitted by different firmwares to be debugged with only one type of communication instruction.

[0024] As a preferred embodiment of this application, the FPGA debug board further includes: a conversion control module, which is used to control the central processing unit of the debug board to run and stop running the firmware to be debugged, receive the chip - end read instruction and / or chip - end write instruction output by the central processing unit of the debug board, and control the communication host module to output corresponding communication instructions based on the received chip - end read instruction and / or chip - end write instruction. Specifically, the control logic of the conversion control module for controlling the central processing unit of the debug board to stop or resume running the firmware to be debugged is as follows: when the conversion control module receives the chip - end read instruction and / or chip - end write instruction transmitted by the central processing unit of the debug board, it controls the central processing unit of the test board to stop running the firmware to be debugged; when the conversion control module receives the target read information corresponding to the chip read instruction transmitted by the communication host module, the conversion control module transmits the target read information to the central processing unit of the debug board, and the central processor of the debug board transmits a target read handshake signal to the conversion module based on the received target read information, and the conversion module controls the central processing unit of the debug board to resume running the firmware to be debugged based on the target read handshake signal. Among them, the target read information refers to the information read from the chip end based on the chip read instruction; the target read handshake signal is a handshake signal output by the central processing unit of the debug board after confirming the successful execution of the chip read instruction based on the target read information, and is used to indicate the completion of the execution of the chip read instruction. This embodiment realizes the control of converting the chip read instruction and / or chip write instruction into communication instructions based on the communication host module by the conversion module, as well as the control of the central processing unit of the debug board to run the firmware to be debugged, ensuring the smoothness of instruction execution.

[0025] As a preferred embodiment of the present application, the chip side specifically includes: a communication slave module, a chip-side central processing unit, and a peripheral module; wherein, the communication slave module is configured to receive communication instructions sent by the communication host module of the FPGA debug board and transmit them to the chip-side central processing unit, and is further configured to send target read information obtained by the chip-side central processing unit from the peripheral module based on the parsed communication instructions to the communication host module of the FPGA debug board; the chip-side central processing unit is configured to run communication instruction parsing firmware stored inside the OTP storage medium to parse the communication instructions transmitted by the communication slave module, and perform read operations and / or write operations on the peripheral module based on the parsed communication instructions; the peripheral module is controlled by the chip-side central processing unit to perform write operations and / or read operations. Specifically, the communication slave module and the communication host module adopt the same communication protocol, and the communication protocol can be, but is not limited to, full-duplex communication protocols such as IIC communication protocol, SPI communication protocol, UART communication protocol, etc.; the communication slave module and the communication host module achieve bidirectional data transmission through a serial data line and a serial clock line. The peripheral module includes at least one set of peripheral components, and the peripheral components can be, but are not limited to, asynchronous receive and transmit peripheral components, timing peripheral components, and / or pulse width modulation peripheral components, etc. The chip side provided by this embodiment realizes master-slave communication based on the communication slave module and the communication host module of the FPGA debugger, ensuring stable transmission of instruction information during the firmware debugging process. At the same time, based on the operation of the communication instruction parsing firmware by the chip-side central processing unit, different communication instructions can be parsed, so that the chip-side central processing unit can perform read operations and / or write operations on the corresponding peripheral components in the peripheral module based on the obtained chip read instructions and / or chip write instructions after parsing.

[0026] As a preferred embodiment of the present application, the chip debugging system further includes: the FPGA debugging board internally includes a debugging board random access memory and a debugging board non-volatile memory; the debugging board random access memory is used to store the debugging intermediate data generated during the operation of the debugging board central processing unit running the firmware to be debugged; the debugging board non-volatile memory is used to store the firmware to be debugged; the chip end internally includes a chip end random access memory, which is used to store the parsing intermediate data generated during the operation of the chip end central processing unit running the communication instruction parsing firmware. Among them, the debugging board random access memory and the chip end random access memory used in the FPGA debugging board and the chip end both have the characteristic of data loss when power is off. After each power-off, the intermediate data generated during the operation of the firmware to be debugged or the communication instruction parsing firmware stored in the random access memory is lost, and there is no need to perform additional cleaning work on the data stored in the random access memory, ensuring that the intermediate data stored in the random access memory is all generated during the current operation of the firmware to be debugged or the communication instruction parsing firmware. The debugging board non-volatile memory has the characteristic of being erasable and writable repeatedly. Therefore, the firmware to be debugged stored in the FPGA debugging board can be updated by erasing and writing.

[0027] As a preferred embodiment of the present application, the chip end further includes: a chip end interrupt port, connected to the FPGA debugging board, for transmitting the chip end total interrupt signal output by the chip end central processor to the FPGA debugging board. The FPGA debugging board further includes: a debugging board interrupt port, connected to the chip end interrupt port of the chip end, for receiving the chip end total interrupt signal transmitted by the chip end and transmitting the received chip end total interrupt signal to the debugging board central processor.

[0028] Specifically, in this embodiment, the transmission of the chip end total interrupt signal between the chip end and the FPGA debugging board is independent of the transmission channels of the communication host module and the communication slave module. The chip end interrupt port and the debugging board interrupt port are independently set, so that the chip end total interrupt signal generated by the chip end central processing unit can be directly transmitted to the debugging board without passing through the communication slave module. The FPGA debugging board can directly transmit the received chip end total interrupt signal to the debugging board central processing unit without passing through the communication host module and the conversion module, and directly receive and transmit it to the debugging board central processing unit through a dedicated debugging board interrupt port, making the reception of the trigger signal (i.e., the chip end total interrupt signal) of the interrupt response process independent of the transmission path of the chip end read request instruction / chip end write request instruction, so that during the execution of the chip end read request instruction / chip end write request instruction, the debugging board central processor can quickly receive the chip end total interrupt signal generated by the chip end and make a response.

[0029] As a preferred embodiment of the present application, the peripheral component is further configured to output a peripheral interrupt signal and transmit it to the central processor of the chip end, so that the central processor of the chip end generates a total chip end interrupt signal based on the received peripheral interrupt signal.

[0030] As a preferred embodiment of the present application, the central processor of the debug board is further configured to run the firmware to be debugged based on the received total chip end interrupt signal to output corresponding chip end read instructions and / or chip end write instructions. Specifically, when the debug board receives the total chip end interrupt signal transmitted from the chip end, in order to understand the reason for the issuance of the total chip end interrupt signal, the central processor of the debug board executes an interrupt response process, and the interrupt response process includes: executing a chip end read request operation to read the total chip end interrupt status register; determining the peripheral component status register of the chip end that issues the peripheral interrupt signal according to the read total chip end interrupt status register; executing the chip end read request operation again to read the peripheral component status register of the chip end that issues the peripheral interrupt signal; determining the reason for the peripheral component of the chip end to issue the peripheral interrupt signal according to the read peripheral component status register of the chip end that issues the peripheral interrupt signal; and performing a corresponding chip end write request operation and / or performing a corresponding chip end read request operation on the chip end based on the reason for the peripheral component of the chip end to issue the peripheral interrupt signal in combination with the operation of the firmware to be debugged.

[0031] Specifically, the FPGA debug board reads the total chip end interrupt status register by performing a chip end read request operation on the chip end, so as to realize the peripheral component of the FPGA debug board to understand the content of the new event occurring in the chip end. The reading purposes of the two chip end read request operations are different. One is to read the total chip end interrupt status register, and the other is to read the peripheral component status register. The chip debugging system provided by this embodiment can not only actively debug the firmware on the chip end during the firmware debugging process of the chip end, but also respond based on the new events occurring inside the chip end.

[0032] As a preferred embodiment of the present application, a chip debugging method based on an OTP storage medium is provided. The chip debugging method based on the OTP storage medium is implemented based on the chip debugging system based on the OTP storage medium described in any of the above embodiments, and specifically includes the following steps: The central processor of the debug board runs the firmware to be debugged stored in the debug firmware memory, and outputs corresponding chip end read and write instructions to the conversion control module during the operation of the firmware to be debugged; wherein, the chip end read and write instructions refer to instructions for instructing to perform a read operation or a write operation on the chip end; The conversion control module controls the communication host module to convert the chip end read and write instructions into corresponding communication instructions according to the adopted communication protocol and transmit them to the communication slave module; The communication slave module receives the communication instructions transmitted by the communication master module and transmits the received communication instructions to the central processing unit of the chip side; The central processing unit of the chip side parses the communication instructions transmitted by the communication slave module through the communication instruction parsing firmware stored in the OTP storage medium, and performs read operations and / or write operations on the peripheral module based on the parsed communication instructions. The chip debugging method based on the OTP storage medium provided in this embodiment is realized by externalizing the running process of the firmware to be debugged in the debug board. The chip side using the OTP storage medium only parses the communication instructions transmitted by the debug board based on the communication instruction parsing firmware stored in the OTP storage medium, and performs read operations or write operations based on the parsing results, so that when the firmware to be debugged changes, the chip side does not need to erase and write the stored content of the OTP storage medium. The chip side using the OTP storage medium can be applied to the debugging of different firmware to be debugged, ensuring the number of available times of the chip side using the OTP storage medium during the firmware debugging process.

[0033] As a preferred embodiment of the present application, the chip debugging method based on the OTP storage medium further includes: when the central processor of the debug board outputs the chip side read / write instruction to the conversion control module, the conversion control module controls the central processor of the debug board to stop running the firmware to be debugged based on the received chip side read / write instruction, until after the central processing unit of the chip side performs the read operation and / or write operation on the peripheral module based on the parsed communication instructions, the conversion control module controls the central processor of the debug board to resume running the firmware to be debugged based on the completion signal of the chip side read / write instruction.

[0034] Among them, the chip - side read - write instruction completion signal is used to indicate the execution completion status of the chip - side read - write instruction at the chip side; specifically, when the chip - side read - write instruction is used to indicate a read operation on the chip side, the chip - side read - write instruction completion signal is the target read handshake signal transmitted from the central processor of the debug board to the conversion control module. When the chip - side read - write instruction is used to indicate a write operation on the chip side, the chip - side read - write instruction completion signal is the target write completion signal transmitted from the communication host module to the conversion control module. The communication host module converts all chip - side read - write instructions into communication instructions and transmits them to the communication slave module. After the communication instruction transmission is completed, the communication host module transmits the target write completion signal to the conversion control module. This embodiment realizes the control of the central processor of the debug board to run the firmware to be debugged based on the conversion control module, preventing the central processor of the debug board from still running the firmware to be debugged when the debug board performs a read operation on the chip side, which may lead to a situation where multiple chip - side read - write instructions are continuously output waiting to be debugged on the chip side. Multiple chip - side read - write instructions are likely to affect the firmware debugging execution logic of the FPGA debug board for the chip side. Therefore, in this embodiment, it is specified that when the conversion control module receives a chip - side read - write instruction once, it controls the central processor of the debug board to pause running the firmware to be debugged, and based on the chip - side read - write instruction completion signal, controls the central processor of the debug board to resume running the firmware to be debugged.

[0035] As a preferred embodiment of the present application, the chip debugging method based on the OTP storage medium further includes: The peripheral module generates a peripheral interrupt signal based on a new event occurring in the peripheral component and transmits the peripheral interrupt signal to the central processing unit of the chip side; among them, the peripheral interrupt signal is used to indicate that a new event has occurred in the peripheral component. The central processing unit of the chip side generates a chip - side total interrupt signal based on the received peripheral interrupt signal and transmits the chip - side total interrupt signal to the debug board through the chip - side interrupt port; the debug board receives the chip - side total interrupt signal transmitted by the chip side based on the debug - board interrupt interface and transmits the received chip - side total interrupt signal to the central processor of the debug board; among them, the chip - side total interrupt signal is used to indicate that a new event has occurred inside the chip side. The central processor of the debug board executes the debug - board interrupt response process based on the received chip - side total interrupt signal. This embodiment controls the central processor of the debug board to execute the debug - board interrupt response process according to the chip - side total interrupt signal, so that the debug board can respond based on the new events occurring on the chip side on the basis of the firmware debugging function.

[0036] As a preferred embodiment of the present application, the central processor of the debug board executes the debug - board interrupt response process based on the received chip - side total interrupt signal, which specifically includes: The central processor of the debug board outputs a first chip - side read instruction to the conversion control module based on the chip - side total interrupt signal. The conversion control module controls the communication host module to convert the first chip - side read instruction into a corresponding first communication instruction according to the adopted communication protocol and transmit it to the communication slave module. The communication slave module receives the first communication instruction transmitted by the communication host module and transmits the received first communication instruction to the chip - side central processing unit. The chip - side central processing unit parses the first communication instruction transmitted by the communication slave module by running the communication instruction parsing firmware stored in the OTP storage medium, and performs a read operation on the chip - side total interrupt status register of the chip - side central processor to determine the peripheral component that issues the peripheral interrupt signal at the chip - side, and transmits the information of the read chip - side total interrupt status register to the debug board via the communication slave module; wherein, since the generation of the chip - side total interrupt signal is based on the peripheral interrupt signal transmitted from the peripheral module to the chip - side central processing unit, therefore, the chip - side total interrupt status register should record the information related to the peripheral interrupt signal that causes the chip - side total interrupt signal to be generated. Thus, in this step, the FPGA debugger can determine the peripheral component that issues the peripheral interrupt signal at the chip - side by performing a read operation on the chip - side total interrupt status register.

[0037] The debug board receives the chip - side total interrupt status register information based on the communication host module and transmits it to the central processor of the debug board. The central processor of the debug board determines the peripheral component that issues the peripheral interrupt signal at the chip - side based on the chip - side total interrupt status register information, outputs a second chip - side read instruction to the conversion control module. The conversion control module controls the communication host module to convert the second chip - side read instruction into a corresponding second communication instruction according to the adopted communication protocol and transmit it to the communication slave module. The communication slave module receives the second communication instruction transmitted by the communication host module and transmits the received second communication instruction to the chip - side central processing unit. The chip - side central processing unit parses the second communication instruction transmitted by the communication slave module by running the communication instruction parsing firmware stored in the OTP storage medium, and performs a read operation on the interrupt status register of the peripheral component that issues the peripheral interrupt signal to determine the reason for the peripheral component to issue the peripheral interrupt signal, and transmits the information of the read peripheral component interrupt status register to the debug board via the communication slave module; The debug board receives the information of the read peripheral component interrupt status register based on the communication host module and transmits it to the central processor of the debug board to determine the reason for the peripheral component to issue the peripheral interrupt signal.

[0038] This embodiment performs read operations on the chip side by the debug board twice. The first read operation is implemented through the first chip-side read instruction to seek the reading of the information in the chip-side total interrupt status register. The second read operation is implemented through the second chip-side read instruction. The target reading object of the second chip-side read instruction is the peripheral component that issues the peripheral interrupt signal determined in the first read operation, to seek the reading of the interrupt status register information of the peripheral component that issues the peripheral interrupt signal. Thus, the debug board can understand the reason for the issuance of the peripheral interrupt signal and realize the response of the debugger to the feedback from the chip side during the chip debugging process.

[0039] As a preferred embodiment of the present application, the central processor of the debug board executes the debug board interrupt response process based on the received chip-side total interrupt signal, and further includes: when the central processor of the debugger determines the reason for the peripheral component to issue the peripheral interrupt signal, the central processor of the debugger executes the first chip-side write instruction based on the peripheral component that issues the peripheral interrupt signal to clear the interrupt status register of the peripheral component; when the clearing of the interrupt status register of the peripheral component is completed, the central processor of the debugger executes the second chip-side write instruction to clear the chip-side total interrupt status register. Among them, in this embodiment, the information related to the peripheral interrupt signal stored in the interrupt status register of the peripheral component and the information related to the chip-side total interrupt signal stored in the chip-side total interrupt status register are overwritten by writing, so as to achieve the purpose of clearing the interrupt signal.

[0040] Specifically, since the chip-side total interrupt signal issued by the chip side is generated based on the peripheral interrupt signal issued by the peripheral component inside the chip side, in order to avoid the situation that the chip-side total interrupt status register is cleared first, and then the peripheral component issues the peripheral interrupt signal to the chip-side central processor again based on the interrupt status register of the peripheral component, resulting in the chip-side central processor generating the chip total interrupt signal again. This embodiment adopts the method of first clearing the interrupt status register of the peripheral component and then clearing the chip-side total interrupt status register. After the interrupt status register of the peripheral component is cleared first, there will be no problem that the interrupt status register of the peripheral component issues the same peripheral interrupt signal again to trigger the regeneration of the chip total interrupt signal, optimizing the interrupt signal clearing logic of the interrupt response process.

[0041] It should be noted that any process or method description in the flowchart or described in other ways herein can be understood as: representing a module, segment or part of executable instructions including one or more steps for implementing a specific logical function or process, and the scope of the preferred embodiment of the present application includes additional implementations, where the functions can be executed in a way that is not in the order shown or discussed, including in a substantially simultaneous manner or in the reverse order according to the involved functions, which should be understood by those skilled in the technical field to which the embodiments of the present application belong.

[0042] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than limiting them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A chip debugging system based on an OTP storage medium, characterized in that, The chip debugging system includes: an FPGA debugging board and a chip side; wherein, The FPGA debugging board stores the firmware to be debugged for debugging the chip side internally, and realizes the read operation and / or write operation of the chip side data by transmitting communication instructions to the chip side during the running of the firmware to be debugged. The chip side includes an OTP storage medium internally, and the OTP storage medium stores communication instruction parsing firmware internally. The communication instructions transmitted by the FPGA debugging board are parsed through the running of the communication instruction parsing firmware, and the corresponding read operation and / or write operation is executed based on the parsed communication instructions.

2. The chip debugging system based on the OTP storage medium according to claim 1, wherein The FPGA debugging board specifically includes: A debugging firmware memory for storing the firmware to be debugged for debugging the chip side; A debugging board central processing unit for running the firmware to be debugged stored in the debugging firmware memory, and outputting corresponding chip side read instructions and / or chip side write instructions during the running of the firmware to be debugged; A communication host module for sending communication instructions to the chip side based on the chip side read instructions and / or chip side write instructions output by the debugging board central processing unit during the running of the firmware to be debugged.

3. The chip debugging system based on the OTP storage medium according to claim 2, characterized in that, The FPGA debugging board further includes: A conversion control module for controlling the running and stopping of the firmware to be debugged by the debugging board central processing unit, receiving the chip side read instructions and / or chip side write instructions output by the debugging board central processing unit, and controlling the communication host module to output corresponding communication instructions based on the received chip side read instructions and / or chip side write instructions.

4. The chip debugging system based on the OTP storage medium according to claim 3, characterized in that, The chip side specifically includes: A communication slave module for receiving the communication instructions sent by the communication host module of the FPGA debugging board and transmitting them to the chip side central processing unit, and also for sending the target read information obtained by the chip side central processing unit from the peripheral module through the read operation based on the parsed communication instructions to the communication host module of the FPGA debugging board; A chip side central processing unit for running the communication instruction parsing firmware stored internally in the OTP storage medium to parse the communication instructions transmitted by the communication slave module, and performing read operation and / or write operation on the peripheral module based on the parsed communication instructions; A peripheral module controlled by the chip side central processing unit to perform write operation and / or read operation.

5. The chip debugging system based on the OTP storage medium according to claim 4, wherein The chip debugging system further includes: The FPGA debugging board includes a debugging board random access memory and a debugging board non-volatile memory internally; the debugging board random access memory is used for storing the debugging intermediate data generated during the running of the firmware to be debugged by the debugging board central processing unit; the debugging board non-volatile memory is used for storing the firmware to be debugged; The chip side includes a chip side random access memory internally, which is used for storing the parsing intermediate data generated during the running of the communication instruction parsing firmware by the chip side central processing unit.

6. The chip debugging system based on the OTP storage medium according to claim 4, characterized in that, The chip side further includes: a chip side interrupt port, connected to the FPGA debugging board, for transmitting the chip side total interrupt signal output by the chip side central processor to the FPGA debugging board.

7. The chip debugging system based on the OTP storage medium according to claim 6, characterized in that, The FPGA debug board further includes: a debug board interrupt port, connected to the chip - side interrupt port of the chip, for receiving the chip - side total interrupt signal transmitted from the chip - side, and transmitting the received chip - side total interrupt signal to the central processor of the debug board.

8. The chip debugging system based on the OTP storage medium according to claim 7, wherein, The central processor of the debug board is further configured to run the firmware to be debugged based on the received chip - side total interrupt signal to output corresponding chip - side read instructions and / or chip - side write instructions.

9. The chip debugging system based on the OTP storage medium according to claim 8, characterized in that, The peripheral module is further configured to output a peripheral interrupt signal and transmit it to the central processor of the chip - side, so that the central processor of the chip - side generates a chip - side total interrupt signal based on the received peripheral interrupt signal.

10. A chip debugging method based on an OTP storage medium, characterized in that, The chip debugging method based on the OTP storage medium is implemented based on the chip debugging system based on the OTP storage medium according to any one of claims 1 to 9, and specifically includes the following steps: The central processor of the debug board runs the firmware to be debugged stored in the debug firmware memory, and outputs corresponding chip - side read and write instructions to the conversion control module during the running of the firmware to be debugged; The conversion control module controls the communication host module to convert the chip - side read and write instructions into corresponding communication instructions according to the adopted communication protocol and transmit them to the communication slave module; The communication slave module receives the communication instructions transmitted by the communication host module, and transmits the received communication instructions to the central processing unit of the chip - side; The central processing unit of the chip - side parses the communication instructions transmitted by the communication slave module through running the communication instruction parsing firmware stored in the OTP storage medium, and performs read operations and / or write operations on the peripheral module based on the parsed communication instructions.

11. The chip debugging method based on an OTP storage medium according to claim 10, characterized in that The chip debugging method further includes: when the central processor of the debug board outputs chip - side read and write instructions to the conversion control module, the conversion control module controls the central processor of the debug board to stop running the firmware to be debugged based on the received chip - side read and write instructions, until after the central processing unit of the chip - side has performed read operations and / or write operations on the peripheral module based on the parsed communication instructions, the conversion control module controls the central processor of the debug board to resume running the firmware to be debugged based on the chip - side read and write instruction completion signal.

12. The chip debugging method based on an OTP storage medium according to claim 11, wherein, The chip debugging method further includes: The peripheral module generates a peripheral interrupt signal based on a new event occurring in the peripheral component, and transmits the peripheral interrupt signal to the central processing unit of the chip - side; The central processing unit of the chip - side generates a chip - side total interrupt signal based on the received peripheral interrupt signal, and transmits the chip - side total interrupt signal to the debug board through the chip - side interrupt port; The debug board receives the chip - side total interrupt signal transmitted from the chip - side based on the debug board interrupt interface, and transmits the received chip - side total interrupt signal to the central processor of the debug board; The central processor of the debug board executes the debug board interrupt response process based on the received chip - side total interrupt signal.

13. The chip debugging method based on the OTP storage medium according to claim 12, wherein, The central processor of the debug board executes the debug board interrupt response process based on the received chip - side total interrupt signal, specifically including: The central processor of the debug board outputs a first chip - side read instruction to the conversion control module based on the chip - side total interrupt signal; The conversion control module controls the communication host module to convert the first chip - side read instruction into a corresponding first communication instruction according to the adopted communication protocol and transmit it to the communication slave module; The communication slave module receives the first communication instruction transmitted by the communication master module and transmits the received first communication instruction to the central processing unit at the chip end. The central processing unit at the chip end parses the first communication instruction transmitted by the communication slave module by running the communication instruction parsing firmware stored in the OTP storage medium, and performs a read operation on the chip end total interrupt status register of the central processor at the chip end based on the parsed first communication instruction to determine the peripheral component that issues the peripheral interrupt signal at the chip end, and transmits the information of the read chip end total interrupt status register to the debug board via the communication slave module; The debug board receives the information of the chip end total interrupt status register based on the communication master module and transmits it to the central processor of the debug board; The central processor of the debug board determines the peripheral component that issues the peripheral interrupt signal at the chip end based on the information of the chip end total interrupt status register, and outputs the second chip end read instruction to the conversion control module; The conversion control module controls the communication master module to convert the second chip end read instruction into the corresponding second communication instruction according to the adopted communication protocol and transmit it to the communication slave module. The communication slave module receives the second communication instruction transmitted by the communication master module and transmits the received second communication instruction to the central processing unit at the chip end. The central processing unit at the chip end parses the second communication instruction transmitted by the communication slave module by running the communication instruction parsing firmware stored in the OTP storage medium, and performs a read operation on the interrupt status register of the peripheral component that issues the peripheral interrupt signal based on the parsed second communication instruction to determine the reason for the peripheral component to issue the peripheral interrupt signal, and transmits the information of the read peripheral component interrupt status register to the debug board via the communication slave module; The debug board receives the information of the read peripheral component interrupt status register based on the communication master module and transmits the information of the peripheral component interrupt status register to the central processor of the debug board to determine the reason for the peripheral component to issue the peripheral interrupt signal.

14. The chip debugging method based on the OTP storage medium according to claim 13, wherein, The central processor of the debug board executes the debug board interrupt response process based on the received chip end total interrupt signal, and further includes: When the central processor of the debugger determines the reason for the peripheral component to issue the peripheral interrupt signal, the central processor of the debugger executes the first chip end write instruction based on the peripheral component that issues the peripheral interrupt signal to clear the interrupt status register of the peripheral component; When the clearing of the interrupt status register of the peripheral component is completed, the central processor of the debugger executes the second chip end write instruction to clear the chip end total interrupt status register.

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