Cache division method, system and device and storage medium

Abstract

The invention discloses a cache division method, system and device and a storage medium. The method comprises the following steps: analyzing a device tree to obtain hardware resource information; creating a plurality of address space domains based on the hardware resource information, and configuring a hardware register; dynamically dividing the cache size of each address space domain based on a received re-division instruction according to the hardware register; the redivision instruction is issued by the address space domain. According to the method, dynamic division of the cache resources is realized through the re-division instruction of the address space domain, and the cache division efficiency and flexibility can be improved. The method can be widely applied to the technical field of computers.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular, to a cache partitioning method, system, device, and storage medium. Background Art

[0002] L3 Cache (Level 3 Cache) is an important part of the CPU cache hierarchy in modern computers. Its main function is to improve system performance by accelerating the speed at which the processor accesses data and reducing memory access latency. In multi-core processors, the L3 Cache is usually a shared cache used to coordinate data access between cores and reduce conflicts caused by accessing the same data between cores. Here, there will be a problem: multiple cores may simultaneously compete for cache resources, resulting in the eviction of data from some cores from the cache, causing misses. In industrial control or vehicle-mounted scenarios where high requirements are placed on system performance and real-time performance, the impact will be extremely large once the data of some critical tasks misses.

[0003] The cache partitioning techniques in the related art are all static. Once partitioned, they cannot be dynamically modified, resulting in poor flexibility. Summary of the Invention

[0004] The purpose of the present invention is to solve at least to some extent one of the technical problems existing in the prior art.

[0005] To this end, the purpose of the present invention is to provide an efficient cache partitioning method, system, device, and storage medium.

[0006] In order to achieve the above technical objectives, on the one hand, an embodiment of the present invention provides a cache partitioning method, including the following steps: parsing a device tree to obtain hardware resource information; creating a plurality of address space domains based on the hardware resource information and configuring hardware registers; dynamically partitioning the cache size of each address space domain based on the received re-partitioning instruction according to the hardware register; the re-partitioning instruction is issued by the address space domain. The present application realizes the dynamic partitioning of cache resources through the re-partitioning instruction of the address space domain, which is beneficial to improving the efficiency and flexibility of cache partitioning.

[0007] In some embodiments, for the cache partitioning method of the embodiment of the present invention, the dynamically partitioning the cache size of each address space domain based on the received re-partitioning instruction according to the hardware register includes:

[0008] If there is excess cache in the cache pool and the excess cache is not reserved, dynamically partition the cache size of each address space domain according to the load of each current address space domain.

[0009] In some embodiments, in one embodiment of the present invention, dynamically partitioning the cache size of each of the address space domains based on the received re-partitioning instruction according to the hardware register includes:

[0010] If the first address space domain dies, the first address space domain issues a re-partitioning instruction for recycling;

[0011] Or, if the first address space domain needs to be expanded, the first address space domain issues a re-partitioning instruction for expansion;

[0012] Or, if the first address space domain needs to be shrunk, the first address space domain issues a re-partitioning instruction for shrinking.

[0013] In some embodiments, in one embodiment of the present invention, the method further includes:

[0014] If a re-partitioning instruction representing recycling is received, recycle the cache of the first address space domain to the cache pool;

[0015] Or, if a re-partitioning instruction representing expansion is received, allocate cache from the cache pool to the first address space domain;

[0016] Or, if a re-partitioning instruction representing shrinking is received, recycle a part of the cache of the first address space domain to the cache pool.

[0017] In some embodiments, in one embodiment of the present invention, creating a number of address space domains based on the hardware resource information and configuring the hardware register includes:

[0018] Based on the hardware resource information, perform static resource partitioning to determine the cache resource attributes of the current address space domain; the cache resource attributes include the size of the cache resource and whether the cache resource is shared.

[0019] In some embodiments, in one embodiment of the present invention, dynamically partitioning the cache size of each of the address space domains based on the received re-partitioning instruction according to the hardware register includes:

[0020] The virtual memory manager runs at the secondary privilege level and interacts with the address space domain through the re-partitioning instruction;

[0021] According to the re-partitioning instruction, request the cache partitioning module to perform cache recycling or cache allocation.

[0022] In some embodiments, in one embodiment of the present invention, the method further includes:

[0023] uboot starts, and the virtual memory manager executes system control rights.

[0024] On the other hand, an embodiment of the present invention provides a cache partitioning system, including:

[0025] A first module, configured to parse a device tree to obtain hardware resource information;

[0026] A second module, configured to create a plurality of address space domains based on the hardware resource information and configure hardware registers;

[0027] A third module, configured to dynamically partition the cache size of each of the address space domains based on the received re-partitioning instruction according to the hardware registers; the re-partitioning instruction is issued by the address space domain.

[0028] On the other hand, an embodiment of the present invention provides a cache partitioning device, including:

[0029] At least one processor;

[0030] At least one memory, configured to store at least one program;

[0031] When the at least one program is executed by the at least one processor, the at least one processor implements the above-mentioned cache partitioning method.

[0032] On the other hand, an embodiment of the present invention provides a storage medium, in which a processor-executable program is stored, and the processor-executable program is used to implement the above-mentioned cache partitioning method when executed by a processor.

[0033] The embodiments of the present application at least include the following beneficial effects: The method provided by the embodiments of the present invention includes: parsing a device tree to obtain hardware resource information; creating a plurality of address space domains based on the hardware resource information and configuring hardware registers; dynamically partitioning the cache size of each of the address space domains based on the received re-partitioning instruction according to the hardware registers; the re-partitioning instruction is issued by the address space domain. Through the re-partitioning instruction of the address space domain, the present application realizes the dynamic partitioning of cache resources, which is beneficial to improving the efficiency and flexibility of cache partitioning. Description of the Drawings

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following introduces the accompanying drawings related to the technical solutions in the embodiments of the present invention or the prior art. It should be understood that the accompanying drawings below only conveniently and clearly illustrate some embodiments of the technical solutions in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative efforts.

[0035] Figure 1Flow diagram of an embodiment of the cache partitioning method provided by the present invention;

[0036] Figure 2 Flow diagram of another embodiment of the cache partitioning method provided by the present invention;

[0037] Figure 3 Flow diagram of an embodiment of the cache allocation process provided by the present invention;

[0038] Figure 4 Flow diagram of an embodiment of the cache recycling process provided by the present invention;

[0039] Figure 5 Structural diagram of an embodiment of the cache partitioning system provided by the present invention;

[0040] Figure 6 Structural diagram of an embodiment of the cache partitioning device provided by the present invention. Detailed implementation manners

[0041] The embodiments of the present invention are described in detail below. The examples of the embodiments are shown in the accompanying drawings, where the same or similar reference numerals represent the same or similar elements or elements with the same or similar functions from beginning to end. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention and should not be construed as a limitation to the present invention. For the step numbers in the following embodiments, they are only set for the convenience of description and illustration, and no limitation is imposed on the order between the steps. The execution order of each step in the embodiments can be adjusted adaptively according to the understanding of those skilled in the art.

[0042] L3 Cache (Level 3 Cache) is an important part of the CPU cache hierarchy in modern computers. Its main function is to improve system performance by accelerating the speed at which the processor accesses data and reducing memory access latency. In a multi-core processor, the L3 Cache is usually a shared cache, which is used to coordinate data access between cores and reduce conflicts caused by accessing the same data between cores. Here, there will be a problem: multiple cores may simultaneously compete for cache resources, resulting in the eviction of data of some cores from the cache, leading to misses. In industrial control or vehicle-mounted scenarios where high requirements are placed on system performance and real-time performance, once the data of some key tasks misses, the impact will be very significant.

[0043] Existing cache partitioning technologies are all static. Once partitioned, they cannot be dynamically modified, resulting in poor flexibility. In addition, it is not very user-friendly in terms of software, and relatively high requirements are placed on users, who need to be familiar with the chip spec.

[0044] In view of the above situation, the present invention proposes a mechanism for dynamic partitioning management of L3 Cache, which realizes flexible partitioning of the L3 Cache size (exclusive or shared) for each core based on the device tree, and can dynamically adjust according to the core load during the operation of the system, improving the overall performance of the system and having positive reference value for engineering applications.

[0045] The following will describe in detail the cache partitioning method and system according to the embodiments of the present invention with reference to the accompanying drawings. First, the cache partitioning method according to the embodiments of the present invention will be described with reference to the accompanying drawings.

[0046] Refer to Figure 1 , in the embodiments of the present invention, a cache partitioning method is provided. The cache partitioning method in the embodiments of the present invention can be applied to terminals, servers, or software running on terminals or servers. The terminal can be a tablet computer, a laptop computer, a desktop computer, etc., but is not limited thereto. The server can be an independent physical server, a server cluster or a distributed system composed of multiple physical servers, or a cloud server providing basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, CDN, and big data and artificial intelligence platforms. The cache partitioning method in the embodiments of the present invention mainly includes the following steps:

[0047] S100: Parse the device tree to obtain hardware resource information;

[0048] S200: Based on the hardware resource information, create several address space domains and configure the hardware registers;

[0049] S300: Based on the hardware registers, dynamically partition the cache size of each address space domain according to the received re-partitioning instruction; the re-partitioning instruction is issued by the address space domain.

[0050] In some possible implementation manners, the hardware resource information in the present application includes information such as the number of CPUs and the number of caches. The hardware registers include configuration information, such as the cache size allocated to the address space domain and whether the cache is shared. It can be understood that in the present application, the virtual memory manager parses the device tree to obtain the hardware resource information; the virtual memory manager creates several address space domains based on the hardware resource information and configures the hardware registers; the virtual memory manager dynamically partitions the cache size of each address space domain according to the hardware registers based on the received re-partitioning instruction. The present invention proposes a general and flexible cache partitioning architecture based on the embedded linux startup process, thus meeting the requirements of industrial / vehicle-mounted and other occasions with high requirements for system performance and real-time performance, and improving the system performance and development efficiency.

[0051] Optionally, in an embodiment of the present invention, according to the hardware register, based on the received re-partitioning instruction, dynamically partition the cache size of each address space domain, including:

[0052] If there is excess cache in the cache pool and the excess cache is not reserved, dynamically partition the cache size of each address space domain according to the current load of each address space domain.

[0053] In some possible implementation manners, the present application dynamically partitions the cache size of each address space domain based on the cache size in the current cache pool and the re-partitioning instruction of the address space domain.

[0054] Optionally, in an embodiment of the present invention, according to the hardware register, based on the received re-partitioning instruction, dynamically partition the cache size of each address space domain, including:

[0055] If the first address space domain dies, the first address space domain issues a re-partitioning instruction for recycling;

[0056] Or, if the first address space domain needs to be expanded, the first address space domain issues a re-partitioning instruction for expansion;

[0057] Or, if the first address space domain needs to be shrunk, the first address space domain issues a re-partitioning instruction for shrinking.

[0058] In some possible implementation manners, if the first address space domain dies, the first address space domain issues a re-partitioning instruction for recycling, and the virtual memory manager receives the re-partitioning instruction representing recycling and requests the cache partitioning module to recycle the cache. It can be understood that the re-partitioning instruction in the present application can represent recycling the cache, allocating cache for expansion, and recycling cache for shrinking.

[0059] Optionally, in an embodiment of the present invention, the method further includes:

[0060] If a re-partitioning instruction representing recycling is received, recycle the cache of the first address space domain to the cache pool;

[0061] Or, if a re-partitioning instruction representing expansion is received, allocate cache from the cache pool to the first address space domain;

[0062] Or, if a re-partitioning instruction representing shrinking is received, recycle a part of the cache of the first address space domain to the cache pool.

[0063] Optionally, in an embodiment of the present invention, based on the hardware resource information, create several address space domains and configure the hardware register, including:

[0064] Based on the hardware resource information, perform static resource partitioning to determine the cache resource attributes of the current address space domain; the cache resource attributes include the size of the cache resource and whether the cache resource is shared.

[0065] In some possible implementation manners, during the first cache partitioning, set the cache resources of each address space domain through static resource partitioning.

[0066] Optionally, in an embodiment of the present invention, based on the hardware register, dynamically partition the cache size of each address space domain according to the received re-partitioning instruction, including:

[0067] The virtual memory manager runs at the second privilege level and interacts with the address space domain through the re-partitioning instruction;

[0068] According to the re-partitioning instruction, request the cache partitioning module to perform cache recycling or cache allocation.

[0069] It can be understood that the privilege level: in some system architectures, such as the ARM architecture, EL2 refers to Exception Level 2, which is a privilege execution level. It is usually used for software such as the hypervisor, responsible for managing virtual machines and resource allocation in the virtualization environment, between the highest privilege level EL3 (usually used for security monitoring, etc.) and EL1 (used for the operating system kernel, etc.).

[0070] Optionally, in an embodiment of the present invention, the method further includes:

[0071] uboot starts, and the virtual memory manager takes over the system control right.

[0072] The following takes a specific embodiment to introduce the cache partitioning method provided by the present application in detail:

[0073] Refer to Figure 2 As shown, the main steps of cache partitioning include:

[0074] (1) The VMM (i.e., the virtual memory manager) parses the device tree to obtain the hardware resource information (number of CPUs, physical core numbers of pCPUs, cache size, whether the cache is shared, etc.) of each domain (i.e., address space domain);

[0075] (2) The VMM creates and boots each domain according to the relevant resource information, and configures the relevant hardware registers according to the information of the cache size and whether the cache is shared;

[0076] (3) The VMM continuously runs at EL2 and dynamically partitions the cache size of each dom, specifically including:

[0077] First, if a dom disappears, the cache partition module of the vmm is responsible for recycling the cache and managing it in the cache pool;

[0078] Second, as long as there is excess cache in the cache pool and it is not reserved, the redistribution mechanism will be activated, and the vmm will dynamically partition according to the load conditions of the remaining doms; the hypversior resides in memory all the time, and it is inevitable to encounter the scenario of dynamically starting a new system during operation. Here, "reserved" means leaving the idle part for the domain to be started.

[0079] Third, the running dom can interact with the vmm using the hvc instruction to request the cache partition module to recycle or allocate a specified cache size.

[0080] Refer to Figure 3 As shown, after the uboot starts, the system control right is handed over to the VMM. The VMM parses the device tree, obtains relevant hardware resources, and then creates each domain according to the configuration of the dom node.

[0081] When creating a domain, a static resource partition will be made according to the cache attribute of the dom node and the cache_partition node, and the cache resources belonging to the current domain will be partitioned and the limit conditions (size, whether to share) will be set. The specific process can refer to Figure 3 , Figure 3 In the embodiment given, for a 4-core soc with an L3 cache size of 512KB, 3 domains are started. Dom1 is allocated two cores and shares 128K of the L3 cache. Dom2 and Dom3 are each allocated 1 core and exclusively enjoy 128K and 256K of the L3 cache respectively.

[0082] After the system runs, the VMM continuously runs in EL2. The running dom can interact with the vmm using the hvc instruction to request the cache partition module to recycle or allocate a specified cache size.

[0083] If a dom disappears (such as Figure 4 dom2), the cache partition module of the vmm is responsible for recycling the cache and managing it in the cache pool. As long as there is excess cache in the cache pool and it is not reserved, the redistribution mechanism will be activated, and the scheduler module of the vmm will dynamically partition the idle cache into specific doms according to the load conditions of the remaining doms.

[0084] The present invention designs a mechanism for dynamic partitioning management of the L3 cache, which realizes flexible partitioning of the L3 cache size (exclusive or shared) for each core based on the device tree, and can dynamically adjust according to the core load situation during the system operation, improving the overall performance of the system and having positive reference value for engineering applications. For related IC solutions of the ARM architecture including the DSU module, the cache partitioning method provided by this application can be used for dynamic allocation of the cache.

[0085] In summary, the method provided by the embodiment of this application includes: parsing the device tree to obtain hardware resource information; creating several address space domains based on the hardware resource information and configuring hardware registers; dynamically partitioning the cache size of each address space domain based on the received re-partitioning instruction according to the hardware registers; the re-partitioning instruction is issued by the address space domain. This application realizes the dynamic partitioning of cache resources through the re-partitioning instruction of the address space domain, which is beneficial to improving the efficiency and flexibility of cache partitioning.

[0086] Secondly, refer to the attached Figure 5 Describe a cache partitioning system according to an embodiment of the present invention.

[0087] Figure 5 It is a schematic structural diagram of the cache partitioning system according to an embodiment of the present invention. The system specifically includes:

[0088] The first module 510 is used to parse the device tree to obtain hardware resource information;

[0089] The second module 520 is used to create several address space domains based on the hardware resource information and configure hardware registers;

[0090] The third module 530 is used to dynamically partition the cache size of each address space domain based on the received re-partitioning instruction according to the hardware registers; the re-partitioning instruction is issued by the address space domain.

[0091] Optionally, in an embodiment of the present invention, the system further includes a fourth module for: when uboot starts, the virtual memory manager executes the system control right.

[0092] It can be seen that the content in the above method embodiments is applicable to the system embodiments of this system. The functions specifically implemented by the system embodiments of this system are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those of the above method embodiments.

[0093] Refer to Figure 6 , the embodiment of the present invention provides a cache partitioning device, including:

[0094] At least one processor 610;

[0095] At least one memory 620 for storing at least one program;

[0096] A cache partitioning method implemented by at least one processor 610 when the at least one program is executed by the at least one processor 610.

[0097] Similarly, the content in the above method embodiments is applicable to the embodiments of this device. The functions specifically implemented by the embodiments of this device are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those of the above method embodiments.

[0098] The embodiments of the present invention further provide a computer-readable storage medium, which stores a program executable by a processor. The program executable by the processor is used to execute the above cache partitioning method when executed by the processor.

[0099] Similarly, the content in the above method embodiments is applicable to the embodiments of this storage medium. The functions specifically implemented by the embodiments of this storage medium are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those of the above method embodiments.

[0100] In some alternative embodiments, the functions / operations mentioned in the block diagram may not occur in the order mentioned in the operation diagram. For example, depending on the functions / operations involved, two consecutive blocks shown may actually be executed substantially simultaneously or the blocks can sometimes be executed in the reverse order. In addition, the embodiments presented and described in the flowcharts of the present invention are provided by way of example for the purpose of providing a more comprehensive understanding of the technology. The disclosed method is not limited to the operations and logical flows presented herein. Alternative embodiments are contemplated, where the order of various operations is changed and where sub-operations described as part of a larger operation are executed independently.

[0101] In addition, although the present invention has been described in the context of functional modules, it should be understood that, unless otherwise stated to the contrary, one or more of the functions and / or features may be integrated in a single physical device and / or software module, or one or more functions and / or features may be implemented in separate physical devices or software modules. It can also be understood that a detailed discussion of the actual implementation of each module is not necessary for understanding the present invention. Rather, considering the attributes, functions, and internal relationships of the various functional modules in the device disclosed herein, the actual implementation of the module will be understood within the ordinary skills of an engineer. Therefore, those skilled in the art can implement the present invention as set forth in the claims without undue experimentation. It can also be understood that the specific concepts disclosed are merely illustrative and are not intended to limit the scope of the present invention, which is determined by the full scope of the appended claims and their equivalents.

[0102] When the above-mentioned functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several programs for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present invention. The aforementioned storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical discs that can store program codes.

[0103] The logic and / or steps represented in the flowchart or described in other ways herein, for example, can be considered as a sequenced list of executable programs for implementing logical functions, and can be specifically implemented in any computer-readable medium for use by a program execution system, apparatus, or device (such as a computer-based system, a system including a processor, or other systems that can retrieve and execute programs from a program execution system, apparatus, or device), or in combination with these program execution systems, apparatuses, or devices. For the purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by or in combination with a program execution system, apparatus, or device.

[0104] More specific examples (nonexhaustive list) of computer-readable media include the following: electrical connection parts (electronic devices) having one or more wirings, portable computer disk cartridges (magnetic devices), random access memories (RAMs), read-only memories (ROMs), erasable programmable read-only memories (EPROMs or flash memories), optical fiber devices, and portable compact disc read-only memories (CDROMs). Additionally, a computer-readable medium can even be paper or other suitable media on which the program can be printed, because the program can be obtained electronically, for example, by optically scanning the paper or other media, followed by editing, interpretation, or other suitable processing as necessary, and then storing it in a computer memory.

[0105] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable program execution system. For example, if implemented by hardware, as in another embodiment, any one or a combination of the following techniques well known in the art can be used: discrete logic circuits having logic gate circuits for implementing logical functions on data signals, application specific integrated circuits having appropriate combinational logic gate circuits, programmable gate arrays (PGAs), field programmable gate arrays (FPGAs), etc.

[0106] In the above description of this specification, the descriptions referring to the terms "one embodiment / example", "another embodiment / example" or "certain embodiments / examples", etc. mean that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0107] Although the embodiments of the present invention have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and spirit of the present invention, and the scope of the present invention is defined by the claims and their equivalents.

[0108] The above has specifically described the preferred embodiments of the present invention, but the present invention is not limited to the described embodiments. Those skilled in the art can also make various equivalent deformations or substitutions without departing from the spirit of the present invention, and these equivalent deformations or substitutions are all included within the scope defined by the claims of the present invention.

Claims

1. A cache partitioning method, characterized in that: The following steps are involved: Parse the device tree to obtain hardware resource information; Based on the hardware resource information, create a number of address space domains and configure hardware registers; According to the hardware register, based on the received repartition instruction, the cache size of each address space domain is dynamically divided; the repartition instruction is issued by the address space domain.

2. The cache partitioning method according to claim 1, characterized in that: The dynamically dividing the cache size of each of the address space domains according to the hardware register and based on the received re-dividing instruction includes: If there is excess cache in the cache pool and the excess cache is not reserved, the cache size of each address space domain is dynamically divided according to the current load of each address space domain.

3. The cache partitioning method according to claim 1, characterized in that: The dynamically dividing the cache size of each of the address space domains according to the hardware register and based on the received re-dividing instruction includes: If the first address space domain disappears, the first address space domain issues a reclaiming repartitioning instruction; Alternatively, if the first address space domain needs to be expanded, the first address space domain issues a re-division instruction for expansion; Alternatively, if the first address space domain needs to be reduced in capacity, the first address space domain issues a reduction and re-division instruction.

4. The cache partitioning method according to claim 3, characterized in that: The method further comprises: If a repartitioning instruction representing recycling is received, recycling the cache of the first address space domain into a cache pool; Alternatively, if a repartition instruction representing capacity expansion is received, cache is allocated from the cache pool to the first address space domain; Alternatively, if a re-partition instruction representing a reduction in capacity is received, part of the cache in the first address space domain is reclaimed and returned to a cache pool.

5. The cache partitioning method according to claim 1, characterized in that: The step of creating a plurality of address space domains based on the hardware resource information and configuring hardware registers includes: Based on the hardware resource information, static resource partitioning is performed to determine cache resource attributes of the current address space domain; the cache resource attributes include the size of the cache resource and whether the cache resource is shared.

6. The cache partitioning method according to claim 1, characterized in that: The dynamically dividing the cache size of each of the address space domains according to the hardware register and based on the received re-dividing instruction includes: A virtual memory manager runs at a secondary privilege level and interacts with the address space domain via the repartition instruction; According to the repartition instruction, the cache partition module is requested to execute cache recovery or cache allocation.

7. The cache partitioning method according to claim 1, characterized in that: The method further comprises: Uboot starts and the virtual memory manager takes control of the system.

8. A cache partitioning system, characterized in that: include: The first module is used to parse the device tree and obtain hardware resource information; The second module is used to create a number of address space domains and configure hardware registers based on the hardware resource information; The third module is used to dynamically divide the cache size of each of the address space domains according to the hardware register and based on the received re-division instruction; the re-division instruction is issued by the address space domain.

9. A cache partitioning device, characterized in that: include: at least one processor; at least one memory for storing at least one program; When the at least one program is executed by the at least one processor, the at least one processor implements the cache partitioning method according to any one of claims 1 to 7.

10. A computer-readable storage medium storing a program executable by a processor, characterized in that: The processor-executable program is used to implement the cache partitioning method according to any one of claims 1 to 7 when executed by the processor.

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