Processing method for accelerating extraction of layout resistance of panel display

Abstract

The invention discloses a processing method for accelerating extraction of panel display layout resistance. The processing method comprises the following steps: determining a basic graph unit in an original layout; adding an auxiliary line grid in the original layout according to the size of the basic graph unit; cutting the original layout according to an auxiliary line grid to obtain each auxiliary line grid unit and a position coordinate, and sequentially solving a difference set of each auxiliary line grid unit and a basic graph unit to obtain a set with a limited number of reusable units and a group of corresponding position coordinate arrays; and calculating the resistance and capacitance of each reusable unit, and performing corresponding combination according to the position coordinate information. According to the layout designed by a limited number of complex units which are similar in layout and wiring but not completely the same, the layout structure is simplified, so that the resistance extraction of the panel display layout can be effectively accelerated.

Description

Technical Field

[0001] The present invention relates to the technical field of computer-aided design, and in particular to a processing method for accelerating the extraction of resistance of a flat panel display layout. Background Art

[0002] With the rapid development of flat panel display (FPD) technology, the design of large-scale layouts is becoming more and more complex. The layout and wiring design of the pixel display area is becoming more and more complex, and it has gradually evolved from a single repeatable unit to a limited number of unit designs with similar but not identical layouts and wiring. The array features are no longer obvious, which poses a great challenge to design tools. The calculation of resistance directly affects the overall performance of the FPD. The technology of fast and accurate resistance extraction for large-scale layouts has become one of the key technologies in FPD design tools. The graphics in the FPD layout are complex, and the accurate extraction of resistance is based on numerical analysis methods, which is relatively slow. Therefore, it is very time-consuming or even impossible to directly extract the resistance of the entire panel layout.

[0003] If the layout is based on a simple structure of repeated array units, the resistance extraction of the entire panel layout can be transformed into calculating the resistance of a few repeated patterns, and the final result can be obtained by simply combining the results. Summary of the invention

[0004] In order to solve the defects of the prior art, the purpose of the present invention is to provide a processing method for accelerating the extraction of resistance of a flat panel display layout. For a layout designed by a user with a limited number of complex units with similar but not completely identical layouts and wirings, a method of first obtaining locally similar graphics is then grouped according to similar units, simplified, and finally generating a locally repeated simple unit structure, which can effectively accelerate the extraction of resistance from the flat panel display layout.

[0005] In order to achieve the above-mentioned object, the present invention provides a method for accelerating the extraction of resistance of a flat panel display layout, comprising the following steps:

[0006] Determine a basic graphic unit in the original layout;

[0007] Add auxiliary line grids to the original layout according to the size of the basic graphic unit;

[0008] Cut the original layout according to the auxiliary line grid to obtain each auxiliary line grid unit and position coordinates, and calculate the difference set of each auxiliary line grid unit and the basic graphic unit in turn to obtain a set of finitely many reusable units and a set of corresponding position coordinate arrays;

[0009] The resistance and capacitance of each reusable unit are calculated, and then combined accordingly according to the position coordinate information.

[0010] Further, the original layout is a layout designed for a finite number of complex cells with similar but not identical layout and wiring.

[0011] Further, the basic graphic unit is the minimum repeated arrangement period of each pixel area in the original layout.

[0012] Further, the step of cutting the original layout according to the auxiliary line grid to obtain each auxiliary line grid unit and position coordinates, and successively taking the difference set of each auxiliary line grid unit and the basic graphic unit to obtain a set of reusable units with a finite number and a corresponding position coordinate array includes: in the order of the position coordinates, performing a graphic Boolean operation to take the difference set of each layer of the first auxiliary line grid unit and each layer of the basic graphic unit, and recording the obtained graphic result; then taking the difference set of the second auxiliary line grid unit and the basic graphic unit, and comparing the obtained graphic result with the previous result, and so on; if they are exactly the same, they are classified into the same type of reusable unit, and if they are different, they are recorded as a newly added type of reusable unit.

[0013] Still further, it further includes: tracing the metal lines of each signal path for which a resistor is to be extracted in the original layout, and marking each grid as an extraction identifier; deleting the metal lines without labels according to the extraction identifiers marked in each reusable unit, and retaining the metal lines to be extracted.

[0014] To achieve the above object, the present invention also provides an electronic device, including a memory and a processor, wherein a computer program is stored on the memory and runs on the processor, and when the processor runs the computer program, it executes the steps of the above-mentioned method for accelerating the extraction of resistors in a flat panel display layout.

[0015] To achieve the above object, the present invention also provides a computer-readable storage medium, on which a computer program is stored, and when the computer program runs, it executes the steps of the above-mentioned method for accelerating the extraction of resistors in a flat panel display layout.

[0016] The method for accelerating the extraction of resistors in a flat panel display layout provided by the present invention has the following beneficial effects compared with the prior art: By simplifying the layout structure, this method solves the extraction of resistors and capacitors in the layout and wiring design of pixel units that can be divided into a finite number of layout and wiring similar but not identical ones, and realizes the acceleration of resistor extraction in the flat panel display layout.

[0017] Other features and advantages of the present invention will be described in the following specification, and in part, will be obvious from the specification, or will be understood by implementing the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings are used to provide a further understanding of the present invention, and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation to the present invention. In the accompanying drawings:

[0019] Figure 1 It is a flowchart of a method for accelerating the extraction of the layout resistance of a flat panel display according to an embodiment of the present invention;

[0020] Figure 2 It is a schematic diagram of the original layout in an embodiment of the present invention;

[0021] Figure 3 It is a schematic diagram of the determined basic graphic unit in an embodiment of the present invention;

[0022] Figure 4 It is a schematic diagram of adding an auxiliary line grid to the original layout in an embodiment of the present invention;

[0023] Figure 5 It is a schematic diagram of the local difference in layout routing in each auxiliary line grid of the original layout in an embodiment of the present invention;

[0024] Figure 6 It is a schematic diagram of the simplified layout in an embodiment of the present invention. Detailed implementation manners

[0025] The following describes the preferred embodiments of the present invention with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention and are not used to limit the present invention.

[0026] The embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although some embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided to more thoroughly and completely understand the present invention. It should be understood that the drawings and embodiments of the present invention are only for exemplary purposes and are not used to limit the protection scope of the present invention.

[0027] The term "including" and its variations used herein are open-ended, that is, "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". The relevant definitions of other terms will be given in the following description.

[0028] It should be understood that concepts such as "first" and "second" that may be mentioned in the present invention are only used to distinguish different data or units, and are not used to limit the order or interdependence of the functions performed by these data or units. These terms are only used to distinguish one feature from another. For example, without departing from the scope of the exemplary embodiments, the first feature may be referred to as the second feature, and similarly the second feature may be referred to as the first feature.

[0029] It should be noted that the modifications of "one" and "multiple" that may be mentioned in the present invention are illustrative rather than restrictive. Those skilled in the art should understand that unless otherwise clearly specified in the context, it should be understood as "one or more". "Multiple" should be understood as two or more.

[0030] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0031] Figure 1 For the flowchart of the method for accelerating the extraction of the layout resistance of a flat panel display according to the present invention, reference will be made below Figure 1 to describe in detail the method for accelerating the extraction of the layout resistance of a flat panel display according to the present invention.

[0032] First, in step 101, a basic graphic unit is determined in the original layout.

[0033] In the embodiments of the present invention, Figure 2 a diagram of an original layout is shown, which is a layout designed with a finite number of complex units that are similar but not exactly the same in layout and wiring.

[0034] In the embodiments of the present invention, a basic graphic unit is determined in the original layout. The size of the basic graphic unit is usually the minimum repeating arrangement period of each pixel area in the original layout. According to this original layout, the graphic subset of the traces within each arrangement period is determined as the basic graphic unit, that is, the graphics of each pixel arrangement period are not necessarily exactly the same as the basic graphic unit, but must all contain the basic graphic unit, as Figure 3 shown.

[0035] In step 102, auxiliary line grids are added to the original layout according to the size of the basic graphic unit, as Figure 4 shown. It can be seen that the layout and wiring in each auxiliary line grid in the original layout exhibit highly similar characteristics, but there are local differences. The difference points are shown in Figure 5 the marked red boxes.

[0036] In step 103, the metal lines of each signal path for which the resistance is to be extracted are traced in the original layout, and tags are placed in each grid as extraction identifiers.

[0037] In step 104, the original layout is cut according to the auxiliary line grid to obtain each auxiliary line grid unit and position coordinates. The difference set of each auxiliary line grid unit and the basic graphic unit is obtained in turn, and a set with a finite number of reusable units and a corresponding position coordinate array are obtained.

[0038] In the embodiment of the present invention, the original layout is cut according to the auxiliary line grid to obtain each auxiliary line grid unit and position coordinates. In the order of the position coordinates, the difference set of each layer of the first auxiliary line grid unit and each layer of the basic graphic unit is obtained by performing graphic Boolean operations, and the obtained graphic result is recorded. Then, the difference set of the second auxiliary line grid unit and the basic graphic unit is obtained, and the obtained graphic result is compared with the previous result. If they are exactly the same, they are classified into the same type of reusable units. If they are different, they are recorded as a new type of reusable units.

[0039] In the embodiment of the present invention, the difference set of each auxiliary line grid unit is obtained in turn, and then the different types of difference set results recorded previously are traversed and compared, and the classification is recorded. Finally, the layout is transformed into a set with a finite number of reusable units and a corresponding position coordinate array.

[0040] In step 105, according to the extraction identifiers marked in each reusable unit, the metal lines without labels are deleted, and the metal lines to be extracted are retained, as Figure 6 shown.

[0041] In step 106, the resistance and capacitance of each reusable unit are calculated, and then corresponding combinations are made according to the position coordinate information.

[0042] In the embodiment of the present invention, in this way, the resistance and capacitance calculation can be transformed into first calculating the resistance and capacitance of each reusable unit, and then making corresponding combinations of the results according to the position coordinate information, so as to accelerate the extraction.

[0043] To achieve the above object, the present invention also provides an electronic device, including a memory and a processor. The memory stores a computer program that runs on the processor. When the processor runs the computer program, it executes the steps of the method for accelerating the extraction of the resistance of the flat panel display layout as described above.

[0044] To achieve the above object, the present invention also provides a computer-readable storage medium, on which a computer program is stored. When the computer program runs, it executes the steps of the method for accelerating the extraction of the resistance of the flat panel display layout as described above.

[0045] In this embodiment, the computer-readable storage medium may include, but is not limited to: various media such as USB flash drives, read-only memory (ROM for short), random access memory (RAM for short), mobile hard disks, magnetic disks, or optical discs that can store computer programs.

[0046] Those of ordinary skill in the art can understand that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, for those skilled in the art, they can still modify the technical solutions described in the foregoing embodiments or perform equivalent replacements for some of the technical features. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A method for accelerating the extraction of flat panel display layout resistance, comprising the following steps: Determine a basic graphic unit in the original layout; Add auxiliary line grids to the original layout according to the size of the basic graphic unit; Cut the original layout according to the auxiliary line grid to obtain each auxiliary line grid unit and position coordinates, and calculate the difference set of each auxiliary line grid unit and the basic graphic unit in turn to obtain a set of finitely many reusable units and a set of corresponding position coordinate arrays; The resistance and capacitance of each reusable unit are calculated, and then combined accordingly according to the position coordinate information.

2. The method for accelerating the extraction of flat panel display layout resistance according to claim 1, characterized in that: The original layout is a layout designed for a finite number of complex cells with similar but not identical layouts and wirings.

3. The method for accelerating the extraction of flat panel display layout resistance according to claim 1, characterized in that: The basic graphic unit is the minimum repetitive arrangement period of each pixel area in the original layout.

4. The method for accelerating the extraction of flat panel display layout resistance according to claim 1, characterized in that: The steps of cutting the original layout according to the auxiliary line grid to obtain each auxiliary line grid unit and the position coordinates, and sequentially finding the difference set between each auxiliary line grid unit and the basic graphic unit to obtain a set of finitely multiple reusable units and a set of corresponding position coordinate arrays include: performing graphic Boolean operations on each layer of the first auxiliary line grid unit and each layer of the basic graphic unit to find the difference set in the order of the position coordinates, and recording the obtained graphic results; then finding the difference set between the second auxiliary line grid unit and the basic graphic unit, and comparing the obtained graphic result with the previous result, and so on; if they are exactly the same, they are classified as the same type of reusable units, and if they are different, they are recorded as a newly added type of reusable units.

5. The method for accelerating the extraction of flat panel display layout resistance according to claim 1, characterized in that: Also includes: Trace the metal lines of each signal path whose resistance is to be extracted in the original layout, and put a label in each grid as an extraction mark; According to the extraction mark in each reusable unit, the metal wires without labels are deleted and the metal wires to be extracted are retained.

6. An electronic device, characterized in that: The invention comprises a memory and a processor, wherein the memory stores a computer program running on the processor, and the processor executes the steps of the processing method for accelerating the extraction of resistance of a flat panel display layout as claimed in any one of claims 1 to 5 when running the computer program.

7. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is running, the steps of the processing method for accelerating the extraction of flat panel display layout resistance described in any one of claims 1 to 5 are executed.

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