A logic board fault locating device and method

Abstract

The present application relates to the technical field of electronic testing, in particular to a logic board fault positioning device and method. Firstly, the present application detects and locates the explicit physical faults on the surface of the logic board through an image recognition model, improving the accuracy and speed of fault detection. Secondly, the present application evaluates the detection points of the logic board by introducing a weighted Euclidean distance, more accurately considering the relative importance of different signals in fault judgment, and giving priority to the signals most critical to fault diagnosis, thereby improving the sensitivity of fault positioning. Finally, the present application combines fault knowledge graph and Bayesian network to realize comprehensive tracking and reasoning of component faults, accurately positioning potential fault components through dynamic updating of posterior probability, thereby improving the accuracy and reliability of fault diagnosis. Through the combination of the above schemes, high-intelligence and high-efficiency logic board fault detection and positioning are realized.

Description

Technical Field

[0001] This invention relates to the field of electronic testing technology, specifically to a logic board fault location device and method. Background Technology

[0002] Logic boards are crucial components of electronic devices, widely used in various complex electronic products and systems, such as computers, communication equipment, and automated control systems. With the increasing integration and complexity of electronic devices, logic board failures have a profound impact on the performance and stability of the entire system. Therefore, accurate and timely logic board fault location is of great importance. Efficient fault location techniques can quickly identify and diagnose fault points on logic boards, thereby shortening repair time, reducing maintenance costs, and improving equipment reliability and system operating efficiency.

[0003] However, existing logic board fault location technologies still have certain shortcomings. Traditional fault location methods mainly rely on manual inspection or experience-based diagnosis, which are often inefficient, inaccurate, and difficult to adapt to the diverse fault modes in complex systems. Current automated detection methods, although employing technologies such as image recognition and electrical signal analysis, often can only detect surface-obvious faults, and have limited diagnostic capabilities for hidden component faults or complex multi-point faults. Furthermore, existing technologies also have problems with the accuracy of fault path tracing and component fault location, especially when dealing with signal interference and the fusion of multiple signal data, which easily leads to misjudgments and missed detections. Therefore, improving the comprehensiveness, accuracy, and real-time performance of fault location has become a pressing challenge that needs to be addressed.

[0004] To address this, a logic board fault location device and method are proposed. Summary of the Invention

[0005] The purpose of this invention is to provide a logic board fault location device and method. It accurately detects the type and location of physical faults on the logic board surface using an image recognition model, achieving rapid location of explicit faults. By introducing a weighted Euclidean distance to evaluate the detection points on the logic board, it more accurately considers the relative importance of different signals to fault judgment, prioritizing the voltage signals most critical for fault diagnosis. Through a combination of fault knowledge graphs and Bayesian networks, it achieves deep reasoning and location of potential component faults, outputs the most likely faulty component based on posterior probability criteria, and provides high-confidence fault diagnosis results.

[0006] To achieve the above objectives, the present invention provides the following technical solution:

[0007] A logic board fault location device, comprising:

[0008] The physical fault detection module is used to acquire surface image data of the logic board using a high-definition camera device, detect physical faults in the surface image data through an image recognition model, and map the physical fault locations to corresponding locations in the logic board topology diagram.

[0009] The component fault detection module includes:

[0010] The data acquisition submodule is used to acquire real-time electrical signal data of test points on the logic board through an electrical signal probe;

[0011] The fault analysis submodule is used to calculate the weighted Euclidean distance between the real-time electrical signal data and the pre-stored historical electrical signal data, and to determine abnormal signal nodes based on a preset fluctuation threshold.

[0012] The fault location submodule is used to track fault components based on the topological location of the abnormal signal node, combined with a pre-built fault knowledge graph and a Bayesian network, to obtain the confidence level of each component within the region of the abnormal signal node; output the component with the highest confidence level as the fault component and determine the fault type; and map the fault location of the fault component to the corresponding location in the logic board topology diagram.

[0013] The fault report generation module is used to collect fault locations and fault types, combine them with a fault knowledge base to generate fault repair suggestions, and print fault reports.

[0014] Furthermore, the physical fault detection using the surface image data includes:

[0015] The surface image data of the logic board is captured using a high-definition camera; the surface image data is preprocessed to obtain preprocessed data; the preprocessed data is input into a pre-trained image recognition model; the image recognition model outputs the physical fault type and physical fault location.

[0016] Furthermore, the electrical signal data includes voltage signals, current signals, and frequency signals, and the formula for calculating the weighted Euclidean distance is:

[0017]

[0018] Where D represents the weighted Euclidean distance, U r I r and f r These are real-time voltage signal, real-time current signal, and real-time frequency signal, respectively. h I h and f h These represent historical voltage signals, historical current signals, and historical frequency signals, respectively. α represents the voltage distance weight, and β represents the composite distance weight.

[0019] Furthermore, the component fault tracing process includes:

[0020] Based on the location of the abnormal signal node in the logic board topology, an upstream power supply path and a downstream load path are generated along the signal transmission direction as candidate fault paths.

[0021] Based on a pre-built fault knowledge graph, candidate fault paths are tracked and potential fault components are located.

[0022] The confidence scores of each potentially faulty component are calculated and output using a Bayesian network.

[0023] Furthermore, the computation process of the Bayesian network includes:

[0024] Construct a Bayesian network node, wherein the Bayesian network node includes abnormal signal nodes, potential faulty components, and fault types;

[0025] The initial prior probability of component failure is set based on the fault knowledge graph;

[0026] The weighted Euclidean distance is used as observational evidence to update the posterior probability of nodes;

[0027] Output the confidence level of the potential faulty component based on the maximum a posteriori probability criterion.

[0028] This invention also proposes a method for locating logic board faults, comprising:

[0029] High-definition camera equipment is used to acquire surface image data of the logic board. Physical fault detection is performed on the surface image data through image recognition model detection, and the physical fault points are mapped to the corresponding points in the logic board topology diagram.

[0030] Real-time electrical signal data of test points on the logic board is acquired using an electrical signal probe.

[0031] Calculate the weighted Euclidean distance between the real-time electrical signal data and the pre-stored historical electrical signal data, and determine abnormal signal nodes based on a preset fluctuation threshold;

[0032] Based on the topological location of the abnormal signal node, fault component tracking is performed using a pre-built fault knowledge graph and a Bayesian network to obtain the confidence level of each component within the abnormal signal node region; the component with the highest confidence level is output as the fault component and the fault type is determined, and the fault location of the fault component is mapped to the corresponding location in the logic board topology diagram.

[0033] Collect fault locations and fault types, combine them with a fault knowledge base to generate fault repair suggestions, and print fault reports.

[0034] Furthermore, the physical fault detection using the surface image data includes:

[0035] The surface image data of the logic board is captured using a high-definition camera; the surface image data is preprocessed to obtain preprocessed data; the preprocessed data is input into a pre-trained image recognition model; the image recognition model outputs the physical fault type and physical fault location.

[0036] Furthermore, the electrical signal data includes voltage signals, current signals, and frequency signals, and the formula for calculating the weighted Euclidean distance is:

[0037]

[0038] Where D represents the weighted Euclidean distance, U r I r and f r These are real-time voltage signal, real-time current signal, and real-time frequency signal, respectively. h I h and f h These represent historical voltage signals, historical current signals, and historical frequency signals, respectively. α represents the voltage distance weight, and β represents the composite distance weight.

[0039] Furthermore, the component fault tracing process includes:

[0040] Based on the location of the abnormal signal node in the logic board topology, an upstream power supply path and a downstream load path are generated along the signal transmission direction as candidate fault paths.

[0041] Based on a pre-built fault knowledge graph, candidate fault paths are tracked and potential fault components are located.

[0042] The confidence scores of each potentially faulty component are calculated and output using a Bayesian network.

[0043] Furthermore, the computation process of the Bayesian network includes:

[0044] Construct a Bayesian network node, wherein the Bayesian network node includes abnormal signal nodes, potential faulty components, and fault types;

[0045] The initial prior probability of component failure is set based on the fault knowledge graph;

[0046] The weighted Euclidean distance is used as observational evidence to update the posterior probability of nodes;

[0047] Output the confidence level of the potential faulty component based on the maximum a posteriori probability criterion.

[0048] The beneficial effects of this invention are:

[0049] 1. This invention introduces a weighted Euclidean distance to evaluate the detection points of the logic board. Compared to the traditional Euclidean distance, the weighted Euclidean distance can more accurately consider the relative importance of different signals to fault diagnosis. By assigning different weights to different signals, the weighted Euclidean distance can prioritize the voltage signal most critical to fault diagnosis. Therefore, even when there are large signal fluctuations or interference from multiple signals, it can still effectively identify the most influential fault characteristics, avoiding the influence of the overall judgment on the instability or noise of a certain signal, and improving the accuracy and reliability of fault location.

[0050] 2. This invention uses Bayesian networks to infer and locate faulty components in anomalous signal nodes. By combining observational evidence of real-time signals with prior fault knowledge, it dynamically updates the posterior probability of each potential faulty component, thereby accurately identifying the faulty component and its fault mode. This process can output the most probable faulty component based on the maximum a posteriori probability criterion and provide the corresponding confidence level, improving the accuracy, reliability, and decision support capabilities of fault diagnosis.

[0051] 3. This invention uses an image recognition model to detect and locate explicit physical faults on the surface of the logic board, and uses weighted Euclidean distance, fault knowledge graphs, and Bayesian networks to detect and locate implicit component faults within the logic board components. By combining physical and component faults, a more comprehensive and accurate fault diagnosis can be achieved. This method can not only identify visible faults but also locate potential component problems through electrical signal analysis and probabilistic reasoning, thereby improving the accuracy of fault location, reducing the probability of missed detections, and accelerating fault diagnosis and repair, ultimately improving system reliability and maintenance efficiency. Attached Figure Description

[0052] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings:

[0053] Figure 1 This is a schematic diagram of a logic board fault location device provided by the present invention;

[0054] Figure 2 This invention provides a flowchart of a Bayesian network computation process.

[0055] Figure 3 This is a flowchart of a logic board fault location method provided by the present invention. Detailed Implementation

[0056] The preferred embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.

[0057] Example 1

[0058] A logic board fault location device, such as Figure 1 As shown, it includes:

[0059] The physical fault detection module is used to acquire surface image data of the logic board using a high-definition camera device, detect physical faults in the surface image data through an image recognition model, and map the physical fault locations to corresponding locations in the logic board topology diagram.

[0060] Furthermore, the physical fault detection using the surface image data includes:

[0061] The surface image data of the logic board is captured using a high-definition camera; the surface image data is preprocessed to obtain preprocessed data; the preprocessed data is input into a pre-trained image recognition model; the image recognition model outputs the physical fault type and physical fault location.

[0062] Specifically, the high-definition camera has a resolution of no less than 20 megapixels and is equipped with a ring-polarized light source. The image acquisition covers the entire surface of the logic board, including all components, solder joints, and circuits. The surface image data is preprocessed, including using filtering algorithms (such as Gaussian filtering, mean filtering, etc.) to remove noise from the image and adjust the image contrast to make physical faults (such as broken pins, burnt components, or detached solder joints) more prominent. The pre-trained model is a target detection model, which can be a ResNet, VIT, or YOLO series detection model. In this embodiment, the YOLO v5 model is preferred. The pre-trained model has been trained with logic board physical fault data.

[0063] This solution acquires images of the logic board surface and combines them with image preprocessing techniques and a pre-trained target detection model to accurately identify the types and locations of physical faults on the logic board, thereby enabling the troubleshooting and location of obvious physical faults on the logic board surface.

[0064] The component fault detection module includes:

[0065] The data acquisition submodule is used to acquire real-time electrical signal data of test points on the logic board through an electrical signal probe;

[0066] Furthermore, the electrical signal probe is a multi-channel probe array that supports detection of voltage (0-50V), current (0-10A), and frequency (0-100MHz) ranges; the test points include the gate drive circuit, source drive circuit, timing control circuit, DC-DC conversion circuit, and gamma correction circuit.

[0067] The fault analysis submodule is used to calculate the weighted Euclidean distance between the real-time electrical signal data and the pre-stored historical electrical signal data, and to determine abnormal signal nodes based on a preset fluctuation threshold.

[0068] Furthermore, the electrical signal data includes voltage signals, current signals, and frequency signals, and the formula for calculating the weighted Euclidean distance is:

[0069]

[0070] Where D represents the weighted Euclidean distance, U r I r and f r These are real-time voltage signal, real-time current signal, and real-time frequency signal, respectively. h I h and f h These represent historical voltage signals, historical current signals, and historical frequency signals, respectively. α represents the voltage distance weight, and β represents the composite distance weight.

[0071] Specifically, α and β change with the test point; in one feasible implementation, α = 0.75 and β = 0.25 in the gate drive circuit. h I h and f h Let Wt be the mean value of each item in the historical electrical signal database, and let Wt satisfy the following formula:

[0072]

[0073] By calculating the weighted Euclidean distance between real-time electrical signal data and pre-stored historical electrical signal data, the degree of anomaly in current voltage, current, and frequency signals can be accurately assessed. By setting fluctuation thresholds, abnormal signal nodes can be effectively identified, and potential faults in the system can be promptly detected. This weighted Euclidean distance-based metric takes into account the relative importance of different signals, improving the accuracy and sensitivity of fault detection.

[0074] The fault location submodule is used to track fault components based on the topological location of the abnormal signal node, combined with a pre-built fault knowledge graph and a Bayesian network, to obtain the confidence level of each component within the region of the abnormal signal node; output the component with the highest confidence level as the fault component and determine the fault type; and map the fault location of the fault component to the corresponding location in the logic board topology diagram.

[0075] Furthermore, the component fault tracing process is as follows: Figure 2 As shown, it includes:

[0076] Based on the location of the abnormal signal node in the logic board topology, an upstream power supply path and a downstream load path are generated along the signal transmission direction as candidate fault paths.

[0077] Based on a pre-built fault knowledge graph, candidate fault paths are tracked and potential fault components are located.

[0078] The confidence scores of each potentially faulty component are calculated and output using a Bayesian network.

[0079] Specifically, the upstream power supply path is the source of signal transmission, usually a power module, and the downstream load path is the final output of the signal, usually a load or execution component. The fault knowledge graph includes the dependencies between components, fault modes, fault paths, and component parameter ranges. In one feasible implementation, the detected abnormal signal node is a timing control circuit. After detection, the downstream load path is determined to be a candidate fault path. Combining the pre-built fault knowledge graph, potential faulty components, including program memory, signal processor, and capacitors, are located. A Bayesian network is used to calculate and output the confidence of each potential faulty component.

[0080] By generating upstream power supply paths and downstream load paths along the signal transmission path based on the location of abnormal signal nodes in the logic board topology, candidate fault paths can be accurately traced. This process, combined with a pre-built fault knowledge graph, can effectively locate potential faulty components. Furthermore, a Bayesian network is used to calculate the fault confidence of each component, ultimately outputting the most likely faulty component and its confidence score. This method improves the accuracy and efficiency of fault location, enabling rapid and accurate identification of fault sources, reducing troubleshooting time, and optimizing maintenance decisions.

[0081] Furthermore, the computation process of the Bayesian network includes:

[0082] Construct a Bayesian network node, wherein the Bayesian network node includes abnormal signal nodes, potential faulty components, and fault types;

[0083] The initial prior probability of component failure is set based on the fault knowledge graph;

[0084] The weighted Euclidean distance is used as observational evidence to update the posterior probability of nodes;

[0085] Output the confidence level of the potential faulty component based on the maximum a posteriori probability criterion.

[0086] Furthermore, Bayesian nodes are established based on anomalous signal nodes, potential faulty components, and fault types. An initial prior probability of failure is assigned to each component based on the fault knowledge graph and historical data. For example, capacitors have a higher failure probability under certain high-load conditions, so a higher prior probability can be assigned to them. Weighted Euclidean distance is used to measure the deviation between real-time electrical signal data and historical data. These distance values ​​can serve as observational evidence for the Bayesian network, updating the posterior probability of the nodes. According to Bayes' theorem, the posterior probability update formula for each potential faulty component is:

[0087]

[0088] Where P(C|E) represents the posterior probability of component C failing given observational evidence E, P(E|C) represents the probability of observing evidence E (i.e., weighted Euclidean distance) under the condition that component C fails, P(C) is the prior probability of component C, and P(E) is the marginal probability of evidence E. According to the maximum posterior probability criterion, the potential faulty component with the highest posterior probability is selected, and the confidence level of the component is output.

[0089] By constructing Bayesian network nodes, abnormal signal nodes, potentially faulty components, and fault types are effectively linked, and an initial prior probability of component failure is set using a fault knowledge graph. By introducing weighted Euclidean distance as observational evidence, the posterior probability of nodes can be dynamically updated, reflecting changes in system state in real time. Finally, based on the maximum a posteriori probability criterion, the confidence level of potentially faulty components is accurately output, thereby improving the accuracy and reliability of fault diagnosis, helping to quickly locate the source of the problem, and supporting more targeted maintenance decisions.

[0090] The fault report generation module is used to collect fault locations and fault types, combine them with a fault knowledge base to generate fault repair suggestions, and print fault reports.

[0091] Example 2

[0092] To achieve intelligent and efficient motherboard fault location, an electronic equipment R&D company adopted a logic board fault location method proposed in this invention, such as... Figure 3 As shown, it includes:

[0093] High-definition camera equipment is used to acquire surface image data of the logic board. Physical fault detection is performed on the surface image data through image recognition model detection, and the physical fault points are mapped to the corresponding points in the logic board topology diagram.

[0094] Real-time electrical signal data of test points on the logic board is acquired using an electrical signal probe.

[0095] Calculate the weighted Euclidean distance between the real-time electrical signal data and the pre-stored historical electrical signal data, and determine abnormal signal nodes based on a preset fluctuation threshold;

[0096] Based on the topological location of the abnormal signal node, fault component tracking is performed using a pre-built fault knowledge graph and a Bayesian network to obtain the confidence level of each component within the abnormal signal node region; the component with the highest confidence level is output as the fault component and the fault type is determined, and the fault location of the fault component is mapped to the corresponding location in the logic board topology diagram.

[0097] Collect fault locations and fault types, combine them with a fault knowledge base to generate fault repair suggestions, and print fault reports.

[0098] Furthermore, the physical fault detection using the surface image data includes:

[0099] The surface image data of the logic board is captured using a high-definition camera; the surface image data is preprocessed to obtain preprocessed data; the preprocessed data is input into a pre-trained image recognition model; the image recognition model outputs the physical fault type and physical fault location.

[0100] Furthermore, the electrical signal data includes voltage signals, current signals, and frequency signals, and the formula for calculating the weighted Euclidean distance is:

[0101]

[0102] Where D represents the weighted Euclidean distance, U r I r and f r These are real-time voltage signal, real-time current signal, and real-time frequency signal, respectively. h I h and f h These represent historical voltage signals, historical current signals, and historical frequency signals, respectively. α represents the voltage distance weight, and β represents the composite distance weight.

[0103] Furthermore, the component fault tracing process includes:

[0104] Based on the location of the abnormal signal node in the logic board topology, an upstream power supply path and a downstream load path are generated along the signal transmission direction as candidate fault paths.

[0105] Based on a pre-built fault knowledge graph, candidate fault paths are tracked and potential fault components are located.

[0106] The confidence scores of each potentially faulty component are calculated and output using a Bayesian network.

[0107] Furthermore, the computation process of the Bayesian network includes:

[0108] Construct a Bayesian network node, wherein the Bayesian network node includes abnormal signal nodes, potential faulty components, and fault types;

[0109] The initial prior probability of component failure is set based on the fault knowledge graph;

[0110] The weighted Euclidean distance is used as observational evidence to update the posterior probability of nodes;

[0111] Output the confidence level of the potential faulty component based on the maximum a posteriori probability criterion.

[0112] Finally, it should be noted that the above descriptions are merely preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A logic board fault locating apparatus, characterized by, The physical fault detection module is configured to acquire surface image data of the logic board using a high-definition camera device, detect physical faults in the surface image data by using an image recognition model, and map physical fault points to corresponding points on a topology map of the logic board. The component fault detection module includes: The data acquisition submodule is configured to acquire real-time electrical signal data of test points on the logic board by using an electrical signal probe. The fault analysis submodule is configured to calculate a weighted Euclidean distance between the real-time electrical signal data and pre-stored historical electrical signal data, and determine an abnormal signal node based on a preset fluctuation threshold. The fault location submodule is configured to track a fault component based on a topology position of the abnormal signal node, a pre-constructed fault knowledge graph, and a Bayesian network, to obtain a confidence degree of each component in a region of the abnormal signal node, output a component with the highest confidence degree as the fault component, determine a fault type, and map a fault point of the fault component to a corresponding point on a topology map of the logic board. The fault report generation module is configured to collect the fault point and the fault type, generate a fault maintenance suggestion in combination with a fault knowledge base, and print a fault report. The electrical signal data includes voltage signals, current signals, and frequency signals, and a calculation formula of the weighted Euclidean distance is as follows: The fault component tracking process includes: ； wherein, denotes the weighted Euclidean distance, , and are real-time voltage signal, real-time current signal and real-time frequency signal, respectively, , and are historical voltage signal, historical current signal and historical frequency signal, respectively, denotes the voltage distance weight, denotes the compound distance weight; Based on a position of the abnormal signal node in the topology map of the logic board, an upstream power supply path and a downstream load path are generated as candidate fault paths along a signal transmission direction. Based on the pre-constructed fault knowledge graph, potential fault components are tracked and located in the candidate fault paths. The confidence degrees of the potential fault components are calculated by using the Bayesian network and output. The physical fault detection of the surface image data includes:

2. The logic board fault locating apparatus of claim 1, wherein, The surface image data of the logic board is captured by using a high-definition camera device, the surface image data is preprocessed to obtain preprocessed data, and the preprocessed data is input into a pre-trained image recognition model. The calculation process of the Bayesian network includes:

3. The logic board fault locating apparatus of claim 1, wherein, The Bayesian network nodes include abnormal signal nodes, potential fault components, and fault types. An initial prior probability of component failure is set based on a fault knowledge graph. The weighted Euclidean distance is used as observation evidence to update the posterior probability of the nodes. The confidence degrees of the potential fault components are output based on a maximum posterior probability criterion. The physical fault detection module is configured to acquire surface image data of the logic board using a high-definition camera device, detect physical faults in the surface image data by using an image recognition model, and map physical fault points to corresponding points on a topology map of the logic board.

4. A logic board fault location method characterized by, The data acquisition submodule is configured to acquire real-time electrical signal data of test points on the logic board by using an electrical signal probe. The fault analysis submodule is configured to calculate a weighted Euclidean distance between the real-time electrical signal data and pre-stored historical electrical signal data, and determine an abnormal signal node based on a preset fluctuation threshold. ​ ​ According to the topological position of the abnormal signal node, combined with a pre-constructed fault knowledge graph and a Bayesian network, a fault component is tracked to obtain a confidence of each component inside a region of the abnormal signal node; a component with the highest confidence is output as a fault component and a fault type is judged, and a fault point of the fault component is mapped to a corresponding point on a logical board topological graph; A fault maintenance suggestion is generated by combining a fault knowledge base with the fault point and the fault type, and a fault report is printed; The electrical signal data includes voltage signals, current signals and frequency signals, and a calculation formula of the weighted Euclidean distance is: ； wherein, denotes the weighted Euclidean distance, , and are real-time voltage signal, real-time current signal and real-time frequency signal, respectively, , and are historical voltage signal, historical current signal and historical frequency signal, respectively, denotes the voltage distance weight, denotes the compound distance weight; The fault component tracking process includes: According to the position of the abnormal signal node on the logical board topological graph, an upstream power supply path and a downstream load path are generated along a signal transmission direction as candidate fault paths; Based on the pre-constructed fault knowledge graph, the candidate fault paths are tracked and potential fault components are located; The confidence of each potential fault component is calculated using the Bayesian network and is output.

5. The method of claim 4, wherein, The surface image data for physical fault detection includes: High-definition camera equipment is used to capture surface image data of the logical board; the surface image data is preprocessed to obtain preprocessed data; the preprocessed data is input into a pre-trained image recognition model; and the image recognition model outputs a physical fault type and a physical fault point.

6. The method of claim 4, wherein, The calculation process of the Bayesian network includes: A Bayesian network node is constructed, which includes an abnormal signal node, a potential fault component and a fault type; An initial prior probability of component failure is set based on the fault knowledge graph; The weighted Euclidean distance is used as observation evidence to update the posterior probability of the node; According to the maximum a posteriori probability criterion, the confidence of the potential fault component is output.

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