Display driving circuit and display panel

Abstract

A display driving circuit and a display panel, the display driving circuit comprises a light-emitting module, an acquisition module and a compensation module, the light-emitting module comprises a scanning line, a data line and a light-emitting piece, the scanning line and the data line are electrically connected with the light-emitting piece, the light-emitting piece is used for emitting light according to a first scanning signal on the scanning line and a data signal on the data line, the acquisition module is electrically connected with the light-emitting module, the compensation module is electrically connected with the light-emitting module and the acquisition module, there is a parasitic capacitance between the scanning line and the data line, when the first scanning signal is switched from high level to low level, the parasitic capacitance divides the data signal to make the voltage of the drain of the first thin film transistor of the light-emitting module drop from the first voltage to the second voltage to generate an offset voltage, the acquisition module is used for outputting a charging voltage to the compensation module according to the offset voltage, the compensation module is used for outputting a compensation voltage to the light-emitting piece according to the charging voltage, the compensation voltage is used for compensating the voltage drop of the light-emitting piece caused by the parasitic capacitance, and the display effect is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display driving circuit and display panel. BACKGROUND

[0002] The organic light emitting diode (Organic Light Emitting Display, OLED) display realizes display by emitting light under current driving through pixel units composed of organic semiconductor material and light emitting material. In the prior art, due to the small spacing between the scanning line and the data line, there is a parasitic capacitance, and the coupling between the high-frequency signal on the scanning line and the digital signal on the data line will cause the voltage of the data line to deviate from the theoretical value, resulting in insufficient charging of the pixel, uneven brightness and flicker problems. SUMMARY

[0003] The purpose of the present application is to provide a display driving circuit and display panel, which solves the problem of voltage deviation of the data line from the theoretical value, resulting in insufficient charging of the pixel unit, uneven brightness and flicker.

[0004] To achieve the purpose of the present application, the present application provides the following technical solutions:

[0005] In a first aspect, the present application provides a display driving circuit, comprising: a light-emitting module, comprising a scan line, a data line, a first thin film transistor, a second thin film transistor, a first storage capacitor, a power supply line and a light-emitting component, the source of the first thin film transistor is electrically connected with the data line, the gate of the first thin film transistor is electrically connected with the scan line, the drain of the first thin film transistor is electrically connected with the gate of the second thin film transistor, the source of the second thin film transistor is electrically connected with the power supply line, the drain of the second thin film transistor is electrically connected with the anode of the light-emitting component, the cathode of the light-emitting component is connected with a ground terminal, one end of the first storage capacitor is electrically connected with the gate of the second thin film transistor, and the other end is electrically connected with the source of the second thin film transistor, the scan line is used for inputting a first scan signal, the data line is used for inputting a data signal, the power supply line is used for inputting a power supply signal, and the light-emitting component is used for emitting light according to the first scan signal and the data signal; a collection module, which is electrically connected with the drain of the first thin film transistor, the data line, the power supply line and the ground terminal; a compensation module, which is electrically connected with the anode of the light-emitting component and the collection module; wherein, there is a parasitic capacitor between the scan line and the data line, when the first scan signal is switched from high level to low level, the parasitic capacitor divides the data signal to make the voltage of the drain of the first thin film transistor drop from a first voltage to a second voltage to generate an offset voltage, the drain of the first thin film transistor is used for outputting the offset voltage to the collection module, the collection module is used for outputting a charging voltage to the compensation module according to the offset voltage, the compensation module is used for outputting a compensation voltage to the light-emitting component according to the charging voltage, and the compensation voltage is used for compensating the voltage drop of the light-emitting component caused by the parasitic capacitor.

[0006] In an embodiment, the collection module comprises a first operation module, a second operation module and a third operation module, the first operation module is electrically connected with the drain of the first thin film transistor, the data line and the third operation module, the second operation module is electrically connected with the power supply line, the third operation module and the ground terminal, and the third operation module is electrically connected with the compensation module; wherein, the first operation module is used for outputting a first intermediate signal to the third operation module according to the offset voltage and the data signal, the second operation module is used for outputting a second intermediate signal to the third operation module according to the power supply signal and the light emitted by the light-emitting component, and the third operation module is used for outputting the charging voltage.

[0007] In one embodiment, the first operation module includes a first trace, a third thin film transistor, a first capacitor, a second capacitor, a first resistor, a second resistor, a third resistor and an operational amplifier, the source of the third thin film transistor is electrically connected with the drain of the first thin film transistor, the gate of the third thin film transistor is electrically connected with the first trace, the drain of the third thin film transistor is electrically connected with one end of the first capacitor, the first resistor is connected in series with the other end of the first capacitor and the negative input terminal of the operational amplifier, the second resistor is connected in series with the negative input terminal of the operational amplifier and the output terminal of the operational amplifier, the third resistor is connected in series with the output terminal of the operational amplifier and the third operation module, one end of the second capacitor is electrically connected with the positive input terminal of the operational amplifier and the data line, and the other end is electrically connected with a ground terminal; wherein the first trace is used for inputting a second scanning signal, and the operational amplifier is used for outputting the first intermediate signal to the third operation module according to the offset voltage and the data signal.

[0008] In one embodiment, the second operation module includes a second trace, a fourth resistor, a fourth thin film transistor, a first crystal triode, a second crystal triode, an operational subtractor and a third capacitor, the first crystal triode and the light emitting component constitute a photoelectric coupler, the fourth resistor is connected in series with the source of the second thin film transistor and the source of the fourth thin film transistor, the gate of the fourth thin film transistor is electrically connected with the second trace, the drain of the fourth thin film transistor is electrically connected with the collector of the first crystal triode, the collector of the second crystal triode and the negative input terminal of the operational subtractor, the emitter of the first crystal triode is electrically connected with the base of the second crystal triode, the emitter of the second crystal triode is electrically connected with a ground terminal, one end of the third capacitor is electrically connected with the positive input terminal of the operational subtractor, the other end of the third capacitor is used for inputting the first voltage, and the output terminal of the operational subtractor is electrically connected with the third operation module; wherein the second trace is used for inputting a third scanning signal, the first crystal triode is used for outputting a photoelectric signal to the base of the second crystal triode according to the light emitted by the light emitting component, the collector of the second crystal triode is used for outputting a third intermediate signal to the operational subtractor, and the operational subtractor is used for outputting the second intermediate signal according to the third intermediate signal and the first voltage.

[0009] In one embodiment, the third operation module includes an operational adder, the third resistor is connected in series with one input terminal of the operational adder and the output terminal of the operational amplifier, the output terminal of the operational subtractor is electrically connected with the other input terminal of the operational adder, and the operational adder is used for outputting the charging voltage according to the first intermediate signal and the second intermediate signal.

[0010] In an embodiment, the acquisition module further comprises a stop module, the stop module comprises an AND gate and a fifth thin film transistor, the drain of the fifth thin film transistor is electrically connected to one input terminal of the operational amplifier, the source of the fifth thin film transistor is electrically connected to one end of the third resistor away from the operational amplifier, the gate of the fifth thin film transistor is electrically connected to the output terminal of the AND gate, one input terminal of the AND gate is electrically connected to the output terminal of the operational subtractor, and the other input terminal of the AND gate is electrically connected to the positive input terminal of the operational subtractor; wherein, when the third intermediate signal is the same as the first voltage, the AND gate outputs a low level to make the fifth thin film transistor closed.

[0011] In an embodiment, the compensation module comprises a second storage capacitor, a sixth thin film transistor, a fifth resistor and a third trace, one end of the second storage capacitor is electrically connected to the drain of the second thin film transistor, the other end is electrically connected to the drain of the sixth thin film transistor, one end of the fifth resistor is electrically connected to the ground terminal, and the other end is electrically connected to the source of the sixth thin film transistor, and the third trace is electrically connected to the gate of the sixth thin film transistor, and the third trace is used for inputting a fourth scanning signal.

[0012] In an embodiment, the display driving circuit comprises a display area and a non-display area, the non-display area is arranged around the display area, and the light emitting module is arranged in the display area; the acquisition module is wholly arranged in the display area, or at least part of the acquisition module is arranged in the non-display area; the compensation module is wholly arranged in the display area, or at least part of the compensation module is arranged in the non-display area.

[0013] In a second aspect, the present application further provides a display panel comprising a cathode layer and the display driving circuit in the embodiments of the first aspect, and the cathode layer constitutes the ground terminal of the display driving circuit.

[0014] By arranging the acquisition module and the compensation module, the acquisition module is electrically connected to the light emitting module, and the compensation module is electrically connected to the light emitting module and the acquisition module, wherein the parasitic capacitor is arranged between the scanning line and the data line, when the first scanning signal is switched from the high level to the low level, the parasitic capacitor divides the voltage of the data signal to make the voltage of the drain of the first thin film transistor of the light emitting module drop from the first voltage to the second voltage to generate the offset voltage, the acquisition module is used for outputting the charging voltage to the compensation module according to the offset voltage, and the compensation module is used for outputting the compensation voltage to the light emitting piece according to the charging voltage, and the compensation voltage is used for compensating the voltage drop of the light emitting piece caused by the parasitic capacitor to make the light emitting piece charge normally and reach the theoretical brightness, thereby avoiding the risk of uneven brightness and flicker and improving the display effect. BRIEF DESCRIPTION OF DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the description of the embodiments or the prior art. Obviously, the drawings in the following description only show some of the embodiments of the present application, and for those skilled in the art, other drawings can also be obtained from these drawings without any creative effort.

[0016] Figure 1 FIG. 1 is a circuit diagram of a display driving circuit according to an embodiment;

[0017] Figure 2 FIG. 2 is a potential diagram of a display driving circuit according to a comparative example;

[0018] Figure 3 FIG. 3 is a potential diagram of a display driving circuit according to an embodiment;

[0019] Figure 4 FIG. 4 is a panel schematic diagram of a display driving circuit according to an embodiment;

[0020] Figure 5 FIG. 5 is a panel schematic diagram of a display driving circuit according to another embodiment.

[0021] Explanation of reference signs:

[0022] 100 - display driving circuit;

[0023] 10 - light emitting module, T1 - first thin film transistor, T2 - second thin film transistor, Cs1 - first storage capacitor, Co - parasitic capacitor, Gate - scanning line, S - data line, VDD - power supply line, OLED - light emitting element;

[0024] 20 - acquisition module, 21 - first operation module, T3 - third thin film transistor, R1 - first resistor, R2 - second resistor, R3 - third resistor, Q1 - operational amplifier, C1 - first capacitor, C2 - second capacitor, L1 - first wire, 22 - second operation module, T4 - fourth thin film transistor, K1 - first crystal triode, K2 - second crystal triode, R4 - fourth resistor, L2 - second wire, Q2 - operational subtractor, C3 - third capacitor, 23 - third operation module, Q3 - operational adder, 24 - stop module, T5 - fifth thin film transistor, Q4 - AND gate;

[0025] 30 - compensation module, T6 - sixth thin film transistor, Cs2 - second storage capacitor, R5 - fifth resistor, L3 - third wire;

[0026] 40 - driving circuit board;

[0027] GOA - scan driving unit, SOC - data driving unit, GDL1 - first signal driving unit, GDL2 - second signal driving unit, GDL3 - third signal driving unit, GND - ground terminal, PS1 - first power supply, PS2 - second power supply, DA - display area, AA - active display area, IA - inactive display area, NA - non-display area;

[0028] G1 - first scan signal, G2 - second scan signal, G3 - third scan signal, G4 - fourth scan signal, VO - operating voltage, V1 - first voltage, V2 - second voltage, V3 - offset voltage;

[0029] T - driving period, t1 - first time period, t2 - second time period, t3 - third time period, t4 - fourth time period, t5 - fifth time period, t6 - sixth time period. DETAILED DESCRIPTION

[0030] The technical solutions in the embodiments of the present application will be clearly and completely described in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0031] It should be noted that when a component is referred to as being "fixed" to another component, it can be directly on the other component or there can be an intervening component. When a component is referred to as being "connected" to another component, it can be directly connected to the other component or there can be an intervening component.

[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The use of the terms "and / or" includes a combination of one or more of the associated listed items.

[0033] Some embodiments of the present application will be described in detail with reference to the drawings. The following embodiments and features of the embodiments can be combined with each other in the case of no conflict.

[0034] Reference will be made to Figures 1 to 3The application provides a display driving circuit 100, which comprises a light-emitting module 10, an acquisition module 20 and a compensation module 30. The light-emitting module 10 comprises a scanning line Gate, a data line S and a light-emitting component OLED. The scanning line Gate and the data line S are electrically connected with the light-emitting component OLED. The scanning line Gate is used for inputting a first scanning signal G1. The data line S is used for inputting a data signal. The light-emitting component OLED is used for emitting light according to the first scanning signal G1 and the data signal. The acquisition module 20 is electrically connected with the light-emitting module 10. The compensation module 30 is electrically connected with the light-emitting module 10 and the acquisition module 20. The scanning line Gate and the data line S have a parasitic capacitor Co. When the first scanning signal G1 is switched from a high level to a low level, the parasitic capacitor Co divides the data signal to generate an offset voltage V3, in which the voltage of the drain of a first thin film transistor T1 decreases from a first voltage V1 to a second voltage V2. The acquisition module 20 is used for outputting a charging voltage to the compensation module 30 according to the offset voltage V3. The compensation module 30 is used for outputting a compensation voltage to the light-emitting component OLED according to the charging voltage. The compensation voltage is used for compensating the voltage drop of the light-emitting component OLED caused by the parasitic capacitor Co.

[0035] Please refer to Figure 2 , Figure 2 The potential diagram of a display driving circuit 100 of a comparative example is shown in FIG. 1. In order to ensure the compactness of the design of the display panel, the distance between the scanning line Gate and the data line S is small, and thus the parasitic capacitor Co exists. The parasitic capacitor Co causes the mutual interference between the first scanning signal G1 on the scanning line Gate and the data signal on the data line S, and thus the signal distortion occurs. The first scanning signal G1 is a high-frequency signal. The data signal contains a rapidly changing digital signal. The voltage of the first scanning signal G1 is usually greater than the voltage of the data signal. When the first scanning signal G1 and the data signal are coupled due to the parasitic capacitor Co, the voltage of the drain of the first thin film transistor T1 decreases from the first voltage V1 to the second voltage V2, and thus the light-emitting component OLED is insufficiently charged, and the problems of uneven brightness and flicker occur.

[0036] Please refer to Figure 3 , Figure 3 The potential diagram of the display driving circuit 100 in the embodiment of the application is shown in FIG. 2. When the voltage of the drain of the first thin film transistor T1 decreases from the first voltage V1 to the second voltage V2 to generate the offset voltage V3, the acquisition module 20 is used for outputting the charging voltage to the compensation module 30 according to the offset voltage V3. The compensation module 30 is used for outputting the compensation voltage to the light-emitting component OLED according to the charging voltage. The compensation voltage is used for compensating the voltage drop of the light-emitting component OLED caused by the parasitic capacitor Co, so that the light-emitting component OLED maintains the normal display state.

[0037] Wherein, the first voltage V1 is greater than the second voltage V2, and the offset voltage V3 is the difference between the first voltage V1 and the second voltage V2, i.e. V3 = V1-V2.

[0038] By setting the acquisition module 20 and the compensation module 30, the acquisition module 20 is electrically connected with the light-emitting module 10, and the compensation module 30 is electrically connected with the light-emitting module 10 and the acquisition module 20, wherein the parasitic capacitance Co is between the scanning line Gate and the data line S, when the first scanning signal G1 is switched from high level to low level, the parasitic capacitance Co divides the voltage of the data signal, so that the voltage of the drain of the first thin film transistor T1 of the light-emitting module 10 decreases from the first voltage V1 to the second voltage V2 to generate the offset voltage V3, the acquisition module 20 is used to output the charging voltage to the compensation module 30 according to the offset voltage V3, and the compensation module 30 is used to output the compensation voltage to the light-emitting piece OLED according to the charging voltage, the compensation voltage is used to compensate the voltage drop of the light-emitting piece OLED caused by the parasitic capacitance Co, so that the light-emitting piece OLED charges normally to reach the theoretical brightness, avoiding the risk of uneven brightness and flicker, and improving the display effect.

[0039] Please refer to Figures 1 to 3 , the light-emitting module 10 further comprises a first thin film transistor T1, a second thin film transistor T2, a first storage capacitor Cs1 and a power line VDD, the source of the first thin film transistor T1 is electrically connected with the data line S, the gate of the first thin film transistor T1 is electrically connected with the scanning line Gate, the drain of the first thin film transistor T1 is electrically connected with the gate of the second thin film transistor T2, the drain of the second thin film transistor T2 is electrically connected with the anode of the light-emitting piece OLED, the cathode of the light-emitting piece OLED is connected with the ground terminal GND, the source of the second thin film transistor T2 is electrically connected with the power line VDD, one end of the first storage capacitor Cs1 is electrically connected with the gate of the second thin film transistor T2, and the other end is electrically connected with the source of the second thin film transistor T2, the acquisition module 20 is electrically connected with the drain of the first thin film transistor T1, the data line S, the power line VDD and the ground terminal GND, one end of the compensation module 30 is electrically connected with the anode of the light-emitting piece OLED, and the other end is connected with the ground terminal GND, wherein the power line VDD is used to input the power signal, and the drain of the first thin film transistor T1 is used to output the offset voltage V3 to the acquisition module 20.

[0040] Optionally, the parasitic capacitance Co outputs the offset voltage V3 to the acquisition module 20 through the drain of the first thin film transistor T1.

[0041] When the first scanning signal G1 is at a high level, the first thin film transistor T1 is opened, the first voltage V1 of the data signal is input to the first storage capacitor Cs1 and the gate of the second thin film transistor T2 through the first thin film transistor T1, so that the second thin film transistor T2 is opened and the first storage capacitor Cs1 is charged to the first voltage V1, and the power supply signal is input to the anode of the light emitting piece OLED through the second thin film transistor T2 to make the light emitting piece OLED normally emit light. When the first scanning signal G1 drops from the high level to the low level, the first thin film transistor T1 is closed, and due to the parasitic capacitance Co between the scanning line Gate and the data line S, the first voltage V1 of the storage capacitor is divided by the parasitic capacitance Co and drops to the second voltage V2, at this time, the opening degree of the second thin film transistor T2 is reduced, so that the brightness of the light emitting piece OLED is reduced. But because the acquisition module 20 and the compensation module 30 input the compensation voltage to the anode of the light emitting piece OLED according to the offset voltage V3, so that the light emitting piece OLED normally emits light.

[0042] By setting the source of the first thin film transistor T1 to be electrically connected with the data line S, the gate of the first thin film transistor T1 to be electrically connected with the scanning line Gate, the drain of the first thin film transistor T1 to be electrically connected with the gate of the second thin film transistor T2, the drain of the second thin film transistor T2 to be electrically connected with the anode of the light emitting piece OLED, the cathode of the light emitting piece OLED to be connected with the ground terminal GND, the source of the second thin film transistor T2 to be electrically connected with the power supply line VDD, one end of the first storage capacitor Cs1 to be electrically connected with the gate of the second thin film transistor T2, and the other end to be electrically connected with the source of the second thin film transistor T2, the acquisition module 20 to be electrically connected with the drain of the first thin film transistor T1, the data line S, the power supply line VDD and the ground terminal GND, one end of the compensation module 30 to be electrically connected with the anode of the light emitting piece OLED, and the other end to be connected with the ground terminal GND, wherein the power supply line VDD is used to input the power supply signal, the drain of the first thin film transistor T1 is used to output the offset voltage V3 to the acquisition module 20, so that the acquisition module 20 can receive the offset voltage V3 output by the light emitting module 10 and output the charging voltage to the compensation module 30 according to the offset voltage V3, and then the compensation module 30 outputs the compensation voltage to the light emitting piece OLED, so that the light emitting piece OLED is normally charged and reaches the theoretical brightness, avoiding the risk of uneven brightness and flicker, and improving the display effect.

[0043] Please refer to Figures 1 to 3The acquisition module 20 comprises a first operation module 21, a second operation module 22 and a third operation module 23. The first operation module 21 is electrically connected with the drain of the first thin film transistor T1, the data line S and the third operation module 23. The second operation module 22 is electrically connected with the power supply line VDD, the third operation module 23 and the ground terminal GND. The third operation module 23 is electrically connected with the compensation module 30. The first operation module 21 is configured to output a first intermediate signal to the third operation module 23 according to the offset voltage V3 and the data signal. The second operation module 22 is configured to output a second intermediate signal to the third operation module 23 according to the power supply signal and the light emitted by the light emitting element OLED. The third operation module 23 is configured to output the charging voltage.

[0044] Specifically, the first operation module 21 is configured to acquire the offset voltage V3 of the light emitting module 10 and output a first intermediate signal according to the first voltage V1 of the data signal. The second operation module 22 is configured to acquire the luminous brightness of the light emitting element OLED and output a second intermediate signal according to the first voltage V1 of the power supply signal. The third operation module 23 is configured to output a corresponding charging voltage according to the first intermediate signal and the second intermediate signal, so that the compensation module 30 is charged and outputs a compensation voltage to the light emitting element OLED.

[0045] By arranging the acquisition module 20 to comprise the first operation module 21, the second operation module 22 and the third operation module 23, and electrically connecting the first operation module 21 with the drain of the first thin film transistor T1, the data line S and the third operation module 23, electrically connecting the second operation module 22 with the power supply line VDD, the third operation module 23 and the ground terminal GND, and electrically connecting the third operation module 23 with the compensation module 30, wherein the first operation module 21 is configured to output a first intermediate signal to the third operation module 23 according to the offset voltage V3 and the data signal, the second operation module 22 is configured to output a second intermediate signal to the third operation module 23 according to the power supply signal and the light emitted by the light emitting element OLED, and the third operation module 23 is configured to output the charging voltage, the acquisition module 20 can output a corresponding charging voltage to the compensation module 30 according to the offset voltage V3, the first voltage V1 and the luminous intensity of the light emitting element OLED, so that the compensation module 30 can output a corresponding compensation voltage to the light emitting element OLED to make the light emitting element OLED charged normally and reach the theoretical brightness, thereby avoiding the risk of uneven brightness and flicker and improving the display effect.

[0046] Please refer to Figures 1 to 3The first operation module 21 comprises a first wire L1, a third thin film transistor T3, a first capacitor C1, a second capacitor C2, a first resistor R1, a second resistor R2, a third resistor R3 and an operational amplifier Q1. The source of the third thin film transistor T3 is electrically connected with the drain of the first thin film transistor T1. The gate of the third thin film transistor T3 is electrically connected with the first wire L1. The drain of the third thin film transistor T3 is electrically connected with one end of the first capacitor C1. The first resistor R1 is connected in series with the other end of the first capacitor C1 and the negative input end of the operational amplifier Q1. The second resistor R2 is connected in series with the negative input end of the operational amplifier Q1 and the output end of the operational amplifier Q1. The third resistor R3 is connected in series with the output end of the operational amplifier Q1 and the third operation module 23. One end of the second capacitor C2 is electrically connected with the positive input end of the operational amplifier Q1 and the data line S. The other end of the second capacitor C2 is electrically connected with the ground terminal GND. The first wire L1 is used for inputting the second scanning signal G2. The operational amplifier Q1 is used for outputting the first intermediate signal to the third operation module 23 according to the offset voltage V3 and the data signal. The voltage value of the first intermediate signal is V1+(R2 / R1)V3.

[0047] Specifically, when the second scanning signal G2 is high, the third thin film transistor T3 is opened. The light emitting module 10 inputs the offset voltage V3 to the negative input end of the operational amplifier Q1 through the third thin film transistor T3, the first capacitor C1 and the first resistor R1. The first voltage V1 is inputted to the positive input end of the operational amplifier Q1 by the data line S. The operational amplifier Q1 outputs the first intermediate signal according to the offset voltage V3 and the first voltage V1. The third operation module 23 further outputs the charging voltage according to the first intermediate signal and the second intermediate signal.

[0048] Optionally, the first operation module 21 can adjust the voltage value of the first intermediate signal by adjusting the resistance value of the first resistor R1 and the resistance value of the second resistor R2, so as to cooperate with different working states of the display driving circuit 100.

[0049] The first operation module 21 includes the first trace L1, the third thin film transistor T3, the first capacitor C1, the second capacitor C2, the first resistor R1, the second resistor R2, the third resistor R3, and the operational amplifier Q1. The source of the third thin film transistor T3 is electrically connected with the drain of the first thin film transistor T1. The gate of the third thin film transistor T3 is electrically connected with the first trace L1. The drain of the third thin film transistor T3 is electrically connected with one end of the first capacitor C1. The first resistor R1 is connected in series with the other end of the first capacitor C1 and the negative input end of the operational amplifier Q1. The second resistor R2 is connected in series with the negative input end of the operational amplifier Q1 and the output end of the operational amplifier Q1. The third resistor R3 is connected in series with the output end of the operational amplifier Q1 and the third operation module 23. One end of the second capacitor C2 is electrically connected with the positive input end of the operational amplifier Q1 and the data line S. The other end of the second capacitor C2 is electrically connected with the ground terminal GND. The first trace L1 is used for inputting the second scanning signal G2. The operational amplifier Q1 is used for outputting the first intermediate signal to the third operation module 23 according to the offset voltage V3 and the data signal. The first operation module 21 can output the first intermediate signal according to the offset voltage V3, so that the third operation module 23 can output the charging voltage according to the first intermediate signal and the second intermediate signal. The compensation module 30 can output the corresponding compensation voltage to the light emitting piece OLED, so that the light emitting piece OLED can be charged normally to achieve the theoretical brightness. The risk of uneven brightness and flicker is avoided, and the display effect is improved.

[0050] Please refer to Figures 1 to 3 The second operation module 22 includes the second trace L2, the fourth resistor R4, the fourth thin film transistor T4, the first crystal triode K1, the second crystal triode K2, the operational subtractor Q2, and the third capacitor C3. The first crystal triode K1 and the light emitting piece OLED constitute a photoelectric coupler. The fourth resistor R4 is connected in series with the source of the second thin film transistor T2 and the source of the fourth thin film transistor T4. The gate of the fourth thin film transistor T4 is electrically connected with the second trace L2. The drain of the fourth thin film transistor T4 is electrically connected with the collector of the first crystal triode K1, the collector of the second crystal triode K2, and the negative input end of the operational subtractor Q2. The emitter of the first crystal triode K1 is electrically connected with the base of the second crystal triode K2. The emitter of the second crystal triode K2 is electrically connected with the ground terminal GND. One end of the third capacitor C3 is electrically connected with the positive input end of the operational subtractor Q2. The other end of the third capacitor C3 is used for inputting the first voltage V1. The output end of the operational subtractor Q2 is electrically connected with the third operation module 23. The second trace L2 is used for inputting the third scanning signal G3. The first crystal triode K1 is used for outputting the photoelectric signal to the base of the second crystal triode K2 according to the light emitted by the light emitting piece OLED. The collector of the second crystal triode K2 is used for outputting the third intermediate signal to the operational subtractor Q2. The operational subtractor Q2 is used for outputting the second intermediate signal according to the third intermediate signal and the first voltage V1.

[0051] The voltage value of the third intermediate signal is βV1, the voltage value of the second intermediate signal is βV1-V1, and β is a positive number. Specifically, when the third scan signal G3 is high, the fourth thin film transistor T4 is turned on, the power supply line VDD outputs the power supply signal to the collector of the first crystal triode K1 through the fourth thin film transistor T4, and at the same time, the first crystal triode K1 outputs the photoelectric signal to the base of the second crystal triode K2 according to the light emitted by the light-emitting component OLED, so that the power supply signal is amplified by the first crystal triode K1 and the second crystal triode K2 and output as the third intermediate signal. Secondly, the operation subtractor Q2 outputs the second intermediate signal according to the first voltage V1 and the third intermediate signal, wherein the voltage of the third intermediate signal is greater than the first voltage V1, and the second intermediate signal is the difference between the third intermediate signal and the first voltage V1. The third operation module 23 can further output the charging voltage according to the first intermediate signal and the second intermediate signal.

[0052] By setting the second operation module 22 to include the second wire L2, the fourth resistor R4, the fourth thin film transistor T4, the first crystal triode K1, the second crystal triode K2, the operation subtractor Q2, and the third capacitor C3, the first crystal triode K1 and the light-emitting component OLED form a photoelectric coupler, the fourth resistor R4 is connected in series between the source of the second thin film transistor T2 and the source of the fourth thin film transistor T4, the gate of the fourth thin film transistor T4 is electrically connected to the second wire L2, the drain of the fourth thin film transistor T4 is electrically connected to the collector of the first crystal triode K1, the collector of the second crystal triode K2, and the negative input terminal of the operation subtractor Q2, the emitter of the first crystal triode K1 is electrically connected to the base of the second crystal triode K2, the emitter of the second crystal triode K2 is electrically connected to the ground GND, one end of the third capacitor C3 is electrically connected to the positive input terminal of the operation subtractor Q2, the other end of the third capacitor C3 is used to input the first voltage V1, and the output terminal of the operation subtractor Q2 is electrically connected to the third operation module 23. The second wire L2 is used to input the third scan signal G3, the first crystal triode K1 is used to output the photoelectric signal to the base of the second crystal triode K2 according to the light emitted by the light-emitting component OLED, the collector of the second crystal triode K2 is used to output the third intermediate signal to the operation subtractor Q2, and the operation subtractor Q2 is used to output the second intermediate signal according to the third intermediate signal and the first voltage V1, so that the second operation module 22 can output the second intermediate signal according to the light intensity of the light-emitting component OLED, the third operation module 23 can output the charging voltage according to the first intermediate signal and the second intermediate signal, and the compensation module 30 can output the corresponding compensation voltage to the light-emitting component OLED to make the light-emitting component OLED charge normally and reach the theoretical brightness, thereby avoiding the risks of uneven brightness and flicker and improving the display effect.

[0053] Please refer toFigures 1 to 3 The third operation module 23 comprises an operation adder Q3, a third resistor R3 is connected in series between an input end of the operation adder Q3 and an output end of the operation amplifier Q1, an output end of the operation subtractor Q2 is electrically connected to another input end of the operation adder Q3, and the operation adder Q3 is configured to output the charging voltage according to the first intermediate signal and the second intermediate signal.

[0054] The charging voltage is the sum of the first intermediate signal and the second intermediate signal, and specifically, the voltage of the charging voltage is βV1+(R2 / R1)(V1-V2).

[0055] By setting the third operation module 23 comprising the operation adder Q3, the third resistor R3 connected in series between the input end of the operation adder Q3 and the output end of the operation amplifier Q1, the output end of the operation subtractor Q2 electrically connected to the other input end of the operation adder Q3, and the operation adder Q3 configured to output the charging voltage according to the first intermediate signal and the second intermediate signal, the collection module 20 can output the corresponding charging voltage according to the offset voltage V3 and the light intensity of the light emitting element OLED, so that the compensation module 30 can output the corresponding compensation voltage to the light emitting element OLED to make the light emitting element OLED charge normally and reach the theoretical brightness, avoiding the risk of uneven brightness and flicker, and improving the display effect.

[0056] For reference Figures 1 to 3 The collection module 20 further comprises a stop module 24, the stop module 24 comprising an AND gate Q4 and a fifth thin film transistor T5, a drain of the fifth thin film transistor T5 is electrically connected to an input end of the operation adder Q3, a source of the fifth thin film transistor T5 is electrically connected to one end of the third resistor R3 away from the operation amplifier Q1, a gate of the fifth thin film transistor T5 is electrically connected to an output end of the AND gate Q4, one input end of the AND gate Q4 is electrically connected to an output end of the operation subtractor Q2, and the other input end of the AND gate Q4 is electrically connected to a positive input end of the operation subtractor Q2, wherein when the third intermediate signal is the same as the first voltage V1, the AND gate Q4 outputs a low level to make the fifth thin film transistor T5 closed.

[0057] Specifically, when the light emitting element OLED normally emits light, the third intermediate signal is the same as the first voltage V1, so that the voltage outputted by the operation subtractor Q2 to the AND gate Q4 and the operation adder Q3 is 0V (volt), and further the fifth thin film transistor T5 is closed to disconnect the electrical connection between the third operation module 23 and the first operation module 21, so that the charging voltage outputted by the operation adder Q3 is 0V, and at this time the compensation module 30 stops outputting the compensation voltage to the light emitting element OLED.

[0058] The stop module 24 includes an AND gate Q4 and a fifth thin film transistor T5. The drain of the fifth thin film transistor T5 is electrically connected to an input terminal of the operational amplifier Q3. The source of the fifth thin film transistor T5 is electrically connected to one end of the third resistor R3 away from the operational amplifier Q1. The gate of the fifth thin film transistor T5 is electrically connected to the output terminal of the AND gate Q4. One input terminal of the AND gate Q4 is electrically connected to the output terminal of the operational amplifier Q2. The other input terminal of the AND gate Q4 is electrically connected to the positive input terminal of the operational amplifier Q2. When the third intermediate signal is equal to the first voltage V1, the AND gate Q4 outputs a low level to turn off the fifth thin film transistor T5. When the light emitting element OLED is normally lighted or the light emitting element OLED receives the compensation voltage to the first voltage V1, the compensation process of the compensation module 30 can be ended by the stop module 24 to prevent overcharging of the light emitting element OLED.

[0059] Please refer to Figures 1 to 3 The compensation module 30 includes a second storage capacitor Cs2, a sixth thin film transistor T6, a fifth resistor R5 and a third trace L3. One end of the second storage capacitor Cs2 is electrically connected to the drain of the second thin film transistor T2. The other end of the second storage capacitor Cs2 is electrically connected to the drain of the sixth thin film transistor T6. One end of the fifth resistor R5 is electrically connected to the ground terminal GND. The other end of the fifth resistor R5 is electrically connected to the source of the sixth thin film transistor T6. The third trace L3 is electrically connected to the gate of the sixth thin film transistor T6. The third trace L3 is used to input a fourth scanning signal G4.

[0060] Specifically, when the fourth scanning signal G4 is a high level, the sixth thin film transistor T6 is turned on. The second storage capacitor Cs2 is grounded to make the voltage of the second storage capacitor Cs2 0V. When the fourth scanning signal G4 is a low level and the charging voltage is outputted from the collection module 20 to the second storage capacitor Cs2, the second storage capacitor Cs2 is charged and outputs the compensation voltage to the light emitting element OLED.

[0061] Optionally, the first thin film transistor T1 is turned off and the sixth thin film transistor T6 is turned on by setting the first scanning signal G1 to be a low level and the fourth scanning signal G4 to be a high level. Thus, the anode of the light emitting element OLED is grounded through the second storage capacitor Cs2 and the fifth resistor R5. At this time, the light emitting process of the light emitting element OLED is ended.

[0062] By setting the compensation module 30 comprising the second storage capacitor Cs2, the sixth thin film transistor T6, the fifth resistor R5 and the third wire L3, one end of the second storage capacitor Cs2 is electrically connected with the drain of the second thin film transistor T2, the other end is electrically connected with the drain of the sixth thin film transistor T6, one end of the fifth resistor R5 is electrically connected with the ground terminal GND, the other end is electrically connected with the source of the sixth thin film transistor T6, the third wire L3 is electrically connected with the gate of the sixth thin film transistor, and the third wire L3 is used for inputting the fourth scanning signal G4, so that the second storage capacitor Cs2 can be voltage reset before receiving the charging voltage, the accuracy of the compensation module 30 for outputting the compensation voltage to the light emitting element OLED is improved, and the insufficient charging of the light emitting element OLED or the overcharging of the light emitting element OLED is prevented.

[0063] Please refer to Figure 4 and Figure 5 The display driving circuit 100 comprises a display area DA and a non-display area NA, the non-display area NA is arranged around the display area DA, and the light emitting module 10 is arranged in the display area DA.

[0064] Optionally, the display driving circuit 100 further comprises a data driving unit SOC and a scanning driving unit GOA, the scanning driving unit GOA is electrically connected with the scanning line Gate, and the data driving unit SOC is electrically connected with the data line S, the scanning driving unit GOA is used for outputting the first scanning signal G1, and the data driving unit SOC is used for outputting the data signal. Optionally, the data driving unit SOC and the scanning driving unit GOA are both arranged in the non-display area NA.

[0065] Optionally, the display driving circuit 100 further comprises a first signal driving unit GDL1, a second signal driving unit GDL2 and a third signal driving unit GDL3, the first signal driving unit GDL1 is electrically connected with the first wire L1, the first signal driving unit GDL1 is used for outputting the second scanning signal G2 to the first wire L1, the second signal driving unit GDL2 is electrically connected with the second wire L2, the second signal driving unit GDL2 is used for outputting the third scanning signal G3 to the second wire L2, and the third signal driving unit GDL3 is electrically connected with the third wire L3, the third signal driving unit GDL3 is used for outputting the fourth scanning signal G4 to the third wire L3. Optionally, the first signal driving unit GDL1, the second signal driving unit GDL2 and the third signal driving unit GDL3 are all arranged in the non-display area NA.

[0066] Optionally, the display driving circuit 100 further comprises a first power supply PS1, the first power supply PS1 is electrically connected with the power line VDD of the light emitting module 10, and the first power supply PS1 is configured to output a power signal to the power line VDD. Optionally, the display driving circuit 100 further comprises a second power supply PS2, the second power supply PS2 is electrically connected with the third capacitor C3 of the second operation module 22, and the second power supply PS2 is configured to output a first voltage to the third capacitor C3. Optionally, the first power supply PS1 and the second power supply PS2 are both arranged in the non-display area NA.

[0067] Optionally, the display driving circuit 100 further comprises a driving circuit board 40, the data driving unit SOC, the first signal driving unit GDL1, the second signal driving unit GDL2, the third signal driving unit GDL3, the first power supply PS1 and the second power supply PS2 are all integrally arranged in the driving circuit board 40, so as to improve the integration of the display driving circuit 100. For example, please refer to Figure 4 and Figure 5 the data driving unit SOC and the second power supply PS2 are integrally arranged in the driving circuit board 40. For example, please refer to Figure 5 the first signal driving unit GDL1, the second signal driving unit GDL2 and the third signal driving unit GDL3 are integrally arranged in the driving circuit board 40.

[0068] Optionally, when at least part of the acquisition module 20 is arranged in the non-display area NA, the part of the acquisition module 20 located in the non-display area NA can be integrally arranged in the driving circuit board 40. Optionally, when at least part of the compensation module 30 is arranged in the non-display area NA, the part of the compensation module 30 located in the non-display area NA can be integrally arranged in the driving circuit board 40.

[0069] The acquisition module 20 is arranged in the display area DA or at least part of the non-display area will be explained in detail below.

[0070] In one embodiment, please refer to Figure 4 the acquisition module 20 is arranged in the display area DA. Specifically, the acquisition module 20 comprises the first operation module 21, the second operation module 22, the third operation module 23 and the stop module 24, and the first operation module 21, the second operation module 22, the third operation module 23, the stop module 24 and the compensation module 30 are all arranged in the display area DA. Optionally, the display area DA comprises an effective display area AA and a non-effective display area IA, the non-effective display area IA is arranged around the effective display area AA, the light emitting module 10 is arranged in the effective display area AA, and the acquisition module 20 and the compensation module 30 are both arranged in the non-effective display area IA.

[0071] By setting the collection module 20 entirely within the display area DA, the integration of the light-emitting module 10 and the collection module 20 is high, so that the collection module 20 can detect the real-time voltage or signal of the light-emitting module 10 at a close distance, reducing transmission loss or noise interference, improving data accuracy and compensation accuracy, and avoiding long wire delay.

[0072] In another embodiment, referring to Figure 5 , at least part of the collection module 20 is arranged in the non-display area NA. Optionally, part of the collection module 20 is located in the display area DA, and another part of the collection module 20 is located in the non-display area NA, or the collection module 20 is entirely located in the non-display area NA.

[0073] Optionally, the first operation module 21 includes a first wire L1, a third thin film transistor T3, a first capacitor C1, a second capacitor C2, a first resistor R1, a second resistor R2, a third resistor R3, and an operational amplifier Q1. When the first operation module 21 is entirely arranged in the non-display area NA, the first operation module 21 can be electrically connected to the drain of the first thin film transistor T1 and the data line S of the light-emitting module 10 one by one through different wires. Optionally, when part of the first operation module 21 is arranged in the non-display area NA, the part of the first operation module 21 directly connected to the light-emitting module 10 can be arranged in the display area DA, and the remaining part can be arranged in the non-display area NA. For example, the third thin film transistor T3 and / or the second capacitor C2 are arranged in the display area DA, and the first capacitor C1, the first resistor R1, the second resistor R2, the third resistor R3, and the operational amplifier Q1 are arranged in the non-display area NA.

[0074] Optionally, part of the second operation module 22 is arranged in the non-display area NA. Specifically, the second operation module 22 includes a second wire L2, a fourth resistor R4, a fourth thin film transistor T4, a first crystal triode K1, a second crystal triode K2, an operational subtractor Q2, and a third capacitor C3. Since the first crystal triode K1 and the light-emitting component OLED form a photoelectric coupler, the first crystal triode K1 is arranged in the display area DA, and at least one of the second wire L2, the fourth resistor R4, the fourth thin film transistor T4, the second crystal triode K2, the operational subtractor Q2, and the third capacitor C3 is arranged in the non-display area NA, without limitation.

[0075] Optionally, the third operation module 23 includes an operational adder Q3, which can be arranged in the non-display area NA or the display area DA, without limitation.

[0076] Optionally, the stop module 24 includes an AND gate Q4 and a fifth thin film transistor T5, both of which can be arranged in the display area DA, or both of which can be arranged in the non-display area NA, or one of which is arranged in the display area DA and the other is arranged in the non-display area NA, without limitation. In an example, both the AND gate Q4 and the fifth thin film transistor T5 are arranged in the non-display area NA. In an example, the AND gate Q4 is arranged in the non-display area NA and the fifth thin film transistor T5 is arranged in the display area DA.

[0077] By arranging at least part of the acquisition module 20 in the non-display area NA, the circuit occupation of the display area DA is reduced, the panel light transmittance and resolution are improved, and the space of the non-display area NA is relatively large, which is beneficial to the design and production of integrated circuits.

[0078] The following will explain in detail that the compensation module 30 is arranged entirely in the display area DA or at least partially in the non-display area.

[0079] In an embodiment, please refer to Figure 4 The compensation module 30 is arranged entirely in the display area DA. Specifically, the compensation module 30 includes a second storage capacitor Cs2, a sixth thin film transistor T6, a fifth resistor R5, and a third wire L3, all of which are arranged in the display area DA. In an example, the second storage capacitor Cs2, the sixth thin film transistor T6, the fifth resistor R5, and the third wire L3 are all arranged in the inactive display area IA.

[0080] By arranging the compensation module 30 entirely in the display area DA, the integration of the compensation module 30 and the light-emitting module 10 is high, the voltage fluctuation can be quickly responded, the display uniformity is improved, and the long-distance transmission of the compensation voltage is avoided, thereby reducing the risk of noise coupling.

[0081] In another embodiment, please refer to Figure 5 At least part of the compensation module 30 is arranged in the non-display area NA.

[0082] Optionally, when the compensation module 30 is arranged entirely in the non-display area NA, the compensation module 30 can be electrically connected to the light-emitting module 10 one by one through different wires and electrically connected to the acquisition module 20 through different wires. Optionally, when the compensation module 30 is partially arranged in the non-display area NA, the part of the compensation module 30 directly connected to the light-emitting module 10 can be arranged in the display area DA, and the remaining part can be arranged in the non-display area NA.

[0083] Optionally, when the second storage capacitor Cs2 is arranged in the display area DA, the first storage capacitor Cs1 and the second storage capacitor Cs2 can share the structure to improve the integration of the display driving circuit 100, reduce the transmission loss or noise interference, improve the data accuracy and compensation accuracy, and avoid long wire delay. Optionally, when the second storage capacitor Cs2 is arranged in the non-display area NA, the circuit occupation of the display area DA is reduced, and the panel light transmittance and resolution are improved.

[0084] Optionally, when the sixth thin film transistor T6 is arranged in the display area DA, the sixth thin film transistor T6 can be directly integrated in the light-emitting module 10, and long wire delay is avoided. Optionally, when the sixth thin film transistor T6 is arranged in the non-display area NA, the circuit occupation of the display area DA is reduced, and the panel light transmittance and resolution are improved. Optionally, when the fifth resistor R5 is arranged in the non-display area NA, the circuit occupation of the display area DA is reduced, and the panel light transmittance and resolution are improved.

[0085] By arranging at least part of the compensation module 30 in the non-display area NA, the circuit occupation of the display area DA is reduced, the panel light transmittance and resolution are improved, and the space of the non-display area NA is large, which is beneficial to the design and production of integrated circuits.

[0086] Please refer to Figure 4 and Figure 5 , the light-emitting module 10 is NM, and the NM light-emitting modules 10 are arranged in an N-row and M-column array, N≥1 and N is an integer, and M≥1 and M is an integer. Optionally, the scan driving unit GOA is N, and each scan driving unit GOA is electrically connected with the M light-emitting modules 10 in each row.

[0087] In an embodiment, please refer to Figure 4 , each light-emitting module 10 is correspondingly provided with one acquisition module 20 and one compensation module 30, the acquisition module 20 and the compensation module 30 are both NM, and the acquisition module 20 and the compensation module 30 are both located in the display area DA, which is beneficial to improve the integration, compensation response speed and display uniformity of the display driving circuit 100. Optionally, the acquisition module 20 and the compensation module 30 can also be at least partially arranged in the non-display area NA to reduce the circuit occupation of the display area DA.

[0088] Optionally, the first signal driving unit GDL1, the second signal driving unit GDL2 and the third signal driving unit GDL3 are all N, each first signal driving unit GDL1 is electrically connected with a plurality of first wires L1 in each row, each second signal driving unit GDL2 is electrically connected with a plurality of second wires L2 in each row, and each third signal driving unit GDL3 is electrically connected with a plurality of third wires L3 in each row.

[0089] In another embodiment, referring to Figure 5 , the plurality of light emitting modules 10 are electrically connected to the same acquisition module 20 and the same compensation module 30. For example, the plurality of light emitting modules 10 arranged in the same column and in sequence along the extension direction of the data line S are electrically connected to the same acquisition module 20 and the same compensation module 30. It should be noted that Figure 5 , only one acquisition module 20 and one compensation module 30 integrated in the drive circuit board 40 are shown, and the acquisition module 20 and the compensation module 30 are not shown in the part of the display area DA. The display drive circuit 100 further includes other groups of acquisition modules 20 and compensation modules 30 which are not shown. Alternatively, the plurality of light emitting modules 10 arranged on any adjacent rows and in sequence along the extension direction of the scan line Gate are electrically connected to the same acquisition module 20 and the same compensation module 30.

[0090] Alternatively, when the plurality of light emitting modules 10 are electrically connected to the same acquisition module 20 and the same compensation module 30, the acquisition module 20 and the compensation module 30 can be at least partially disposed in the non-display area NA to reduce the circuit occupation of the display area DA.

[0091] Alternatively, when the plurality of light emitting modules 10 are electrically connected to the same acquisition module 20 and the same compensation module 30, the acquisition module 20 is electrically connected to the plurality of light emitting modules 10 through a selection operator (not shown), which is used to receive the offset voltages V3 output by the plurality of light emitting modules 10 and output the average or median value of the plurality of offset voltages V3 to the compensation module 30, so that the compensation module 30 can output the same compensation voltage to the plurality of light emitting modules 10, which is beneficial to eliminate the abnormal fluctuations of individual light emitting modules 10 caused by process deviation or device aging, and improve the uniformity of overall brightness and chrominance.

[0092] By electrically connecting the plurality of light emitting modules 10 to the same acquisition module 20 and the same compensation module 30, the circuit size of the display drive circuit 100 is smaller, which is beneficial to reduce production cost and improve pixels.

[0093] Referring to Figures 1 to 3 , the present application also provides a driving method applied to the display drive circuit 100 in the embodiments of the present application. The driving method sequentially passes through a first period t1, a second period t2, a third period t3, a fourth period t4, a fifth period t5 and a sixth period t6 in one driving period T. The driving method comprises:

[0094] In one driving period T, the data line S always inputs a data signal, the first power supply PS1 always inputs a power supply signal to the power supply line VDD, and the second power supply PS2 always inputs a first voltage V1 to the second capacitor C2 and the third capacitor C3.

[0095] In the first time period t1, the scan line Gate inputs the first scan signal G1 of high level to the gate of the first thin film transistor T1, the data line S inputs the data signal of the first voltage V1 to the source of the first thin film transistor T1, the first wire L1 inputs the second scan signal G2 of low level to the gate of the third thin film transistor T3, the second wire L2 inputs the third scan signal G3 of low level to the gate of the fourth thin film transistor T4, and the third wire L3 inputs the fourth scan signal G4 of low level to the gate of the sixth thin film transistor T6.

[0096] In the second time period t2, the scan line Gate inputs the first scan signal G1 of high level to the gate of the first thin film transistor T1, the first wire L1 inputs the second scan signal G2 of low level to the gate of the third thin film transistor T3, the second wire L2 inputs the third scan signal G3 of low level to the gate of the fourth thin film transistor T4, and the third wire L3 inputs the fourth scan signal G4 of high level to the gate of the sixth thin film transistor T6.

[0097] In the third time period t3, the scan line Gate inputs the first scan signal G1 of high level to the gate of the first thin film transistor T1, the first wire L1 inputs the second scan signal G2 of low level to the gate of the third thin film transistor T3, the second wire L2 inputs the third scan signal G3 of low level to the gate of the fourth thin film transistor T4, and the third wire L3 inputs the fourth scan signal G4 of low level to the gate of the sixth thin film transistor T6.

[0098] In the fourth time period t4, the scan line Gate inputs the first scan signal G1 of high level to the gate of the first thin film transistor T1, the first wire L1 inputs the second scan signal G2 of high level to the gate of the third thin film transistor T3, the second wire L2 inputs the third scan signal G3 of low level to the gate of the fourth thin film transistor T4, and the third wire L3 inputs the fourth scan signal G4 of low level to the gate of the sixth thin film transistor T6.

[0099] In the fifth time period t5, the scan line Gate inputs the first scan signal G1 of low level to the gate of the first thin film transistor T1, the first wire L1 inputs the second scan signal G2 of high level to the gate of the third thin film transistor T3, the second wire L2 inputs the third scan signal G3 of low level to the gate of the fourth thin film transistor T4, and the third wire L3 inputs the fourth scan signal G4 of low level to the gate of the sixth thin film transistor T6.

[0100] In the sixth time period t6, the scan line Gate inputs the first scan signal G1 of low level to the gate of the first thin film transistor T1, the first walk line L1 inputs the second scan signal G2 of high level to the gate of the third thin film transistor T3, the second walk line L2 inputs the third scan signal G3 of high level to the gate of the fourth thin film transistor T4, and the third walk line L3 inputs the fourth scan signal G4 of low level to the gate of the sixth thin film transistor T6.

[0101] Specifically, the first time period t1 includes a charging time period and a light emitting time period, in the charging time period, the first storage capacitor Cs1 is charged and the voltage of the first storage capacitor Cs1 is charged from 0V to the first voltage V1, the second thin film transistor T2 is closed, and the light emitting part OLED does not emit light. In the light emitting time period, the first storage capacitor Cs1 is charged, the second thin film transistor T2 is opened, and the light emitting part OLED emits light.

[0102] In the second time period t2, the voltage of the first storage capacitor Cs1 is the first voltage V1, and the voltage of the second storage capacitor Cs2 is 0V by grounding the second storage capacitor Cs2 through the fifth resistor R5.

[0103] The working state of the light emitting part OLED in the third time period t3 and the fourth time period t4 is the same as that in the light emitting time period of the first time period t1. In the fourth time period t4, the second scan voltage is switched from low level to high level, and the third thin film transistor T3 is opened.

[0104] In the sixth time period t6, the third thin film transistor T3, the fourth thin film transistor T4 and the fifth thin film transistor T5 are all opened, the offset voltage V3 enters the first operation module 21 through the third thin film transistor T3, the first operation module 21 outputs the first intermediate signal to the third operation module 23, the power supply signal enters the second operation module 22 through the fourth thin film transistor T4, the second operation module 22 also outputs the second intermediate signal to the third operation module 23 according to the light emitting intensity of the light emitting part OLED, the third operation module 23 outputs the charging voltage to the second storage capacitor Cs2 according to the first intermediate signal and the second intermediate signal to charge the second storage capacitor Cs2, and the second storage capacitor Cs2 outputs the compensation voltage to the light emitting part OLED to make the light emitting part OLED emit light normally.

[0105] Please refer to Figure 3 and Figure 4 The application further provides a display panel, which comprises a cathode layer and the display driving circuit 100 in the embodiment of the application, and the cathode layer constitutes the ground end GND of the display driving circuit 100. The display panel provided by the application realizes uniform display brightness, is not prone to flicker, and improves the display effect by arranging the display driving circuit 100 in the embodiment of the application.

[0106] In the description of the embodiments of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like, indicate the orientation or positional relationship based on the drawings described in the application, and are only for the purpose of facilitating the description of the application and simplifying the description, and therefore cannot be understood as indicating or implying that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the application.

[0107] The above disclosure is only a preferred embodiment of the present application, and of course cannot limit the scope of the patent rights of the present application, and those of ordinary skill in the art can understand that the implementation of all or part of the above-mentioned processes, and the equivalent changes made according to the claims of the present application, still belong to the scope covered by the present application.

Claims

1. A display drive circuit, characterized by comprising: The application relates to a display device and a display method thereof. The display device comprises a light-emitting module, a collection module and a compensation module. The light-emitting module comprises a scanning line, a data line, a first thin film transistor, a second thin film transistor, a first storage capacitor, a power supply line and a light-emitting element, the source electrode of the first thin film transistor is electrically connected with the data line, the gate electrode of the first thin film transistor is electrically connected with the scanning line, the drain electrode of the first thin film transistor is electrically connected with the gate electrode of the second thin film transistor, the source electrode of the second thin film transistor is electrically connected with the power supply line, the drain electrode of the second thin film transistor is electrically connected with the anode of the light-emitting element, the cathode of the light-emitting element is connected with a ground terminal, one end of the first storage capacitor is electrically connected with the gate electrode of the second thin film transistor, and the other end of the first storage capacitor is electrically connected with the source electrode of the second thin film transistor, the scanning line is used for inputting a first scanning signal, the data line is used for inputting a data signal, the power supply line is used for inputting a power supply signal, and the light-emitting element is used for emitting light according to the first scanning signal and the data signal. The collection module is electrically connected with the drain electrode of the first thin film transistor, the data line, the power supply line and the ground terminal. The compensation module is electrically connected with the anode of the light-emitting element and the collection module.

2. The display driving circuit according to claim 1, wherein The scanning line and the data line have a parasitic capacitor, when the first scanning signal is switched from a high level to a low level, the parasitic capacitor divides the data signal to make the voltage of the drain electrode of the first thin film transistor drop from a first voltage to a second voltage to generate an offset voltage, the drain electrode of the first thin film transistor is used for outputting the offset voltage to the collection module, the collection module is used for outputting a charging voltage to the compensation module according to the offset voltage, the compensation module is used for outputting a compensation voltage to the light-emitting element according to the charging voltage, and the compensation voltage is used for compensating the voltage drop of the light-emitting element caused by the parasitic capacitor. The collection module comprises a first operation module, a second operation module and a third operation module, the first operation module is electrically connected with the drain electrode of the first thin film transistor, the data line and the third operation module, the second operation module is electrically connected with the power supply line, the third operation module and the ground terminal, and the third operation module is electrically connected with the compensation module. The first operation module is used for outputting a first intermediate signal to the third operation module according to the offset voltage and the data signal, the second operation module is used for outputting a second intermediate signal to the third operation module according to the power supply signal and the light emitted by the light-emitting element, and the third operation module is used for outputting the charging voltage.

3. The display driving circuit according to claim 2, wherein The first operation module comprises a first trace, a third thin film transistor, a first capacitor, a second capacitor, a first resistor, a second resistor, a third resistor and an operational amplifier, the source of the third thin film transistor is electrically connected with the drain of the first thin film transistor, the gate of the third thin film transistor is electrically connected with the first trace, the drain of the third thin film transistor is electrically connected with one end of the first capacitor, the first resistor is connected with the other end of the first capacitor and the negative input end of the operational amplifier in series, the second resistor is connected with the negative input end of the operational amplifier and the output end of the operational amplifier in series, the third resistor is connected with the output end of the operational amplifier and the third operation module in series, one end of the second capacitor is electrically connected with the positive input end of the operational amplifier and the data line, and the other end is electrically connected with a grounding end; The first trace is used for inputting a second scanning signal, and the operational amplifier is used for outputting the first intermediate signal to the third operation module according to the offset voltage and the data signal.

4. The display driving circuit according to claim 3, wherein The second operation module comprises a second trace, a fourth resistor, a fourth thin film transistor, a first crystal triode, a second crystal triode, an operational subtractor and a third capacitor, the first crystal triode and the light emitting piece constitute a photoelectric coupler, the fourth resistor is connected with the source of the second thin film transistor and the source of the fourth thin film transistor in series, the gate of the fourth thin film transistor is electrically connected with the second trace, the drain of the fourth thin film transistor is electrically connected with the collector of the first crystal triode, the collector of the second crystal triode and the negative input end of the operational subtractor, the emitter of the first crystal triode is electrically connected with the base of the second crystal triode, the emitter of the second crystal triode is electrically connected with a grounding end, one end of the third capacitor is electrically connected with the positive input end of the operational subtractor, the other end of the third capacitor is used for inputting the first voltage, and the output end of the operational subtractor is electrically connected with the third operation module. The second trace is used for inputting a third scanning signal, the first crystal triode is used for outputting a photoelectric signal to the base of the second crystal triode according to the light emitted by the light emitting piece, the collector of the second crystal triode is used for outputting a third intermediate signal to the operational subtractor, and the operational subtractor is used for outputting a second intermediate signal according to the third intermediate signal and the first voltage.

5. The display driving circuit according to claim 4, wherein The third operation module comprises an operational adder, the third resistor is connected with one input end of the operational adder and the output end of the operational amplifier in series, the output end of the operational subtractor is electrically connected with the other input end of the operational adder, and the operational adder is used for outputting the charging voltage according to the first intermediate signal and the second intermediate signal.

6. The display driving circuit according to claim 5, wherein, The acquisition module further comprises a stop module, the stop module comprises an AND gate and a fifth thin film transistor, the drain electrode of the fifth thin film transistor is electrically connected with an input end of the operational amplifier, the source electrode of the fifth thin film transistor is electrically connected with one end of the third resistor away from the operational amplifier, the gate electrode of the fifth thin film transistor is electrically connected with the output end of the AND gate, one input end of the AND gate is electrically connected with the output end of the operational subtractor, and the other input end of the AND gate is electrically connected with the positive input end of the operational subtractor. When the third intermediate signal is the same as the first voltage, the AND gate outputs a low level to make the fifth thin film transistor close.

7. The display driving circuit according to claim 1, wherein The compensation module comprises a second storage capacitor, a sixth thin film transistor, a fifth resistor and a third trace, one end of the second storage capacitor is electrically connected with the drain electrode of the second thin film transistor, the other end is electrically connected with the drain electrode of the sixth thin film transistor, one end of the fifth resistor is electrically connected with a ground end, the other end is electrically connected with the source electrode of the sixth thin film transistor, and the third trace is electrically connected with the gate electrode of the sixth thin film transistor, and the third trace is used for inputting a fourth scanning signal.

8. The display driving circuit according to any one of claims 1 to 7, wherein The display driving circuit comprises a display area and a non-display area, the non-display area is arranged around the display area, and the light-emitting module is arranged in the display area. The acquisition module is wholly arranged in the display area, or at least part of the acquisition module is arranged in the non-display area. The compensation module is wholly arranged in the display area, or at least part of the compensation module is arranged in the non-display area.

9. A display panel, characterized by, The display driving circuit comprises a cathode layer and the display driving circuit as claimed in any one of claims 1-8, and the cathode layer constitutes a ground end of the display driving circuit.

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