Source driving circuit control method, display panel driving circuit and display device

Abstract

The present invention proposes a control method for a source driver circuit, a display panel driver circuit, and a display device. In the control method for the source driver circuit, after the corresponding frame driving is completed, the first charge sharing circuit in the source driver circuit is controlled to perform charge sharing, and the grayscale voltage signals of the two data lines are respectively compared with the polarity reference voltage. When one of the voltages is greater than the polarity reference voltage, in the next frame display image, the input selection switch and the output selection switch in the source driver circuit are controlled to switch accordingly, and a positive polarity grayscale voltage signal is output to the data line. When the voltage is less than the polarity reference voltage, in the next frame display image, the input selection switch and the output selection switch in the source driver circuit are controlled to switch accordingly, so as to output a negative polarity grayscale voltage signal to the data line, thereby reducing the size of the charging cross-voltage and the charging charge, thereby reducing the driving power consumption.

Description

Technical Field

[0001] The present invention belongs to the technical field of display panels, and in particular relates to a control method for a source drive circuit, a display panel drive circuit, and a display device. Background Art

[0002] TFT-LCD (Thin Film Transistor Liquid Crystal Display) is one of the main types of flat panel displays and has become a key display platform in modern IT and video products. Liquid crystals have the characteristic of maintaining torque in an electric field. To prevent liquid crystal polarization problems, polarity inversion control is performed during the driving process. The grayscale voltage signal input in the next frame has the opposite polarity to the grayscale voltage signal in the current frame.

[0003] Furthermore, in order to reduce the power consumption of the display device, after a frame of picture is displayed, two adjacent data lines of different polarities are short-circuited so that the charges of different polarities in the data lines cancel each other out, thereby achieving charge sharing. When the polarity is reversed in the next frame, the pixel unit is charged starting from the potential with the middle polarity, thereby reducing the charging voltage and reducing the power consumption of the display device.

[0004] Due to the limitations of past hardware performance, the refresh rate of display panels is mostly around 30Hz to 60Hz. In low refresh rate scenarios, polarity reversal is required in each frame. With the development of technology, current hardware performance can support display panels to reach a refresh rate of more than 120Hz. In high refresh rate scenarios, polarity reversal in each frame affects refresh efficiency, and because the voltage difference before and after charging is large during polarity reversal, power consumption increases. Summary of the Invention

[0005] The object of the present invention is to provide a control method for a source driving circuit, aiming to solve the problem of high power consumption in a traditional polarity inversion method at a high refresh rate.

[0006] A first aspect of an embodiment of the present invention provides a control method for a source driver circuit. The source driver circuit includes multiple driver units, each of which is connected one-to-one to multiple groups of data lines of a display panel. Each group of data lines includes two adjacent odd-numbered column data lines and two adjacent even-numbered column data lines. The driver units include at least a positive polarity digital-to-analog converter, a negative polarity digital-to-analog converter, an input selection switch, an output selection switch, and a first charge sharing circuit.

[0007] The control method of the source driving circuit includes:

[0008] After the i-th frame ends, outputting a first channel selection signal to control the first charge sharing circuit to perform charge sharing on the two data lines of the corresponding group, and comparing the voltage signals on the two data lines after charge sharing with the polarity reference voltage respectively;

[0009] When the grayscale voltage signal of a corresponding data line of each group is greater than the polarity reference voltage, in the (i+1)th frame, the first channel selection signal and the second channel selection signal are output successively to control the input selection switch and the output selection switch to switch to the first switch state and the second switch state successively, so as to convert the digital grayscale voltage signal input from the odd input terminal and / or the even input terminal into a positive polarity grayscale voltage signal through the positive polarity digital-to-analog converter and transmit the converted signal to the corresponding data line;

[0010] When the grayscale voltage signal of a data line corresponding to each group is less than the polarity reference voltage, in the (i+1)th frame, the first channel selection signal and the second channel selection signal are output successively to control the input selection switch and the output selection switch to switch to the third switch state and the fourth switch state successively, so as to convert the digital grayscale voltage signal inputted from the odd input terminal and / or the even input terminal into a negative polarity grayscale voltage signal through the negative polarity digital-to-analog converter and transmit it to the corresponding data line.

[0011] Optionally, the control method of the source driver circuit further includes:

[0012] In the first frame, the output polarity switching control signal controls the input selection switch and the output selection switch to switch to the fifth switch state, so as to convert the digital grayscale voltage signals input from the odd input terminal and the even input terminal into positive polarity grayscale voltage signals and negative polarity grayscale voltage signals through the positive polarity digital-to-analog converter and the negative polarity digital-to-analog converter, respectively, and transmit them to the odd column data lines and the even column data lines;

[0013] Every n1 frames, the output polarity switching control signal controls the input selection switch and the output selection switch to switch between the sixth switch state and the fifth switch state, so as to switch the polarity of the grayscale voltage signals of the two data lines of each group and the polarities of the two adjacent data lines of each group are opposite, where n1 is a positive integer.

[0014] Optionally, the source driving circuit further includes a plurality of second charge sharing circuits, each of the second charge sharing circuits being connected between two adjacent odd-numbered column data lines and even-numbered column data lines of two adjacent driving units;

[0015] The control method of the source driving circuit further includes:

[0016] After the (i+1)th frame ends, outputting a second channel selection signal to control the second charge sharing circuit to perform charge sharing on the two correspondingly connected data lines, and comparing the voltage signals on the two data lines after charge sharing with the polarity reference voltage respectively;

[0017] When the grayscale voltage signal of a corresponding data line is greater than the polarity reference voltage, in the (i+2)th frame, the first channel selection signal and the second channel selection signal are output sequentially to control the input selection switch and the output selection switch to switch to the first switch state and the second switch state respectively, so as to convert the digital grayscale voltage signal input from the odd input terminal and / or the even input terminal into a positive polarity grayscale voltage signal through the positive polarity digital-to-analog converter and transmit the converted signal to the corresponding data line;

[0018] When the grayscale voltage signal of a corresponding data line of each group is less than the polarity reference voltage, in the (i+2)th frame, the first channel selection signal and the second channel selection signal are output successively to control the input selection switch and the output selection switch to switch to the third switch state and the fourth switch state successively, so as to convert the digital grayscale voltage signal inputted from the odd input terminal and / or the even input terminal into a negative polarity grayscale voltage signal through the negative polarity digital-to-analog converter and transmit it to the corresponding data line.

[0019] Optionally, after the corresponding frame ends and before the grayscale voltage signals of the corresponding two data lines are charged and shared, the method further includes:

[0020] Acquire the grayscale voltage signals of the next frame corresponding to the two data lines, and compare the voltage difference between the grayscale voltage signals of adjacent frames of the two data lines in each group with a preset difference;

[0021] When the voltage difference between the two corresponding data lines is less than the preset difference, charge sharing is not performed, and the grayscale voltage signal of the next frame is output to the two corresponding data lines;

[0022] When the voltage difference corresponding to at least one data line is greater than a preset difference, the grayscale voltage signals corresponding to the two data lines are charge-shared.

[0023] Optionally, the preset difference is a difference between the grayscale voltage signal of the next frame and the polarity reference voltage.

[0024] A second aspect of an embodiment of the present invention provides a display panel driving circuit, comprising a connected timing control circuit and a source driving circuit, the source driving circuit comprising a plurality of driving units, the plurality of driving units being connected one-to-one to a plurality of groups of data lines of the display panel, each group of data lines comprising two adjacent odd-numbered data lines and two adjacent even-numbered data lines, the driving units comprising at least a positive polarity digital-to-analog converter, a negative polarity digital-to-analog converter, an input selection switch, an output selection switch, and a first charge sharing circuit, the first charge sharing circuit being connected between two adjacent odd-numbered data lines and two adjacent even-numbered data lines in each group;

[0025] The source driving circuit further includes a plurality of second charge sharing circuits, each of which is connected between two adjacent odd-numbered column data lines and even-numbered column data lines of two adjacent driving units;

[0026] The timing control circuit is used to implement the control method of the source driving circuit as described above.

[0027] Optionally, the source driver circuit further includes:

[0028] The first charge sharing circuit includes a first switch, a second switch, and a third switch, wherein a first end of the first switch is connected to a first output end of an output selection switch of a driving unit, a first end of the second switch is connected to a second output end of an output selection switch of a driving unit, a second end of the first switch and a first end of the third switch are connected to odd-numbered columns of data lines in a corresponding group of data lines, and a second end of the second switch and a second end of the third switch are connected to even-numbered columns of data lines in a corresponding group of data lines;

[0029] The second charge sharing circuit includes a fourth switch connected between two adjacent odd-numbered column data lines and an even-numbered column data line of two adjacent driving units.

[0030] Optionally, the timing control circuit includes a multi-channel comparison circuit and a timing controller;

[0031] Each comparison circuit is connected to the two data lines and the source driver circuit of each group, and the comparison circuit is used to compare the voltage signals of the two data lines with the polarity reference voltage respectively, and output a comparison signal to control the source driver circuit to output a grayscale voltage signal of corresponding polarity to the two adjacent data lines of each group;

[0032] The timing controller is connected to the multi-channel comparison circuit and the source driving circuit respectively, and is used to obtain the comparison signal and control the source driving circuit to implement the control method of the source driving circuit as described above.

[0033] Optionally, the comparison circuit includes a first comparator and a second comparator;

[0034] The first comparator is connected to one of the data lines of each group, and the second comparator is connected to the other data line of each group. The reference voltage ends of the first comparator and the second comparator also input polarity reference voltages, and the output ends of the first comparator and the second comparator are connected to the timing controller.

[0035] A third aspect of the embodiments of the present invention provides a display device, including a display panel and the above display panel driving circuit, wherein the display panel is connected to the display panel driving circuit.

[0036] Compared with the prior art, the embodiments of the present invention have the following beneficial effects: in the above-mentioned control method of the source driving circuit, after the corresponding frame driving is completed, the first charge sharing circuit in the source driving circuit is controlled to perform charge sharing, and the grayscale voltage signals of the two data lines are respectively compared with the polarity reference voltage. When one of the voltages is greater than the polarity reference voltage, in the next frame display picture, the input selection switch and the output selection switch in the source driving circuit are controlled to switch accordingly, and a positive polarity grayscale voltage signal is output to the data line, thereby realizing the same polarity voltage switching from the neutralization voltage to the positive polarity grayscale voltage signal, reducing the size of the charging cross voltage and the charging charge, and reducing the driving power consumption; and when the voltage is less than the polarity reference voltage, in the next frame display picture, the input selection switch and the output selection switch in the source driving circuit are controlled to switch accordingly to output a negative polarity grayscale voltage signal to the data line, thereby realizing the same polarity voltage switching from the neutralization voltage to the negative polarity grayscale voltage signal, reducing the size of the charging cross voltage and the charging charge, and reducing the driving power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments or descriptions of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0038] Figure 1 A schematic structural diagram of a display panel provided in Embodiment 1 and Embodiment 5 of the present invention;

[0039] Figure 2 A schematic structural diagram of the source driver circuit provided in the first and fifth embodiments of the present invention;

[0040] Figure 3 A circuit diagram of a digital-to-analog converter provided in Embodiments 1 and 5 of the present invention;

[0041] Figure 4 A circuit diagram of the selection switch provided in Embodiments 1 and 5 of the present invention;

[0042] Figure 5 A circuit diagram of a first charge sharing circuit provided in Embodiment 1 and Embodiment 5 of the present invention;

[0043] Figure 6 A schematic flow chart of a method for controlling a source driver circuit according to a first embodiment of the present invention;

[0044] Figure 7 A schematic flow chart of a control method for a source driver circuit according to a second embodiment of the present invention;

[0045] Figure 8 A schematic structural diagram of a source driver circuit provided in a third embodiment of the present invention;

[0046] Figure 9 A circuit diagram of a first charge sharing circuit and a second charge sharing circuit provided in Embodiment 3 of the present invention;

[0047] Figure 10 A timing diagram of a first channel selection signal and a second channel selection signal provided in the third embodiment of the present invention;

[0048] Figure 11 A schematic flow chart of a control method for a source driver circuit according to a third embodiment of the present invention;

[0049] Figure 12 A schematic flow chart of a method for controlling a source driver circuit according to a fourth embodiment of the present invention;

[0050] Figure 13 A schematic diagram of a first structure of a display panel driving circuit and a display device provided in the fifth and sixth embodiments of the present invention;

[0051] Figure 14 A second structural diagram of a display panel driving circuit and a display device provided in the fifth embodiment of the present invention;

[0052] Figure 15 This is a circuit diagram of a comparison circuit provided in Embodiment 5 of the present invention.

[0053] Among them, the reference numerals in the figures are:

[0054] 1. Display panel; 2. Display panel driving circuit; 10. Pixel unit; 100. Timing control circuit; 200. Source driving circuit; 300. Gate driving circuit; 110. Timing controller; 120. Comparison circuit; 210. Driving unit; 211. Input selection switch; 212. Positive polarity digital-to-analog converter; 213. Negative polarity digital-to-analog converter; 214. Output selection switch; 215. First charge sharing circuit; 220. Second charge sharing circuit;

[0055] U1, first comparator; U2, second comparator; TP1, first channel selection signal; TP2, second channel selection signal; S1, first data line; S2, second data line; K1, first switch; K2, second switch; K3, third switch; K4, fourth switch; K11, first sub-switch; K12, second sub-switch; K13, third sub-switch; K14, fourth sub-switch; OP1, signal amplifier. DETAILED DESCRIPTION

[0056] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0057] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature identified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0058] Example 1

[0059] A first aspect of an embodiment of the present invention provides a control method for a source driver circuit 200 .

[0060] The source driving circuit 200 is used to output multiple grayscale voltage signals to multiple columns of data lines and pixel units 10 of the display panel 1. Figure 1 As shown, the display panel 1 includes a plurality of data lines, a plurality of scan lines, and a plurality of pixel units 10 arranged in an array. The pixel unit 10 is connected to one data line and one scan line respectively. The plurality of columns of data lines are divided into a plurality of groups in turn. Each group of data lines includes two adjacent odd-numbered column data lines and two adjacent even-numbered column data lines. The display panel 1 is connected to the source driver circuit 200 through the data lines. Figure 2 and Figure 13 As shown, the source driving circuit 200 includes multiple driving units 210, which are connected one by one to multiple groups of data lines of the display panel 1. The driving unit 210 includes at least a positive polarity digital-to-analog converter 212, a negative polarity digital-to-analog converter 213, an input selection switch 211, an output selection switch 214 and a first charge sharing circuit 215.

[0061] The first input terminal of the input selection switch 211 constitutes the odd-numbered column input terminal Y2n-1 of the driving unit 210, the second input terminal of the input selection switch 211 constitutes the even-numbered column input terminal Y2n of the driving unit 210, the first output terminal of the input selection switch 211 is connected to the input terminal of the positive polarity digital-to-analog converter 212, the second output terminal of the input selection switch 211 is connected to the input terminal of the negative polarity digital-to-analog converter 213, the output terminal of the positive polarity digital-to-analog converter 212 is connected to the first input terminal of the output selection switch 214, the output terminal of the negative polarity digital-to-analog converter 213 is connected to the second input terminal of the output selection switch 214, the first output terminal of the output selection switch 214 is connected to the first input terminal of the first charge sharing circuit 215, the second output terminal of the output selection switch 214 is connected to the second input terminal of the first charge sharing circuit 215, the first output terminal of the first charge sharing circuit 215 is connected to the odd-numbered column data lines in each group of data lines, and the second output terminal of the first charge sharing circuit 215 is connected to the even-numbered column data lines in each group of data lines.

[0062] Among them, the positive polarity digital-to-analog converter 212 is used to convert the input digital data signal into a positive polarity grayscale voltage signal, and the negative polarity digital-to-analog converter 213 is used to convert the input digital data signal into a negative polarity grayscale voltage signal. The positive polarity refers to a voltage signal greater than the polarity reference voltage, and the negative polarity refers to a grayscale voltage signal less than the polarity reference voltage. For example, the polarity reference voltage is 7.5V, and the voltage greater than 7.5V is a positive polarity grayscale voltage signal, and the voltage less than 7.5V is a negative polarity grayscale voltage signal. The interval range of the positive polarity grayscale voltage signal can be 8V~15V, and the voltage range of the negative polarity grayscale voltage signal can be 0.2V~6V.

[0063] The digital-to-analog converter includes a plurality of gate MOS transistors, which are composed of NMOS transistors that are turned on corresponding to high level and PMOS transistors that are turned on corresponding to low level. Figure 4 As shown, taking a 3-bit digital-to-analog converter as an example, the digital data signal D2D1D0 input to the digital-to-analog converter is 011, then / D2 / D1 / D0 is 100. According to the 8421 encoding principle, the output of the selection switch is the V3 voltage value, and the V3 voltage value can be amplified and output by the back-end signal amplifier OP1 to obtain the V3 grayscale voltage. The grayscale voltage corresponds to the analog-to-digital grayscale voltage signal corresponding to the digital signal 011.

[0064] The input selection switch 211 can connect its own first input terminal and second input terminal to its own first output terminal and second output terminal according to the received control signal, and the output selection switch 214 can connect its own first input terminal and second input terminal to its own first output terminal and second output terminal according to the received control signal.

[0065] For example, assuming that it is initially necessary to output a positive polarity grayscale voltage signal to the odd-numbered column data lines in the corresponding group, and output a negative polarity grayscale voltage signal to the even-numbered column data lines in the same group, at this time, the first digital data signal is input to the first input terminal of the input selection switch 211 and the second digital data signal is input to the second input terminal of the input selection switch 211, and a control signal can be output to control the input selection switch 211 to connect its own first input terminal and first output terminal, and to control the input selection switch 211 to connect its own second input terminal and second output terminal, the first digital data signal is transmitted to the positive polarity digital-to-analog converter 212 through the input selection switch 211, and is converted into a positive polarity digital-to-analog converter 212. The second digital data signal is transmitted to the negative polarity digital-to-analog converter 213 via the input selection switch 211 and converted into a negative polarity grayscale voltage signal. While controlling the input selection switch 211, the output selection switch 214 is controlled to connect its own first input terminal and first output terminal, as well as its own second input terminal and second output terminal. The positive polarity grayscale voltage signal is transmitted to the odd column data line via the output selection switch 214 and the first charge sharing circuit 215, and the negative polarity grayscale voltage signal is transmitted to the even column data line via the output selection switch 214 and the first charge sharing circuit 215, thereby completing the output of the grayscale voltage of the current frame.

[0066] And in the next frame, assuming that the grayscale voltage polarity of the odd-numbered column data lines and the even-numbered column data lines needs to be switched, at this time, the first digital data signal corresponding to the next frame is input to the first input end of the input selection switch 211 and the second digital data signal corresponding to the next frame is input to the second input end of the input selection switch 211, and the control signal can be output to control the input selection switch 211 to connect its own first input end and second output end, and control the input selection switch 211 to connect its own second input end and first output end, the first digital data signal is transmitted to the negative polarity digital-to-analog converter 213 through the input selection switch 211, and is converted into a negative polarity grayscale voltage signal, and the second digital data signal is output to the negative polarity digital-to-analog converter 213. The positive polarity digital-to-analog converter 212 is transmitted via the input selection switch 211 and converted into a positive polarity grayscale voltage signal. While controlling the input selection switch 211, the output selection switch 214 is controlled to connect its own first input terminal and second output terminal, as well as its own second input terminal and first output terminal. The positive polarity grayscale voltage signal is transmitted to the even-numbered column data line via the output selection switch 214 and the first charge sharing circuit 215, and the negative polarity grayscale voltage signal is transmitted to the odd-numbered column data line via the output selection switch 214 and the first charge sharing circuit 215, thereby completing the output of the grayscale voltage of the current frame and the polarity switching, which can solve the problem of liquid crystal polarization caused by long-term same polarity.

[0067] The input selection switch 211 and the output selection switch 214 may be multi-input and multi-output switches, for example Figure 4 As shown, the input selection switch 211 and the output selection switch 214 can select the first sub-switch K11, the second sub-switch K12, the third sub-switch K13 and the fourth sub-switch K14. The first sub-switch K11 is connected to the first input terminal and the first output terminal of the corresponding selection switch, the second sub-switch K12 is connected to the first input terminal and the second output terminal of the corresponding selection switch, the third sub-switch K13 is connected to the second input terminal and the first output terminal of the corresponding selection switch, and the fourth sub-switch K14 is connected to the second input terminal and the second output terminal of the corresponding selection switch. In each frame, the first sub-switch K11 is connected to the first input terminal and the first output terminal of the corresponding selection switch, the second sub-switch K12 is connected to the first input terminal and the second output terminal of the corresponding selection switch, the third sub-switch K13 is connected to the second input terminal and the first output terminal of the corresponding selection switch, and the fourth sub-switch K14 is connected to the second input terminal and the second output terminal of the corresponding selection switch. By controlling the on and off of corresponding sub-switches among the first sub-switch K11, the second sub-switch K12, the third sub-switch K13 and the fourth sub-switch K14, the digital data signal can be selectively output to the positive polarity digital-to-analog converter 212 and the negative polarity digital-to-analog converter 213, and the converted positive polarity grayscale voltage signal and the negative polarity grayscale voltage signal can be correspondingly transmitted to the odd-column data lines and the even-column data lines connected to the driving unit 210, and transmitted to the pixel units 10 in two adjacent columns in the display panel 1 through the data lines, thereby realizing the driving display of the pixel units 10.

[0068] When the grayscale voltage signal is normally output, the first input terminal and the first output terminal of the first charge sharing circuit 215 remain in a connected state, and the second input terminal and the second output terminal of the first charge sharing circuit 215 remain in a connected state; and when charge sharing is performed at the end of frame data output, the first input terminal and the first output terminal of the first charge sharing circuit 215 are switched to an off state, the second input terminal and the second output terminal of the first charge sharing circuit 215 are switched to an off state, and the first output terminal and the second output terminal of the first charge sharing circuit 215 are switched to a connected state, that is, adjacent data lines are switched to a connected state, and the grayscale voltage signals on the adjacent data lines are charge-shared and neutralized.

[0069] like Figure 5 As shown, the first charge sharing circuit 215 includes a first switch K1, a second switch K2 and a third switch K3. When the grayscale voltage signal is normally transmitted, the first switch K1 and the second switch K2 are controlled to be turned on, and the third switch K3 is controlled to be turned off. The grayscale voltage signal of the corresponding polarity is output to the first data line S1 of the display panel 1 through the first switch K1 of the first charge sharing circuit 215, and the grayscale voltage signal of the corresponding polarity is output to the second data line S2 of the display panel 1 through the second switch K2 of the first charge sharing circuit 215.

[0070] After the current frame display ends, the first switch K1 and the second switch K2 are controlled to be turned off, and the third switch K3 is controlled to be turned on. The charges of different or same polarities on the first data line S1 and the second data line S2 of the group cancel each other out, realizing charge sharing.

[0071] In order to reduce the driving power consumption of the display panel 1 and the display device, Figure 6 As shown, the control method of the source driver circuit 200 includes:

[0072] S10 , after the end of the i-th frame, output the first channel selection signal TP1 to control the first charge sharing circuit 215 to share charges between the two data lines of the corresponding group, and compare the voltage signals on the two data lines after charge sharing with the polarity reference voltage respectively.

[0073] In this embodiment, within the same frame, the polarity of the grayscale voltage signal output to each data line is the same, that is, during the line-by-line scanning process of the display panel 1, the polarity of the grayscale voltage signal on the same data line remains unchanged, and the voltage magnitude of the grayscale voltage signal on the same data line may change during the line-by-line scanning process of the same frame.

[0074] The voltage comparison may occur after the display panel 1 is powered on and controls the corresponding circuits to output multiple grayscale voltage signals to the display panel 1 after receiving display control instructions and image information. Alternatively, the voltage comparison may occur after the display panel 1 has finished displaying a corresponding frame of an image. For example, after the first frame, the first charge sharing circuit 215 is controlled to perform charge sharing, and the grayscale voltage signals at the first output terminal and the second output terminal of the first charge sharing circuit 215 are respectively compared with the polarity reference voltage. Alternatively, after the fourth frame, the first charge sharing circuit 215 is controlled to perform charge sharing, and the grayscale voltage signals at the first output terminal and the second output terminal of the first charge sharing circuit 215 are respectively compared with the polarity reference voltage. The specific timing of the comparison is not limited.

[0075] Among them, in the first frame, the source driving circuit 200 is controlled to normally output grayscale voltage signals with opposite polarities to two adjacent data lines. Taking the first data line S1 and the second data line S2 of the display panel 1 as an example, in the control method, a control signal is first output to control the input selection switch 211 and the output selection switch 214 to connect the input end and the output end respectively, and one of the digital data signals is converted and output into a positive polarity grayscale voltage signal through the positive polarity digital-to-analog converter 212, and the other digital data signal is converted and output into a negative polarity grayscale voltage signal through the negative polarity digital-to-analog converter 213. The positive polarity grayscale voltage signal and the negative polarity grayscale voltage signal are output to the first data line S1 and the second data line S2, respectively.

[0076] After the first frame ends, the first charge sharing circuit 215 is controlled to perform charge sharing. For example, the first switch K1 and the second switch K2 are turned off, and the third switch K3 is turned on. The charges of different polarities on the first data line S1 and the second data line S2 of the group cancel each other out, thereby achieving charge sharing.

[0077] For example, after the current frame display ends, the final grayscale voltage signal output to the first data line is 10V, and the grayscale voltage signal output to the second data line is 4V. After the grayscale voltage signals on the two data lines share charge, when the charge sharing is complete, the voltages on the two data lines are both 7V. Alternatively, for example, after the current frame display ends, the final grayscale voltage signal output to the first data line is 14V, and the grayscale voltage signal output to the second data line is 4V. After the grayscale voltage signals on the two data lines share charge, when the charge is fully charged, the voltages on the two data lines are both 9V.

[0078] In the control method, the voltage comparison may be performed after the charge sharing of the first frame is completed or after the charge sharing of the subsequent frames is completed according to the adjustment strategy.

[0079] Assuming that no voltage comparison is performed in the initial stage of the second frame, after the charge sharing is completed, the control method normally outputs the control signal to control the input selection switch 211 and the output selection switch 214 to connect the input end and the output end respectively, and converts the digital data signal input in the second frame into a positive polarity grayscale voltage signal through the positive polarity digital-to-analog converter 212, and converts the other digital data signal input in the second frame into a negative polarity grayscale voltage signal through the negative polarity digital-to-analog converter 213. The positive polarity grayscale voltage signal and the negative polarity grayscale voltage signal are respectively output to the second data line S2 and the first data line S1, thereby completing the output of the grayscale voltage of the current frame and the polarity switching, which can solve the problem of liquid crystal polarization caused by long-term same polarity.

[0080] In an optional embodiment, i=1, that is, the control method performs voltage comparison after each frame of charge sharing is completed, and selects the polarity switching and output of the grayscale voltage signal according to the comparison result.

[0081] That is, after the first frame grayscale voltage signal is output, the first channel selection signal TP1 is first output to the first charge sharing circuit 215 for charge sharing. The charges of the positive grayscale voltage signal and the negative grayscale voltage signal cancel each other, thus achieving charge sharing.

[0082] After charge sharing is completed, the voltages on the first data line S1 and the second data line S2 are obtained, and the grayscale voltage signal on the first data line S1 is compared with the polarity reference voltage, and the grayscale voltage signal on the second data line S2 is compared with the memory reference voltage signal. The voltages can be directly connected to the first data line S1 and the second data line S2 to obtain the voltages, or the voltages on the first data line S1 and the second data line S2 can be indirectly obtained by selectively connecting to the two output terminals of the first charge sharing circuit 215.

[0083] The specific timing of outputting the grayscale voltage signal with opposite polarity can be set accordingly according to requirements. In an optional embodiment, the timing of outputting the grayscale voltage signal with opposite polarity occurs at the initial moment of the first frame displayed in the power-on state.

[0084] S20. When the grayscale voltage signal of a data line corresponding to each group is greater than the polarity reference voltage, in the (i+1)th frame, the first channel selection signal TP1 and the second channel selection signal TP2 are output successively to control the input selection switch 211 and the output selection switch 214 to switch to the first switch K1 state and the second switch K2 state successively, so as to convert the digital grayscale voltage signal input from the odd input terminal and / or the even input terminal into a positive polarity grayscale voltage signal through the positive polarity digital-to-analog converter 212 and transmit it to the corresponding data line.

[0085] When the grayscale voltage signal on the data line is greater than the polarity reference voltage, for example, when the voltages on both data lines are 9V, at this time, it is greater than the polarity reference voltage of 7.5V, and in the next frame display image, the source driver circuit 200 is controlled to output a positive polarity grayscale voltage signal to the two data lines.

[0086] Among them, since there is only one positive polarity digital-to-analog converter 212 in the source driving circuit 200, in order to realize the output of two positive polarity grayscale voltage signals, the positive polarity digital-to-analog converter 212 needs to perform digital-to-analog conversion on the two input digital data signals in sequence. To this end, the first channel selection signal TP1 is first output to control the input selection switch 211 and the output selection switch 214 to switch to the first switch K1 state. The first switch K1 state is that the first input end and the first output end of the input selection switch 211 are connected, and the first input end and the first output end of the output selection switch 214 are connected, and the first digital data signal inputted from the odd column input end Y2n-1 of the driving unit 210 is transmitted to the positive polarity digital-to-analog converter 212, and converted into a first positive polarity grayscale voltage signal and transmitted to the first data line S1 through the output selection switch 214.

[0087] Then, the second channel selection signal TP2 is output to control the input selection switch 211 and the output selection switch 214 to switch to the second switch K2 state. The second switch K2 state is that the second input end and the first output end of the input selection switch 211 are connected, and the first input end and the second output end of the output selection switch 214 are connected. The second digital data signal input by the even column input end Y2n of the driving unit 210 is transmitted to the positive polarity digital-to-analog converter 212, and converted into a second positive polarity grayscale voltage signal and transmitted to the second data line S2 through the output selection switch 214, thereby outputting a positive polarity grayscale voltage signal of the same polarity to the two data lines. By outputting the grayscale voltage signal of the same polarity in the previous and next frames, the charging cross-voltage can be reduced, thereby reducing the charging charge and charging power consumption.

[0088] For example, assuming that the voltage of the two data lines is 9V after the charge sharing of the current frame is completed, and the negative polarity grayscale voltage signal of the first data line originally scheduled for polarity switching in the next frame is 6V, and the positive polarity grayscale voltage signal of the second data line is 10V, when the polarity switching is performed, the voltage on the first data line S1 needs to be switched from 9V to 6V, and the voltage on the second data line S2 needs to be switched from 9V to 10V, with a total voltage difference of 4V, which requires the replenishment of 4V of charge and power consumption.

[0089] When the polarity is not switched, the positive polarity grayscale voltage signal output to the first data line in the next frame is 9V, which has the same voltage difference as the original 6V negative polarity voltage and the polarity reference voltage, and has the same display effect. The voltage on the first data line S1 is maintained at 9V, and its cross-voltage size is 0. The positive polarity grayscale voltage signal output to the second data line in the next frame is 10V, and the voltage of the second data line S2 needs to be switched from 9V cross-voltage to 10V, and its cross-voltage size is 1V. The total cross-voltage size is 1V. The cross-voltage is reduced, and the corresponding 1V of charge and power consumption need to be supplemented. For this reason, when it is judged that the voltage after charge sharing is greater than the polarity reference voltage and the positive polarity grayscale voltage signal is selected to be output, the total cross-voltage of the previous and next frames is reduced by 3V, and correspondingly, the charging power consumption is reduced.

[0090] S30. When the grayscale voltage signal of a data line corresponding to each group is less than the polarity reference voltage, in the (i+1)th frame, the first channel selection signal TP1 and the second channel selection signal TP2 are output successively to control the input selection switch 211 and the output selection switch 214 to switch to the third switch K3 state and the fourth switch K4 state successively, so as to convert the digital grayscale voltage signal input from the odd input terminal and / or the even input terminal into a negative polarity grayscale voltage signal through the negative polarity digital-to-analog converter 213 and transmit it to the corresponding data line.

[0091] When the grayscale voltage signal on the data line is less than the polarity reference voltage, for example, when the voltages on both data lines are 7V, which is less than the polarity reference voltage of 7.5V, the source driver circuit 200 is controlled to output a negative polarity grayscale voltage signal to the two data lines in the next frame display.

[0092] Among them, since there is only one negative polarity digital-to-analog converter 213 in the source driving circuit 200, in order to realize the output of two positive polarity grayscale voltage signals, the negative polarity digital-to-analog converter 213 needs to perform digital-to-analog conversion on the two input digital data signals in sequence. To this end, the first channel selection signal TP1 is first output to control the input selection switch 211 and the output selection switch 214 to switch to the third switch K3 state. The state of the third switch K3 is that the first input end and the second output end of the input selection switch 211 are connected, and the second input end and the first output end of the output selection switch 214 are connected, and the first digital data signal inputted from the odd column input end Y2n-1 of the driving unit 210 is transmitted to the negative polarity digital-to-analog converter 213, and converted into a first negative polarity grayscale voltage signal and transmitted to the first data line S1 through the output selection switch 214.

[0093] Then, the second channel selection signal TP2 is output to control the input selection switch 211 and the output selection switch 214 to switch to the fourth switch K4 state. The fourth switch K4 state is that the second input end and the second output end of the input selection switch 211 are connected, and the second input end and the second output end of the output selection switch 214 are connected, and the second digital data signal input by the even column input terminal Y2n of the driving unit 210 is transmitted to the negative polarity digital-to-analog converter 213, and converted into a second negative polarity grayscale voltage signal and transmitted to the second data line S2 through the output selection switch 214, thereby outputting a negative polarity grayscale voltage signal of the same polarity to the two data lines. By outputting the grayscale voltage signal of the same polarity in the previous and next frames, the charging cross-voltage can be reduced, thereby reducing the charging charge and charging power consumption.

[0094] For example, assuming that the voltage of the two data lines is 7V after the charge sharing of the current frame is completed, and the negative polarity grayscale voltage signal of the first data line originally scheduled to switch polarity in the next frame is 6V, and the positive polarity grayscale voltage signal of the second data line is 10V, when the polarity switching is performed, the voltage on the first data line S1 needs to be switched from 7V to 6V, and the voltage on the second data line S2 needs to be switched from 7V to 10V, with a total voltage difference of 4V, which requires the replenishment of 4V of charge and power consumption.

[0095] When the polarity is not switched, the negative grayscale voltage signal output to the first data line in the next frame is 6V, and the voltage on the first data line S1 needs to be switched from 7V to 6V, and the voltage is 1V. The negative grayscale voltage signal output to the second data line in the next frame is 5V, which has the same voltage difference as the original 10V positive polarity voltage and polarity reference voltage, and has the same display effect. The voltage of the second data line S2 needs to be switched from 7V to 5V, and the voltage is 2V. The total voltage is 3V. The voltage is reduced, and the corresponding 3V of charge and power consumption need to be supplemented. For this reason, when it is judged that the voltage after charge sharing is less than the polarity reference voltage and the negative grayscale voltage signal is selected to be output, the total voltage of the previous and next frames is reduced by 1V, and correspondingly, the charging power consumption is reduced.

[0096] Therefore, by comparing the voltages after charge sharing and switching the polarity of the output grayscale voltage signal, the purpose of reducing charging power consumption can be achieved.

[0097] Furthermore, due to incomplete neutralization during charge sharing, or when a grayscale voltage signal of the same polarity is subsequently output to two adjacent data lines, leakage current may occur and when the output grayscale voltage signal is close to the polarity reference voltage, the voltage signal on one of the data lines may be greater than the polarity reference voltage, while the voltage signal on the other data line may be less than the polarity reference voltage. Subsequently, when the grayscale voltage signal of the same polarity continues to be output to the two adjacent data lines, the cross-voltage is excessively large, resulting in increased charging power consumption. In the control method, voltage comparison and polarity judgment output are performed after the charge sharing of each frame is completed, thereby reducing the cross-voltage of each frame.

[0098] For example, a positive polarity grayscale voltage signal is output to the first data line S1 in the first frame, and a negative polarity grayscale voltage signal is output to the second data line S2, and charge sharing and voltage comparison are performed after the first frame display is completed. When the voltage signal of the first data line S1 and / or the second data line S2 is greater than the polarity reference voltage, a positive polarity voltage signal is output to the data line at the initial moment of the second frame, and when the voltage signal of the first data line S1 and / or the second data line S2 is less than the polarity reference voltage, a negative polarity voltage signal is output at the initial moment of the second frame.

[0099] Then, during the second frame progressive scanning process, the polarity of the grayscale voltage signal on the same data line remains unchanged, and charge sharing and voltage comparison are performed again after the second frame display is completed, and the grayscale voltage signal of the corresponding polarity is output to the first data line S1 and the second data line S2 at the initial moment of the third frame. Similarly, charge sharing and voltage comparison can be performed after the display of each frame is completed, and the source driver circuit 200 can be controlled to output the grayscale voltage signal of the corresponding polarity to the two adjacent data lines, thereby reducing the excessive cross-voltage caused by leakage or incomplete charge sharing and reducing charging power consumption.

[0100] Example 2

[0101] After voltage comparison and polarity switching control are performed, the polarities of two adjacent data lines in each group are always maintained at positive polarity or negative polarity. In order to avoid liquid crystal polarity, in an optional embodiment, as shown in FIG. Figure 7 As shown, the control method of the source driver circuit 200 further includes:

[0102] S40. In the first frame, the output polarity switching control signal controls the input selection switch 211 and the output selection switch 214 to switch to the fifth switch state, so as to convert the digital grayscale voltage signals input from the odd input terminal and the even input terminal into positive polarity grayscale voltage signals and negative polarity grayscale voltage signals respectively through the positive polarity digital-to-analog converter 212 and the negative polarity digital-to-analog converter 213, and transmit the converted signals to the odd column data lines and the even column data lines.

[0103] S50, every n1 frames, the interval output polarity switching control signal controls the input selection switch 211 and the output selection switch 214 to switch between the sixth switch state and the fifth switch state, so as to intervally switch the polarity of the grayscale voltage signals of the two data lines of each group and the polarities of the two adjacent data lines of each group are opposite, wherein n1 is a positive integer.

[0104] In this embodiment, in the first frame, it is assumed that the source driving circuit 200 is controlled to normally output grayscale voltage signals with opposite polarities to two adjacent data lines. Taking the first data line S1 and the second data line S2 of the display panel 1 as an example, it is assumed that a positive polarity grayscale voltage signal is initially output to the first data line S1 and a negative polarity grayscale voltage signal is initially output to the second data line S2.

[0105] First, the polarity switching control signal is input to the input selection switch 211 and the output selection switch 214, and the input selection switch 211 and the output selection switch 214 are controlled to switch to the fifth switch state, wherein the fifth switch state may be that the input selection switch 211 is connected to its own first input terminal and first output terminal and to its own second input terminal and second output terminal, the output selection switch 214 is connected to its own first input terminal and first output terminal and to its own second input terminal and second output terminal, and the first digital data signal input to the odd column input terminal Y2n-1 of the driving unit 210 is converted and output into a positive polarity grayscale voltage signal through the positive polarity digital-to-analog converter 212 and transmitted to the first data line S1, and the second digital data signal input to the even column input terminal Y2n of the driving unit 210 is converted into a negative polarity grayscale voltage signal through the negative polarity digital-to-analog converter 213 and transmitted to the second data line S2.

[0106] After the first frame and subsequent frames are completed, charge sharing and voltage comparison are performed normally, and in the n1+1th frame, another polarity switching control signal is output to switch the polarity of the first data line S1 and the second data line S2. First, the polarity switching control signal is input to the input selection switch 211 and the output selection switch 214, and the input selection switch 211 and the output selection switch 214 are controlled to switch to the sixth switch state, wherein the sixth switch state can be that the input selection switch 211 connects its first input end and the second output end and connects its second input end and the first output end, and the output selection switch 211 connects its second input end and the first output end. 214 is connected to its own first input terminal and second output terminal and its own second input terminal and first output terminal, and converts the first digital data signal input from the odd column input terminal Y2n-1 of the driving unit 210 into a negative polarity grayscale voltage signal through the negative polarity digital-to-analog converter 213 and transmits it to the first data line S1, and converts the second digital data signal input from the even column input terminal Y2n of the driving unit 210 into a positive polarity grayscale voltage signal through the positive polarity digital-to-analog converter 212 and transmits it to the second data line S2, thereby switching the polarity on each data line and reducing the liquid crystal polarity.

[0107] After the end of the n1+1th frame and subsequent frames, charge sharing and voltage comparison are performed normally, and in the 2n1+1th frame, another polarity switching control signal is output to switch the polarity of the first data line S1 and the second data line S2, and the input selection switch 211 and the output selection switch 214 are controlled to switch to the fifth switch state again, and the first digital data signal input to the odd column input terminal Y2n-1 of the driving unit 210 is converted and output into a positive polarity grayscale voltage signal through the positive polarity digital-to-analog converter 212 and transmitted to the first data line S1, and the second digital data signal input to the even column input terminal Y2n of the driving unit 210 is converted into a negative polarity grayscale voltage signal through the negative polarity digital-to-analog converter 213 and transmitted to the second data line S2, thereby switching the polarity on each data line and reducing the liquid crystal polarity.

[0108] By analogy, the polarity of each data line can be switched every n1 frames to avoid liquid crystal polarization caused by the same polarity.

[0109] Among them, the size of n1 can be set according to needs. In an optional embodiment, in order to avoid excessive switching that causes failure of voltage comparison and subsequent polarity judgment, and based on high refresh rate considerations, there is no need to frequently switch polarity. In an optional embodiment, n1=30, that is, the polarity of the grayscale voltage signal on each data line is switched every 30 frames.

[0110] Example 3

[0111] After voltage comparison and polarity switching control are performed, the polarities of two adjacent data lines in each group are always maintained at positive polarity or negative polarity. In order to avoid liquid crystal polarity, in an optional embodiment, as shown in FIG. Figure 8 As shown, the source driving circuit 200 further includes a plurality of second charge sharing circuits 220. Each second charge sharing circuit 220 is connected between two adjacent odd-numbered column data lines and an even-numbered column data line of two adjacent driving units 210. The second charge sharing circuit 220 can share charges between adjacent data lines of two adjacent driving units 210.

[0112] Among them, such as Figure 9 As shown, the second charge sharing circuit 220 may include a fourth switch K4 , and the fourth switch K4 is connected between two adjacent odd-numbered column data lines and an even-numbered column data line of two adjacent driving units 210 .

[0113] like Figure 11 As shown, the control method of the source driver circuit 200 further includes:

[0114] S60, after the (i+1)th frame ends, outputting a second channel selection signal TP2 to control the second charge sharing circuit 220 to perform charge sharing on the two corresponding data lines, and comparing the voltage signals on the two data lines after charge sharing with the polarity reference voltage respectively;

[0115] S70: When the grayscale voltage signal of the corresponding data line is greater than the polarity reference voltage, in the (i+2)th frame, the first channel selection signal TP1 and the second channel selection signal TP2 are output sequentially to control the input selection switch 211 and the output selection switch 214 to switch to the first switch K1 state and the second switch K2 state, respectively, so as to convert the digital grayscale voltage signal input from the odd input terminal and / or the even input terminal into a positive polarity grayscale voltage signal through the positive polarity digital-to-analog converter 212 and transmit the signal to the corresponding data line.

[0116] S80. When the grayscale voltage signal of a data line corresponding to each group is less than the polarity reference voltage, in the (i+2)th frame, the first channel selection signal TP1 and the second channel selection signal TP2 are output successively to control the input selection switch 211 and the output selection switch 214 to switch to the third switch K3 state and the fourth switch K4 state successively, so as to convert the digital grayscale voltage signal inputted from the odd input terminal and / or the even input terminal into a negative polarity grayscale voltage signal through the negative polarity digital-to-analog converter 213 and transmit it to the corresponding data line.

[0117] In this embodiment, reference Figure 10 As shown, the first charge sharing circuit 215 triggers charge sharing based on the first channel selection signal TP1 outputted first, and the second charge sharing circuit 220 triggers charge sharing based on the second channel selection signal TP2 outputted first.

[0118] After the i-th frame ends, according to S10, the first channel selection signal TP1 is first output to the first charge sharing circuit 215. The first charge sharing circuit 215 performs charge sharing on two adjacent data lines in the same group. When the neutralization voltage is greater than the polarity reference voltage, in S20, the first channel selection signal TP1 and the second channel selection signal TP2 are output successively. The first digital data signal and the second digital data signal input by the driving unit 210 are converted into positive polarity grayscale voltage signals successively through the positive polarity digital-to-analog converter 212 and are transmitted to the two data lines in the same group. And when the neutralization voltage is greater than the polarity reference voltage, in S30, the first channel selection signal TP1 and the second channel selection signal TP2 are output successively. The first digital data signal and the second digital data signal input by the driving unit 210 are converted into negative polarity grayscale voltage signals successively through the negative polarity digital-to-analog converter 213 and are transmitted to the two data lines in the same group.

[0119] like Figure 9As shown, when S10, S20 and S30 are adopted, multiple data lines may be in the polarity state of positive-positive-negative-negative-positive-negative-negative continuously in multiple frames, resulting in the problem of liquid crystal polarization.

[0120] Therefore, in this embodiment, assuming i=1, in the second frame, the second channel selection signal TP2 is output to the second charge sharing circuit 220, and the second charge sharing circuit 220 performs charge sharing on the adjacent data lines of two adjacent driving units 210, thereby performing charge sharing on the positive and negative polarity grayscale voltage signals of the adjacent data lines in the adjacent driving units 210, for example Figure 9 The second data line S2 with positive polarity and the third data line with negative polarity share charge, and the neutral voltage of the positive and negative grayscale voltage signals of the two adjacent data lines after charge sharing may be greater than the polarity reference voltage or less than the polarity reference voltage.

[0121] Assuming that the voltage is greater than the polarity reference voltage, then in the third frame, S70 can sequentially output the first channel selection signal TP1 and the second channel selection signal TP2 in the same manner as S20 to control the input selection switch 211 and the output selection switch 214 of the first driving unit 210 to switch to the first switch K1 state and the second switch K2 state. The first driving unit 210 is connected to the first data line S1 and the second data line S2, thereby outputting a positive polarity grayscale voltage signal to the second data line S2. Furthermore, the first channel selection signal TP1 and the second channel selection signal TP2 can be sequentially output to control the input selection switch 211 and the output selection switch 214 of the second driving unit 210 to switch to the first switch K1 state and the second switch K2 state. The second driving unit 210 is connected to the third data line and the fourth data line, thereby outputting a positive polarity grayscale voltage signal to the third data line. Similarly, in the third frame, the polarity of each data line can be switched to negative, positive, positive, negative, negative, positive, and negative. Half of the data lines can switch polarity.

[0122] Assuming that it is less than the polarity reference voltage, then in the third frame, S80 can be the same as S30, successively outputting the first channel selection signal TP1 and the second channel selection signal TP2 to control the input selection switch 211 and the output selection switch 214 of the first driving unit 210 to switch to the third switch K3 state and the fourth switch K4 state, thereby outputting a negative polarity grayscale voltage signal to the second data line S2. And successively outputting the first channel selection signal TP1 and the second channel selection signal TP2 to control the input selection switch 211 and the output selection switch 214 of the second driving unit 210 to switch to the first switch K1 state and the second switch K2 state, thereby outputting a negative polarity grayscale voltage signal to the third data line, and so on. In the third frame, as shown in FIG. Figure 9As shown on the right, the polarity of each data line can be switched to positive-negative-negative-positive-positive-negative-negative-positive, and the other half of the multiple data lines can switch polarity, thereby preventing the problem of liquid crystal polarization caused by the data lines having the same polarity for a long time.

[0123] The first channel selection signal TP1 and the second channel selection signal TP2 are alternately output on a frame basis. That is, after the charge sharing of the first frame is completed, the first channel selection signal TP1 is output and controls the first charge sharing circuit 215 to perform charge sharing. After the charge sharing of the second frame is completed, the second channel selection signal TP2 is output and controls the second charge sharing circuit 220 to perform charge sharing. After the charge sharing of the third frame is completed, the first channel selection signal TP1 is output and controls the first charge sharing circuit 215 to perform charge sharing. After the charge sharing of the fourth frame is completed, the second channel selection signal TP2 is output and controls the second charge sharing circuit 220 to perform charge sharing. This switches the polarity of different data lines accordingly, reducing the problem of liquid crystal polarization. At the same time, the grayscale voltage signal of the corresponding polarity is selected and output to the corresponding data line based on the comparison result, thereby reducing the charging cross-voltage between adjacent frames and lowering the charging drive power consumption.

[0124] Example 4

[0125] When charge sharing is used, additional heat energy is generated during the neutralization of the positive and negative polarity voltages, affecting the temperature of the driving circuit. To prevent excessive temperature rise, in an optional embodiment, after the corresponding frame ends and before charge sharing is performed on the grayscale voltage signals of the corresponding two data lines, the following steps are further included:

[0126] S90, obtaining grayscale voltage signals of the next frame corresponding to two data lines, and comparing a voltage difference between grayscale voltage signals of adjacent frames of two data lines in each group with a preset difference;

[0127] S100, when the voltage difference between the two corresponding data lines is less than the preset difference, no charge sharing is performed, and the grayscale voltage signal of the next frame is output to the two corresponding data lines;

[0128] S110 , when the voltage difference corresponding to at least one data line is greater than a preset difference, charge sharing is performed on the grayscale voltage signals corresponding to the two data lines.

[0129] In this embodiment, the voltage difference between the grayscale voltage signals of two adjacent frames of two adjacent data lines in each group is calculated and compared with the preset voltage difference. When the voltage difference change is small, charge sharing is not performed and the grayscale voltage signal of the corresponding polarity is directly output in the next frame. When the voltage difference change is large, charge sharing is selected.

[0130] For example, assuming that the voltage of the current frame of one of the data lines is 10V, and the voltage of the next frame is 7V, and assuming that the preset difference is 1V, at this time, the difference between the two adjacent frames is 3V, which is greater than the preset difference. At this time, charge sharing is selected, and after charge sharing, voltage comparison and output polarity control of the grayscale voltage signal of the data line are performed. After charge sharing, the cross-voltage of the grayscale voltage signals of the two frames before and after is smaller, thereby reducing charging power consumption.

[0131] Alternatively, assuming that the voltage of the current frame of one of the data lines is 7.6V and the voltage of the next frame is 7V, and assuming that the preset difference is 1V, at this time, the difference between the two adjacent frames is 0.6V, which is less than the preset difference. At this time, you can choose not to share the charge and directly output a grayscale voltage signal with opposite polarity to the data line in the next frame. The cross-voltage of the grayscale voltage signals of the previous and next frames is smaller, which reduces the charging power consumption.

[0132] The preset difference can be determined according to demand or set according to the magnitude of the grayscale voltage signal of the current frame. In an optional embodiment, the preset difference is the difference between the grayscale voltage signal of the next frame and the polarity reference voltage.

[0133] For example, assuming that the voltage of the current frame of one of the data lines is 10V, the voltage of the next frame is 7V, assuming that the polarity reference voltage is 7.5V, the preset difference is 0.5V, and the difference between the two adjacent frames is 3V, which is greater than the preset difference. At this time, charge sharing is selected, and after charge sharing, voltage comparison and output polarity control of the grayscale voltage signal of the data line are performed. After charge sharing, the cross-voltage of the grayscale voltage signals of the two frames before and after is smaller, thereby reducing charging power consumption.

[0134] Alternatively, assuming that the voltage of the current frame of one of the data lines is 10V, the voltage of the next frame is 13V, and the preset difference is 5.5V, at this time, the difference between the two adjacent frames is 3V, which is less than the preset difference. At this time, you can choose not to share the charge, and directly output a grayscale voltage signal with opposite polarity to the data line in the next frame. The cross-voltage of the grayscale voltage signals between the previous and next frames is smaller, which reduces the charging power consumption.

[0135] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0136] Example 5

[0137] The second aspect of the embodiment of the present invention provides a display panel driving circuit 2, such as Figure 1 、 Figure 2 and Figure 13As shown, the display panel 1 includes multiple data lines, multiple scan lines and multiple pixel units 10 arranged in an array. The pixel unit 10 is connected to one data line and one scan line respectively. The multiple columns of data lines are divided into multiple groups in turn. Each group of data lines includes two adjacent odd-numbered column data lines and even-numbered column data lines. The display panel 1 is connected to the source driver circuit 200 through the data lines. The source driver circuit 200 includes multiple driving units 210. The multiple driving units 210 are connected one by one to the multiple groups of data lines of the display panel 1. The driving unit 210 at least includes a positive polarity digital-to-analog converter 212, a negative polarity digital-to-analog converter 213, an input selection switch 211, an output selection switch 214 and a first charge sharing circuit 215.

[0138] The first input terminal of the input selection switch 211 constitutes the odd-numbered column input terminal Y2n-1 of the driving unit 210, the second input terminal of the input selection switch 211 constitutes the even-numbered column input terminal Y2n of the driving unit 210, the first output terminal of the input selection switch 211 is connected to the input terminal of the positive polarity digital-to-analog converter 212, the second output terminal of the input selection switch 211 is connected to the input terminal of the negative polarity digital-to-analog converter 213, the output terminal of the positive polarity digital-to-analog converter 212 is connected to the first input terminal of the output selection switch 214, the output terminal of the negative polarity digital-to-analog converter 213 is connected to the second input terminal of the output selection switch 214, the first output terminal of the output selection switch 214 is connected to the first input terminal of the first charge sharing circuit 215, the second output terminal of the output selection switch 214 is connected to the second input terminal of the first charge sharing circuit 215, the first output terminal of the first charge sharing circuit 215 is connected to the odd-numbered column data lines in each group of data lines, and the second output terminal of the first charge sharing circuit 215 is connected to the even-numbered column data lines in each group of data lines.

[0139] The source driving circuit 200 further includes a plurality of second charge sharing circuits 220, each of which is connected between two adjacent odd-numbered column data lines and even-numbered column data lines of two adjacent driving units 210. Figure 9 As shown, the second charge sharing circuit 220 may include a fourth switch K4 , and the fourth switch K4 is connected between two adjacent odd-numbered column data lines and an even-numbered column data line of two adjacent driving units 210 .

[0140] The timing control circuit 100 is used to implement the control method of the source driver circuit 200 described above.

[0141] In this embodiment, the display panel driving circuit 2 further includes a gate driving circuit 300, which is used to output row scanning signals row by row in each frame to turn on each row of pixel units 10 row by row and display corresponding image information in combination with the input grayscale voltage signal.

[0142] Among them, the positive polarity digital-to-analog converter 212 is used to convert the input digital data signal into a positive polarity grayscale voltage signal, and the negative polarity digital-to-analog converter 213 is used to convert the input digital data signal into a negative polarity grayscale voltage signal. The positive polarity refers to a voltage signal greater than the polarity reference voltage, and the negative polarity refers to a grayscale voltage signal less than the polarity reference voltage. For example, the polarity reference voltage is 7.5V, and the voltage greater than 7.5V is a positive polarity grayscale voltage signal, and the voltage less than 7.5V is a negative polarity grayscale voltage signal. The interval range of the positive polarity grayscale voltage signal can be 8V~15V, and the voltage range of the negative polarity grayscale voltage signal can be 0.2V~6V.

[0143] The digital-to-analog converter includes a plurality of gate MOS transistors, which are composed of NMOS transistors that are turned on corresponding to high level and PMOS transistors that are turned on corresponding to low level. Figure 4 As shown, taking a 3-bit digital-to-analog converter as an example, the digital data signal D2D1D0 input to the digital-to-analog converter is 011, then / D2 / D1 / D0 is 100. According to the 8421 encoding principle, the output of the selection switch is the V3 voltage value, and the V3 voltage value can be amplified by the back-end signal amplifier to obtain the V3 grayscale voltage. The grayscale voltage corresponds to the analog-to-digital grayscale voltage signal corresponding to the digital signal 011.

[0144] The input selection switch 211 can connect its own first input terminal and second input terminal to its own first output terminal and second output terminal according to the received control signal, and the output selection switch 214 can connect its own first input terminal and second input terminal to its own first output terminal and second output terminal according to the received control signal.

[0145] For example, assuming that it is initially necessary to output a positive polarity grayscale voltage signal to the odd-numbered column data lines in the corresponding group, and output a negative polarity grayscale voltage signal to the even-numbered column data lines in the same group, at this time, the first digital data signal is input to the first input terminal of the input selection switch 211 and the second digital data signal is input to the second input terminal of the input selection switch 211, and a control signal can be output to control the input selection switch 211 to connect its own first input terminal and first output terminal, and to control the input selection switch 211 to connect its own second input terminal and second output terminal, the first digital data signal is transmitted to the positive polarity digital-to-analog converter 212 through the input selection switch 211, and is converted into a positive polarity digital-to-analog converter 212. The second digital data signal is transmitted to the negative polarity digital-to-analog converter 213 via the input selection switch 211 and converted into a negative polarity grayscale voltage signal. While controlling the input selection switch 211, the output selection switch 214 is controlled to connect its own first input terminal and first output terminal, as well as its own second input terminal and second output terminal. The positive polarity grayscale voltage signal is transmitted to the odd column data line via the output selection switch 214 and the first charge sharing circuit 215, and the negative polarity grayscale voltage signal is transmitted to the even column data line via the output selection switch 214 and the first charge sharing circuit 215, thereby completing the output of the grayscale voltage of the current frame.

[0146] And in the next frame, assuming that the grayscale voltage polarity of the odd-numbered column data lines and the even-numbered column data lines needs to be switched, at this time, the first digital data signal corresponding to the next frame is input to the first input end of the input selection switch 211 and the second digital data signal corresponding to the next frame is input to the second input end of the input selection switch 211, and the control signal can be output to control the input selection switch 211 to connect its own first input end and second output end, and control the input selection switch 211 to connect its own second input end and first output end, the first digital data signal is transmitted to the negative polarity digital-to-analog converter 213 through the input selection switch 211, and is converted into a negative polarity grayscale voltage signal, and the second digital data signal is output to the negative polarity digital-to-analog converter 213. The positive polarity digital-to-analog converter 212 is transmitted via the input selection switch 211 and converted into a positive polarity grayscale voltage signal. While controlling the input selection switch 211, the output selection switch 214 is controlled to connect its own first input terminal and second output terminal, as well as its own second input terminal and first output terminal. The positive polarity grayscale voltage signal is transmitted to the even-numbered column data line via the output selection switch 214 and the first charge sharing circuit 215, and the negative polarity grayscale voltage signal is transmitted to the odd-numbered column data line via the output selection switch 214 and the first charge sharing circuit 215, thereby completing the output of the grayscale voltage of the current frame and the polarity switching, which can solve the problem of liquid crystal polarization caused by long-term same polarity.

[0147] The input selection switch 211 and the output selection switch 214 may be multi-input and multi-output switches, for example Figure 4As shown, the input selection switch 211 and the output selection switch 214 can select the first sub-switch K11, the second sub-switch K12, the third sub-switch K13 and the fourth sub-switch K14. The first sub-switch K11 is connected to the first input terminal and the first output terminal of the corresponding selection switch, the second sub-switch K12 is connected to the first input terminal and the second output terminal of the corresponding selection switch, the third sub-switch K13 is connected to the second input terminal and the first output terminal of the corresponding selection switch, and the fourth sub-switch K14 is connected to the second input terminal and the second output terminal of the corresponding selection switch. In each frame, the first sub-switch K11 is connected to the first input terminal and the first output terminal of the corresponding selection switch, the second sub-switch K12 is connected to the first input terminal and the second output terminal of the corresponding selection switch, the third sub-switch K13 is connected to the second input terminal and the first output terminal of the corresponding selection switch, and the fourth sub-switch K14 is connected to the second input terminal and the second output terminal of the corresponding selection switch. By controlling the on and off of corresponding sub-switches among the first sub-switch K11, the second sub-switch K12, the third sub-switch K13 and the fourth sub-switch K14, the digital data signal can be selectively output to the positive polarity digital-to-analog converter 212 and the negative polarity digital-to-analog converter 213, and the converted positive polarity grayscale voltage signal and the negative polarity grayscale voltage signal can be correspondingly transmitted to the odd-column data lines and the even-column data lines connected to the driving unit 210, and transmitted to the pixel units 10 in two adjacent columns in the display panel 1 through the data lines, thereby realizing the driving display of the pixel units 10.

[0148] When the grayscale voltage signal is normally output, the first input terminal and the first output terminal of the first charge sharing circuit 215 remain in a connected state, and the second input terminal and the second output terminal of the first charge sharing circuit 215 remain in a connected state; and when charge sharing is performed at the end of frame data output, the first input terminal and the first output terminal of the first charge sharing circuit 215 are switched to an off state, the second input terminal and the second output terminal of the first charge sharing circuit 215 are switched to an off state, and the first output terminal and the second output terminal of the first charge sharing circuit 215 are switched to a connected state, that is, adjacent data lines are switched to a connected state, and the grayscale voltage signals on the adjacent data lines are charge-shared and neutralized.

[0149] like Figure 5 As shown, the first charge sharing circuit 215 includes a first switch K1, a second switch K2 and a third switch K3. When the grayscale voltage signal is normally transmitted, the first switch K1 and the second switch K2 are controlled to be turned on, and the third switch K3 is controlled to be turned off. The grayscale voltage signal of the corresponding polarity is output to the first data line S1 of the display panel 1 through the first switch K1 of the first charge sharing circuit 215, and the grayscale voltage signal of the corresponding polarity is output to the second data line S2 of the display panel 1 through the second switch K2 of the first charge sharing circuit 215.

[0150] After the current frame display ends, the first switch K1 and the second switch K2 are controlled to be turned off, and the third switch K3 is controlled to be turned on. The charges of different or same polarities on the first data line S1 and the second data line S2 of the group cancel each other out, realizing charge sharing.

[0151] The timing control circuit 100 first controls the source driving circuit 200 to output grayscale voltage signals with opposite polarities, and transmits the grayscale voltage signals with opposite polarities to two adjacent data lines of each group of the display panel 1 .

[0152] After the current frame display ends, the first channel selection signal TP1 is output to control the source driver circuit 200 to perform charge sharing. After the charge sharing is completed, the grayscale voltage signals of the two adjacent data lines in each group are obtained and compared with the polarity reference voltage. Based on the comparison result, the grayscale voltage signals of the corresponding polarity are output to the two adjacent data lines in each group in the next frame.

[0153] The timing control circuit 100 may then switch the polarity of two adjacent data lines in each group at intervals of n1 frames to avoid polarization of the liquid crystal.

[0154] The timing control circuit 100 can also obtain the grayscale voltage signal of the next frame before charge sharing, and calculate the voltage difference between the grayscale voltage signals of two adjacent frames of two adjacent data lines in each group, and compare it with the preset voltage difference. When the voltage difference changes slightly, charge sharing is not performed and the grayscale voltage signal of the corresponding polarity is directly output in the next frame. When the voltage difference changes significantly, charge sharing is selected.

[0155] The timing control circuit 100 can also switch and output the first channel selection signal TP1 and the second channel selection signal TP2 in adjacent frames to control the first charge sharing circuit 215 and the second charge sharing circuit 220 to share charges on different adjacent data lines in two adjacent frames, thereby further reducing liquid crystal polarization and lowering power consumption.

[0156] The timing control circuit 100 may adopt a timing controller 110, or may also adopt a corresponding comparator, etc. In an optional embodiment, as shown in FIG. Figure 14 As shown, the timing control circuit 100 includes a multi-channel comparison circuit 120 and a timing controller 110;

[0157] Each comparison circuit 120 is connected to each group of two data lines and the source driver circuit 200. The comparison circuit 120 is used to compare the voltage signals of the two data lines with the polarity reference voltage and output a comparison signal to control the source driver circuit 200 to output a grayscale voltage signal of corresponding polarity to the two adjacent data lines in each group.

[0158] The timing controller 110 is connected to the multi-channel comparison circuit 120 and the source driver circuit 200 respectively, and is used to obtain comparison signals and control the source driver circuit 200 to implement the above-mentioned control method of the source driver circuit 200.

[0159] In this embodiment, each comparison circuit 120 is connected to two adjacent data lines in each group, and the timing controller 110 can control the working timing of the comparison circuit 120 .

[0160] The timing controller 110 first controls the source driver circuit 200 to output grayscale voltage signals with opposite polarities, and controls the first switch K1 and the second switch K2 in the first charge sharing circuit 215 to be turned on, thereby transmitting the grayscale voltage signals with opposite polarities to two adjacent data lines of each group of the display panel 1 .

[0161] After the current frame display ends, the third switch K3 in the first charge sharing circuit 215 is controlled to be turned on to perform charge sharing. After the charge sharing ends, the comparison circuit 120 is controlled to start. The comparison circuit 120 obtains the voltage signals of the two adjacent data lines in each group, compares them with the polarity reference voltage, and outputs the comparison signals to the positive polarity output unit 21 and the negative polarity output unit 22 in the source driver circuit 200, so as to output the grayscale voltage signals of the corresponding polarity to the two adjacent data lines in each group in the next frame.

[0162] The timing controller 110 can then receive the comparison signal to determine the current output status of the positive polarity output unit 21 and the negative polarity output unit 22. The timing controller 110 can also output the polarity switching control signal to the positive polarity output unit 21 and the negative polarity output unit 22 in the source driver circuit 200 at intervals of n2 frames to switch the polarity of the two adjacent data lines in each group to avoid liquid crystal polarization.

[0163] The timing controller 110 can also obtain the voltage signal of the next frame before charge sharing, and calculate the voltage difference between the grayscale voltage signals of two adjacent frames of two adjacent data lines in each group, and compare it with the preset voltage difference. When the voltage difference changes slightly, charge sharing is not performed, and the source driver circuit 200 is directly controlled to output the grayscale voltage signal of the corresponding polarity in the next frame. When the voltage difference changes significantly, the first charge sharing circuit 215 is controlled to perform charge sharing.

[0164] like Figure 15As shown, each comparison circuit 120 may include a first comparator U1 connected to one of the data lines of each group, and a second comparator U2 connected to the other data line of each group. The reference voltage terminals of the first comparator U1 and the second comparator U2 also input a polarity reference voltage. The output terminals of the first comparator U1 and the second comparator U2 are connected to the timing controller 110. The first comparator U1 and the second comparator U2 respectively compare the voltages of the two data lines of each group and output comparison signals to the timing controller 110 respectively. The timing controller 110 selects to output the first channel selection signal TP1 and the second channel selection signal TP2 according to the received comparison signal, and controls the input selection switch 211 and the output selection switch 214 to switch to different switch states accordingly, thereby controlling the source driver circuit 200 to output grayscale voltage signals of corresponding polarity to each data line.

[0165] Example 6

[0166] The present invention also provides a display device, such as Figure 14 As shown, the display device includes a display panel 1 and a display panel driving circuit 2. The specific structure of the display panel driving circuit 2 is similar to the above-mentioned embodiment. Since the present display device adopts all the technical solutions of all the above-mentioned embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above-mentioned embodiments, and will not be described in detail here. The display panel 1 is connected to the display panel driving circuit 2.

[0167] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention, and should all be included in the scope of protection of the present invention.

Claims

1. A control method for a source driver circuit, characterized in that: The source driving circuit includes a plurality of driving units, each of which is connected one by one to a plurality of groups of data lines of the display panel, each group of data lines including two adjacent odd-numbered column data lines and two adjacent even-numbered column data lines, and the driving unit includes at least a positive polarity digital-to-analog converter, a negative polarity digital-to-analog converter, an input selection switch, an output selection switch, and a first charge sharing circuit; The control method of the source driving circuit includes: After the i-th frame ends, outputting a first channel selection signal to control the first charge sharing circuit to perform charge sharing on the two data lines of the corresponding group, and comparing the voltage signals on the two data lines after charge sharing with the polarity reference voltage respectively; When the grayscale voltage signal of a corresponding data line of each group is greater than the polarity reference voltage, in the (i+1)th frame, the first channel selection signal and the second channel selection signal are output successively to control the input selection switch and the output selection switch to switch to the first switch state and the second switch state successively, so as to convert the digital grayscale voltage signal input from the odd input terminal and / or the even input terminal into a positive polarity grayscale voltage signal through the positive polarity digital-to-analog converter and transmit the converted signal to the corresponding data line; When the grayscale voltage signal of a data line corresponding to each group is less than the polarity reference voltage, in the (i+1)th frame, the first channel selection signal and the second channel selection signal are output successively to control the input selection switch and the output selection switch to switch to the third switch state and the fourth switch state successively, so as to convert the digital grayscale voltage signal inputted from the odd input terminal and / or the even input terminal into a negative polarity grayscale voltage signal through the negative polarity digital-to-analog converter and transmit it to the corresponding data line.

2. The control method of the source driver circuit according to claim 1, wherein: The control method of the source driving circuit further includes: In the first frame, the output polarity switching control signal controls the input selection switch and the output selection switch to switch to the fifth switch state, so as to convert the digital grayscale voltage signals input from the odd input terminal and the even input terminal into positive polarity grayscale voltage signals and negative polarity grayscale voltage signals through the positive polarity digital-to-analog converter and the negative polarity digital-to-analog converter, respectively, and transmit them to the odd column data lines and the even column data lines; Every n1 frames, the output polarity switching control signal controls the input selection switch and the output selection switch to switch between the sixth switch state and the fifth switch state, so as to switch the polarity of the grayscale voltage signals of the two data lines of each group and the polarities of the two adjacent data lines of each group are opposite, where n1 is a positive integer.

3. The control method of the source driver circuit according to claim 1, wherein: The source driving circuit further includes a plurality of second charge sharing circuits, each of which is connected between two adjacent odd-numbered column data lines and even-numbered column data lines of two adjacent driving units; The control method of the source driving circuit further includes: After the (i+1)th frame ends, outputting a second channel selection signal to control the second charge sharing circuit to perform charge sharing on the two correspondingly connected data lines, and comparing the voltage signals on the two data lines after charge sharing with the polarity reference voltage respectively; When the grayscale voltage signal of a corresponding data line is greater than the polarity reference voltage, in the (i+2)th frame, the first channel selection signal and the second channel selection signal are output sequentially to control the input selection switch and the output selection switch to switch to the first switch state and the second switch state respectively, so as to convert the digital grayscale voltage signal input from the odd input terminal and / or the even input terminal into a positive polarity grayscale voltage signal through the positive polarity digital-to-analog converter and transmit the converted signal to the corresponding data line; When the grayscale voltage signal of a corresponding data line of each group is less than the polarity reference voltage, in the (i+2)th frame, the first channel selection signal and the second channel selection signal are output successively to control the input selection switch and the output selection switch to switch to the third switch state and the fourth switch state successively, so as to convert the digital grayscale voltage signal inputted from the odd input terminal and / or the even input terminal into a negative polarity grayscale voltage signal through the negative polarity digital-to-analog converter and transmit it to the corresponding data line.

4. The control method of the source driver circuit according to any one of claims 1 to 3, wherein: After the corresponding frame ends, before the grayscale voltage signals of the corresponding two data lines are charged and shared, the method further includes: Acquire the grayscale voltage signals of the next frame corresponding to the two data lines, and compare the voltage difference between the grayscale voltage signals of adjacent frames of the two data lines in each group with a preset difference; When the voltage difference between the two corresponding data lines is less than the preset difference, charge sharing is not performed, and the grayscale voltage signal of the next frame is output to the two corresponding data lines; When the voltage difference corresponding to at least one data line is greater than a preset difference, the grayscale voltage signals corresponding to the two data lines are charge-shared.

5. The control method of the source driver circuit according to claim 4, wherein: The preset difference is a difference between the grayscale voltage signal of the next frame and the polarity reference voltage.

6. A display panel driving circuit, characterized in that: The device comprises a timing control circuit and a source driving circuit connected to each other, wherein the source driving circuit comprises a plurality of driving units, wherein the plurality of driving units are connected one by one to a plurality of groups of data lines of the display panel, wherein each group of data lines comprises two adjacent odd-numbered data lines and two adjacent even-numbered data lines, and the driving units comprise at least a positive polarity digital-to-analog converter, a negative polarity digital-to-analog converter, an input selection switch, an output selection switch, and a first charge sharing circuit, wherein the first charge sharing circuit is connected between two adjacent odd-numbered data lines and two adjacent even-numbered data lines in each group; The source driving circuit further includes a plurality of second charge sharing circuits, each of which is connected between two adjacent odd-numbered column data lines and even-numbered column data lines of two adjacent driving units; A timing control circuit, used to implement the control method of the source driver circuit according to any one of claims 1 to 5.

7. The display panel driving circuit according to claim 6, wherein: The first charge sharing circuit includes a first switch, a second switch, and a third switch, wherein a first end of the first switch is connected to a first output end of an output selection switch of a driving unit, a first end of the second switch is connected to a second output end of an output selection switch of a driving unit, a second end of the first switch and a first end of the third switch are connected to odd-numbered columns of data lines in a corresponding group of data lines, and a second end of the second switch and a second end of the third switch are connected to even-numbered columns of data lines in a corresponding group of data lines; The second charge sharing circuit includes a fourth switch connected between two adjacent odd-numbered column data lines and an even-numbered column data line of two adjacent driving units.

8. The display panel driving circuit according to claim 6 or 7, wherein: The timing control circuit includes a multi-channel comparison circuit and a timing controller; Each comparison circuit is connected to the two data lines and the source driver circuit of each group, and the comparison circuit is used to compare the voltage signals of the two data lines with the polarity reference voltage respectively, and output a comparison signal to control the source driver circuit to output a grayscale voltage signal of corresponding polarity to the two adjacent data lines of each group; The timing controller is connected to the multi-channel comparison circuit and the source driving circuit respectively, and is used to obtain the comparison signal and control the source driving circuit to implement the source driving circuit control method according to any one of claims 1 to 5.

9. The display panel driving circuit according to claim 8, wherein: The comparison circuit includes a first comparator and a second comparator; The first comparator is connected to one of the data lines of each group, and the second comparator is connected to the other data line of each group. The reference voltage ends of the first comparator and the second comparator also input polarity reference voltages, and the output ends of the first comparator and the second comparator are connected to the timing controller.

10. A display device, characterized in that: The device comprises a display panel and a display panel driving circuit according to any one of claims 6 to 9, wherein the display panel is connected to the display panel driving circuit.

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