Apparatus and method for managing threshold voltage drift of selector device

Abstract

An apparatus is provided that includes a memory cell and a control circuit coupled to the memory cell. The memory cell includes a reversible resistance-switching memory element coupled in series with a selector element, the selector element having a threshold voltage. The control circuit is configured to access the memory cell for a first time using a first pulse having a first polarity and to access the memory cell for a second time using a second pulse having the first polarity. The first pulse is configured to reduce a threshold voltage drift rate of the selector element.

Description

BACKGROUND OF THE INVENTION

[0001] Memories are widely used in various electronic devices such as cellular phones, digital cameras, personal digital assistants, medical electronics, mobile computing devices, non-mobile computing devices, and data servers. Memories can be non-volatile memories or volatile memories. Non-volatile memories allow storage and retention of information even when not connected to a power source (e.g., a battery).

[0002] One example of a non-volatile memory is a magnetoresistive random access memory (MRAM), which uses magnetization to represent stored data as compared to some other memory technologies that use electric charge to store data. Generally, an MRAM includes a large number of magnetic memory cells formed on a semiconductor substrate, where each memory cell represents a data bit.

[0003] Data bits are written to the memory cells by changing the magnetization direction of magnetic elements within the memory cells, and bits are read by measuring the resistance of the memory cells (low resistance generally represents a "0" bit, and high resistance generally represents a "1" bit). As used herein, the magnetization direction is the direction of the orientation of the magnetic moment. Some memory cells may include selector devices such as two-way threshold switches or other selector devices.

[0004] Although MRAM is a promising technology, there are still many design and process challenges. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figures 1A to 1H Various embodiments of a memory system are depicted.

[0006] Figure 2A An embodiment of a portion of a three-dimensional memory array is depicted.

[0007] Figure 2B Depicts Figure 2A an embodiment of a memory cell of a three-dimensional memory array.

[0008] Figure 2C Depicts Figure 2B exemplary current-voltage characteristics of a threshold selector device.

[0009] Figures 3A to 3B An embodiment of a cross-point memory array is depicted.

[0010] Figure 4 An exemplary read and write sequence for determining the bit error rate of one or more memory cells in a memory array is depicted.

[0011] Figure 5A Two consecutive self-reference read operations separated by bit access time are depicted.

[0012] Figure 5B Depicts a graph showing the relationship between the average bit error rate and the bit access time.

[0013] Figure 5C Depicts a graph showing the relationship between exemplary threshold voltage values of a population of memory cells and the delay.

[0014] Figure 5D Depicts a graph showing the relationship between other exemplary threshold voltage values of a population of memory cells and the delay.

[0015] Figure 6A Depicts two consecutive self - reference read operations separated by a bit access time interval.

[0016] Figure 6B Depicts two alternative consecutive self - reference read operations separated by a bit access time interval.

[0017] Figure 7 Depicts an embodiment of the read and write sequence of the present technology.

[0018] Figure 8 Depicts another embodiment of the read and write sequence of the present technology.

[0019] Figure 9 Depicts a graph showing the relationship between yet other exemplary threshold voltage values of a population of memory cells and the delay.

[0020] Figure 10 Depicts an embodiment of a gate control signal superimposed on a pre - read pulse.

[0021] Figure 11 Depicts yet another embodiment of the read and write sequence of the present technology.

[0022] Figure 12 Is a flowchart of an embodiment of a method for determining the bit error rate of a plurality of memory cells.

[0023] Figure 13 Is a flowchart of another embodiment of a method for determining the bit error rate of a plurality of memory cells.

[0024] Figure 14 Is a flowchart of yet another embodiment of a method for determining the bit error rate of a plurality of memory cells. Detailed Description

[0025] Describes techniques for managing threshold voltage drift in memory cells, where the memory cells include a memory element serially coupled with a selector device. In some embodiments, the memory cell may include a threshold selector device (such as a two-way threshold switch) that has a threshold voltage that varies over time after accessing the threshold selector device. In some embodiments, the memory cell may include a threshold selector device (such as a two-way threshold switch) that has a threshold voltage that increases in magnitude (e.g., drifts higher) over time after accessing the threshold selector device. In some embodiments, the memory cell may include a threshold selector device (such as a two-way threshold switch) that has a threshold voltage that increases in magnitude after accessing the threshold selector device with access pulses of opposite polarities. The effect of threshold voltage drift and / or the increase in threshold voltage magnitude is that the memory state of the memory element may be disturbed during a read operation, resulting in an increase in the bit error rate as the bit access time increases.

[0026] In one embodiment, a post-set pulse is used to manage threshold voltage drift after each SET pulse applied to the memory cell. In one embodiment, the post-set pulse turns the selector device on and off and has a polarity opposite to that of the SET pulse.

[0027] In another embodiment, shortly before each read access, a pre-read pulse is used to turn the selector device on and off. In one embodiment, the pre-read pulse has the same polarity as the read access.

[0028] In yet another embodiment, in another embodiment, a polarity-switching bit access pulse is used to turn the selector device on and off shortly before each read access. In one embodiment, the polarity-switching bit access pulse has a polarity opposite to that of the read access.

[0029] In one embodiment, the memory cell includes a memory element serially coupled with a selector device. In one embodiment, the memory element is a magnetic memory element. In one embodiment, the memory element is a magnetic tunnel junction memory element. In one embodiment, the selector device is a two-way threshold switch.

[0030] In one embodiment, the memory cells within a memory array may include non-volatile memory cells that include reversible resistive switching elements. The reversible resistive switching elements may include a reversible resistivity switching material that has a resistivity that can be reversibly switched between two or more states.

[0031] In one embodiment, the reversible resistive switching material may include a metal oxide, a solid electrolyte, a phase change material, a magnetic material, or other similar resistivity switching materials. A variety of metal oxides may be used, such as transition metal oxides. Examples of metal oxides include, but are not limited to, NiO, Nb2O5, TiO2, HfO2, Al2O3, MgO x , CrO2, VO, BN, TaO2, Ta2O3, and AlN.

[0032] In one embodiment, the non-volatile memory cells within the memory array include one-time programmable memory cells. In one embodiment, the non-volatile memory cells within the memory array include rewritable memory cells.

[0033] Figure 1A An embodiment of a memory system 100 and a host 102 is depicted. The memory system 100 may include a non-volatile storage system connected to the host 102 (e.g., a mobile computing device or a server) via an interface. In some cases, the memory system 100 may be embedded within the host 102. As an example, the memory system 100 may be a memory card, a solid state drive (SSD) (such as a high density MLC SSD (e.g., 2-bit / cell or 3-bit / cell) or a high performance SLC SSD), or a hybrid HDD / SSD drive.

[0034] As shown, the memory system 100 includes a memory chip controller 104 and a memory chip 106. The memory chip 106 may include volatile memory and / or non-volatile memory. Although a single memory chip is depicted, the memory system 100 may include more than one memory chip. The memory chip controller 104 may receive data and commands from the host 102 and provide memory chip data to the host 102.

[0035] The memory chip controller 104 may include one or more of a control circuit, a state machine, page registers, SRAM, a decoder, a sense amplifier, read / write circuitry, and / or a controller, or any combination thereof, for controlling the operation of the memory chip 106. One or more of the control circuit, state machine, page registers, SRAM, decoder, sense amplifier, read / write circuitry, and / or controller for controlling the operation of the memory chip may be referred to as management or control circuitry. The management or control circuitry may facilitate one or more memory array operations, including formation, erase, program, or read operations.

[0036] In some embodiments, a management or control circuit (or a portion of the management or control circuit) for facilitating the operation of one or more memory arrays may be integrated within the memory chip 106. The memory chip controller 104 and the memory chip 106 may be disposed on a single integrated circuit or on a single die. In other embodiments, the memory chip controller 104 and the memory chip 106 may be disposed on different integrated circuits. In some cases, the memory chip controller 104 and the memory chip 106 may be integrated on a system board, a logic board, or a PCB.

[0037] The memory chip 106 includes a memory core control circuit 108 and a memory core 110. The memory core control circuit 108 may include logic for controlling the selection of memory blocks (or arrays) within the memory core 110, controlling the generation of voltage references for biasing a particular memory array into a read or write state, and generating row and column addresses.

[0038] The memory core 110 may include one or more two-dimensional arrays of memory cells and / or one or more three-dimensional arrays of memory cells. In one embodiment, the memory core may include rewritable memory cells, one-time programmable memory cells, and / or multiple-time programmable memory cells or any combination thereof.

[0039] In one embodiment, the memory core control circuit 108 and the memory core 110 may be disposed on a single integrated circuit. In other embodiments, the memory core control circuit 108 (or a portion of the memory core control circuit 108) and the memory core 110 may be disposed on different integrated circuits.

[0040] When the host 102 sends an instruction to the memory chip controller 104 indicating that the host 102 wants to read data from or write data to the memory system 100, a memory operation may be initiated. In the case of a write (or programming) operation, the host 102 may send a write command and the data to be written to the memory chip controller 104.

[0041] The memory chip controller 104 may cache the data to be written and may generate error correction code (ECC) data corresponding to the data to be written. ECC data that enables detection and / or correction of data errors that occur during transmission or storage may be written to the memory core 110 or stored in non-volatile memory within the memory chip controller 104. In one embodiment, ECC data is generated by circuitry within the memory chip controller 104 and data errors are corrected.

[0042] The memory chip controller 104 can control the operation of the memory chip 106. In one example, before issuing a write operation to the memory chip 106, the memory chip controller 104 can check the status register to ensure that the memory chip 106 is capable of accepting the data to be written.

[0043] In another example, before issuing a read operation to the memory chip 106, the memory chip controller 104 can pre-read the overhead information associated with the data to be read. The overhead information can include ECC data associated with the data to be read or a redirect pointer pointing to a new memory location within the memory chip 106 where the requested data is read.

[0044] Once the memory chip controller 104 initiates a read or write operation, the memory core control circuit 108 can generate appropriate bias voltages and / or currents for the word lines and bit lines within the memory core 110, and generate appropriate memory block, row, and column addresses.

[0045] Figure 1B An implementation of the memory core control circuit 108 is shown. In one implementation, the memory core control circuit 108 includes an address decoder 120, a voltage generator 122 for selected control lines, and a voltage generator 124 for unselected control lines. The control lines can include word lines, bit lines, or a combination of word lines and bit lines. The selected control lines can include selected word lines or selected bit lines for placing memory cells in a selected state. The unselected control lines can include unselected word lines or unselected bit lines for placing memory cells in an unselected state.

[0046] The voltage generator (or voltage regulator) 122 for selected control lines can include one or more voltage generators for generating selected control line voltages. The voltage generator 124 for unselected control lines can include one or more voltage generators for generating unselected control line voltages. The address decoder 120 can generate a memory block address, as well as row and column addresses for a specific memory block.

[0047] Figures 1C to 1F An implementation of the memory core organization is depicted, which includes a memory core 110 having a plurality of memory compartments, and each memory compartment having a plurality of memory blocks. Although a memory core organization is disclosed where memory compartments include memory blocks, and memory blocks include a set of memory cells, other organizations or groupings can also be used with the techniques described herein.

[0048] Figure 1C Depicted is Figure 1AEmbodiments of the memory core 110. As depicted, the memory core 110 includes memory compartments 130 and 132. In some embodiments, the number of memory compartments for each memory core may vary for different implementations. For example, a memory core may include only a single memory compartment or multiple memory compartments (e.g., 16 memory compartments, 256 memory compartments, etc.).

[0049] Figure 1D depicts Figure 1C An embodiment of the memory compartment 130. As depicted, the memory compartment 130 includes memory blocks 140 - 144 and read / write circuitry 150. In some embodiments, the number of memory blocks for each memory compartment may vary for different implementations. For example, a memory compartment may include one or more memory blocks (e.g., 32 memory blocks per memory compartment).

[0050] The read / write circuitry 150 includes circuitry for reading from and writing to memory cells within the memory blocks 140 - 144. As depicted, the read / write circuitry 150 may be shared among multiple memory blocks within the memory compartment. This enables a reduction in chip area because a single set of read / write circuitry 150 can be used to support multiple memory blocks. However, in some embodiments, only a single memory block may be electrically coupled to the read / write circuitry 150 at a given time to avoid signal conflicts.

[0051] In some embodiments, the read / write circuitry 150 may be used to write one or more pages of data to the memory blocks 140 - 144 (or to a subset of the memory blocks). The memory cells within the memory blocks 140 - 144 may allow for direct rewriting of a page (i.e., data representing a page or a portion of a page can be written to the memory blocks 140 - 144 without the need to perform an erase or reset operation on the memory cells prior to writing the data).

[0052] In one example, Figure 1A the memory system 100 may receive a write command that includes a target address and a set of data to be written to the target address. The memory system 100 may perform a read - before - write (RBW) operation to read the data currently stored at the target address before performing the write operation of writing the set of data to the target address. The memory system 100 may then determine whether a particular memory cell is to remain in its current state (i.e., the memory cell is already in the correct state), needs to be set to the "0" state, or needs to be reset to the "1" state.

[0053] After that, the memory system 100 may write a first subset of memory cells to the "0" state and then write a second subset of memory cells to the "1" state. Memory cells that are already in the correct state may be skipped, thereby increasing the programming speed and reducing the cumulative voltage stress applied to unselected memory cells.

[0054] By applying a first voltage difference to a specific memory cell at a first polarity (e.g., +1.5V), the specific memory cell may be set to the "1" state. By applying a second voltage difference to the specific memory cell at a second polarity opposite to the first polarity (e.g., -1.5V), the specific memory cell may be reset to the "0" state.

[0055] In some cases, the read / write circuit 150 may be used to program a specific memory cell to be in one of three or more data / resistance states (i.e., the specific memory cell may include multi-level memory cells). In one example, the read / write circuit 150 may apply a first voltage difference (e.g., 2V) to a specific memory cell to program the specific memory cell to a first state among three or more data / resistance states, or apply a second voltage difference (e.g., 1V) less than the first voltage difference to the specific memory cell to program the specific memory cell to a second state among three or more data / resistance states.

[0056] Applying a smaller voltage difference to a specific memory cell may cause the specific memory cell to be partially programmed or programmed at a slower rate than when a larger voltage difference is applied. In another example, the read / write circuit 150 may apply a first voltage difference to a specific memory cell within a first time period (e.g., 150 ns) to program the specific memory cell to a first state among three or more data / resistance states, or apply the first voltage difference to the specific memory cell within a second time period (e.g., 50 ns) less than the first time period. One or more programming pulses followed by a memory cell verification phase may be used to program the specific memory cell to be in the correct state.

[0057] Figure 1E Depicts Figure 1D One embodiment of the memory block 140 is depicted. As depicted, the memory block 140 includes a memory array 160, a row decoder 162, and a column decoder 164. The memory array 160 may include a continuous group of memory cells having continuous word lines and bit lines. The memory array 160 may include one or more memory cell layers and may include a two-dimensional memory array and / or a three-dimensional memory array.

[0058] The row decoder 162 decodes the row address and selects a specific word line in the memory array 160 when appropriate (e.g., when reading from or writing to a memory cell in the memory array 160). The column decoder 164 decodes the column address and selects a specific set of bit lines in the memory array 160 to be electrically coupled to a read / write circuit, such as Figure 1D the read / write circuit 150. In one embodiment, the number of word lines per memory layer is 4K, the number of bit lines per memory layer is 1K, and the number of memory layers is 4, which provides a memory array 160 that includes 16M memory cells. Other numbers of word lines per layer, bit lines per layer, and number of layers may be used.

[0059] Figure 1F An embodiment of the memory compartment 170 is depicted. The memory compartment 170 is Figure 1D an example of an alternative specific implementation of the memory compartment 130. In some embodiments, the row decoder, column decoder, and read / write circuit may be separated or shared among memory arrays. As depicted, the row decoder 172 is shared between the memory arrays 174 and 176 because the row decoder 172 controls the word lines in both the memory arrays 174 and 176 (i.e., the word lines driven by the row decoder 172 are shared).

[0060] The row decoders 178 and 172 may be separate such that the even word lines in the memory array 174 are driven by the row decoder 178 and the odd word lines in the memory array 174 are driven by the row decoder 172. The column decoders 180 and 182 may be separate such that the even bit lines in the memory array 174 are controlled by the column decoder 182 and the odd bit lines in the memory array 174 are controlled by the column decoder 180.

[0061] The selected bit lines controlled by the column decoder 180 may be electrically coupled to the read / write circuit 184. The selected bit lines controlled by the column decoder 182 may be electrically coupled to the read / write circuit 186. Separating the read / write circuit into the read / write circuits 184 and 186 when the column decoder is separated may allow for a more efficient layout of the memory compartment.

[0062] The row decoders 188 and 172 may be separate such that the even word lines in the memory array 176 are driven by the row decoder 188 and the odd word lines in the memory array 176 are driven by the row decoder 172. The column decoders 190 and 192 may be separate such that the even bit lines in the memory array 176 are controlled by the column decoder 192 and the odd bit lines in the memory array 176 are controlled by the column decoder 190.

[0063] The selected bit lines controlled by column decoder 190 can be electrically coupled to read / write circuit 184. The selected bit lines controlled by column decoder 192 can be electrically coupled to read / write circuit 186. Separating the read / write circuit into read / write circuits 184 and 186 when the column decoder is separated can allow for a more efficient layout of the memory compartments.

[0064] Figure 1G depicts an embodiment of a schematic diagram (including word lines and bit lines) corresponding to Figure 1F memory compartments 170 in. As depicted, word lines WL1, WL3, and WL5 are shared between memory arrays 174 and 176 and are controlled by Figure 1F row decoder 172 of. Word lines WL0, WL2, WL4, and WL6 are driven from the left side of memory array 174 and are controlled by Figure 1F row decoder 178 of. Word lines WL14, WL16, WL18, and WL20 are driven from the right side of memory array 176 and are controlled by Figure 1F row decoder 188 of.

[0065] Bit lines BL0, BL2, BL4, and BL6 are driven from the bottom of memory array 174 and are controlled by Figure 1F column decoder 182 of. Bit lines BL1, BL3, and BL5 are driven from the top of memory array 174 and are controlled by Figure 1F column decoder 180 of. Bit lines BL7, BL9, BL11, and BL13 are driven from the bottom of memory array 176 and are controlled by Figure 1F column decoder 192 of. Bit lines BL8, BL10, and BL12 are driven from the top of memory array 176 and are controlled by Figure 1F column decoder 190 of.

[0066] In one embodiment, memory arrays 174 and 176 can include memory layers that are oriented in a plane horizontal to the support substrate. In another embodiment, memory arrays 174 and 176 can include memory layers that are oriented in a plane vertical to the support substrate (i.e., the vertical plane is substantially perpendicular to the support substrate). In this case, the bit lines of the memory array can include substantially vertical bit lines.

[0067] Figure 1H depicts an embodiment of a schematic diagram (including word lines and bit lines) corresponding to a memory compartment arrangement where word lines and bit lines are shared between memory blocks and both the row decoder and the column decoder are separated. Sharing word lines and / or bit lines helps to reduce the layout area because a single row decoder and / or column decoder can be used to support two memory arrays.

[0068] As depicted, word lines WL1, WL3, and WL5 are shared between memory arrays 200 and 202. Bit lines BL1, BL3, and BL5 are shared between memory arrays 200 and 204. Word lines WL8, WL10, and WL12 are shared between memory arrays 204 and 206. Bit lines BL8, BL10, and BL12 are shared between memory arrays 202 and 206.

[0069] The row decoders are separated such that word lines WL0, WL2, WL4, and WL6 are driven from the left side of memory array 200, and word lines WL1, WL3, and WL5 are driven from the right side of memory array 200. Similarly, word lines WL7, WL9, WL11, and WL13 are driven from the left side of memory array 204, and word lines WL8, WL10, and WL12 are driven from the right side of memory array 204.

[0070] The column decoders are separated such that bit lines BL0, BL2, BL4, and BL6 are driven from the bottom of memory array 200, and bit lines BL1, BL3, and BL5 are driven from the top of memory array 200. Similarly, bit lines BL7, BL9, BL11, and BL13 are driven from the bottom of memory array 202, and bit lines BL8, BL10, and BL12 are driven from the top of memory array 202. Separating the row and / or column decoders also helps to alleviate layout constraints (e.g., the column decoder pitch can be reduced by 2x because the separated column decoders only need to drive every other bit line instead of each bit line).

[0071] Figure 2A An embodiment depicting a portion of a monolithic three-dimensional memory array 210 is shown, which includes a first memory layer 212 and a second memory layer 214 located above the first memory layer 212. Memory array 210 is Figure 1E a specific implementation example of memory array 160 in . Word lines 216 and 218 are arranged in a first direction, and bit lines 220 are arranged in a second direction perpendicular to the first direction. As depicted, the upper conductors of the first memory layer 212 can be used as the lower conductors of the second memory layer 214. In a memory array having additional layers of memory cells, there will be corresponding additional layers of bit lines and word lines.

[0072] The memory array 210 includes a plurality of memory cells 222. In one embodiment, the memory cells 222 can include rewritable memory cells, one-time programmable memory cells, and multi-time programmable memory cells. In one embodiment, each of the memory cells 222 is vertically oriented. The memory cells 222 can include non-volatile memory cells or volatile memory cells. Relative to the first memory layer 212, a first portion of the memory cells 222 is located between the word lines 216 and the bit lines 220 and is connected to these word lines and bit lines. Relative to the second memory layer 214, a second portion of the memory cells 222 is located between the word lines 218 and the bit lines 220 and is connected to these word lines and bit lines.

[0073] In one embodiment, each memory cell 222 includes a selector element serially coupled to a resistive switching memory element, where each memory cell 222 represents one data bit. In one embodiment, the resistive switching memory element can be a magnetic memory element, a ReRAM memory element, a phase change memory element, or other types of resistive switching memory elements.

[0074] In one embodiment, each memory cell 222 includes a selector element serially coupled to a magnetic memory element, where each memory cell 222 represents one data bit. Figure 2B is a simplified schematic diagram of the memory cell 222a, which is a Figure 2A exemplary embodiment of the memory cell 222.

[0075] In one embodiment, the memory cell 222a includes a selector element S x serially coupled to a magnetic memory element M x , both of which are coupled between a first terminal T1 and a second terminal T2. In one embodiment, the memory cell 222a is vertically oriented. In Figure 2B the embodiment, the magnetic memory element M x is disposed above the selector element S x . In other embodiments, the selector element S x can be disposed above the magnetic memory element M x .

[0076] In one embodiment, the magnetic memory element M x is a magnetic tunnel junction, and the selector element S x is a threshold selector device. In one embodiment, the selector element S x is a conductive bridge threshold selector device. In other embodiments, the selector element S xis a two-way threshold switch (e.g., binary SiTe, CTe, BTe, AlTe, etc., or ternary types such as AsTeSi, AsTeGe, or AsTeGeSiN, etc.), a metal-insulator transition (MIT) of the phase change material type (e.g., VO2, NbO2, etc.), or other similar threshold selector devices.

[0077] In one embodiment, the magnetic memory element M x includes an upper ferromagnetic layer 230, a lower ferromagnetic layer 232, and a tunnel barrier (TB) 234, which is an insulating layer between the two ferromagnetic layers. In this example, the lower ferromagnetic layer 232 is a free layer (FL) whose magnetization direction can be switched. The upper ferromagnetic layer 230 is a pinned (or fixed) layer (PL) whose magnetization direction is not easily changed.

[0078] In other embodiments, compared with the Figure 2B layers depicted in, the magnetic memory element M x may include fewer, additional, or different layers. In other embodiments, the lower ferromagnetic layer 232 is a pinned layer (PL), and the upper ferromagnetic layer 230 is a free layer (FL).

[0079] When the magnetization direction in the free layer 232 is parallel to the magnetization direction of the pinned layer 230, the memory element M x has a relatively low resistance (referred to herein as the "P state"), and when the magnetization direction in the free layer 232 is antiparallel to the magnetization direction of the pinned layer 230, the memory element M x has a relatively high resistance (referred to herein as the "AP state").

[0080] In one embodiment, the data state ("0" or "1") of the magnetic memory element M is read by measuring the resistance of the magnetic memory element M x . By design, both the parallel configuration and the antiparallel configuration remain stable during the rest state and / or the read operation (at a sufficiently low read current). x

[0081] In one embodiment, the selector element S x is a two-way threshold switch that includes a first region 236 and optionally includes a second region 238 disposed above the first region 236. In one embodiment, the first region 236 is a SiTe alloy, and the optional second region 238 is carbon nitride. Other materials can be used for the first region 236 and the optional second region 238. In other embodiments, the selector element S x is a conductive bridge threshold selector element. In one embodiment, the first region 236 is a solid electrolyte region, and the second region 238 is an ion source region.

[0082] Figure 2C is a graph depicting exemplary current - voltage (I - V) characteristics of a threshold selector device S x Each threshold selector device S x is initially in a high - resistance (off) state. To operate the threshold selector device S x as a threshold switch, an initial forming operation may be necessary such that the threshold selector device S x operates within a current range where switching can occur.

[0083] For example, the forming operation may include applying one or more voltage pulses to the threshold selector device S x each having an amplitude greater than or equal to a forming voltage V FORM . After the forming operation, the threshold selector device S x can be turned on and off and can be used as a unipolar or bipolar threshold selector device. Thus, the threshold selector device S x can be referred to as a bipolar threshold selector device.

[0084] In Figure 2C the exemplary I - V characteristics, for a positive applied voltage, the threshold selector device S x remains in a high - resistance state (HRS) (e.g., off) until the voltage across the device meets or exceeds a first threshold voltage V TP (i.e., has a more positive value than the first threshold voltage), at which point the threshold selector device S x switches to a low - resistance state (LRS) (e.g., on). The threshold selector device S x remains on until the voltage across the device drops to or below a first holding voltage V HP , at which point the threshold selector device S disconnects.

[0085] For a negative applied voltage, the threshold selector device S x remains in the HRS (e.g., off) until the voltage across the device meets or exceeds a second threshold voltage V TN , (i.e., has a less negative value than the second threshold voltage), at which point the threshold selector device S switches to the LRS (e.g., on). The threshold selector device S x remains on until the voltage across the device increases to or exceeds a second holding voltage V HN (i.e., has a more negative value than the second holding voltage), at which point the threshold selector device S x disconnects.

[0086] Referring again to Figure 2B , in one embodiment, a magnetic memory element M xUsing spin-transfer torque (STT) switching. To "set" the bit value of magnetic memory element M x a write current is applied from first terminal T1 to second terminal T2. Electrons in the write current become spin-polarized as they pass through pinned layer 230 since pinned layer 230 is a ferromagnetic metal.

[0087] A substantial majority of the conduction electrons in a ferromagnet will have a spin orientation parallel to the magnetization direction, which gives rise to a net spin-polarized current. (Electron spin refers to angular momentum, which is proportional to the electron magnetic moment but in the direction antiparallel, but for the sake of discussion, this difference in direction will no longer be used.)

[0088] When the spin-polarized electrons tunnel through TB 234, conservation of angular momentum can result in a torque being applied to both free layer 232 and pinned layer 230, but this torque is not sufficient (by design) to affect the magnetization direction of pinned layer 230. Instead, if the initial magnetization direction of free layer 232 is antiparallel to pinned layer 230, this torque (by design) is sufficient to switch the magnetization direction of free layer 232 to be parallel to the magnetization direction of pinned layer 230. Then, the parallel magnetization will remain stable before and after such a write current is turned off.

[0089] In contrast, if the free layer 232 magnetization and the pinned layer 230 magnetization are initially parallel, the magnetization direction of free layer 232 can be switched by STT to be antiparallel to the magnetization direction of pinned layer 230 by applying a write current in the opposite direction to that in the above case. Thus, by the same STT physical mechanism, the magnetization direction of free layer 232 can be deterministically set to either of two stable orientations by wisely choosing the write current direction (polarity).

[0090] In the above example, spin-transfer torque (STT) switching is used to "set" the bit value of magnetic memory element M x In other embodiments, field-induced switching, spin-orbit torque (SOT) switching, VCMA (magnetoelectric) switching, or other switching techniques may be employed.

[0091] Figures 3A to 3B is a simplified schematic diagram of an exemplary cross-point memory array 300 that includes a first memory layer 300a and a second memory layer 300b located above the first memory layer 300a. The cross-point memory array 300 is Figure 1E an example of a specific implementation of memory array 160 in. The cross-point memory array 300 may include more than two memory layers.

[0092] The cross-point memory array 300 includes word lines WL1a, WL2a, WL3a, WL1b, WL2b, and WL3b, and bit lines BL1, BL2, and BL3. The first memory layer 300a includes memory cells 302 coupled to the word lines WL1a, WL2a, WL3a and the bit lines BL1, BL2, and BL3 11a 、302 12a ……302 33a and the second memory layer 300b includes memory cells 302 coupled to the word lines WL1b, WL2b, WL3b and the bit lines BL1, BL2, and BL3 11b 、302 12b ……302 33b 。In one embodiment, the memory cells 302 11a 、302 12a ……302 33a are each vertically oriented. In one embodiment, the memory cells 302 11b 、302 12b ……302 33b are each vertically oriented.

[0093] The first memory layer 300a is Figure 2B a specific implementation example of the first memory layer 212 of the monolithic three-dimensional memory array 210, and the second memory layer 300b is Figure 2B a specific implementation example of the second memory layer 214 of the monolithic three-dimensional memory array 210. In one embodiment, the memory cells 302 11a 、302 12a ……302 33a 、302 11b 、302 12b ……302 33b are each Figure 2B a specific implementation of the memory cell 222a.

[0094] Those of ordinary skill in the art will understand that the cross-point memory array 300 may include more or fewer than six word lines, more or fewer than three bit lines, and more or fewer than eighteen memory cells 302 11a 、302 12a ……302 33a 、302 11b 、302 12b ……302 33b 。In some embodiments, the cross-point memory array 300 may include 1000×1000 memory cells, although other array sizes may also be used.

[0095] Each memory cell 30211a , 302 12a ……302 33a , 302 11b , 302 12b ……302 33b is coupled to one of the word lines and one of the bit lines, and respectively includes corresponding magnetic memory elements M 11a , M 12a ……M 33a , M 11b , M 12b ……M 33b , and these magnetic memory elements are respectively coupled in series to corresponding selector elements S 11a , S 12a ……S 33a , S 11b , S 12b ……S 33b above or below. In one embodiment, the magnetic memory elements M 11a , M 12a ……M 33a , M 11b , M 12b ……M 33b each of which is Figure 2B a specific implementation of the magnetic memory element M x of, and the selector elements S 11a , S 12a ……S 33a , S 11b , S 12b ……S 33b each of which is Figure 2B a specific implementation of the selector element S x of.

[0096] Each memory cell 302 11a , 302 12a ……302 33a has a first terminal coupled to one of the bit lines BL1, BL2, BL3 and a second terminal coupled to one of the word lines WL1a, WL2a, WL3a, and each memory cell 302 11b , 302 12b ……302 33b has a first terminal coupled to one of the bit lines BL1, BL2, BL3 and a second terminal coupled to one of the word lines WL1b, WL2b, WL3b. For example, the memory cell 302 13a includes a magnetic memory element M 13a coupled in series with a selector element S 13a, and includes a first terminal coupled to bit line BL3 and a second terminal coupled to word line WL1a..

[0097] Similarly, memory cell 302 22b includes a magnetic memory element M 22b coupled in series with selector element S 22b , and includes a first terminal coupled to bit line BL2 and a second terminal coupled to word line WL2b. Similarly, memory cell 302 33a includes a magnetic memory element M 33a coupled in series with selector element S 33a , and includes a first terminal coupled to bit line BL3 and a second terminal coupled to word line WL3a.

[0098] Magnetic memory element M 11a 、M 12a ……M 33a can be respectively disposed above or below the corresponding selector elements S 11a 、S 12a ……S 33a , and magnetic memory element M 11b 、M 12b ……M 33b can be respectively disposed above or below the corresponding selector elements S 11b 、S 12b ……S 33b .

[0099] In one embodiment, the memory cells 302 11a 、302 12a ……302 33a in the first memory layer 300a are oriented opposite to the memory cells 302 11b 、302 12b ……302 33b in the second memory layer 300b.

[0100] In another embodiment, the memory cells 302 11a 、302 12a ……302 33a in the first memory layer 300a are oriented opposite to the memory cells 302 11b 、302 12b ……302 33b in the second memory layer 300b.

[0101] Referring again to Figure 1A, in one embodiment, memory core 110 may include one or more two-dimensional arrays of memory cells or one or more three-dimensional arrays of memory cells. In one embodiment, memory core 110 may include rewritable memory cells, once-programmable memory cells, and / or multiple-programmable memory cells or any combination thereof.

[0102] A measure of the performance of one or more memory cells is the bit error rate. In one embodiment, the bit error rate of one or more memory cells is determined by the following steps: writing various data values to the memory cells; reading the written data values from the memory cells; determining the number of times the read values are different from the written values; and then dividing the number of read failures by the total number of reads performed.

[0103] Reference Figure 4 , depicts an exemplary read and write sequence 400 for determining the bit error rate of one or more memory cells in a memory array (such as any of the memory arrays 160, 174, 176, 200, 202, 204, 206, 210, or 300 described above). Specifically, read and write sequence 400 depicts the voltage versus time relationship on a memory cell that includes a memory cell having a selector element serially coupled to a magnetic memory element (such as Figure 2B memory cell 222a). For simplicity, the following description refers to the voltage on the memory cell as the "word line voltage".

[0104] As described in more detail below, in Figure 4 the example depicted, read operations are performed using pulses having a first (e.g., positive) polarity, RESET operations are performed using pulses having the first polarity, and SET operations are performed using pulses having a second (e.g., negative) polarity opposite to the first polarity. Those of ordinary skill in the art will understand that, alternatively, the first polarity may be negative and the second polarity may be positive.

[0105] In one embodiment, the memory cell includes a two-way threshold switch selector element S x serially coupled to a magnetic memory element M x . For simplicity, the remaining description will use the phrase two-way threshold switch S x . Those of ordinary skill in the art will understand that the principles described below apply to any type of selector element having the characteristics described below, which are the same as the characteristics of the two-way threshold switch.

[0106] In one embodiment, each read in read and write sequence 400 is a self-reference read. In an exemplary self-reference read technique, a memory cell is first read, then written to a first memory state, a second read is performed, and then the results of the first read and the second read are compared. If the two read results are the same, it is determined that the memory cell was initially in the first memory state and has remained in the first memory state. However, if the two read results are different, it is determined that the memory cell was initially in the second memory state but is now in the first memory state.

[0107] Reference Figure 4 and Figure 2B where the symbol "P" indicates that the magnetization direction of the memory element M of the memory cell is parallel to the magnetization direction of the pinned layer 230 (and the memory element M x has a relatively low resistance), and the symbol "AP" indicates that the magnetization direction of the memory element M of the memory cell is antiparallel to the magnetization direction of the pinned layer 230 (and the memory element M x has a relatively high resistance). x has a relatively high resistance). x

[0108] Before time t0, the word line voltage is the initial voltage V i (e.g., 0 volts). Between time t0 and time t5, a self-reference read operation is performed. Specifically, starting at time t0, the word line voltage begins to increase above the initial voltage V i . The word line voltage is below the first threshold voltage V TP , and the bidirectional threshold switch S x is off.

[0109] At time t1, the word line voltage equals the first threshold voltage V TP , and the bidirectional threshold switch S x turns on. The voltage across the bidirectional threshold switch S x drops to a value herein referred to as "V offset ", and the remaining word line voltage across the memory element M of the memory cell x drops.

[0110] Between time t1 and time t2, a first read operation RD1 is performed. During the first read operation, a current source generates a first current and a current mirror current coupled to the current source, and the memory cell increases the voltage across the memory cell to conduct the first current through the memory cell. In one embodiment, the first current is approximately 15 μA and has a pulse width between approximately 25 ns and 50 ns, although larger or smaller current values and larger or smaller pulse widths may be used. The voltage across the memory cell equals the first current multiplied by the resistance of the memory element M x . InFigure 4 In the example depicted in x , the magnetization direction of the memory element M a is P, and the word line voltage has a value V

[0111] Between times t2 and t4, a RESET pulse is applied to the memory cell to write the memory element M x to a first memory state (AP). During the RESET operation, a current source generates a second current and a current mirror current coupled to the current source, and the memory cell increases the voltage across the memory cell to conduct the second current through the memory cell. The second current is higher than the first current. In one embodiment, the RESET operation always places the memory element M x in the first memory state AP and is referred to as a "destructive read" in this regard.

[0112] The voltage across the memory cell is equal to the second current multiplied by the resistance of the memory element M x . Specifically, between times t2 and t3, the memory element M x remains in the P state, and the word line voltage has a value V c . Starting at time t3, the memory element M x switches to the (higher resistance) AP state, and between times t3 and t4, the word line voltage has a value V TP .

[0113] At time t4, the RESET pulse ends, the memory element M x is in the AP state, and the word line voltage drops to voltage V b . Between time t4 and time t5, a second read operation RD2 is performed. During the second read operation, a current source generates a first current and a current mirror current coupled to the current source, and the memory cell increases the voltage across the memory cell to conduct the first current through the memory cell. In one embodiment, the first current is approximately 15 μA and has a pulse width between approximately 25 ns and 50 ns, although larger or smaller current values and larger or smaller pulse widths may be used.

[0114] The voltage across the memory cell is equal to the first current multiplied by the resistance of the memory element M x . In the example depicted in Figure 4 , the magnetization direction of the memory element M x is AP, and the word line voltage has a value V b . At time t5, the second read operation ends, the word line voltage returns to the initial voltage V i (e.g., 0 volts), and the bidirectional threshold switch opens.

[0115] Compare the result of the first read RD1 with the result of the second read RD2. If the two read results are the same, determine that the memory element M x was initially in the first memory state AP and has remained in the first memory state AP. However, if the two read results are different, determine that the memory element M x was initially in the second memory state (P), but is now in the first memory state AP.

[0116] During Figure 4 the example, the word line voltage during the first read RD1 and the word line voltage during the second read RD2 are not the same, and thus, it is determined that the memory element M x was initially in the second memory state P. Thus, in one embodiment, a second pulse (the SET pulse between times t6 and t7) is typically used to return the memory element M x to the second memory state P. During Figure 4 the SET pulse between times t6 and t7 is shown as a dashed line to indicate that the SET pulse may or may not be used depending on the operation being performed by the read sequence 400.

[0117] During the SET operation, a current source generates a third current and a current mirror current coupled to the current source, and the memory cell increases the voltage across the memory cell to conduct the third current through the memory cell. The polarity of the third current is opposite to the polarities of the first current and the second current.

[0118] The magnitude of the third current is sufficient to turn on the bidirectional threshold switch. The voltage across the memory cell is equal to the third current multiplied by the resistance of the memory element M x and specifically, if the SET pulse is used between times t6 and t7, the memory element M x remains in the AP state and the word line voltage has a value V s . In one embodiment, during the SET operation, the bidirectional threshold switch is turned on before writing to the memory element M x .

[0119] Figure 4 The exemplary read and write sequence 400 of 10 can be used to determine the bit error rate of the memory cell. Specifically, a first self-reference read operation can be performed between times t0 and t7, a second self-reference read operation can be performed between times t8 and t9, a third self-reference read operation can be performed between times t 11 and t 12 and a fourth self-reference read operation can be performed between times t 13 and so on.

[0120] In one embodiment, no alternating SET pulses are applied such that the memory element M x repeatedly switches between a first memory state AP (“1”) and a second memory state P (“0”). Since the RESET operation always places the memory element M x in the first memory state AP, we know the value that should be read from the memory cell. The bit error rate is determined by comparing the read value with the expected value and then determining the number of errors.

[0121] Using Figure 4 exemplary read and write sequence 400, one phenomenon observed is that if the time between consecutive bit access operations increases, the bit error rate increases. For example, Figure 5A depicts two consecutive self - reference read operations separated by a bit access time Δ t , and Figure 5B depicts a graph showing the relationship between the exemplary average bit error rate and the bit access time. As shown, the average bit error rate increases when the bit access time increases.

[0122] Without wishing to be bound by any particular theory, it is believed that the threshold voltage drift of the memory cell's two - way threshold switch is the cause of the phenomenon that the bit error rate increases as the bit access time increases. Specifically, some selector elements S x (such as two - way threshold switches) exhibit the phenomenon of threshold voltage drift. That is, if the two - way threshold switch is turned on by applying a voltage (e.g., Figure 2C the first threshold voltage V TP ) that exceeds the threshold voltage across the two - way threshold switch, the threshold voltage of the two - way threshold switch begins to drift higher over time.

[0123] For example, Figure 5C depicts a graph showing the relationship between the exemplary threshold voltage V Figure 2B values of a population of memory cells (such as TH memory cell 222a) and the delay, where the selector element S x is a two - way threshold switch. In this example, the two - way threshold switch has an initial threshold voltage V TH of approximately 2.3V. After a delay of approximately 1 ms, the threshold voltage V TH has a value of approximately 2.5V. After approximately 100 s, the threshold voltage V TH has a value of approximately 2.8V. In this exemplary graph, the threshold voltage of the two - way threshold switch increases at a rate of approximately 60 mV / dec. In the example depicted in Figure 5C , the threshold voltage V TH values have a linear relationship with the delay. Those of ordinary skill in the art will understand that the threshold voltage V THThe value and the delay alternatively have a non-linear relationship.

[0124] As a result of the threshold voltage drift, as the delay time increases, the voltage required to turn on the bidirectional threshold switch also increases. As described above, when the bidirectional threshold switch is turned on (when the word line voltage is equal to the threshold voltage V TH ), the voltage across the bidirectional threshold switch S x drops to the value V offset , and the remaining word line voltage across the memory element M x of the memory cell drops.

[0125] This remaining voltage is referred to herein as the "snapback voltage" and is as follows:

[0126] Snapback voltage = (V TH – V offset )

[0127] The value of V offset does not seem to be affected by the delay, and thus, as the bit access time increases, the snapback voltage increases as the threshold voltage V TH increases.

[0128] Without wishing to be bound by any particular theory, it is believed that as the bit access time increases, the increase in the snapback voltage may interfere with the data value stored in the memory element M x of the memory cell. In fact, if the snapback voltage becomes large enough, the memory element M x can switch states (e.g., from a P state to an AP state). Without wishing to be bound by any particular theory, it is believed that as the bit access time increases, the increase in the snapback voltage is the cause of the phenomenon that the bit error rate increases as the bit access time increases.

[0129] Figure 5D depicts a graph of the relationship between the values of the threshold voltage V Figure 2B and the delay for a population of memory cells (such as TH memory cell 222a), where the selector element S x is a bidirectional threshold switch. In this example, the bidirectional threshold switch has an initial threshold voltage V TH of approximately 2.4 V. After a delay of approximately 100 ms, the threshold voltage V TH has a value of approximately 2.5 V. After approximately 100 s, the threshold voltage V TH has a value of approximately 2.7 V. In this exemplary graph, the threshold voltage of the bidirectional threshold switch increases at approximately 45 mV / dec. In the example depicted in Figure 5D , the threshold voltage V THThe value has a linear relationship with the latency. A person of ordinary skill in the art will understand that the threshold voltage V TH The value and the latency may alternatively have a non-linear relationship.

[0130] As described above and as depicted in the example of Figure 4 Each read operation is performed using a pulse having a first (e.g., positive) polarity, and each SET operation is performed using a pulse having a second (e.g., negative) polarity opposite to the first polarity.

[0131] As used herein, a pulse for turning on a two-way threshold switch is referred to as an "access pulse". Thus, each read operation is performed after using an access pulse having a first (e.g., positive) polarity ("positive access pulse"), and each SET operation is performed after using an access pulse having a second (e.g., negative) polarity ("negative access pulse").

[0132] Without wishing to be bound by any particular theory, it is believed that as the bit access time increases, the relationship between the polarities of consecutive access pulses affects the threshold voltage drift rate.

[0133] Without wishing to be bound by any particular theory, it is believed that as the bit access time of a two-way threshold switch increases, the threshold voltage drift rate depends on whether consecutive access pulses have the same polarity or opposite polarities.

[0134] Without wishing to be bound by any particular theory, it is believed that when consecutive access pulses of the same polarity are used to turn on a two-way threshold switch, the threshold voltage drift rate as the bit access time increases is lower than when consecutive access pulses of opposite polarities are used to turn on the two-way threshold switch as the bit access time increases.

[0135] For example, Figure 6A and Figure 6B both depict two consecutive self-reference read operations separated by a bit access time interval Δ t .

[0136] In Figure 6A , after the first self-reference read, no SET pulse is used. Thus, in the first self-reference read, the two-way threshold switch is turned on by a positive access pulse, and then in the second self-reference read, the two-way threshold switch is turned on by another positive access pulse. Thus, the two-way threshold switch is turned on by two consecutive access pulses of the same polarity.

[0137] Conversely, in Figure 6B , after the first self-reference read, a SET pulse is used. The SET pulse has a negative polarity that turns on the two-way threshold switch S x and also sets the memory element Mx The magnetization direction of is changed from AP to P. In the second self-referenced reading, the bidirectional threshold switch is turned on by a positive access pulse. Therefore, the bidirectional threshold switch is turned on by two consecutive access pulses of different polarities.

[0138] Empirical data indicate that as the bit access time increases, the threshold voltage drift rate varies depending on the relationship between the polarities of the consecutive access pulses used to turn on the bidirectional threshold switch. In practice, without wishing to be bound by any particular theory, it is believed that if the bidirectional threshold switch is turned on by two consecutive access pulses of the same polarity, then as the bit access time increases, the threshold voltage drift rate is less than if the bidirectional threshold switch is turned on by two consecutive access pulses of different polarities.

[0139] For example, a bidirectional threshold switch (e.g., such as a Figure 6A ) may exhibit a first threshold voltage drift rate (e.g., such as Figure 5D 45mv / dec shown in ).

[0140] In contrast, a bidirectional threshold switch (such as a Figure 6B ) may exhibit a second threshold voltage drift rate (e.g., such as Figure 5C In one embodiment, the first threshold voltage drift rate is lower than the second threshold voltage drift rate.

[0141] Empirical data also indicates that the magnitude of the threshold voltage varies depending on the relationship between the polarities of consecutive access pulses used to switch on the bidirectional threshold switch. In practice, without wishing to be bound by any particular theory, it is believed that if the bidirectional threshold switch is switched on by two consecutive access pulses of the same polarity, the magnitude of the threshold voltage will remain approximately constant, whereas if the bidirectional threshold switch is switched on by two consecutive access pulses of different polarities, the magnitude of the threshold voltage may increase, and this in turn may increase the snapback voltage.

[0142] Techniques for managing the effects of threshold voltage drift of a bidirectional threshold switch selector element are described. Specifically, techniques for managing the effects of threshold voltage drift of a bidirectional threshold switch selector element on the bit error rate of a memory cell including such a bidirectional threshold switch are described. Without wishing to be bound by any particular theory, it is believed that the present techniques can be used to reduce the effects of threshold voltage drift of a bidirectional threshold switch selector element on the bit error rate of a memory cell including such a bidirectional threshold switch.

[0143] Figure 7Depicts an implementation of a technique for managing the impact of threshold voltage drift of a two-way threshold switch selector element. Specifically, the read and write sequence 700 depicts the voltage versus time relationship on a memory cell that includes a memory cell having a selector element serially coupled to a magnetic memory element (such as Figure 2B memory cell 222a). In one implementation, the selector element is a two-way threshold switch.

[0144] In Figure 7 the implementation, a self-reference read operation is performed, and if the read result indicates that the magnetic memory element was initially in the P state before the RESET operation, a SET pulse is used. In one implementation, after each SET pulse, a post-set pulse 702 having the same polarity as the read operation (e.g., positive polarity) is performed.

[0145] In one implementation, a current source generates a fourth current and a current mirror current coupled to the current source, and the memory cell increases the voltage on the memory cell to transmit the fourth current through the memory cell, thereby generating the post-set pulse 702.

[0146] In one implementation, the post-set pulse 702 should be short enough not to significantly affect the delay, but long enough to turn on the two-way threshold switch. In one implementation, the post-set pulse 702 should not interfere with the state of the magnetic memory element.

[0147] In one implementation, the post-set pulse 702 is generated by a fourth current between about 5 μA and about 20 μA, although larger or smaller current values may be used. Alternatively, the post-set pulse 702 may have a maximum voltage between about 3 V and about 4 V, although larger or smaller maximum voltage values may be used.

[0148] In one implementation, the post-set pulse 702 has a pulse width PW psp . In one implementation, the pulse width PW psp is between about 5 ns and about 40 ns, although larger or smaller pulse widths may be used.

[0149] In one implementation, after each SET pulse, the post-set pulse 702 is applied at time T psp . In one implementation, the time T psp is as short as possible. In one implementation, the time T psp is less than about 1 μs. In one implementation, the time T psp is less than about 100 ns. In one implementation, the time T psp is approximately 0 seconds.

[0150] InFigure 7 In the embodiments depicted, after each SET pulse, a single post - SET pulse 702 is used. In other embodiments, more than one post - SET pulse 702 may be used. In one embodiment, the post - SET pulse is used only after the SET pulse. For example, as Figure 7 depicted, the second self - reference read is not followed by a SET pulse and thus, no post - SET pulse is used after the second self - reference read.

[0151] Without wishing to be bound by any particular theory, it is believed that compared to the threshold voltage drift rate that occurs over time during bit access when no post - SET pulse is included, using a post - SET pulse (such as the exemplary post - SET pulse 702) after each SET pulse may result in a lower threshold voltage drift rate as the bit access time increases. In this regard, without wishing to be bound by any particular theory, it is believed that using a post - SET pulse (such as the exemplary post - SET pulse 702, etc.) after each SET pulse may reduce the threshold voltage drift rate as the bit access time increases.

[0152] Without wishing to be bound by any particular theory, it is believed that using a post - SET pulse (such as the exemplary post - SET pulse 702) after each SET pulse may result in a threshold voltage drift rate that is less than the threshold voltage drift rate when no post - SET pulse is used, as the bit access time increases.

[0153] Without wishing to be bound by any particular theory, it is believed that compared to the threshold voltage amplitude when no post - SET pulse is used, using a post - SET pulse (such as the exemplary post - SET pulse 702) after each SET pulse may reduce the threshold voltage amplitude.

[0154] Without wishing to be bound by any particular theory, it is believed that using a post - SET pulse (such as the exemplary post - SET pulse 702) after each SET pulse may reduce the impact of threshold voltage drift of the two - way threshold - switch selector element on the bit error rate of memory cells including such two - way threshold switches.

[0155] The use of the post - SET pulse (such as the exemplary post - SET pulse 702) does not eliminate threshold voltage drift as the bit access time increases. In fact, the threshold voltage will still drift over time. However, by reducing the threshold voltage drift rate as the bit access time increases, this technique can reduce the amount of threshold voltage drift that does occur.

[0156] Figure 8Depicts another implementation of a technique for managing the impact of threshold voltage drift in a two-way threshold switch selector element. Specifically, the read and write sequence 800 depicts the voltage versus time relationship on a memory cell that includes a memory cell with a selector element serially coupled to a magnetic memory element (such as Figure 2B memory cell 222a). In one implementation, the selector element is a two-way threshold switch.

[0157] In Figure 8 the implementation, a self-reference read operation is performed, and after the read operation, a SET pulse may or may not be used. In one implementation, before each self-reference read operation, a preread pulse 802 with the same polarity as the read operation (e.g., positive polarity) is performed.

[0158] In one implementation, a current source generates a fifth current and a current mirror current coupled to the current source, and the memory cell increases the voltage on the memory cell to transmit the fifth current through the memory cell, thereby generating the preread pulse 802.

[0159] In one implementation, the preread pulse 802 should be short enough not to significantly affect the delay, but long enough to turn on the two-way threshold switch. In one implementation, the preread pulse 802 should not interfere with the state of the magnetic memory element.

[0160] In one implementation, the preread pulse 802 is generated by a fifth current between approximately 5 μA and approximately 20 μA, although larger or smaller current values may be used. Alternatively, the preread pulse 802 may have a maximum voltage between approximately 3 V and approximately 4 V, although larger or smaller maximum voltage values may be used.

[0161] In one implementation, the preread pulse 802 has a pulse width PW prp . In one implementation, the pulse width PW prp is between approximately 5 ns and approximately 40 ns, although larger or smaller pulse widths may be used.

[0162] In one implementation, before each self-reference read, the preread pulse 802 is applied at time T prp . In one implementation, time T prp is as short as possible. In one implementation, time T rap is less than approximately 1 μs. In one implementation, time T prp is less than approximately 100 ns. In one implementation, time T prp is approximately 0 seconds.

[0163] In Figure 8In the embodiments depicted, a single pre-read pulse 802 is used before each self-reference read. In other embodiments, more than one pre-read pulse 802 may be used. In one embodiment, the pre-read pulse 802 is used regardless of whether a SET pulse is used before the self-reference read. For example, as Figure 8 depicted, the second self-reference read is not followed by a SET pulse, but rather a pre-read pulse 802 is used before the second self-reference read.

[0164] Without wishing to be bound by any particular theory, it is believed that using a pre-read pulse (such as the exemplary pre-read pulse 802) before each self-reference read operation can significantly reduce or eliminate threshold voltage drift that occurs before the pre-read pulse 802.

[0165] For example, Figure 9 depicts an exemplary graph of the relationship between the threshold voltage V Figure 2B values of a population of memory cells (such as TH memory cell 222a) and delay, where the selector element S x is a two-way threshold switch. In this graph, it is assumed that exactly 100 seconds of delay has passed before the pre-read pulse 802, and the threshold voltage V TH = 2.8 volts. When the pre-read pulse 802 turns on the two-way threshold switch, the threshold voltage V TH substantially resets to a value with substantially no delay (e.g., V TH = 2.3 volts).

[0166] Without wishing to be bound by any particular theory, it is believed that using a pre-read pulse (such as the exemplary pre-read pulse 802) before each self-reference read operation can reduce the impact of threshold voltage drift of the two-way threshold switch selector element on the bit error rate of memory cells including such a two-way threshold switch.

[0167] Specifically, without wishing to be bound by any particular theory, it is believed that the pre-read pulse (such as the exemplary pre-read pulse 802) can "absorb" the snapback voltage. In fact, without wishing to be bound by any particular theory, it is believed that when the amplitude of the pre-read pulse 802 reaches the threshold voltage V TH of the two-way threshold switch, the switch turns on and the snapback voltage begins to discharge.

[0168] Without wishing to be bound by any particular theory, it is believed that by making the pulse width PW prpShort enough such that the two-way threshold switch is turned off and the snapback voltage discharges (e.g., discharges to ground). In this regard, without wishing to be bound by any particular theory, it is believed that a pre-read pulse (such as exemplary pre-read pulse 802) can “absorb” the snapback voltage and can prevent interference to the memory element M x from interference.

[0169] As described above, in one embodiment, a current source generates a fifth current and a current mirror current coupled to the current source, and the memory cell increases the voltage on the memory cell to conduct the fifth current through the memory cell, thereby generating the pre-read pulse 802.

[0170] In one embodiment, each memory cell is coupled to a word line, which in turn is coupled to various circuits, such as drivers, decoders, and other circuits collectively referred to herein as “external circuits”. The external circuits add a capacitive load to the word line adversely.

[0171] In one embodiment, a transistor having a control gate is coupled between the word line and the external circuit, and a gate control signal having a voltage (VG CON ) coupled to the control gate can be used to selectively connect the external circuit to the word line or disconnect it from the word line. For example, if VG CON has a first value (LOW), the transistor is turned on and the external circuit is connected to the word line, and if VG CON has a second value (HIGH), the transistor is turned off and the external circuit is substantially disconnected from the word line.

[0172] In one embodiment, the gate control signal VG CON can be used to further enhance the effect of the pre-read pulse 802. For example, Figure 10 illustrates an embodiment of the control signal VG CON superimposed on the pre-read pulse 802. In the illustrated embodiment, the control signal VG CON goes HIGH (thereby substantially disconnecting the external circuit from the word line) just before the pre-read pulse 802 and goes LOW (thereby connecting the external circuit to the word line).

[0173] Without wishing to be bound by any particular theory, it is believed that by using the gate control signal VG CON in this way, the capacitive load on the word line can be reduced while applying the pre-read pulse 802 to the word line, and the time required to discharge the snapback voltage (e.g., discharge to ground) can be reduced.

[0174] Those of ordinary skill in the art will understand that the gate control signal VG CON can have values other than LOW and HIGH. For example, VGCON can have a value that causes the transistor to be neither fully on nor fully off. Without wishing to be bound by any particular theory, it is believed that such a gate control signal value VG CON can also reduce the capacitive load on the word line while applying a pre-read pulse 802 to the word line, and can reduce the time required to discharge the snapback voltage (e.g., discharge to ground).

[0175] Additionally, without wishing to be bound by any particular theory, it is believed that the gate control signal VG can also be used as described above CON , while applying a post-set pulse (e.g., Figure 7 the post-set pulse 702) to the word line, and can reduce the time required to discharge the snapback voltage (e.g., discharge to ground).

[0176] As described above, before each self-reference read, a pre-read pulse 802 is applied at time T prp . In one embodiment, time T prp is as short as possible, and desirably, time T prp is 0. However, if time T prp = 0, the bidirectional threshold switch may not be fully turned off, and the snapback voltage may not be fully discharged. As a result, some residual portion of the snapback voltage may interfere with the memory element M x .

[0177] Figure 11 depicts yet another embodiment of a technique for managing the effects of threshold voltage drift in a bidirectional threshold switch selector element. Specifically, the read and write sequence 1100 depicts the voltage versus time relationship on a memory cell that includes a memory cell having a selector element serially coupled to a magnetic memory element (such as Figure 2B the memory cell 222a). In one embodiment, the selector element is a bidirectional threshold switch.

[0178] In Figure 11 the embodiment, a self-reference read operation is performed, and after the read operation, a SET pulse may or may not be used. In one embodiment, before each self-reference read operation, a pre-read pulse 1102 having a polarity opposite to that of the read operation (e.g., negative polarity) is performed.

[0179] In one embodiment, a current source generates a sixth current and a current mirror current coupled to the current source, and the memory cell increases the magnitude of the voltage on the memory cell to conduct the sixth current through the memory cell, thereby generating the pre-read pulse 1102.

[0180] In one embodiment, the pre-read pulse 1102 should be short enough not to significantly affect the latency, but long enough to turn on the bidirectional threshold switch. In one embodiment, the pre-read pulse 1102 should not disturb the state of the magnetic memory element.

[0181] In one embodiment, the pre-read pulse 1102 is generated by a sixth current between about 5 μA and about 20 μA, although larger or smaller current values may be used. Alternatively, the pre-read pulse 1102 may have a maximum voltage amplitude between about 3 V and about 4 V, although larger or smaller maximum voltage values may be used.

[0182] In one embodiment, the pre-read pulse 1102 has a pulse width PW prnp . In one embodiment, the pulse width PW prnp is between about 5 ns and about 15 ns, although larger or smaller pulse widths may be used.

[0183] In one embodiment, the pre-read pulse 1102 is applied at time T prnp before each self-reference read. In one embodiment, the time T prnp is as short as possible. In one embodiment, the time T prnp = 0.

[0184] In Figure 11 the embodiment depicted, a single pre-read pulse 1102 is used before each self-reference read. In other embodiments, more than one pre-read pulse 1102 may be used. In one embodiment, the pre-read pulse 1102 is used regardless of whether a SET pulse is used before the self-reference read. For example, as Figure 11 depicted, the second self-reference read is not followed by a SET pulse, but a pre-read pulse 1102 is used before the second self-reference read.

[0185] Without wishing to be bound by any particular theory, it is believed that using a pre-read pulse (such as the exemplary pre-read pulse 1102) before each self-reference read operation can significantly reduce or eliminate threshold voltage drift that occurs before the pre-read pulse 1102.

[0186] Without wishing to be bound by any particular theory, it is believed that using a pre-read pulse (such as the exemplary pre-read pulse 1102) before each self-reference read operation can reduce the impact of threshold voltage drift of the bidirectional threshold switch selector element on the bit error rate of memory cells including such bidirectional threshold switches.

[0187] Specifically, without wishing to be bound by any particular theory, it is believed that a pre-read pulse (such as exemplary pre-read pulse 1102) can "absorb" the snapback voltage. In fact, without wishing to be bound by any particular theory, it is believed that when the amplitude of the pre-read pulse 1102 reaches the threshold voltage V of the bidirectional threshold switch TH , the switch turns on and the snapback voltage begins to discharge.

[0188] However, without wishing to be bound by any particular theory, it is believed that by making the pulse width PW of the pre-read pulse 1102 prnp short enough, the bidirectional threshold switch turns off and the snapback voltage discharges (e.g., discharges to ground). In this regard, without wishing to be bound by any particular theory, it is believed that a pre-read pulse (such as exemplary pre-read pulse 1102) can "absorb" the snapback voltage and can prevent interference with the memory element M x .

[0189] Furthermore, without wishing to be bound by any particular theory, it is believed that compared to the pre-read pulse 802 Figure 8 , a pre-read pulse 1102 can be created such that the pre-read pulse 1102 is directly adjacent to the start of a self-reference read (i.e., time T prnp = 0). Specifically, without wishing to be bound by any particular theory, it is believed that by using a negative-polarity pre-read pulse 1102 and a positive-polarity access pulse for a self-reference read, the bidirectional threshold switch must turn off from the pre-read pulse 1102 before turning on again at the start of the self-reference read. Thus, without wishing to be bound by any particular theory, it is believed that even when the pre-read pulse 1102 is directly adjacent to the start of a self-reference read, the snapback voltage can be fully discharged.

[0190] Now referring to Figure 12 , an embodiment of a method 1200 for determining the bit error rate of multiple memory cells is described, each memory cell including a bidirectional threshold switch serially coupled to a magnetic memory element.

[0191] In step 1202, a sequence of self-reference read operations is performed on each of the memory cells, each self-reference read operation including a RESET pulse having a first polarity.

[0192] In step 1204, after every other self-reference read operation, a SET pulse having a second polarity and a post-set pulse having a first polarity are applied to the memory cells. In one embodiment, the post-set pulse is configured to reduce the bit error rate of the multiple memory cells.

[0193] Now referring to Figure 13, an embodiment of a method 1300 for determining the bit error rate of multiple memory cells is described, each memory cell including a bidirectional threshold switch serially coupled to a magnetic memory element.

[0194] In step 1302, a self-reference read operation sequence of each of the memory cells is performed, each self-reference read operation including a RESET pulse having a first polarity.

[0195] In step 1304, before each self-reference read operation, a pulse having a first polarity is applied to the memory cell to turn on the bidirectional threshold switch without disturbing the data state of the corresponding magnetic memory element. The pre-read pulse is configured to reduce the bit error rate of the multiple memory cells.

[0196] Now refer to Figure 14 , an embodiment of a method 1400 for determining the bit error rate of multiple memory cells is described, each memory cell including a bidirectional threshold switch serially coupled to a magnetic memory element.

[0197] In step 1402, a self-reference read operation sequence of each of the memory cells is performed, each self-reference read operation including a RESET pulse that includes a first polarity.

[0198] In step 1404, before each self-reference read operation, a pulse including a second polarity opposite to the first polarity is applied to the memory cell to turn on the bidirectional threshold switch without disturbing the data state of the corresponding magnetic memory element. The pre-read pulse is configured to reduce the bit error rate of the multiple memory cells.

[0199] The above techniques have been described with respect to self-reference read operations. Those of ordinary skill in the art will understand that the described techniques can also be used with other read techniques (such as non-destructive read techniques (sometimes referred to as "fast read" techniques)).

[0200] One embodiment of the disclosed technique includes an apparatus that includes a memory cell and a control circuit coupled to the memory cell. The memory cell includes a reversible resistive switching memory element serially coupled to a selector element that has a threshold voltage. The control circuit is configured to first access the memory cell using a first pulse having a first polarity, second access the memory cell using a second pulse having a second polarity opposite to the first polarity, and third access the memory cell using a third pulse having a first polarity. The third pulse is configured to reduce the threshold voltage drift rate of the selector element.

[0201] One embodiment of the disclosed technology includes an apparatus that includes a cross-point memory array and a control circuit coupled to the cross-point memory array. The cross-point memory array includes a plurality of memory cells, each memory cell including a magnetic tunnel junction memory element serially coupled to a selector element. The control circuit is configured to: perform a self-reference read operation on each of the plurality of memory cells; and for each memory cell that changes from a first magnetization direction to a second magnetization direction due to the self-reference read operation: apply a SET pulse to change the magnetization direction from the second magnetization direction to the first magnetization direction; and apply a post-set pulse that includes a polarity opposite to the polarity of the SET pulse.

[0202] One embodiment of the disclosed technology includes a method that includes determining a bit error rate of a plurality of memory cells, each memory cell including a two-way threshold switch serially coupled to a magnetic memory element, by: performing a sequence of self-reference read operations on each of the memory cells, each self-reference read operation including a RESET pulse that includes a first polarity; and after every other self-reference read operation, applying a SET pulse that includes a second polarity and a post-set pulse that includes the first polarity to the memory cells. The post-set pulse is configured to reduce the bit error rate of the plurality of memory cells.

[0203] One embodiment of the disclosed technology includes an apparatus that includes a memory cell and a control circuit coupled to the memory cell. The memory cell includes a reversible resistive switching memory element serially coupled to a selector element that includes a threshold voltage. The control circuit is configured to first access the memory cell using a first pulse having a first polarity and second access the memory cell using a second pulse having the first polarity. The first pulse is configured to reduce a threshold voltage drift rate of the selector element.

[0204] One embodiment of the disclosed technology includes an apparatus that includes a cross-point memory array and a control circuit coupled to the cross-point memory array. The cross-point memory array includes a plurality of memory cells, each memory cell including a magnetic tunnel junction memory element serially coupled to a selector element. The control circuit is configured to perform a self-reference read operation on each of the plurality of memory cells and, prior to each self-reference read operation, apply a pre-read pulse to reset a threshold voltage of a corresponding selector element.

[0205] One embodiment of the disclosed technology includes a method that includes determining a bit error rate of a plurality of memory cells, each memory cell including a two-way threshold switch serially coupled to a magnetic memory element: performing a self-reference read operation sequence on each of the memory cells, each self-reference read operation including a RESET pulse having a first polarity; and prior to each self-reference read operation, applying a pulse having the first polarity to the memory cell to turn on the two-way threshold switch without disturbing the data state of the corresponding magnetic memory element. The pre-read pulse is configured to reduce the bit error rate of the plurality of memory cells.

[0206] One embodiment of the disclosed technology includes an apparatus that includes a memory cell and a control circuit coupled to the memory cell. The memory cell includes a reversible resistive switching memory element serially coupled to a selector element, the selector element including a threshold voltage. The control circuit is configured to first access the memory cell using a first pulse including a first polarity and to second access and read the memory cell using a second pulse including a second polarity opposite the first polarity, the second pulse adjacent to the first pulse. The first pulse is configured to reduce a threshold voltage drift rate of the selector element.

[0207] One embodiment of the disclosed technology includes an apparatus that includes: a cross-point memory array including a plurality of memory cells; and a control circuit coupled to the cross-point memory array. Each memory cell includes a magnetic tunnel junction memory element serially coupled to a selector element. The control circuit is configured to perform a self-reference read operation on each of the plurality of memory cells and, prior to each self-reference read operation, apply a pre-read pulse configured to release a voltage difference between a threshold voltage and an offset voltage of the corresponding selector element.

[0208] One embodiment of the disclosed technology includes a method that includes determining a bit error rate of a plurality of memory cells, each memory cell including a two-way threshold switch serially coupled to a magnetic memory element. The method includes: performing a self-reference read operation sequence on each of the memory cells, each self-reference read operation including a RESET pulse including a first polarity; and prior to each self-reference read operation, applying a pulse including a second polarity opposite the first polarity to the memory cell to turn on the two-way threshold switch without disturbing the data state of the corresponding magnetic memory element. The pre-read pulse is configured to reduce the bit error rate of the plurality of memory cells.

[0209] For the purposes of this disclosure, a first layer may be above or over a second layer if zero, one, or more intermediate layers are between the first layer and the second layer.

[0210] For the purposes of this document, it should be noted that the dimensions of the various features depicted in the drawings are not necessarily drawn to scale.

[0211] For the purposes of this document, references in the specification to "one embodiment", "an embodiment", "some embodiments", or "another embodiment" may be used to describe different embodiments and do not necessarily refer to the same embodiment.

[0212] For the purposes of this document, a connection can be a direct connection or an indirect connection (e.g., through another part). In some cases, when an element is referred to as being connected or coupled to another element, the element can be directly connected to the other element or indirectly connected to the other element via an intervening element. When an element is referred to as being directly connected to another element, there is no intervening element between the element and the other element.

[0213] For the purposes of this document, the term "based on" can be understood as "at least partially based on".

[0214] For the purposes of this document, in the absence of additional context, the use of numerical terms such as "first" object, "second" object, and "third" object may not imply an ordering of the objects, but may be used for identification purposes to identify different objects.

[0215] For the purposes of this document, the term "group" of objects can refer to a "group" of one or more objects.

[0216] Although the subject matter has been described in language specific to structural features and / or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.

Claims

1. A device, comprising: a memory cell comprising a reversible resistance-switching memory element coupled in series with a selector element, the selector element comprising a threshold voltage; and a control circuit coupled to the memory unit, the control circuit being configured to: accessing the memory cell for a first time using a first pulse comprising a first polarity; as well as accessing the memory cell a second time and reading the memory cell using a second pulse comprising the first polarity, Wherein, the first pulse is configured to reduce a threshold voltage drift rate of the selector element.

2. The device according to claim 1, wherein: The reversible resistance-switching memory element includes a magnetic memory element.

3. The device according to claim 1, wherein: The reversible resistance-switching memory element includes a magnetic tunnel junction.

4. The device according to claim 1, wherein: The selector element comprises a threshold selector device.

5. The device according to claim 1, wherein: The selector element comprises a bidirectional threshold switch.

6. The device according to claim 1, wherein: The selector element includes a threshold voltage that drifts at a greater rate over time.

7. The device according to claim 1, wherein: The selector element can be selectively switched on.

8. The device according to claim 1, wherein: The first pulse and the second pulse both turn on the selector element.

9. The device according to claim 1, wherein: The control circuit is further configured to perform a first read and a second read of the reversible resistance-switching memory element after the second pulse.

10. The device according to claim 1, wherein: The control circuit is also configured to perform a destructive read of the reversible resistance-switching memory element after the second pulse.

11. The device according to claim 1, wherein: The second pulse comprises a RESET pulse.

12. The device according to claim 1, wherein: The first pulse is configured to turn on the selector element without disturbing a data state of the reversible resistance-switching memory element.

13. The device according to claim 1, wherein: The control circuit is further configured to access the memory cell for a first time using the first pulse before accessing the memory cell for a second time using the second pulse, and the access time is less than about 100 ns.

14. A device, comprising: a cross-point memory array comprising a plurality of memory cells, each memory cell comprising a magnetic tunnel junction memory element coupled in series with a selector element; a control circuit coupled to the cross-point memory array, the control circuit being configured to: performing a self-referenced read operation of each of the plurality of memory cells; as well as Prior to each self-referenced read operation, a pre-read pulse is applied to reset the threshold voltage of the corresponding selector element.

15. The device according to claim 14, wherein: Each selector element includes a threshold selector device.

16. The device according to claim 14, wherein: Each selector element comprises a bidirectional threshold switch.

17. The device according to claim 14, wherein: Each selector element includes a threshold voltage that drifts at a greater rate over time.

18. The device according to claim 14, wherein: The pre-read pulse is configured to reduce a bit error rate of the plurality of memory cells.

19. A method comprising: The bit error rate of a plurality of memory cells, each memory cell comprising a bidirectional threshold switch coupled in series with a magnetic memory element, is determined by the following steps: performing a sequence of self-referenced read operations for each of the memory cells, Each self-referenced read operation includes a RESET pulse including a first polarity; as well as Prior to each self-referenced read operation, applying a pulse comprising the first polarity to the memory cell to turn on the bidirectional threshold switch without disturbing a data state of a corresponding magnetic memory element, The pre-read pulse is configured to reduce the bit error rate of the plurality of memory cells.

20. The method according to claim 19, wherein: The magnetic memory elements each include a magnetic tunnel junction.

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