Buck-boost conversion circuit for digital power supply

Abstract

The invention belongs to the technical field of digital power supplies, and discloses a buck-boost conversion circuit for a digital power supply. The output end of a main control chip of the conversion circuit is connected with the input end of a first driving circuit and the input end of a second driving circuit, and is used for transmitting driving signals to the first driving circuit and the second driving circuit; a high-side driving signal output end of the first driving circuit is connected with a grid electrode of the first NMOS tube, a low-side driving signal output end of the first driving circuit is connected with a grid electrode of the second NMOS tube, and a source electrode of the first NMOS tube is connected with a drain electrode of the second NMOS tube; a high-side driving signal output end of the second driving circuit is connected with a grid electrode of the third NMOS tube, a low-side driving signal output end of the second driving circuit is connected with a grid electrode of the fourth NMOS tube, and a source electrode of the third NMOS tube is connected with a drain electrode of the fourth NMOS tube; the first bootstrap circuit is used for generating bootstrap voltage to drive the first NMOS tube; the second bootstrap circuit is used for generating bootstrap voltage to drive the third NMOS tube. And low-cost and high-efficiency voltage conversion can be realized.

Description

Technical Field

[0001] This application relates to the field of digital power technology, and particularly to a buck-boost conversion circuit for digital power supplies. Background Art

[0002] In existing digital power supplies, the Buck-boost circuit is a commonly used circuit that can achieve buck-boost conversion. It can operate in three modes according to the input voltage and load requirements: Buck mode (step-down mode), Boost mode (step-up mode), and Buck-boost mode (buck-boost mode). In Buck mode, the output voltage is lower than the input voltage; in Boost mode, the output voltage is higher than the input voltage. To ensure the normal operation of the circuit, in Buck mode and Boost mode, a high-voltage signal is required to turn on the always-on MOSFET. Usually, an external Charge Pump is used to generate a high voltage to drive the always-on MOSFET; or by adjusting the circuit operating mode, the Buck-boost mode is used instead of the Buck mode or Boost mode. However, adding an external Charge Pump requires additional circuit design and components, increasing the hardware cost; the operating efficiency of using the Buck-boost mode is lower than that of the individual Buck mode or Boost mode. Summary of the Invention

[0003] For this reason, an embodiment of this application provides a buck-boost conversion circuit for digital power supplies. This circuit provides a stable gate drive voltage for the NMOS transistor through a bootstrap circuit, and uses the Bootstrap bootstrap voltage generated by the switching-mode half-bridge to turn on the always-on mode half-bridge, which can reduce the circuit cost and improve the overall conversion efficiency.

[0004] This application is achieved through the following technical solutions:

[0005] A buck-boost conversion circuit for digital power supplies, comprising:

[0006] A main control chip, a first drive circuit, a second drive circuit, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first bootstrap circuit, and a second bootstrap circuit;

[0007] The output end of the main control chip is connected to the input ends of the first drive circuit and the second drive circuit, and is used to transmit drive signals to the first drive circuit and the second drive circuit;

[0008] The high-side drive signal output terminal of the first drive circuit is connected to the gate of the first NMOS transistor, and the low-side drive signal output terminal is connected to the gate of the second NMOS transistor. The source of the first NMOS transistor is connected to the drain of the second NMOS transistor.

[0009] The high-side drive signal output terminal of the second drive circuit is connected to the gate of the third NMOS transistor, and the low-side drive signal output terminal is connected to the gate of the fourth NMOS transistor. The source of the third NMOS transistor is connected to the drain of the fourth NMOS transistor.

[0010] The first bootstrap circuit is used to generate a bootstrap voltage to drive the first NMOS transistor.

[0011] The second bootstrap circuit is used to generate a bootstrap voltage to drive the third NMOS transistor.

[0012] In a preferred example of the present application, it can be further set that the first bootstrap circuit includes a first bootstrap diode and a first bootstrap capacitor.

[0013] The anode of the first bootstrap diode is connected to the input power supply terminal, the cathode is connected to one end of the first bootstrap capacitor, and the other end of the first bootstrap capacitor is connected to the gate of the first NMOS transistor.

[0014] In a preferred example of the present application, it can be further set that the first bootstrap circuit further includes a first zener diode. The anode of the first zener diode is connected to the first bootstrap capacitor, the cathode is connected to the gate of the first NMOS transistor, and the regulated voltage of the first zener diode is greater than the input voltage of the input power supply terminal and less than the maximum gate-source voltage of the first NMOS transistor.

[0015] In a preferred example of the present application, it can be further set that the second bootstrap circuit includes a second bootstrap diode and a second bootstrap capacitor.

[0016] The anode of the second bootstrap diode is connected to the input power supply terminal, the cathode is connected to one end of the second bootstrap capacitor, and the other end of the second bootstrap capacitor is connected to the gate of the third NMOS transistor.

[0017] In a preferred example of the present application, it can be further set that the second bootstrap circuit further includes a second zener diode. The anode of the second zener diode is connected to the second bootstrap capacitor, the cathode is connected to the gate of the third NMOS transistor, and the regulated voltage of the second zener diode is greater than the input voltage of the input power supply terminal and less than the maximum gate-source voltage of the third NMOS transistor.

[0018] In a preferred example of the present application, it can be further set that the first driving circuit includes a first driving chip; the input end of the first driving chip is connected to the main control chip, the HO port of the first driving chip is connected to the gate of the first NMOS transistor, the LO port is connected to the gate of the second NMOS transistor, and the HS port is connected to the switching node SW1, where the switching node SW1 is connected to the Buck-on switch.

[0019] In a preferred example of the present application, it can be further set that the second driving circuit includes a second driving chip;

[0020] The input end of the second driving chip is connected to the main control chip, the HO port of the second driving chip is connected to the gate of the third NMOS transistor, the LO port is connected to the gate of the fourth NMOS transistor, and the HS port is connected to the switching node SW2, where the switching node SW2 is connected to the Boost-on switch.

[0021] In a preferred example of the present application, it can be further set that the buck-boost conversion circuit supports the Buck mode: in the Buck mode, the main control chip is configured to transmit a first PWM signal to the first driving circuit, so that the first NMOS transistor and the second NMOS transistor are in the switching state, and the Buck-on switch is turned on; a second PWM signal with a 100% duty cycle is transmitted to the second driving circuit, so that the third NMOS transistor and the fourth NMOS transistor are in the always-on state, and the Boost-on switch is turned off.

[0022] In a preferred example of the present application, it can be further set that the buck-boost conversion circuit supports the Buck-boost mode: in the Buck-boost mode, the main control chip is configured to transmit a first PWM signal to the first driving circuit, so that the first NMOS transistor and the second NMOS transistor are in the switching state, and the Buck-on switch is closed; a second PWM signal is transmitted to the second driving circuit, so that the third NMOS transistor and the fourth NMOS transistor are in the switching state, and the Boost-on switch is turned off.

[0023] In a preferred example of the present application, it can be further set that the buck-boost conversion circuit supports the Boost mode: in the Boost mode, the Boost-on switch is configured to be in the open state, the Buck-on switch is in the closed state, and the duty cycle of the first PWM signal transmitted by the main control chip to the first driving circuit is 100%.

[0024] In summary, compared with the prior art, the beneficial effects brought by the technical solutions provided by the embodiments of the present application at least include:

[0025] The buck-boost conversion circuit of the present application includes a main control chip, a first drive circuit, a second drive circuit, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first bootstrap circuit and a second bootstrap circuit; the output end of the main control chip is connected to the input ends of the first drive circuit and the second drive circuit, and is used to transmit drive signals to the first drive circuit and the second drive circuit; the high-side drive signal output end of the first drive circuit is connected to the gate of the first NMOS transistor, and the low-side drive signal output end is connected to the gate of the second NMOS transistor, and the source of the first NMOS transistor is connected to the drain of the second NMOS transistor; the high-side drive signal output end of the second drive circuit is connected to the gate of the third NMOS transistor, and the low-side drive signal output end is connected to the gate of the fourth NMOS transistor, and the source of the third NMOS transistor is connected to the drain of the fourth NMOS transistor; the first bootstrap circuit is used to generate a bootstrap voltage to drive the first NMOS transistor; the second bootstrap circuit is used to generate a bootstrap voltage to drive the second NMOS transistor. The Bootstrap bootstrap voltage generated by the half-bridge in the switching mode can be used to turn on the half-bridge in the always-on mode. The structure of the bootstrap circuit is simple, and compared with the complex power management scheme, the hardware cost is greatly reduced; the stable gate drive voltage is provided for the NMOS transistor through the bootstrap circuit, ensuring the fast conduction and turn-off of the switching transistor during high-frequency switching, thereby reducing the switching loss and improving the overall conversion efficiency. Description of the Drawings

[0026] Figure 1 Schematic diagram of a Buck-boost circuit in Buck mode in the prior art;

[0027] Figure 2 Schematic diagram of a Buck-boost circuit in Buck mode in the prior art;

[0028] Figure 3 Schematic diagram of a Buck-boost circuit in Buck mode in the prior art;

[0029] Figure 4 Schematic diagram of a buck-boost conversion circuit for digital power provided by an embodiment of the present application;

[0030] Figure 5 Schematic diagram of a first drive circuit provided by an embodiment of the present application;

[0031] Figure 6 Schematic diagram of a second drive circuit provided by an embodiment of the present application. Detailed Description of the Invention

[0032] This specific embodiment is only an interpretation of the present application and does not limit the present application. After reading this specification, those skilled in the art can make modifications to this embodiment that do not contribute creatively, but as long as they are within the scope of the claims of the present application, they are protected by the patent law.

[0033] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without making creative efforts fall within the scope of protection of the present application.

[0034] In addition, the term "and / or" in the present application is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in the present application generally represents an "or" relationship between the associated objects before and after, unless otherwise specified.

[0035] The terms "first", "second", etc. in the present application are used to distinguish between identical or similar items with basically the same functions. It should be understood that there is no logical or chronological dependency between "first", "second", and "nth", nor are the quantity and execution order limited.

[0036] In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or explanations. Any embodiment or design solution described as "exemplary" or "for example" in the embodiments of the present application should not be construed as being more preferred or having more advantages than other embodiments or design solutions. Rather, the use of words such as "exemplary" or "for example" is intended to present relevant concepts in a specific manner.

[0037] In existing digital power supplies, the Buck-boost circuit in the Buck-boost circuit can flexibly switch the working mode according to the relationship between the input and output voltages. Specifically, there are three working modes: Buck mode (step-down mode), Boost mode (step-up mode), and Buck-boost mode (step-up / step-down mode). As Figure 1 shown in the Buck mode, it mainly converts a higher input voltage into a lower output voltage. Among them, the NMOS transistor Q11 and the NMOS transistor Q12 are in the switching state (alternately conducting and turning off), the NMOS transistor Q13 is in the always-on state (always conducting), and the NMOS transistor Q14 is in the always-off state (always off); as Figure 2The figure shows the Buck - boost mode, which realizes seamless conversion of the input voltage to the output voltage. Whether the input voltage is higher than, lower than, or equal to the output voltage, the NMOS transistors Q11, Q12, Q13, and Q14 are all in the switching state (alternately conducting and turning off); as Figure 3 The figure shows the Boost mode, which mainly converts a lower input voltage to a higher output voltage. Among them, the NMOS transistor Q11 is in the always - on state (always conducting), the NMOS transistor Q12 is in the always - off state (always off), and the NMOS transistors Q13 and Q14 are in the switching state (alternately conducting and turning off).

[0038] The following further describes the embodiments of the present application in detail with reference to the accompanying drawings of the specification.

[0039] Figure 4 A buck - boost conversion circuit for a digital power supply provided by the first exemplary embodiment of the present application includes:

[0040] A main control chip, a first driving circuit, a second driving circuit, a first NMOS transistor Q1, a second NMOS transistor Q2, a third NMOS transistor Q3, a fourth NMOS transistor Q4, a first bootstrap circuit, and a second bootstrap circuit;

[0041] The output terminal of the main control chip is connected to the input terminals of the first driving circuit and the second driving circuit. The main control chip is used to transmit driving signals to the first driving circuit and the second driving circuit. Specifically, the output terminal PWM1N / 1P of the main control chip is electrically connected to the input terminal of the first driving circuit, and the output terminal PWM2N / 2P of the main control chip is electrically connected to the input terminal of the second driving circuit. In actual implementation, the main control chip can adopt UM32G4D21.

[0042] The high - side driving signal output terminal HG1 of the first driving circuit is connected to the gate of the first NMOS transistor Q1, the low - side driving signal output terminal LG1 is connected to the gate of the second NMOS transistor Q2, and the source of the first NMOS transistor Q1 is connected to the drain of the second NMOS transistor Q2; and the drain of the first NMOS transistor Q1 is connected to the input voltage VIN, and the source of the second NMOS transistor Q2 is grounded.

[0043] The high - side driving signal output terminal HG2 of the second driving circuit is connected to the gate of the third NMOS transistor Q3, the low - side driving signal output terminal LG2 is connected to the gate of the fourth NMOS transistor Q4, and the source of the third NMOS transistor Q3 is connected to the drain of the fourth NMOS transistor Q4; the drain of the third NMOS transistor Q3 is connected to the power output terminal VOUT, and the source of the fourth NMOS transistor Q4 is grounded.

[0044] The first bootstrap circuit is used to generate a bootstrap voltage to drive the first NMOS transistor Q1;

[0045] The second bootstrap circuit is used to generate a bootstrap voltage to drive the third NMOS transistor Q3.

[0046] In a preferred embodiment, the first bootstrap circuit includes a first bootstrap diode D1 and a first bootstrap capacitor C1; the anode of the first bootstrap diode D1 is connected to the input power supply terminal VCC, the cathode is connected to one end of the first bootstrap capacitor C1, and the other end of the first bootstrap capacitor C1 is connected to the gate of the first NMOS transistor Q1. Among them, the first bootstrap diode D1 is used to provide a charging path for the first bootstrap capacitor C1 and prevent the first bootstrap capacitor C1 from discharging reversely to the input power supply terminal VCC during the discharging process; the first bootstrap capacitor C1 is used to store charges and provide a driving voltage to the gate of the first NMOS transistor Q1 when needed. The capacitance of the first bootstrap capacitor C1 needs to be selected according to the operating frequency and duty cycle of the circuit to ensure that sufficient voltage can be provided to the first NMOS transistor Q1 when it is turned on.

[0047] In a preferred embodiment, the first bootstrap circuit further includes a first zener diode Z1; the anode of the first zener diode Z1 is connected to the first bootstrap capacitor C1, the cathode is connected to the gate of the first NMOS transistor Q1, and the zener voltage of the first zener diode Z1 is greater than the input voltage of the input power supply terminal VCC and less than the maximum gate-source voltage V of the first NMOS transistor Q1 GS . In the first bootstrap circuit, due to the charging and discharging process of the first bootstrap capacitor C1, a transient overvoltage phenomenon may occur. The first zener diode Z1 can be used as an overvoltage protection component to prevent the voltage across the first bootstrap capacitor C1 from being too high, thereby protecting other components in the circuit. In actual implementation, the first zener diode Z1 can be selected as ZD16Vsod123-C.

[0048] In a preferred embodiment, the second bootstrap circuit includes a second bootstrap diode D2 and a second bootstrap capacitor C2; the anode of the second bootstrap diode D2 is connected to the input power supply terminal, the cathode is connected to one end of the second bootstrap capacitor C2, and the other end of the second bootstrap capacitor C2 is connected to the gate of the third NMOS transistor Q3. Among them, the second bootstrap diode D2 is used to provide a charging path for the second bootstrap capacitor C2 and prevent the second bootstrap capacitor C2 from discharging reversely to the input power supply terminal VCC during the discharging process; the second bootstrap capacitor C2 is used to store charges and provide a driving voltage to the gate of the third NMOS transistor Q3 when needed. The capacitance of the second bootstrap capacitor C2 needs to be selected according to the operating frequency and duty cycle of the circuit to ensure that sufficient voltage can be provided to the third NMOS transistor Q3 when it is turned on.

[0049] In a preferred embodiment, the second bootstrap circuit further includes a second zener diode Z2; the anode of the second zener diode Z2 is connected to the second bootstrap capacitor C2, and the cathode is connected to the gate of the third NMOS transistor Q3. The regulated voltage of the second zener diode Z2 is greater than the input voltage of the input power supply terminal and less than the maximum gate-source voltage V of the third NMOS transistor Q3 GS . In the second bootstrap circuit, due to the charging and discharging processes of the second bootstrap capacitor C2, a transient overvoltage phenomenon may occur. The second zener diode Z2 can be used as an overvoltage protection component to prevent the voltage across the second bootstrap capacitor C2 from being too high, thereby protecting other components in the circuit.

[0050] In some preferred embodiments, as Figure 5 shown, the first drive circuit includes a first drive chip U1; the input terminals TIM7-CH2 and TIM7-CH2N of the first drive chip U1 are connected to the main control chip. The HO port of the first drive chip is connected to the gate of the first NMOS transistor Q1, the LO port is connected to the gate of the second NMOS transistor Q2, and the HS port is connected to the switch node SW1, where the switch node SW1 is connected to the Buck-on switch. The VDD port of the first drive chip U1 is connected to the V12 output terminal of the auxiliary power supply, and the VSS port is grounded. In actual implementation, the first drive chip U1 can adopt the model SLM27211so-6x4-9-8p-1-27.

[0051] In some preferred embodiments, as Figure 6 shown, the second drive circuit includes a second drive chip U2; the input terminals TIM7-CH3 and TIM7-CH3N of the second drive chip U2 are connected to the main control chip. The HO port of the second drive chip U2 is connected to the gate of the third NMOS transistor Q3, the LO port is connected to the gate of the fourth NMOS transistor Q4, and the HS port is connected to the switch node SW2, where the switch node SW2 is connected to the Boost-on switch. The VDD port of the second drive chip U2 is connected to the V12 output terminal of the auxiliary power supply, and the VSS port is grounded. In actual implementation, the first drive chip U2 can adopt the model SLM27211so-6x4-9-8p-1-27.

[0052] In some preferred embodiments, the buck-boost conversion circuit supports the Buck mode: In the Buck mode, the main control chip is configured to transmit a first PWM signal to the first drive circuit to make the first NMOS transistor Q1 and the second NMOS transistor Q2 in the switching state and turn on the Buck-on switch; transmit a second PWM signal to the second drive circuit, and the duty cycle of the second PWM signal is set to 100% to make the third NMOS transistor Q3 and the fourth NMOS transistor Q4 in the always-on state and turn off the Boost-on switch.

[0053] In some preferred embodiments, the buck-boost conversion circuit supports the Buck-boost mode: In the Buck-boost mode, the main control chip is configured to transmit a first PWM signal to the first drive circuit to make the first NMOS transistor Q1 and the second NMOS transistor Q2 in the switching state and close the Buck-on switch; transmit a second PWM signal to the second drive circuit to make the third NMOS transistor Q3 and the fourth NMOS transistor Q4 in the switching state and turn off the Boost-on switch.

[0054] In some preferred embodiments, the buck-boost conversion circuit supports the Boost mode: In the Boost mode, the Boost-on switch is configured to be in the open state, the Buck-on switch is in the closed state, and the duty cycle of the first PWM signal transmitted by the main control chip to the first drive circuit is 100%.

[0055] The technical features of the above embodiments can be combined arbitrarily. For the sake of brief description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this specification.

[0056] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the above division of each functional unit and module is used as an example. In actual applications, the above functions can be allocated to different functional units and modules according to needs, that is, the internal structure of the system described in this application is divided into different functional units or modules to complete all or part of the functions described above.

Claims

1. A step-up / step-down conversion circuit for a digital power supply, characterized in that: include: A main control chip, a first driving circuit, a second driving circuit, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first bootstrap circuit and a second bootstrap circuit; The output end of the main control chip is connected to the input end of the first driving circuit and the input end of the second driving circuit, and is used to transmit a driving signal to the first driving circuit and the second driving circuit; The high-side driving signal output terminal of the first driving circuit is connected to the gate of the first NMOS tube, the low-side driving signal output terminal is connected to the gate of the second NMOS tube, and the source of the first NMOS tube is connected to the drain of the second NMOS tube; The high-side drive signal output terminal of the second drive circuit is connected to the gate of the third NMOS tube, the low-side drive signal output terminal is connected to the gate of the fourth NMOS tube, and the source of the third NMOS tube is connected to the drain of the fourth NMOS tube; The first bootstrap circuit is used to generate a bootstrap voltage to drive the first NMOS tube; The second bootstrap circuit is used to generate a bootstrap voltage to drive the third NMOS transistor.

2. The step-up / down conversion circuit for digital power supply according to claim 1, characterized in that: The first bootstrap circuit includes a first bootstrap diode and a first bootstrap capacitor; The anode of the first bootstrap diode is connected to the input power supply terminal, the cathode is connected to one end of the first bootstrap capacitor, and the other end of the first bootstrap capacitor is connected to the gate of the first NMOS tube.

3. The step-up / down conversion circuit for digital power supply according to claim 2, characterized in that: The first bootstrap circuit also includes a first zener diode; the anode of the first zener diode is connected to the first bootstrap capacitor, and the cathode is connected to the gate of the first NMOS tube. The zener voltage of the first zener diode is greater than the input voltage of the input power supply end and less than the maximum gate-source voltage of the first NMOS tube.

4. The step-up / down conversion circuit for digital power supply according to claim 1, characterized in that: The second bootstrap circuit includes a second bootstrap diode and a second bootstrap capacitor; The anode of the second bootstrap diode is connected to the input power supply terminal, the cathode is connected to one end of the second bootstrap capacitor, and the other end of the second bootstrap capacitor is connected to the gate of the third NMOS tube.

5. The step-up / down conversion circuit for digital power supply according to claim 4, characterized in that: The second bootstrap circuit also includes a second zener diode; the anode of the second zener diode is connected to the second bootstrap capacitor, and the cathode is connected to the gate of the third NMOS tube. The zener voltage of the second zener diode is greater than the input voltage of the input power supply terminal and less than the maximum gate-source voltage of the third NMOS tube.

6. The step-up / down conversion circuit for digital power supply according to claim 1, characterized in that: The first driving circuit includes a first driving chip; The input end of the first driver chip is connected to the main control chip, the HO port of the first driver chip is connected to the gate of the first NMOS tube, the LO port is connected to the gate of the second NMOS tube, and the HS port is connected to the switch node SW1, wherein the switch node SW1 is connected to the Buck-on switch.

7. The step-up / down conversion circuit for digital power supply according to claim 6, characterized in that: The second driving circuit includes a second driving chip; The input end of the second driver chip is connected to the main control chip, the HO port of the second driver chip is connected to the gate of the third NMOS tube, the LO port is connected to the gate of the fourth NMOS tube, and the HS port is connected to the switch node SW2, wherein the switch node SW2 is connected to the Boost-on switch.

8. The step-up / down conversion circuit for digital power supply according to claim 7, characterized in that: The buck-boost conversion circuit supports Buck mode: in Buck mode, the main control chip is configured to transmit a first PWM signal to the first drive circuit to put the first NMOS tube and the second NMOS tube in a switching state and turn on the Buck-on switch; and transmit a second PWM signal with a 100% duty cycle to the second drive circuit to put the third NMOS tube and the fourth NMOS tube in an always on state and turn off the Boost-on switch.

9. The step-up / down conversion circuit for digital power supply according to claim 7, characterized in that: The step-up / down conversion circuit supports the Buck-boost mode: in the Buck-boost mode, the main control chip is configured to transmit a first PWM signal to the first drive circuit so that the first NMOS tube and the second NMOS tube are in a switching state and the Buck-on switch is closed; and transmit a second PWM signal to the second drive circuit so that the third NMOS tube and the fourth NMOS tube are in a switching state and the Boost-on switch is closed.

10. The step-up / down conversion circuit for digital power supply according to claim 7, characterized in that: The buck-boost conversion circuit supports Boost mode: in Boost mode, the Boost-on switch is configured to be in an open state, the Buck-on switch is in a closed state, and the duty cycle of the first PWM signal transmitted by the main control chip to the first drive circuit is 100%.

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