Interface multiplexing circuit and electronic equipment

Abstract

The embodiment of the invention provides an interface multiplexing circuit and electronic equipment. The interface multiplexing circuit comprises a latch module, a processing module and an external interface, the input end of the latch module is connected with the external interface, the output end of the latch module is connected with an initial state pin of the processing module, and a data transmission pin of the processing module is connected with the external interface; the latch module is used for acquiring an initial state signal through the external interface and latching the initial state signal when the processing module is in a power-on state; the processing module is used for reading the initial state signal in the latch module through an initial state pin, and determining a starting mode of the processing module based on the initial state signal; and the processing module is also used for acquiring a data signal of the external interface through the data transmission pin after the processing module is started, and realizing external communication based on the data signal.

Description

Technical Field

[0001] This application relates to the field of integrated circuit design technology, and particularly to an interface multiplexing circuit and an electronic device. Background Art

[0002] In the electronic field, the pins of an integrated circuit serve as interfaces to connect the internal circuit of the integrated circuit to the external circuit. Each pin has its specific function, such as for signal input, signal output, signal control, etc. All the pins cooperate with each other to enable the integrated circuit to work properly. The more functions an integrated circuit has, the more pins it will have. Correspondingly, the packaging area of the integrated circuit will increase, resulting in an increase in the occupied space of the integrated circuit. Summary of the Invention

[0003] The purpose of the embodiments of this application is to provide an interface multiplexing circuit and an electronic device to reduce the occupied space of the integrated circuit. The specific technical solutions are as follows:

[0004] In a first aspect, the embodiments of this application provide an interface multiplexing circuit, and the circuit includes:

[0005] A latch module, a processing module, and an external interface;

[0006] The input end of the latch module is connected to the external interface, the output end of the latch module is connected to the initial state pin of the processing module, and the data transfer pin of the processing module is connected to the external interface.

[0007] In a possible implementation, the latch module is used to obtain an initial state signal through the external interface and latch the initial state signal when the processing module is in a powered-on state;

[0008] The processing module is used to read the initial state signal in the latch module through the initial state pin and determine its own startup mode based on the initial state signal;

[0009] The processing module is further used to obtain the data signal of the external interface through the data transfer pin after its own startup is completed and implement external communication based on the data signal.

[0010] In a possible implementation, the control end of the latch module is connected to the processing module;

[0011] The processing module is further used to generate a pulse signal when it is in a powered-on state and transmit the pulse signal to the control end of the latch module, so that the latch module latches the initial state signal based on the pulse signal;

[0012] The processing module is further configured to generate an invalid signal after its own power-on is completed, and transmit the invalid signal to the control end of the latch module, so that the latch module is in an output holding state.

[0013] In a possible implementation manner, the initial state pin includes a plurality of initial state sub-pins, the data transmission pin includes a plurality of data transmission sub-pins, the latch module includes a plurality of latches, and the external interface includes a plurality of external sub-interfaces;

[0014] The input end of the latch is connected to the external sub-interface in a one-to-one correspondence, the output end of the latch is connected to the initial state sub-pin in a one-to-one correspondence, and the data transmission sub-pin is connected to the external sub-interface in a one-to-one correspondence.

[0015] In a possible implementation manner, the latch is configured to obtain an initial state sub-signal of the initial state signal through its corresponding external sub-interface, and latch the initial state sub-signal when the processing module is in a power-on state;

[0016] The processing module is specifically configured to read the initial state sub-signal in the latch corresponding to the initial state sub-pin through the initial state sub-pin, determine its own startup mode based on the read initial state sub-signal; after its own startup is completed, obtain the data sub-signal of the external sub-interface corresponding to the data transmission sub-pin through the data transmission sub-pin, and implement external communication based on the obtained data sub-signal.

[0017] In a possible implementation manner, the initial state pin includes a first startup configuration sub-pin and a second startup configuration sub-pin; the data transmission pin includes a debug data transmission sub-pin and a clock signal transmission sub-pin; the latch module includes a first latch and a second latch; the external interface includes a first external sub-interface and a second external sub-interface;

[0018] The input end of the first latch is connected to the first external sub-interface, the output end of the first latch is connected to the first startup configuration sub-pin, and the debug data transmission sub-pin is connected to the first external sub-interface;

[0019] The input end of the second latch is connected to the second external sub-interface, the output end of the second latch is connected to the second startup configuration sub-pin, and the clock signal transmission sub-pin is connected to the second external sub-interface.

[0020] In a possible implementation manner, the first latch is configured to obtain a first startup configuration sub-signal of the initial state signal through the first external sub-interface, and latch the first startup configuration sub-signal when the processing module is in a power-on state;

[0021] The second latch is configured to obtain a second start-up configuration sub-signal of the initial state signal through the second external sub-interface, and latch the second start-up configuration sub-signal when the processing module is in a powered-on state;

[0022] The processing module is configured to read a first start-up configuration sub-signal in the first latch through the first start-up configuration sub-pin, read a second start-up configuration sub-signal in the second latch through the second start-up configuration sub-pin, and determine its own start-up mode based on the first start-up configuration sub-signal and the second start-up configuration sub-signal;

[0023] After the processing module completes its start-up, the processing module is further configured to obtain a debug data sub-signal of the first external sub-interface through the debug data transmission sub-pin, obtain a clock sub-signal of the second external sub-interface through the clock signal transmission sub-pin, and implement external debug communication based on the debug data sub-signal and the clock sub-signal.

[0024] In a second aspect, an embodiment of the present application provides an electronic device, which includes a signal transmission control circuit and the interface multiplexing circuit according to any one of the first aspects above;

[0025] The signal transmission control circuit includes a pull-up module and a switch module;

[0026] A first end of the pull-up module is connected to the positive power supply terminal, a first end of the switch module is respectively connected to a second end of the pull-up module and a data signal source, a second end of the switch module is connected to the negative power supply terminal, and a third end of the switch module is connected to an external interface of the interface multiplexing circuit.

[0027] In a possible implementation manner, the pull-up module includes a plurality of pull-up resistors, and the switch module includes a plurality of DIP switches;

[0028] A first end of the pull-up resistor is connected to the positive power supply terminal, a first end of the DIP switch is connected to a second end of the pull-up resistor in a one-to-one correspondence, the first end of the DIP switch is further connected to the data signal source, a second end of the DIP switch is connected to the negative power supply terminal, and a third end of the DIP switch is connected to an external sub-interface in a one-to-one correspondence.

[0029] In a possible implementation manner, the pull-up module includes a first pull-up resistor and a second pull-up resistor, and the switch module includes a first DIP switch and a second DIP switch;

[0030] The first end of the first pull-up resistor is connected to the positive power supply terminal. The first end of the first DIP switch is respectively connected to the second end of the first pull-up resistor and the data signal source. The second end of the first DIP switch is connected to the negative power supply terminal. The third end of the first DIP switch is connected to the first external sub-interface.

[0031] The first end of the second pull-up resistor is connected to the positive power supply terminal. The first end of the second DIP switch is respectively connected to the second end of the second pull-up resistor and the data signal source. The second end of the second DIP switch is connected to the negative power supply terminal. The third end of the second DIP switch is connected to the second external sub-interface.

[0032] Advantages of the embodiments of the present application:

[0033] An interface multiplexing circuit and an electronic device provided by the embodiments of the present application. The interface multiplexing circuit includes: a latching module, a processing module, and an external interface (pin). The input end of the latching module is connected to the external interface. The output end of the latching module is connected to the initial state pin of the processing module. The data transmission pin of the processing module is connected to the external interface. By setting the latching module, the signal corresponding to the initial state pin of the processing module is latched, so that the initial state pin of the processing module can perform functions based on the latching module, the external interface is released, and the data transmission pin of the processing module can perform functions based on the external interface, realizing that one external interface corresponds to two functions, achieving the multiplexing of the external interface, reducing the number of external interfaces, reducing the package area of the integrated circuit, and reducing the occupied space of the integrated circuit.

[0034] Of course, when implementing any product or method of the present application, it is not necessarily required to achieve all the above advantages at the same time. Description of the Drawings

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other embodiments can also be obtained based on these drawings.

[0036] Figure 1 It is a schematic diagram of the pin connection of an integrated circuit in the related art;

[0037] Figure 2 It is a first schematic structural diagram of the interface multiplexing circuit provided by the embodiments of the present application;

[0038] Figure 3 It is a second schematic structural diagram of the interface multiplexing circuit provided by the embodiments of the present application;

[0039] Figure 4The first flow schematic diagram of the interface multiplexing method provided by the embodiments of the present application;

[0040] Figure 5 The third structural schematic diagram of the interface multiplexing circuit provided by the embodiments of the present application;

[0041] Figure 6 The fourth structural schematic diagram of the interface multiplexing circuit provided by the embodiments of the present application;

[0042] Figure 7 The first structural schematic diagram of the electronic device provided by the embodiments of the present application;

[0043] Figure 8 The second structural schematic diagram of the electronic device provided by the embodiments of the present application;

[0044] Figure 9 The third structural schematic diagram of the electronic device provided by the embodiments of the present application;

[0045] Figure 10 The fourth structural schematic diagram of the electronic device provided by the embodiments of the present application;

[0046] Figure 11 The second flow schematic diagram of the interface multiplexing method provided by the embodiments of the present application;

[0047] Figure 12 A structural schematic diagram of the interface multiplexing system provided by the embodiments of the present application. Detailed implementation manners

[0048] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art based on the present application belong to the scope of protection of the present application.

[0049] In the field of electronics, the pins of an integrated circuit serve as interfaces to realize the connection between the internal circuit and the external circuit of the integrated circuit. Each pin has its specific function. For example, Figure 1As shown, it is a schematic diagram of pin connections of an integrated circuit in the related art. The boot configuration pins (BOOT0 and BOOT1) are used to connect the internal processor to the positive power supply terminal (VCC) and the negative power supply terminal (VSS). The debug data transfer pins (SWDIO and SWDCLK) are used to connect the internal processor to the SWD communication device. The boot configuration pins (BOOT0 and BOOT1) are used to configure the startup mode of the internal processor. By using the dip switches (S3 and S4), the assignment switching between 0 (low level) and 1 (high level) of the boot configuration pins is realized. Resistors R3 and R4 are pull-up resistors. The debug data transfer pins (SWDIO and SWDCLK) are used to realize the transfer of debug data. SWDIO is used for bidirectional transfer of debug data. SWDCLK is used to provide a clock signal for debug data transfer. The debug data transfer pins need to be pull-up processed (pull-up resistors R5 and R6), which is determined by the SWD (a serial debug protocol) protocol. Figure 1 Among them, BOOT_SEL0 and BOOT_SEL1 are the boot configuration pins of the internal processor, and SWD_IO and SWD_CLK are the debug data transfer pins of the internal processor.

[0050] Each pin of the integrated circuit cooperates with each other, enabling the integrated circuit to work properly. The more functions the integrated circuit has, the more pins there will be. Correspondingly, the package area of the integrated circuit will increase, resulting in an increase in the occupied space of the integrated circuit.

[0051] In order to improve the above problems, an embodiment of the present application provides an interface multiplexing circuit and an electronic device.

[0052] Next, a detailed description will be given of an interface multiplexing circuit 1 provided by an embodiment of the present application. Refer to Figure 2 , which is the first structural schematic diagram of the interface multiplexing circuit 1 provided by an embodiment of the present application. The interface multiplexing circuit 1 includes:

[0053] A latch module 11, a processing module 12, and an external interface 13;

[0054] The input end of the latch module 11 is connected to the external interface 13, the output end of the latch module 11 is connected to the initial state pin PINA of the processing module 12, and the data transfer pin PINB of the processing module 12 is connected to the external interface 13;

[0055] The latch module 11 is used to obtain the initial state signal of the signal source through the external interface 13 and latch the initial state signal when the processing module 12 is in the power-on state;

[0056] The processing module 12 is configured to, after its own power-on is completed, read the initial state signal in the latching module 11 through the initial state pin PINA, and determine its own startup mode based on the initial state signal;

[0057] The processing module 12 is further configured to, after its own startup is completed, obtain the data signal of the external interface 13 through the data transmission pin PINB, and communicate with the signal source based on the data signal.

[0058] It should be noted that the latching operation of the initial state signal has been completed before the processing module 12 starts. That is, when the initial state signal is latched, the processing module 12 has not started yet. Therefore, when the initial state signal is transmitted to the data transmission pin PINB, it will not affect the data transmission pin PINB. After the initial state signal is latched, the acquisition of the initial state signal can be disconnected.

[0059] In the embodiment of the present application, by setting the latching module 11, the initial state signal is latched when the processing module 12 is in the power-on state, so that when the initial state pin PINA of the processing module 12 executes its function, it can read the signal from the latching module 11, and the external interface 13 is released. After the processing module 12 starts, when its own data transmission pin PINB executes its function, it can obtain the data signal through the external interface 13, realizing that one external interface 13 corresponds to two functions, realizing the multiplexing of the external interface 13, which can reduce the number of external interfaces, reduce the packaging area of the integrated circuit, reduce the occupied space of the integrated circuit, and also improve the overall utilization rate of the integrated circuit.

[0060] In a possible implementation manner, refer to Figure 3 , the control end of the latching module 11 is connected to the processing module 12;

[0061] The processing module 12 is further configured to, when it is in the power-on state, generate a pulse signal and transmit the pulse signal to the control end of the latching module 11, so that the latching module 11 latches the initial state signal based on the pulse signal;

[0062] The processing module 12 is further configured to, after its own power-on is completed, generate an invalid signal and transmit the invalid signal to the control end of the latching module 11, so that the latching module 11 is in the output holding state until the next pulse signal is generated, and the initial state signal to be latched is updated.

[0063] The working principle of the latch module 11 is as follows: The latch module 11 is a storage unit sensitive to pulse signals (valid signals). When the control terminal of the latch module 11 receives a pulse signal (is triggered), the latch module 11 latches the input signal. When the control terminal of the latch module 11 becomes an invalid signal, even if the input signal changes, the output remains unchanged until the next pulse signal arrives.

[0064] When the processing module 12 is powered on, it generates a stable pulse signal. During one power-on working cycle of the processing module 12, this pulse signal occurs only once.

[0065] In the embodiment of the present application, during one power-on working cycle of the processing module 12, the pulse signal generated during power-on occurs only once, so that the latch module 11 latches the initial state signal based on this pulse signal. After power-on is completed, only an invalid signal exists at the control terminal of the latch module 11, and there will be no next pulse signal for triggering and updating. Therefore, even if the input signal changes, the output remains unchanged, and data transmission work can be performed at a flexible subsequent time, and the output of the latch module 11 will not be affected during data transmission.

[0066] Based on Figure 2 or Figure 3 the structure of the interface multiplexing circuit shown, the flow schematic of the corresponding interface multiplexing method can be referred to Figure 4 , including the following steps:

[0067] Step S401, obtain the initial state signal through the external interface 13, adjust the initial state signal, and determine the initial state signal to be latched.

[0068] Step S402, latch the initial state signal to be latched when the processing module 12 is in the powered-on state;

[0069] Step S403, after the processing module 12 is powered on, read the initial state signal in the latch module 11 through the initial state pin PINA, and determine the startup mode of the processing module 12 based on the initial state signal;

[0070] Step S404, after the processing module 12 starts up, obtain the data signal of the external interface 13 through the data transmission pin PINB, and communicate with the signal source based on the data signal.

[0071] The specific analysis is the same as above, and will not be elaborated here.

[0072] In the embodiment of the present application, by setting the latch module 11, the initial state signal is latched when the processing module 12 is in the powered-on state, so that when the initial state pin PINA of the processing module 12 executes its function, it can read the signal from the latch module 11, and the external interface 13 is released. After the processing module 12 starts, when its data transmission pin PINB executes its function, it can obtain the data signal through the external interface 13, realizing that one external interface 13 corresponds to two functions, achieving the multiplexing of the external interface 13, which can reduce the number of external interfaces, reduce the package area of the integrated circuit, reduce the occupied space of the integrated circuit, and also improve the overall utilization rate of the integrated circuit.

[0073] In a possible implementation manner, referring to Figure 5 , the initial state pin PINA includes a plurality of initial state sub-pins (PINA_0 to PINA_N), the data transmission pin PINB includes a plurality of data transmission sub-pins (PINB_0 to PINB_N), the latch module 11 includes a plurality of latches (110 to 11N), and the external interface 13 includes a plurality of external sub-interfaces (130 to 13N);

[0074] The input end of the latch is connected to the external sub-interface in a one-to-one correspondence, the output end of the latch is connected to the initial state sub-pin in a one-to-one correspondence, and the data transmission sub-pin is connected to the external sub-interface in a one-to-one correspondence;

[0075] The latch is configured to obtain the initial state sub-signal of the signal source through its corresponding external sub-interface, and latch the initial state sub-signal when the processing module 12 is in the powered-on state;

[0076] The processing module 12 is specifically configured to, after its own power-on is completed, read the initial state sub-signal in the latch corresponding to the initial state sub-pin through the initial state sub-pin, and determine its own startup mode based on the read initial state sub-signal; after its own startup is completed, obtain the data sub-signal of the external sub-interface corresponding to the data transmission sub-pin through the data transmission sub-pin, and communicate with the signal source based on the obtained data sub-signal.

[0077] In the embodiment of the present application, according to the actual situations of the initial state signal and the data signal, a plurality of latches and a plurality of external sub-interfaces can be set to match each sub-signal of the initial state signal and each sub-signal of the data signal.

[0078] In a possible implementation manner, referring to Figure 6, the initial state pin PINA includes a first boot configuration sub-pin BOOT_SEL0 and a second boot configuration sub-pin BOOT_SEL1; the data transfer pin PINB includes a debug data transfer sub-pin SWD_IO and a clock signal transfer sub-pin SWD_CLK; the latch module 11 includes a first latch L1 and a second latch L2; the external interface 13 includes a first external sub-interface PAD1 and a second external sub-interface PAD2;

[0079] The input end of the first latch L1 is connected to the first external sub-interface PAD1, the output end of the first latch L1 is connected to the first boot configuration sub-pin BOOT_SEL0, and the debug data transfer sub-pin SWD_IO is connected to the first external sub-interface PAD1;

[0080] The input end of the second latch L2 is connected to the second external sub-interface PAD2, the output end of the second latch L2 is connected to the second boot configuration sub-pin BOOT_SEL1, and the clock signal transfer sub-pin SWD_CLK is connected to the second external sub-interface PAD2;

[0081] The first latch L1 is used to obtain the first boot configuration sub-signal of the signal source through the first external sub-interface PAD1, and latch the first boot configuration sub-signal when the processing module 12 is in the power-on state;

[0082] The second latch L2 is used to obtain the second boot configuration sub-signal of the signal source through the second external sub-interface PAD2, and latch the second boot configuration sub-signal when the processing module 12 is in the power-on state;

[0083] The processing module 12 is used to read the first boot configuration sub-signal in the first latch L1 through the first boot configuration sub-pin BOOT_SEL0 and read the second boot configuration sub-signal in the second latch L2 through the second boot configuration sub-pin BOOT_SEL1 after its own power-on is completed, and determine its own boot mode based on the first boot configuration sub-signal and the second boot configuration sub-signal;

[0084] The processing module 12 is further used to obtain the debug data sub-signal of the first external sub-interface PAD1 through the debug data transfer sub-pin SWD_IO and obtain the clock sub-signal of the second external sub-interface PAD2 through the clock signal transfer sub-pin SWD_CLK after its own startup is completed, and perform debug communication with the signal source based on the debug data sub-signal, the clock sub-signal;

[0085] As described above, when the processing module 12 is powered on, a stable pulse signal is generated. During one power-on working cycle of the processing module 12, there is only one such pulse signal. The first latch L1 latches the first startup configuration sub-signal based on this one pulse signal, and the second latch L2 latches the second startup configuration sub-signal based on this one pulse signal. When the processing module 12 works until it needs to determine the startup mode, it reads the first startup configuration sub-signal in the first latch L1 through the first startup configuration sub-pin BOOT_SEL0, and reads the second startup configuration sub-signal in the second latch L2 through the second startup configuration sub-pin BOOT_SEL1, and determines the startup mode based on the first startup configuration sub-signal and the second startup configuration sub-signal (the first startup configuration sub-signal and the second startup configuration sub-signal jointly determine the startup mode of the processing module 12).

[0086] After the power-on is completed, only invalid signals exist at the control ends of the first latch L1 and the second latch L2, and there will be no next pulse signal for triggering and updating. Therefore, even if the input signal changes, the outputs of the first latch L1 and the second latch L2 will remain unchanged. When the processing module 12 is reset and restarted to re-read the latched signals, the signals latched in the latches will not be changed either. Only when powering on again can the signals latched in the latches be updated.

[0087] When the processing module 12 starts up and enters the debugging scenario, the external interfaces (the first external sub-interface PAD1 and the second external sub-interface PAD2) can be reused. The debugging data sub-signal of the first external sub-interface PAD1 is obtained through the debugging data transmission sub-pin SWD_IO, and the clock sub-signal of the second external sub-interface PAD2 is obtained through the clock signal transmission sub-pin SWD_CLK. Debugging communication is carried out with the signal source based on the debugging data sub-signal and the clock sub-signal, and the outputs of the first latch L1 and the second latch L2 are not affected during the debugging data transmission.

[0088] In the embodiment of the present application, by setting the first latch L1 and the second latch L2, the first startup configuration sub-signal and the second startup configuration sub-signal are latched when the processing module 12 is in the powered-on state, so that when the first startup configuration sub-pin BOOT_SEL0 and the second startup configuration sub-pin BOOT_SEL1 of the processing module 12 execute functions, they can read the signals from the latches. The first external sub-interface PAD1 and the second external sub-interface PAD2 are released. After the processing module 12 starts up, when the debugging data transmission sub-pin SWD_IO and the clock signal transmission sub-pin SWD_CLK execute functions, they can obtain the debugging data signals through the external interfaces, realizing the reuse of the external interfaces, which can reduce the number of external interfaces, reduce the packaging area of the integrated circuit, reduce the occupied space of the integrated circuit, and also improve the overall utilization rate of the integrated circuit.

[0089] The embodiment of the present application further provides an electronic device 2. Refer to Figure 7 , the electronic device 2 includes a signal transmission control circuit 21 and the interface multiplexing circuit 1 described in any of the above embodiments.

[0090] In a possible implementation manner, refer to Figure 8 , corresponding to Figure 2 the structure of the interface multiplexing circuit shown, the signal transmission control circuit 21 includes a pull-up module 211 and a switch module 212;

[0091] The first end of the pull-up module 211 is connected to the positive power supply terminal VCC, the first end of the switch module 212 is respectively connected to the second end of the pull-up module 211 and the data signal source, the second end of the switch module 212 is connected to the negative power supply terminal VSS, and the third end of the switch module 212 is connected to the external interface 13 of the interface multiplexing circuit 1.

[0092] Before power-on, first determine the initial state signal to be latched. According to the determined initial state signal, conduct between the third end of the switch module 212 and the corresponding end, so that the external interface 13 receives the initial state signal; after the processing module 12 is started, conduct between the third end and the first end of the switch module 212 (pull-up processing is required for data transmission), so that the external interface 13 is connected to the data signal source, and communication between the data signal source and the processing module 12 is realized.

[0093] In a possible implementation manner, refer to Figure 9 , corresponding to Figure 5 the structure of the interface multiplexing circuit shown, the pull-up module 211 includes a plurality of pull-up resistors R, and the switch module 212 includes a plurality of DIP switches S;

[0094] The first end of the pull-up resistor R is connected to the positive power supply terminal VCC, the first end of the DIP switch S is connected to the second end of the pull-up resistor R in one-to-one correspondence, the first end of the DIP switch S is also connected to the data signal source, the second end of the DIP switch S is connected to the negative power supply terminal VSS, and the third end of the DIP switch S is connected to the external sub-interfaces (130 to 13N) in one-to-one correspondence.

[0095] In a possible implementation manner, refer to Figure 10 , corresponding to Figure 6 the structure of the interface multiplexing circuit shown, the pull-up module 211 includes a first pull-up resistor R1 and a second pull-up resistor R2, and the switch module 212 includes a first DIP switch S1 and a second DIP switch S2;

[0096] The first end of the first pull-up resistor R1 is connected to the positive power supply terminal VCC. The first end of the first DIP switch S1 is respectively connected to the second end of the first pull-up resistor R1 and the data signal source. The second end of the first DIP switch S1 is connected to the negative power supply terminal VSS. The third end of the first DIP switch S1 is connected to the first external sub-interface PAD1;

[0097] The first end of the second pull-up resistor R2 is connected to the positive power supply terminal VCC. The first end of the second DIP switch S2 is respectively connected to the second end of the second pull-up resistor R2 and the data signal source. The second end of the second DIP switch S2 is connected to the negative power supply terminal VSS. The third end of the second DIP switch S2 is connected to the second external sub-interface PAD2.

[0098] Based on Figure 10 the structure of the electronic device shown, the process schematic of the corresponding interface multiplexing method can be seen in Figure 11 , including the following steps:

[0099] Step S1001, confirm the startup mode of the processing module 12 before power-on.

[0100] Step S1002, conduct between the third end of the first DIP switch S1 and the corresponding end, and conduct between the third end of the second DIP switch S2 and the corresponding end.

[0101] Step S1003, generate a pulse signal in the power-on state. The first latch L1 latches the first startup configuration sub-signal based on this pulse signal, and the second latch L2 latches the second startup configuration sub-signal based on this pulse signal.

[0102] Step S1004, the processing module 12 reads the first startup configuration sub-signal and the second startup configuration sub-signal, and performs corresponding startup mode operations.

[0103] Step S1005, when the processing module 12 starts and enters the debugging scenario, conduct between the third end of the first DIP switch S1 and the first end, and conduct between the third end of the second DIP switch S2 and the first end, so that the first external sub-interface PAD1 and the second external sub-interface PAD2 are connected to the data signal source, realizing the debugging communication between the data signal source and the processing module 12.

[0104] Before power-on, first confirm the startup mode of the processing module 12. For example, in the "01" mode, conduct between the third terminal and the second terminal of the first DIP switch S1 (the first startup configuration sub-signal is at a low level), and conduct between the third terminal and the first terminal of the second DIP switch S2 (the second startup configuration sub-signal is at a high level); for example, in the "11" mode, conduct between the third terminal and the first terminal of the first DIP switch S1 (the first startup configuration sub-signal is at a high level), and conduct between the third terminal and the first terminal of the second DIP switch S2 (the second startup configuration sub-signal is at a high level).

[0105] Generate a pulse signal in the powered-on state. The first latch L1 latches the first startup configuration sub-signal based on this pulse signal, and the second latch L2 latches the second startup configuration sub-signal based on this pulse signal.

[0106] The processing module 12 reads the first startup configuration sub-signal and the second startup configuration sub-signal, and performs corresponding startup mode operations.

[0107] When the processing module 12 starts up and enters the debugging scenario, conduct between the third terminal and the first terminal of the first DIP switch S1, and conduct between the third terminal and the first terminal of the second DIP switch S2 (the SWD debugging communication needs to be pulled up), so that the first external sub-interface PAD1 is connected to the data signal source with the second external sub-interface PAD2, and the debugging communication between the data signal source and the processing module 12 is realized.

[0108] The embodiment of the present application also provides an interface multiplexing system 3, see Figure 12 , the system 3 includes a data signal source and the electronic device 2 as described in any one of the above embodiments.

[0109] It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including a..." does not exclude the existence of additional identical elements in the process, method, article or device including the element.

[0110] Each embodiment in this specification is described in a related manner. For the same or similar parts among the embodiments, reference can be made to each other. Each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and reference can be made to the relevant part of the method embodiment for the related content.

[0111] The above are only the preferred embodiments of the present application and are not intended to limit the protection scope of the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application are all included in the protection scope of the present application.

Claims

1. An interface multiplexing circuit, characterized in that: The circuit comprises: Latch module, processing module, external interface; The input end of the latch module is connected to the external interface, the output end of the latch module is connected to the initial state pin of the processing module, and the data transmission pin of the processing module is connected to the external interface.

2. The circuit according to claim 1, characterized in that The latch module is used to obtain the initial state signal through the external interface, and latch the initial state signal when the processing module is in a powered-on state; The processing module is used to read the initial state signal in the latch module through the initial state pin, and determine its own startup mode based on the initial state signal; The processing module is further configured to obtain the data signal of the external interface through the data transmission pin after the processing module has started up, and to achieve external communication based on the data signal.

3. The circuit according to claim 2, characterized in that The control end of the latch module is connected to the processing module; The processing module is further configured to generate a pulse signal when the processing module is in a power-on state, and transmit the pulse signal to the control end of the latch module, so that the latch module latches the initial state signal based on the pulse signal; The processing module is further used to generate an invalid signal after the processing module is powered on, and transmit the invalid signal to the control end of the latch module to put the latch module in an output holding state.

4. The circuit according to claim 1, characterized in that The initial state pin includes a plurality of initial state sub-pins, the data transmission pin includes a plurality of data transmission sub-pins, the latch module includes a plurality of latches, and the external interface includes a plurality of external sub-interfaces; The input end of the latch is connected to the external sub-interface in a one-to-one correspondence, the output end of the latch is connected to the initial state sub-pin in a one-to-one correspondence, and the data transmission sub-pin is connected to the external sub-interface in a one-to-one correspondence.

5. The circuit according to claim 4, characterized in that The latch is used to obtain the initial state sub-signal of the initial state signal through its corresponding external sub-interface, and latch the initial state sub-signal when the processing module is in a powered-on state; The processing module is specifically used to read the initial state sub-signal in the latch corresponding to the initial state sub-pin through the initial state sub-pin, and determine its own startup mode based on the read initial state sub-signal; after its own startup is completed, obtain the data sub-signal of the external sub-interface corresponding to the data transmission sub-pin through the data transmission sub-pin, and realize external communication based on the obtained data sub-signal.

6. The circuit according to claim 1 or 4, characterized in that: The initial state pin includes a first startup configuration sub-pin and a second startup configuration sub-pin; the data transmission pin includes a debug data transmission sub-pin and a clock signal transmission sub-pin; the latch module includes a first latch and a second latch; the external interface includes a first external sub-interface and a second external sub-interface; The input end of the first latch is connected to the first external sub-interface, the output end of the first latch is connected to the first startup configuration sub-pin, and the debug data transmission sub-pin is connected to the first external sub-interface; The input end of the second latch is connected to the second external sub-interface, the output end of the second latch is connected to the second startup configuration sub-pin, and the clock signal transmission sub-pin is connected to the second external sub-interface.

7. The circuit according to claim 6, characterized in that The first latch is used to obtain a first startup configuration sub-signal of an initial state signal through the first external sub-interface, and latch the first startup configuration sub-signal when the processing module is in a powered-on state; The second latch is used to obtain a second startup configuration sub-signal of the initial state signal through the second external sub-interface, and latch the second startup configuration sub-signal when the processing module is in a powered-on state; The processing module is configured to read a first startup configuration sub-signal in the first latch through the first startup configuration sub-pin, read a second startup configuration sub-signal in the second latch through the second startup configuration sub-pin, and determine its own startup mode based on the first startup configuration sub-signal and the second startup configuration sub-signal; The processing module is also used to obtain the debug data sub-signal of the first external sub-interface through the debug data transmission sub-pin after its own startup is completed, and obtain the clock sub-signal of the second external sub-interface through the clock signal transmission sub-pin, and realize external debugging communication based on the debug data sub-signal and the clock sub-signal.

8. An electronic device, characterized in that: The electronic device comprises a signal transmission control circuit and an interface multiplexing circuit as described in any one of claims 1 to 7 above; The signal transmission control circuit includes a pull-up module and a switch module; The first end of the pull-up module is connected to the positive end of the power supply, the first end of the switch module is respectively connected to the second end of the pull-up module and the data signal source, the second end of the switch module is connected to the negative end of the power supply, and the third end of the switch module is connected to the external interface of the interface multiplexing circuit.

9. The device according to claim 8, characterized in that The pull-up module includes a plurality of pull-up resistors, and the switch module includes a plurality of dip switches; The first end of the pull-up resistor is connected to the positive terminal of the power supply, the first end of the dip switch is connected to the second end of the pull-up resistor in a one-to-one correspondence, the first end of the dip switch is also connected to the data signal source, the second end of the dip switch is connected to the negative terminal of the power supply, and the third end of the dip switch is connected to the external sub-interface in a one-to-one correspondence.

10. The device according to claim 8 or 9, characterized in that The pull-up module includes a first pull-up resistor and a second pull-up resistor, and the switch module includes a first dip switch and a second dip switch; The first end of the first pull-up resistor is connected to the positive terminal of the power supply, the first end of the first dip switch is connected to the second end of the first pull-up resistor and the data signal source respectively, the second end of the first dip switch is connected to the negative terminal of the power supply, and the third end of the first dip switch is connected to the first external sub-interface; The first end of the second pull-up resistor is connected to the positive terminal of the power supply, the first end of the second dip switch is respectively connected to the second end of the second pull-up resistor and the data signal source, the second end of the second dip switch is connected to the negative terminal of the power supply, and the third end of the second dip switch is connected to the second external sub-interface.

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