Pulse per second frequency phase synchronization system and method based on digital fractional accumulation

Abstract

The invention discloses a pulse-per-second frequency phase synchronization system and method based on digital fraction accumulation, and mainly solves the problem that the pulse-per-second output precision is deteriorated due to low time sequence precision of the existing pulse-per-second frequency adjustment. The system comprises a clock crystal oscillator, a digital frequency multiplication module connected with the clock crystal oscillator, a counter group module connected with the digital frequency multiplication module, and a frequency and phase resolving or identifying module connected with the counter group module. According to the invention, the T0 parameter, the DDS and the frequency control word number are reasonably designed, so that high-precision digital frequency control can be realized; all adjustment amounts are completed in a digital circuit, simulation frequency adjustment is not needed, adjustment time delay is controllable, adjustment precision is high, measurement and compensation are easy, and individual compensation does not need to be carried out on a voltage-controlled curve of the voltage-controlled crystal oscillator.

Description

Technical Field

[0001] The present invention belongs to the technical field of second pulse synchronization, and specifically relates to a second pulse frequency and phase synchronization system and method based on digital fractional accumulation. Background Art

[0002] In satellite navigation and timing systems, it is usually necessary to output a second pulse (1PPS) signal. Generally, a method of closed-loop calibration of frequency deviation by a voltage-controlled crystal oscillator and correction of the second pulse phase by digital clock delay is used. For a GNSS baseband processing circuit (or chip), the deviation of the local clock and frequency is usually obtained by position and speed calculation, the frequency is adjusted by adjusting the control voltage of the voltage-controlled crystal oscillator, and the phase of the second pulse is adjusted by a second pulse delay circuit, as Figure 1 shown.

[0003] The GNSS software obtains the frequency deviation and phase deviation through satellite information calculation or comparison with the time-frequency reference. The frequency deviation is calculated and mapped into a digital voltage, sent to a D / A converter to be converted into an analog control voltage Vc, and the voltage-controlled end of the frequency source voltage-controlled crystal oscillator is controlled to achieve frequency adjustment; the phase deviation is directly controlled by the second pulse delay circuit for phase adjustment of the output second pulse signal.

[0004] The existing control methods mainly have the following deficiencies:

[0005] 1. The voltage-controlled crystal oscillator is an analog circuit device, and there will be individual deviations in the response curve of the frequency output under the control of the analog voltage Vc, and a large amount of debugging work is required.

[0006] 2. To ensure the accuracy of the output second pulse, strict timing control is required for frequency adjustment and phase adjustment. Since the frequency adjustment is implemented in the analog domain and the phase adjustment is implemented in the digital domain, the timing accuracy of the adjustment is not high, and ultimately the output accuracy of the second pulse will deteriorate.

[0007] 3. After obtaining the error through satellite calculation and frequency and phase discrimination and then performing closed-loop adjustment on the circuit, there is a certain hysteresis effect, which will increase the adjustment error of the output pulse. Summary of the Invention

[0008] The purpose of the present invention is to provide a second pulse frequency and phase synchronization system and method based on digital fractional accumulation, mainly to solve the problem that the timing accuracy of the existing second pulse frequency adjustment is not high, and ultimately the output accuracy of the second pulse will deteriorate.

[0009] To achieve the above purpose, the technical solution adopted by the present invention is as follows:

[0010] A second pulse frequency and phase synchronization system based on digital fraction accumulation, comprising a clock oscillator, a digital frequency multiplier module connected to the clock oscillator, a counter group module connected to the digital frequency multiplier module, and a frequency and phase calculation or discrimination module connected to the counter group module; wherein, the clock oscillator is used to generate a local clock, the digital frequency multiplier module is used to multiply the local clock by a fixed ratio to provide a system clock; the counter group module obtains a second pulse signal by counting and dividing the system clock; the frequency and phase calculation or discrimination module is used to correct the digital quantities of the local frequency difference and phase difference.

[0011] Further, in the present invention, the counter group module adopts a two-stage counter.

[0012] Based on the above synchronization system, the present invention also provides a method for realizing second pulse frequency and phase synchronization based on digital fraction accumulation, comprising the following steps:

[0013] S1, generating a local clock by the clock oscillator, and converting the local clock into a system clock at a fixed ratio through the digital frequency multiplier module;

[0014] S2, the first-stage counter in the counter group module counts the system clock to a set T0; wherein, T0 < 1S; the second-stage counter in the counter group module counts T0 to 1S and then outputs;

[0015] S3, using the time scale of the set T0 as a synchronization enable to drive the enable frequency, phase calculation or discrimination module; the frequency, phase calculation or discrimination module accumulates the frequency control word FCW through a DDS accumulator, and judges the polarity of the frequency control word FCW and the most significant bit MSB of the DDS accumulator; adjusts the reference modulus value of the first-stage counter, and adds the output to the phase control quantity as the modulus value of the counter for T0.

[0016] Compared with the prior art, the present invention has the following beneficial effects:

[0017] (1) By reasonably designing the T0 parameter, DDS and the number of bits of the frequency control word, the present invention can achieve high-precision digital frequency control; all adjustment amounts are completed in the digital circuit, without the need to adjust the analog frequency, the adjustment time delay is controllable, the adjustment accuracy is high, it is easy to measure and compensate, and there is no need to individually compensate the voltage-controlled curve of the voltage-controlled crystal oscillator.

[0018] (2) By the action of writing the frequency adjustment amount, the present invention only needs to monitor the frequency difference, without the need to write the adjustment amount for each time source, reducing the software real-time requirement and improving the stability of the system. Description of the Drawings

[0019] Figure 1 It is a block diagram of a second pulse synchronization system in the prior art.

[0020] Figure 2 This is the block diagram of the second pulse synchronization system of the present invention.

[0021] Figure 3 This is the schematic diagram for adjusting the counter modulus value of T0 in an embodiment of the present invention. Detailed implementation manners

[0022] The present invention will be further described below in conjunction with the accompanying drawings and embodiments. The implementation manners of the present invention include but are not limited to the following embodiments.

[0023] Embodiment

[0024] As Figure 2 shown, a second pulse frequency and phase synchronization system based on digital fractional accumulation disclosed by the present invention includes a clock oscillator, a digital frequency multiplication module, a counter group module, and a frequency and phase resolution or discrimination module. Among them, the clock oscillator is generally implemented by a crystal oscillation device and is mainly used to generate a local reference clock (clock A), such as a 10 MHz clock oscillator. If a voltage-controlled oscillator is used, the frequency of the oscillator can be finely adjusted by adjusting the control voltage Vc. The digital frequency multiplication module provides various system clocks (clock B) required for digital circuits through frequency multiplication and frequency dividers, and has a fixed ratio with the oscillator clock. For example, a 10 MHz oscillator input generates a 50 MHz system clock or a 100 MHz system clock. The counter group module obtains a second pulse signal by counting and frequency dividing the system clock. The counter therein can be a single stage or multiple stages. For example, the two-stage counter in this embodiment: the first-stage counter completes the counting from 50 MHz to 0.5 ms (the counting modulus is 25000), and the second-stage counter completes the counting from 0.5 ms to 1 s (the counting modulus is 2000). The frequency and phase resolution or discrimination module is usually an algorithm module, which compares the local frequency and phase with the reference value obtained externally and obtains a digital quantity for correcting the local frequency difference and phase difference through algorithms.

[0025] In the present invention, the counter group design adopts a two-stage (or more) design. The first-stage counter counts from the system clock B to T0 (T0 is less than 1 s), and the second-stage counter counts from the T0 input to the 1 s output.

[0026] As Figure 3 shown, the frequency control word FCW is accumulated through DDS. By judging the polarity of the FCW and the most significant bit MSB of the accumulator, the reference modulus value of the counter for the T0 time is adjusted. After output, it is added to the phase control quantity to serve as the counter modulus value for the T0 time. All these calculations and judgments are synchronously enabled and driven by the T0 time scale.

[0027] Assume that the frequency of the system clock (clock B) is f s , and the calculated or discriminated system clock deviation is f d, if the number of bits of the DDS is N bits, then:

[0028]

[0029] Through the design of the T0 parameter, the frequency adjustment range can be determined as For example, when T0 is taken as 0.5 ms, the system frequency adjustment range is ±1 kHz.

[0030] By determining the DDS bit number N, the frequency adjustment accuracy can be determined. For example, when the system clock fs is 50 MHz, T0 is taken as 0.5 ms, and N is 16 bits, the frequency adjustment accuracy is

[0031] The input phase control quantity is the number of system clock cycles corresponding to the phase adjustment quantity, which can be adjusted by adjusting the modulus value of the counter. For example, if it is calculated that the local second pulse signal lags behind by 1 us in phase, then by reducing the modulus value by 50 within one counting cycle of the T0 counter (setting the phase control quantity register to -50 once), the local output second pulse signal can be advanced by 1 us to reach the required adjusted phase. If the adjustment amount exceeds 0.5 ms, the method of adjusting the modulus value of the T0 counter multiple times can be used to achieve the phase adjustment of the second pulse. Through hardware design, it can be fully ensured that the phase deviation is adjusted in place within 1 s.

[0032] The present invention uses a fractional accumulation DDS system. By judging the DDS overflow and the FCW sign, the modulus value of the counter is corrected to achieve the purpose of accurate frequency control. Combining the correction of the modulus value of the counter due to the phase error, the synchronous adjustment of the local second pulse frequency and phase can be realized. In addition, the present invention can adapt to the requirements of different frequency adjustment accuracies and adjustment ranges by flexibly configuring the bits of T0, FCW, and DDS, and has a certain generality.

[0033] The above embodiments are only one of the preferred embodiments of the present invention and should not be used to limit the protection scope of the present invention. Any meaningless changes or polishings made on the main design concept and spirit of the present invention, as long as the technical problems solved are still the same as those of the present invention, should be included in the protection scope of the present invention.

Claims

1. A pulse-per-second frequency phase synchronization system based on digital fractional accumulation, characterized in that: It includes a clock crystal oscillator, a digital frequency multiplication module connected to the clock crystal oscillator, a counter group module connected to the digital frequency multiplication module, and a frequency, phase resolution or identification module connected to the counter group module; wherein the clock crystal oscillator is used to generate a local clock, the digital frequency multiplication module is used to multiply the local clock by a fixed ratio to provide a system clock; the counter group module obtains a second pulse signal by counting and dividing the system clock; the frequency, phase resolution or identification module is used to correct the digital value of the local frequency difference and phase difference.

2. A pulse per second frequency phase synchronization system based on digital fractional accumulation according to claim 1, characterized in that: The counter group module adopts a two-level counter.

3. A method for realizing second pulse frequency phase synchronization based on digital fractional accumulation, characterized in that: The system as claimed in claim 2 is used, comprising the following steps: S1, a local clock is generated by a clock crystal oscillator, and the local clock is converted into a system clock at a fixed ratio through a digital frequency multiplication module; S2, the first-level counter in the counter group module counts the system clock to the set T0; where T0<1S; the second-level counter in the counter group module counts T0 to 1S and then outputs; S3, uses the set T0 time stamp as a synchronous enable to drive the frequency, phase resolution or identification module; the frequency, phase resolution or identification module accumulates the frequency control word FCW through the DDS accumulator, and determines the polarity of the frequency control word FCW and the highest bit MSB of the DDS accumulator; adjusts the reference modulus value of the first-level counter, outputs it and adds it to the phase control amount as the counter modulus value of T0.

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