Switch driving device of digital-to-analog converter

Abstract

The invention discloses a switch driving device of a digital-to-analog converter, which is arranged between a data synchronization module and a DAC core module, and comprises an enhancement unit used for accessing a differential signal output by the data synchronization module, improving the driving capability of the differential signal and outputting the differential signal as a driving signal to an adjustment unit; and the adjusting unit is used for receiving the driving signal, controlling the rising and falling time of the output voltage and the waveform, reducing the output amplitude and then outputting a switching signal to the DAC core module so as to drive digital-to-analog conversion. The driving capability of differential signals is improved through the enhancement unit, signal delay is reduced, and signal transmission stability is ensured; the position of the cross point is lowered through the adjusting unit, source jitter of the current-steering switch is reduced, and therefore output burrs are reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and particularly relates to a switch driving device for a digital-to-analog converter. Background Art

[0002] A high-speed digital-to-analog converter (D / A converter) can achieve a high conversion rate, and is mainly used in communication systems to provide an effective solution for multi-band and multi-standard radio frequency transceiver systems, and there is an urgent need in modern communication systems. With the development of communication technology towards higher frequencies and larger bandwidths, the performance requirements for digital-to-analog converters are becoming increasingly stringent.

[0003] However, the existing driving mechanism of high-speed digital-to-analog converters still has significant defects. For example, the driving ability of the switching signals in traditional high-speed digital-to-analog converters is weak, the signal has a large delay due to the limited charging and discharging speed of the load capacitance during transmission, and the synchronization between differential signals is poor, affecting the signal transmission stability. When the differential signal crossover point is too high, the two switches may be turned off due to a short overlap, resulting in an instantaneous interruption of the current source output, generating source-level jitter and causing output glitches in the current source. Summary of the Invention

[0004] Aiming at the above deficiencies of the prior art, the technical problem to be solved by the present invention is: to provide a switch driving device for a digital-to-analog converter that can improve the driving ability of switching signals and reduce the source-level jitter of switches.

[0005] To solve the above technical problem, a technical solution adopted by the present invention is: to provide a switch driving device for a digital-to-analog converter, which is arranged between a data synchronization module and a DAC core module, and includes:

[0006] An enhancement unit, configured to access the differential signals output by the data synchronization module, and after enhancing the driving ability of the differential signals, output them as driving signals to an adjustment unit; and

[0007] An adjustment unit, configured to receive the driving signals, control the rising and falling times of the output voltage and waveform, and after reducing the output amplitude, output switching signals to the DAC core module to drive digital-to-analog conversion.

[0008] Further, the differential signals include a first signal and a second signal that is inverted with respect to the first signal, and the driving signals include a first driving signal and a second driving signal;

[0009] The enhancement unit includes a first enhancement subunit and a second enhancement subunit. The first enhancement subunit is used to access a first signal, enhance the driving ability of the first signal, and then form a first driving signal to be output to the adjustment unit. The second enhancement subunit is used to access a second signal, enhance the driving ability of the second signal, and then form a second driving signal to be output to the adjustment unit.

[0010] Further, the first enhancement subunit includes a first inverter D1. The input terminal of the first inverter D1 serves as the first signal input terminal of the first enhancement subunit to access the first signal, and the output terminal of the first inverter D1 serves as the first driving signal output terminal of the first enhancement subunit and is electrically connected to the first driving signal input terminal of the adjustment unit.

[0011] Further, the second enhancement subunit includes a second inverter D2. The input terminal of the second inverter D2 serves as the second signal input terminal of the second enhancement subunit to access the second signal, and the output terminal of the second inverter D2 serves as the second driving signal output terminal of the second enhancement subunit and is electrically connected to the second driving signal input terminal of the adjustment unit.

[0012] Further, the switching signal includes a first switching signal and a second switching signal;

[0013] The adjustment unit includes a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, and a fourth MOS transistor M4. The gate of the first MOS transistor M1 serves as the first driving signal input terminal of the adjustment unit and is electrically connected to the output terminal of the first inverter. The source of the first MOS transistor M1 is grounded, and the drain of the first MOS transistor M1 serves as the first switching signal output terminal of the adjustment unit to output the first switching signal. The gate of the second MOS transistor M2 serves as the second driving signal input terminal of the adjustment unit and is electrically connected to the output terminal of the second inverter. The source of the second MOS transistor M2 serves as the first switching signal output terminal of the adjustment unit to output the first switching signal, and the drain of the second MOS transistor M2 is connected to a reference voltage Vref. The gate of the third MOS transistor M3 is electrically connected to the gate of the first MOS transistor M1. The source of the third MOS transistor M3 is connected to the reference voltage Vref, and the drain of the third MOS transistor M3 serves as the second switching signal output terminal of the adjustment unit to output the second switching signal. The gate of the fourth MOS transistor M4 is electrically connected to the gate of the third MOS transistor M3. The source of the fourth MOS transistor M4 serves as the second switching signal output terminal of the adjustment unit to output the second switching signal, and the drain of the fourth MOS transistor M4 is grounded.

[0014] Further, the intersection position of the switching signal is adjusted by changing the sizes of the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3, and the fourth MOS transistor M4.

[0015] Further, it further includes:

[0016] A latching unit for accelerating signal establishment through positive feedback, reducing the delay between differential signals, and stabilizing the position of the intersection of the rising edge and the falling edge of the switching signal.

[0017] Further, the latching unit includes a first latching subunit, and the first latching subunit includes a fifth inverter D5 and a sixth inverter D6; the input end of the fifth inverter D5 is electrically connected to the output end of the first inverter D1, and the output end of the fifth inverter D5 is electrically connected to the output end of the second inverter D2; the output end of the sixth inverter D6 is electrically connected to the output end of the first inverter D1, and the input end of the sixth inverter D6 is electrically connected to the output end of the second inverter D2.

[0018] Further, the first enhancement subunit further includes a third inverter D3, the input end of the third inverter D3 is electrically connected to the output end of the first inverter D1, and the output end of the third inverter D3 is electrically connected to the first drive signal input end of the adjustment unit;

[0019] The second enhancement subunit further includes a fourth inverter D4, the input end of the fourth inverter D4 is electrically connected to the output end of the second inverter D2, and the output end of the fourth inverter D4 is electrically connected to the first drive signal input end of the adjustment unit.

[0020] Further, the latching unit further includes a second latching subunit, and the second latching subunit includes a seventh inverter D7 and an eighth inverter D8; the input end of the seventh inverter D7 is electrically connected to the output end of the third inverter D3, and the output end of the seventh inverter D7 is electrically connected to the output end of the fourth inverter D4; the input end of the eighth inverter D8 is electrically connected to the output end of the fourth inverter D4, and the output end of the eighth inverter D8 is electrically connected to the output end of the third inverter D3.

[0021] The switching drive device of the digital-to-analog converter of the present invention has at least the following beneficial effects: By means of the enhancement unit, the driving ability of the differential signal is improved, and the number of expandable inverters is used to flexibly adapt to different load requirements. On the premise of ensuring controllable cost and volume, signal delay is reduced to ensure signal transmission stability. The latching unit is used to accelerate signal establishment and reduce the delay between differential signals, thereby reducing the error at the intersection of the rising and falling edges of the switching signal, and greatly improving the accuracy of the switching signal. The adjustment unit consists of PMOS transistors. By adjusting the gate voltage and transistor size, the intersection position can be lowered, and at the same time, the reference voltage Vref is introduced to limit the switching signal, reducing the amplitude of the switching signal and significantly improving the switching speed. The enhancement unit and the latching unit work together to reduce the source jitter of the current-steering switch and suppress the problem of simultaneous turn-off of differential switches caused by too high intersection points in traditional designs, thereby reducing output glitches and improving the overall linearity of the digital-to-analog converter. Compared with the traditional intersection adjustment scheme using operational amplifiers, this scheme is completely based on inverters and MOS transistors, reducing power consumption and eliminating the need for additional compensation circuits, simplifying the design complexity. The switching drive device of the present invention can optimize the signal-to-noise ratio and spurious-free dynamic range of the digital-to-analog converter to meet the high-precision requirements of multi-band radio frequency systems. Brief Description of the Drawings

[0022] The drawings described herein are used to provide a further understanding of the present application, and constitute a part of the present application. The illustrative embodiments and descriptions thereof are used to explain the present application and do not constitute an improper limitation of the present application. In the drawings:

[0023] Figure 1 It is a structural diagram of a high-speed digital-to-analog converter.

[0024] Figure 2 It is a structural block diagram of an embodiment of the switching drive device of the digital-to-analog converter of the present invention.

[0025] Figure 3 It is a circuit diagram of an embodiment of the switching drive device of the digital-to-analog converter of the present invention.

[0026] Figure 4 It is a comparison diagram of switching signal waveforms before and after using the switching drive device of the digital-to-analog converter of the present invention.

[0027] Figure 5 For Figure 1 the performance simulation spectrum diagram of the digital-to-analog converter. Detailed Embodiments

[0028] The present invention will be further described below with reference to the drawings.

[0029] Please refer to Figure 1, which is a structural diagram of a high-speed digital-to-analog converter. The switch driving device of the digital-to-analog converter of the present invention is arranged between the data synchronization module and the DAC core module. High-speed digital-to-analog converters are usually applied to radio frequency transmission channels. The output signal from the baseband is first processed through the data channel, and then the driving ability is improved and the signal crossover point is adjusted through the device designed by the present invention. Finally, the digital-to-analog converter core is driven to complete digital-to-analog conversion.

[0030] Please refer to Figure 2 and Figure 3 , the switch driving device of the digital-to-analog converter of the present invention includes an enhancement unit 100 and an adjustment unit 200. The enhancement unit 100 is used to access the differential signal output by the data synchronization module, and after enhancing the driving ability of the differential signal, it outputs the driving signal to the adjustment unit 200. The adjustment unit 200 is used to receive the driving signal, control the rising and falling times of the output voltage and waveform, and reduce the output amplitude, and then output a switching signal to the DAC core module to drive digital-to-analog conversion. The differential signal includes a first signal and a second signal that is inverted with respect to the first signal. The driving signal includes a first driving signal and a second driving signal.

[0031] The enhancement unit 100 includes a first enhancement sub-unit 110 and a second enhancement sub-unit 120. The first enhancement sub-unit 110 is used to access the first signal, and after enhancing the driving ability of the first signal, it forms a first driving signal and outputs it to the adjustment unit 200; the second enhancement sub-unit 120 is used to access the second signal, and after enhancing the driving ability of the second signal, it forms a second driving signal and outputs it to the adjustment unit 200. The first enhancement sub-unit 110 includes a first inverter D1. The input terminal of the first inverter D1 serves as the first signal input terminal D of the first enhancement sub-unit 110 to access the first signal; the output terminal of the first inverter D1 serves as the first driving signal output terminal of the first enhancement sub-unit 110 and is electrically connected to the first driving signal input terminal of the adjustment unit 200. The second enhancement sub-unit 120 includes a second inverter D2. The input terminal of the second inverter D2 serves as the second signal input terminal DN of the second enhancement sub-unit 120 to access the second signal; the output terminal of the second inverter D2 serves as the second driving signal output terminal of the second enhancement sub-unit 120 and is electrically connected to the second driving signal input terminal of the adjustment unit 200.

[0032] It should be understood that the number of inverters in the first enhancer unit 110 and the second enhancer unit 120 is the same, and they can be increased or decreased simultaneously according to actual requirements. The more inverters there are, the stronger the driving ability of the differential signal. To improve the driving ability of the differential signal and taking into account cost and device volume at the same time, in this embodiment, both the first enhancer unit 110 and the second enhancer unit 120 are provided with two inverters. Specifically, the first enhancer unit 110 further includes a third inverter D3. The input end of the third inverter D3 is electrically connected to the output end of the first inverter D1, and the output end of the third inverter D3 is electrically connected to the first drive signal input end of the adjustment unit 200. The second enhancer unit 120 further includes a fourth inverter D4. The input end of the fourth inverter D4 is electrically connected to the output end of the second inverter D2, and the output end of the fourth inverter D4 is electrically connected to the first drive signal input end of the adjustment unit 200.

[0033] The adjustment unit 200 includes a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, and a fourth MOS transistor M4. The gate of the first MOS transistor M1 serves as the first drive signal input end of the adjustment unit 200 and is electrically connected to the output end of the first inverter; the source of the first MOS transistor M1 is grounded; the drain of the first MOS transistor M1 serves as the first switch signal output end S of the adjustment unit 200 to output a first switch signal. The gate of the second MOS transistor M2 serves as the second drive signal input end of the adjustment unit 200 and is electrically connected to the output end of the second inverter; the source of the second MOS transistor M2 serves as the first switch signal output end S of the adjustment unit 200 to output a first switch signal; the drain of the second MOS transistor M2 is connected to a reference voltage Vref. The gate of the third MOS transistor M3 is electrically connected to the gate of the first MOS transistor M1; the source of the third MOS transistor M3 is connected to the reference voltage Vref; the drain of the third MOS transistor M3 serves as the second switch signal output end SN of the adjustment unit 200 to output a second switch signal. The gate of the fourth MOS transistor M4 is electrically connected to the gate of the third MOS transistor M3; the source of the fourth MOS transistor M4 serves as the second switch signal output end SN of the adjustment unit 200 to output a second switch signal; the drain of the fourth MOS transistor M4 is grounded. The first switch signal and the second switch signal constitute a switch signal. The first MOS transistor M1 and the fourth MOS transistor M4 control the waveform falling time, and the second MOS transistor M2 and the third MOS transistor M3 control the waveform rising time. By changing the sizes of the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3, and the fourth MOS transistor M4, the intersection position of the switch signal can be adjusted. At the same time, by introducing a reference voltage Vref, the limiting of the switch signal is realized.

[0034] To stabilize the intersection point of the switching signal, as a preferred embodiment, a latch unit 300 is further provided. The latch unit 300 is used to accelerate signal establishment through positive feedback, reduce the delay between differential signals, and stabilize the position of the intersection point of the rising edge and falling edge of the switching signal. The latch unit 300 includes a first latch sub-unit 310, and the first latch sub-unit 310 includes a fifth inverter D5 and a sixth inverter D6. The input end of the fifth inverter D5 is electrically connected to the output end of the first inverter D1, and the output end of the fifth inverter D5 is electrically connected to the output end of the second inverter D2. The output end of the sixth inverter D6 is electrically connected to the output end of the first inverter D1, and the input end of the sixth inverter D6 is electrically connected to the output end of the second inverter D2. When the second signal received by the second enhancer unit 120 is delayed, the first signal received by the first latch sub-unit 310 can also output a second driving signal through the latch unit 300 to control the on / off of the second MOS transistor M2 and the fourth MOS transistor M4. The latch unit 300 can reduce the delay between differential signals, thereby reducing the error in the position of the intersection point of the rising edge and falling edge of the switching signal.

[0035] It should be understood that the number of latch sub-units can be set according to actual requirements. To improve the stability of the switching signal and considering cost and power consumption at the same time, as a preferred embodiment, the latch unit 300 further includes a second latch sub-unit 320. The second latch sub-unit 320 includes a seventh inverter D7 and an eighth inverter D8. The input end of the seventh inverter D7 is electrically connected to the output end of the third inverter D3, and the output end of the seventh inverter D7 is electrically connected to the output end of the fourth inverter D4. The input end of the eighth inverter D8 is electrically connected to the output end of the fourth inverter D4, and the output end of the eighth inverter D8 is electrically connected to the output end of the third inverter D3.

[0036] The working principle of this embodiment is as follows:

[0037] After the enhancement unit 100 accesses the differential signal, the inverters in the first enhancer unit 110 and the second enhancer unit 120 improve the driving ability of the differential signal. If the first enhancer unit 110 accesses a high level, the second enhancer unit 120 accesses a low level. At this time, the first MOS transistor M1 and the third MOS transistor M3 are turned on, and the second MOS transistor M2 and the fourth MOS transistor M4 are turned off. The first switch signal output terminal S outputs a low level, and the second switch signal output terminal SN outputs Vref. If the first enhancer unit 110 accesses a low level, the second enhancer unit 120 accesses a high level. At this time, the first MOS transistor M1 and the third MOS transistor M3 are cut off, and the second MOS transistor M2 and the fourth MOS transistor M4 are turned on. The first switch signal output terminal S outputs Vref, and the second switch signal output terminal SN outputs a low level. If the second signal is delayed, the first signal outputs a second driving signal through the latch unit 300 to control the working states of the second MOS transistor M2 and the fourth MOS transistor M4; if the first signal is delayed, the second signal outputs a first driving signal through the latch unit 300 to control the working states of the first MOS transistor M1 and the third MOS transistor M3. The crossover point position of the switch signal can also be adjusted by changing the sizes of the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3, and the fourth MOS transistor M4.

[0038] Please refer to Figure 4 , which is a comparison diagram of switch signal waveforms before and after using the switch driving device of the digital-to-analog converter of the present invention. The upper waveform is the switch signal waveform before using the switch driving device of the digital-to-analog converter. The crossover error between its rising edge and falling edge is 50 mV, the signal amplitude is 1.1 V, and the crossover point position is at 50% of the full amplitude. The lower waveform is the switch signal waveform after using the switch driving device of the digital-to-analog converter. It can be seen that the crossover error between its rising edge and falling edge drops to 2 mV, the signal amplitude is limited to 400 mV, and the crossover point position drops to 25% of the full amplitude. After using the switch driving device of the digital-to-analog converter, the error between the rising edge and falling edge of the switch signal decreases and the crossover point position drops, thereby reducing the source jitter of the current-steering switch of the digital-to-analog converter. The amplitude of the switch signal waveform decreases, improving the switching speed of the switch. And this solution does not use an operational amplifier, so the power consumption is lower compared with other switch crossover adjustment circuits. Figure 1 The performance simulation of the digital-to-analog converter shown is as Figure 5 shown, the SNR (signal-to-noise ratio) reaches 36 dB, and the SFDR (spurious-free dynamic range) reaches 50 dB.

[0039] The present invention enhances the driving ability of the switching signal through the enhancement unit 100, flexibly adapts to different load requirements through the scalable number of inverters, reduces signal delay while ensuring controllable cost and volume, and ensures signal transmission stability; accelerates signal establishment through the latch unit 300, reduces the delay between differential signals, thereby reducing the cross-point error between the rising edge and the falling edge of the switching signal, and greatly improves the accuracy of the switching signal; the adjustment unit 200 is composed of PMOS transistors, can reduce the cross-point position by adjusting the gate voltage and transistor size, and at the same time introduces a reference voltage Vref to limit the switching signal, reducing the amplitude of the switching signal, and significantly improving the switching speed; the enhancement unit 100 and the latch unit 300 cooperate to reduce the source jitter of the current-steering switch, suppress the problem of simultaneous turn-off of differential switches caused by too high cross-points in traditional designs, thereby reducing output glitches and improving the overall linearity of the digital-to-analog converter; compared with the traditional cross-point adjustment scheme using operational amplifiers, this scheme is completely implemented based on inverters and MOS transistors, reduces power consumption and does not require additional compensation circuits, simplifying the design complexity; the switching drive device of the present invention can optimize the signal-to-noise ratio and spurious-free dynamic range of the digital-to-analog converter, meeting the high-precision requirements of multi-band radio frequency systems.

[0040] The above content only expresses the preferred embodiments of the present invention, and its description is relatively specific and detailed, but it cannot be understood as a limitation to the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can be made, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the invention patent should be subject to the appended claims.

Claims

1. A switch driving device of a digital-to-analog converter, arranged between a data synchronization module and a DAC core module, characterized in that: include: An enhancement unit, used for accessing the differential signal output by the data synchronization module, and improving the driving capability of the differential signal and then outputting it as a driving signal to the adjustment unit; as well as The adjustment unit is used to receive the driving signal and control the rise and fall time of the output voltage and waveform, and output the switching signal to the DAC core module after reducing the output amplitude to drive the digital-to-analog conversion.

2. The switch driving device of the digital-to-analog converter according to claim 1, characterized in that: The differential signal includes a first signal and a second signal which is inverted with respect to the first signal, and the drive signal includes a first drive signal and a second drive signal; The enhancement unit includes a first enhancement subunit and a second enhancement subunit. The first enhancement subunit is used to access a first signal and enhance the driving ability of the first signal to form a first driving signal output to the adjustment unit. The second enhancement subunit is used to access a second signal and enhance the driving ability of the second signal to form a second driving signal output to the adjustment unit.

3. The switch driving device of the digital-to-analog converter according to claim 2, characterized in that: The first enhancement subunit includes a first inverter D1, an input end of the first inverter D1 is used as a first signal input end of the first enhancement subunit to access a first signal, and an output end of the first inverter D1 is used as a first drive signal output end of the first enhancement subunit to be electrically connected to a first drive signal input end of the adjustment unit.

4. The switch driving device of the digital-to-analog converter according to claim 3, characterized in that: The second enhancer unit includes a second inverter D2, an input end of the second inverter D2 is used as a second signal input end of the second enhancer unit to access the second signal, and an output end of the second inverter D2 is used as a second drive signal output end of the second enhancer unit to be electrically connected to the second drive signal input end of the adjustment unit.

5. The switch driving device of the digital-to-analog converter according to claim 4, characterized in that: The switch signal includes a first switch signal and a second switch signal; The adjustment unit includes a first MOSFET M1, a second MOSFET M2, a third MOSFET M3 and a fourth MOSFET M4; the gate of the first MOSFET M1 is electrically connected to the output end of the first inverter as the first drive signal input end of the adjustment unit, the source of the first MOSFET M1 is grounded, and the drain of the first MOSFET M1 is used as the first switch signal output end of the adjustment unit to output the first switch signal; the gate of the second MOSFET M2 is electrically connected to the output end of the second inverter as the second drive signal input end of the adjustment unit, and the source of the second MOSFET M2 is used as the first switch signal output end of the adjustment unit. The first switching signal is outputted at the switching signal output terminal of the adjustment unit, and the drain of the second MOSFET M2 is connected to the reference voltage Vref; the gate of the third MOSFET M3 is electrically connected to the gate of the first MOSFET M1, the source of the third MOSFET M3 is connected to the reference voltage Vref, and the drain of the third MOSFET M3 serves as the second switching signal output terminal of the adjustment unit to output the second switching signal; the gate of the fourth MOSFET M4 is electrically connected to the gate of the third MOSFET M3, the source of the fourth MOSFET M4 serves as the second switching signal output terminal of the adjustment unit to output the second switching signal, and the drain of the fourth MOSFET M4 is grounded.

6. The switch driving device of the digital-to-analog converter according to claim 5, characterized in that: The cross point position of the switch signal is adjusted by changing the sizes of the first MOS transistor M1 , the second MOS transistor M2 , the third MOS transistor M3 and the fourth MOS transistor M4 .

7. The switch driving device of the digital-to-analog converter according to claim 4, characterized in that: Also includes: The latch unit is used to accelerate signal establishment through positive feedback, reduce the delay between differential signals, and stabilize the position of the intersection of the rising edge and the falling edge of the switching signal.

8. The switch driving device of the digital-to-analog converter according to claim 7, characterized in that: The latch unit includes a first latch sub-unit, which includes a fifth inverter D5 and a sixth inverter D6; the input end of the fifth inverter D5 is electrically connected to the output end of the first inverter D1, and the output end of the fifth inverter D5 is electrically connected to the output end of the second inverter D2; the output end of the sixth inverter D6 is electrically connected to the output end of the first inverter D1, and the input end of the sixth inverter D6 is electrically connected to the output end of the second inverter D2.

9. The switch driving device of the digital-to-analog converter according to claim 8, characterized in that: The first enhancement subunit further includes a third inverter D3, an input end of the third inverter D3 is electrically connected to an output end of the first inverter D1, and an output end of the third inverter D3 is electrically connected to a first driving signal input end of the adjustment unit; The second enhancement subunit further includes a fourth inverter D4, an input end of the fourth inverter D4 is electrically connected to the output end of the second inverter D2, and an output end of the fourth inverter D4 is electrically connected to the first driving signal input end of the adjustment unit.

10. The switch driving device of the digital-to-analog converter according to claim 9, characterized in that: The latch unit also includes a second latch sub-unit, which includes a seventh inverter D7 and an eighth inverter D8; the input end of the seventh inverter D7 is electrically connected to the output end of the third inverter D3, and the output end of the seventh inverter D7 is electrically connected to the output end of the fourth inverter D4; the input end of the eighth inverter D8 is electrically connected to the output end of the fourth inverter D4, and the output end of the eighth inverter D8 is electrically connected to the output end of the third inverter D3.

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