Circuit for suppressing POP sound of TDA7265 power amplifier system
By adopting adaptive timing control, on-chip integrated slow-lift circuit and common-mode-signal collaborative isolation technology in the TDA7265 amplifier system, the problems of hardware complexity and suppression accuracy conflicts and dynamic operating conditions are solved, and better POP sound suppression effect and production efficiency are achieved.
Patent Information
- Application Number
- CN202510562403.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-30
- Publication Date
- 2025-06-27
AI Technical Summary
There are problems in the existing TDA7265 amplifier system where hardware complexity conflicts with suppression accuracy and dynamic operating conditions are not matched, resulting in unsatisfactory POP sound suppression effect.
Adaptive timing control, on-chip integrated slow-lift circuit and common-mode-signal collaborative isolation technology are adopted, and the delay time is dynamically adjusted by the IO pin and transistor switch to achieve stable control of the amplifier power supply, reduce external DAC modules and filter capacitors, and reduce BOM cost and chip area.
Systematically solves the problems of conflicts between hardware complexity and suppression accuracy and mismatch between dynamic working conditions, improves the POP sound suppression effect, reduces production costs and energy consumption, and is suitable for high-demand scenarios such as high-fidelity audio equipment and vehicle electronics.
Smart Images
Figure CN120224077A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of audio engineering, and in particular to a circuit for suppressing POP noise in a TDA7265 power amplifier system. Background Art
[0002] As a classic class-AB power amplifier chip, the TDA7265 power amplifier system is widely used in scenarios such as car audio, home theater, smart speakers, etc. Especially in the field of car audio, it is required to meet the stability and low POP noise requirements under the wide temperature condition of -40°C - 85°C. The existing POP noise suppression technologies are mainly divided into two categories: hardware control and feedback optimization. There are problems in the prior art such as the conflict between hardware complexity and suppression accuracy, and the mismatch of dynamic working conditions. The traditional reference voltage slow-rise scheme requires an external DAC or RC filter network, resulting in a 15% - 20% increase in chip area, and additional filter pins and capacitors are needed. The traditional mute circuit cuts off the output path through an external triode switch, but the multi-stage discrete component layout is complex and the failure rate is high. The traditional delay control circuit relies on the fixed resistor voltage division timing and cannot adapt to the power supply voltage fluctuation, making the POP noise suppression effect unsatisfactory. Summary of the Invention
[0003] The purpose of the present invention is to solve the deficiencies existing in the prior art, and to propose a circuit for suppressing POP noise in a TDA7265 power amplifier system.
[0004] To achieve the above purpose, the present invention adopts the following technical solution: A circuit for suppressing POP noise in a TDA7265 power amplifier system, including a system sound source, an ASP processing circuit, a power amplifier power supply control circuit, a power amplifier circuit, an STBY\MUTE control circuit, and a speaker. The system sound source is electrically connected to the ASP processing circuit, the ASP processing circuit is electrically connected to the power amplifier circuit, the power amplifier power supply control circuit is electrically connected to the ASP processing circuit and the power amplifier circuit respectively, the STBY and MUTE control circuit is electrically connected to the power amplifier circuit, the power amplifier circuit is electrically connected to the speaker, and the power amplifier power supply control circuit is responsible for managing and controlling the power supply of the power amplifier VS pin and the power amplifier pin 5 of the power amplifier circuit in the audio system, and supplying power to the ASP processing circuit.
[0005] Preferably, the components of the power amplifier power supply control circuit that supply power to the VS pin of the power amplifier include a first capacitor C192, a second capacitor C206, a third capacitor C184, a fourth capacitor C171, a first transistor Q110, a second transistor Q111, a first resistor R161, a second resistor R162, a third resistor R105, a fourth resistor R194, a first timer TP139, and a second timer TP104. The source of the first transistor Q110 is electrically connected to VIN_POW, the drain of the first transistor Q110 is electrically connected to AMP_POW, the first timer TP139 is electrically connected to the electrical connection node between the drain of the first transistor Q110 and AMP_POW, one end of the first resistor R161 is electrically connected to the source of the first transistor Q110, and the other end is electrically connected to the gate of the first transistor Q110. One end of the fourth capacitor C171 is electrically connected to the source of the first transistor Q110, and the other end is electrically connected to the gate of the first transistor Q110. One end of the first capacitor C192 is electrically connected to one end of the second capacitor C206, and the other end of the first capacitor C192 is electrically connected to the electrical connection node between the fourth capacitor C171 and VIN_POW. The other end of the second capacitor C206 is electrically connected to the electrical connection node between the fourth capacitor C171 and VIN_POW. The connection node between the first capacitor C192 and the second capacitor C206 is grounded. The gate of the first transistor Q110 is electrically connected to the collector of the second transistor Q111 through the second resistor R162. The second timer TP104 is electrically connected to the electrical connection node between the other end of the second resistor R162 and the collector of the second transistor Q111. The emitter of the second transistor Q111 is grounded. One end of the third capacitor C184 is electrically connected to the base of the second transistor Q111, and the other end is electrically connected to the emitter of the second transistor Q111. The third resistor R105 is electrically connected to the electrical connection node between one end of the third capacitor C184 and the base of the second transistor Q111, and the other end is connected to AMP_POW_EN. The fourth resistor R194 is electrically connected to the electrical connection node between one end of the third capacitor C184 and the base of the second transistor Q111, and the other end is connected to MCU_AMP_POW_EN.
[0006] Preferably, the components of the power amplifier power supply control circuit that supply power to the 5th pin of the power amplifier include a third transistor Q117, a fourth transistor Q116, a fifth resistor R191, a sixth resistor R192, a seventh resistor R193, a fifth capacitor C248, and a sixth capacitor C249. The source of the fourth transistor Q116 is electrically connected to VIN_POW, the drain of the fourth transistor Q116 is electrically connected to AMP_5Viao, the gate of the fourth transistor Q116 is electrically connected to the collector of the third transistor Q117 through the sixth resistor R192. One end of the fifth capacitor C248 is electrically connected to VIN_POW, and the other end is electrically connected to the gate of the fourth transistor Q116. One end of the fifth resistor R191 is electrically connected to the source of the fourth transistor Q116, and the other end is electrically connected to the gate of the fourth transistor Q116. One end of the sixth capacitor C249 is electrically connected to the base of the third transistor Q117, and the other end is electrically connected to the emitter of the third transistor Q117. One end of the seventh resistor R193 is electrically connected to the electrical connection node between the base of the third transistor Q117 and the sixth capacitor C249, and the other end is electrically connected to receive the MCU_AMP_5Viao_EN signal. The emitter of the third transistor Q117 is grounded.
[0007] Preferably, the components of the power amplifier power supply control circuit for supplying power to the ASP processing circuit include a first voltage regulator U115, an eighth resistor R172, a ninth resistor R173, a tenth resistor R174, an eleventh resistor R175, a twelfth resistor R177, a thirteenth resistor R195, a third timer TP110, a fourth timer TP111, a fifth timer TP112, a seventh capacitor C130, an eighth capacitor C131, and a ninth capacitor C132. One end of the seventh capacitor C130 is electrically connected to the first pin of the first voltage regulator U115, and the other end is electrically connected to the second pin of the first voltage regulator U115. The electrical connection node between the seventh capacitor C130 and the first pin of the first voltage regulator U115 is electrically connected to DVDD_12V. The third timer TP110 is electrically connected to the electrical connection node between DVDD_12V and the first pin of the first voltage regulator U115. The electrical connection node between the seventh capacitor C130 and the second pin of the first voltage regulator U115 is grounded. The third pin of the first voltage regulator U115 is grounded through the twelfth resistor R177. One end of the ninth resistor R173 is electrically connected to the electrical connection node between the third pin of the first voltage regulator U115 and the twelfth resistor R177, and the other end is electrically connected to DVDD_12V. One end of the tenth resistor R174 is electrically connected to the electrical connection node between the third pin of the first voltage regulator U115 and the twelfth resistor R177, and the other end is electrically connected to receive the DVDD_8V_EN signal. One end of the thirteenth resistor R195 is electrically connected to the electrical connection node between the third pin of the first voltage regulator U115 and the twelfth resistor R177, and the other end is electrically connected to receive the MCU_DVDD_8V_EN signal. The fourth pin of the first voltage regulator U115 is electrically connected to the fifth pin of the first voltage regulator U115 through the eighth resistor R172. The eleventh resistor R175 and the eighth capacitor C131 are connected in series and are in parallel with the eighth resistor R172. The fourth timer TP111 is electrically connected to the electrical connection node between the eighth resistor R172 and the eleventh resistor R175. The electrical connection node between the eleventh resistor R175 and the eighth capacitor C131 is grounded. The ninth capacitor C132 is in parallel with the eighth capacitor C131. The electrical connection node between the ninth capacitor C132 and the eighth capacitor C131 is electrically connected to DVDD_8V. The fifth timer TP112 is electrically connected to the electrical connection node between DVDD_8V and the ninth capacitor C132.
[0008] Preferably, the components of the STBY\MUTE control circuit include a first NPN transistor N600, a tenth capacitor C681, a second NPN transistor N601, a fourteenth resistor R623, a fifteenth resistor R624, a sixteenth resistor R625, a seventeenth resistor R626, an eighteenth resistor R627, a nineteenth resistor R628, a twentieth resistor R629, a twenty-first resistor R660, a twenty-second resistor R637, a sixth timer TP660, a seventh timer TP661, an eighth timer TP662, a ninth timer TP663, a tenth timer TP664, an eleventh timer TP665, a twelfth timer TP666, and a thirteenth timer TP655. The collector of the first NPN transistor N600 is electrically connected to receive the STBY signal.The thirteenth timer is electrically connected to the electrical connection node between the collector of the first NPN transistor N600 and the reception of the STBY signal. The base of the first NPN transistor N600 is electrically connected to one end of the fourteenth resistor R623 through the fifteenth resistor R624. The other end of the fifteenth resistor R624 is grounded. The electrical connection node between the fifteenth resistor R624 and the fourteenth resistor R623 is electrically connected to receive the AMP_STBY signal. The sixth timer TP660 is electrically connected to the electrical connection node between the fifteenth resistor R624 and the fourteenth resistor R623. One end of the sixteenth resistor R625 is electrically connected to the electrical connection node between the fourteenth resistor R623 and the base of the first NPN transistor N600, and the other end is grounded. The tenth capacitor C681 is in parallel with the sixteenth resistor R625. One end of the twenty-first resistor R660 is electrically connected to the electrical connection node between the sixteenth resistor R625 and the tenth capacitor C681, and the other end is electrically connected to receive the MCU_AMP_STBY signal. The seventh timer TP661 is electrically connected to the electrical connection node between the base of the first NPN transistor N600 and the tenth capacitor C681. The emitter of the first NPN transistor N600 is electrically connected to the collector of the second NPN transistor N601 through the seventeenth resistor R626. The emitter of the second NPN transistor N601 is grounded. One end of the eighteenth resistor R627 is electrically connected to the emitter of the first NPN transistor N600, and the other end is electrically connected to the emitter of the second NPN transistor N601. The eighth timer TP662 is electrically connected to the electrical connection node between the eighteenth resistor R627 and the emitter of the first NPN transistor N600. The base of the second NPN transistor N601 is electrically connected to receive the MUTE signal through the nineteenth resistor R628. One end of the twentieth resistor R629 is electrically connected to the electrical connection node between the nineteenth resistor R628 and the base of the second NPN transistor N601, and the other end is grounded. One end of the twenty-second resistor R637 is electrically connected to the electrical connection node between the nineteenth resistor R628 and the twentieth resistor R629, and the other end is electrically connected to receive the MCU_MUTE signal. The eleventh timer TP665 is electrically connected to the electrical connection node between the nineteenth resistor R628 and the twenty-second resistor R637. The twelfth timer TP666 is electrically connected to the electrical connection node between the nineteenth resistor R628 and the reception of the MUTE signal.,
[0009] Preferably, the system sound source is the entrance of the entire audio processing system, responsible for receiving externally input audio signals and providing an initial audio data source for the sound system. The ASP processing circuit performs analog signal processing on the received audio signals, including preliminary conditioning and format conversion of the audio signals, to ensure the accuracy and compatibility of subsequent audio signal processing. The processed audio signals are transmitted to the power amplifier circuit, which amplifies the power of the audio signals and drives the speaker to emit corresponding sounds, ensuring clear and loud sound quality. The STBY\MUTE control circuit performs control and power-off identification functions, and the power amplifier power control circuit ensures that the power amplifier circuit can be stably supplied with electrical energy under the conditions of STBY\MUTE control and power-off identification.
[0010] Preferably, the power amplifier VS pin power supply circuit of the power amplifier power control circuit controls the base of the first transistor Q110 through the control signal AMP_POW_EN, thereby controlling the conduction and cutoff of the second transistor Q111. Under normal circumstances, when VIN_POW supplies power, the circuit provides a stable power supply for the subsequent power amplifier module through the filtering of the capacitor and the switching action of the transistor. When the AMP_POW_EN signal is triggered, the drive circuit operates to control the operating states of the first transistor Q110 and the second transistor Q111, ensuring the protection and stable operation of the circuit.
[0011] Preferably, the power amplifier 5-pin power supply circuit of the power amplifier power control circuit controls the conduction and cutoff of the third transistor Q117 through the internal logic of the fourth transistor Q116, realizing the control of the power amplifier power supply, effectively suppressing the POP sound, and ensuring the stable operation of the TDA7265 power amplifier system. The third transistor Q117 is used to control the switching state of the circuit. The collector of the third transistor Q117 is connected to the gate of the fourth transistor Q116 through the sixth resistor R192 to control the conduction and cutoff of the fourth transistor Q116. The fourth transistor Q116 is used to conduct under the action of the control signal to complete the switching and control of the circuit.
[0012] Preferably, under normal circumstances, the DVDD_12V provides power for the ASP processing power supply circuit of the power amplifier power control circuit. Through the filtering of the capacitor and the voltage regulation of the first voltage regulator U115, the circuit can provide a stable and pure power supply voltage for the subsequent ASP processing circuit. When the MCU_DVDD_8V_EN signal is triggered, the drive circuit will operate to ensure a smooth transition when the ASP processing system is turned on or off, effectively suppressing the generation of POP sound and ensuring a smooth transition when the ASP processing system is turned on or off.
[0013] Preferably, the STBY\MUTE control circuit controls the power amplifier to be in different states through different voltage domains. The collector of the first NPN transistor N600 receives the STBY signal, and the emitter is connected to pin 5 of the power amplifier through the eighteenth resistor R627. When the STBY signal is high, the first NPN transistor N600 conducts, so that the voltage of pin 5 of the power amplifier can be maintained. When the STBY signal is low, the first NPN transistor N600 cuts off, and the voltage of pin 5 of the power amplifier is pulled low through other paths, avoiding the POP sound caused by complete power-off; the second NPN transistor N601 directly pulls the voltage of pin 5 of the power amplifier to the ground potential under the control of the MUTE signal. When the MUTE signal is low, the second NPN transistor N601 does not conduct, and the voltage of pin 5 of the power amplifier remains normal. When the MUTE signal is high, the second NPN transistor N601 conducts, pulling down the voltage of pin 5 of the power amplifier to achieve muting.
[0014] Compared with the prior art, the beneficial effects of the present invention are as follows: The present invention systematically solves the problems of the conflict between hardware complexity and suppression accuracy and the mismatch of dynamic working conditions through adaptive timing control, on-chip integrated slow-rise circuit, and common-mode-signal collaborative isolation technology, while taking into account production efficiency, energy consumption optimization, and environmental protection requirements, and is applicable to high-fidelity audio equipment, automotive electronics and other high-demand scenarios; The present invention adopts adaptive timing control (that is, dynamically adjusts the delay time by combining IO pins and triode switches) and dynamic loop feedback, improves the dynamic response accuracy, suppresses transient noise, and has strong adaptability to power supply fluctuations; The present invention uses an on-chip integrated slow-rise circuit (that is, reuses the audio DAC to generate a slow-rise reference voltage) to replace the traditional external DAC module and discrete filtering components, reduces external DAC chips, filtering capacitors and other components, reduces the BOM cost, reduces the chip area, makes the PCB layout more compact, omits the welding and debugging steps of external components, improves the production line yield, and shortens the production cycle; The present invention adopts common-mode-signal collaborative isolation (covering the temperature range of -40°C to 85°C) and the temperature drift compensation design of the internal resistor network, enhances the temperature adaptability and reliability, enhances the surge resistance, and reduces the failure rate; The present invention adopts reverse timing control and RC network fast discharge, improves the shutdown transient suppression efficiency, eliminates shutdown noise, and reduces energy consumption; The present invention uses a lead-free packaging process and long-life electrolytic capacitors, reduces electronic waste, extends the equipment life, and meets environmental protection requirements. Description of the Drawings
[0015] Figure 1 It is a flowchart of the audio working link of the present invention.
[0016] Figure 2 It is a schematic circuit diagram of a power amplifier circuit in which the power amplifier power supply control circuit of the present invention independently supplies power to the VS pin of the power amplifier.
[0017] Figure 3The power amplifier power supply control circuit of the present invention is a schematic diagram of a power amplifier circuit that independently supplies power to the 5th pin of the power amplifier.
[0018] Figure 4 The power amplifier power supply control circuit of the present invention is a schematic diagram of a power amplifier circuit that independently supplies power to the ASP processing circuit.
[0019] Figure 5 The STBY and MUTE control circuit diagram of the present invention.
[0020] Figure 6 The scenario where POP sound appears in the car audio of the present invention.
[0021] Figure 7 The power-on mode scenario audio system timing of the present invention.
[0022] Figure 8 The ACC off sleep scenario audio system timing of the present invention.
[0023] Figure 9 The factory reset scenario audio system timing of the present invention. Detailed implementation manners
[0024] To further understand the purpose, structure, features, and functions of the present invention, the following is a detailed description in conjunction with embodiments.
[0025] Please refer to Figure 1 , the present invention provides a circuit for suppressing POP sound in a TDA7265 power amplifier system, including a system sound source 101, an ASP processing circuit 102, a power amplifier power supply control circuit 103, a power amplifier circuit 104, an STBY\MUTE control circuit 105, and a speaker 106. The system sound source 101 is electrically connected to the ASP processing circuit 102, the ASP processing circuit 102 is electrically connected to the power amplifier circuit 104, the power amplifier power supply control circuit 103 is respectively electrically connected to the ASP processing circuit 102 and the power amplifier circuit 104, the STBY and MUTE control circuit 105 is electrically connected to the power amplifier circuit 104, the power amplifier circuit 104 is electrically connected to the speaker 106, and the power amplifier power supply control circuit 103 is responsible for managing and controlling the power supply of the power amplifier VS pin and the 5th pin of the power amplifier in the audio system and supplying power to the ASP processing circuit.
[0026] The system sound source 101, the ASP processing circuit 102, the power amplifier circuit 104, and the speaker 106 adopt existing technologies, and the present invention does not make improvements thereto.
[0027] In an embodiment, as Figure 1As shown, the system sound source 101 is the entrance of the entire audio processing system, responsible for receiving externally input audio signals and providing the initial audio data source for the audio system. The ASP processing circuit 102 performs analog signal processing on the received audio signals, including preliminary conditioning and format conversion of the audio signals, to ensure the accuracy and compatibility of subsequent processing of the audio signals. The processed audio signals are transmitted to the power amplifier circuit 104. The power amplifier circuit 104 amplifies the power of the audio signals and drives the speaker 106 to emit corresponding sounds, ensuring clear and loud sound quality. The STBY\MUTE control circuit 105 performs control and power-off identification functions. The power amplifier power supply control circuit 103 ensures that electrical energy can be stably provided to the power amplifier circuit under the conditions of STBY\MUTE control and power-off identification.
[0028] In one embodiment, as Figure 2As shown, the components of the power amplifier power supply control circuit 103 that supply power to the VS pin of the power amplifier include a first capacitor C192, a second capacitor C206, a third capacitor C184, a fourth capacitor C171, a first transistor Q110, a second transistor Q111, a first resistor R161, a second resistor R162, a third resistor R105, a fourth resistor R194, a first timer TP139, and a second timer TP104. The source of the first transistor Q110 is electrically connected to VIN_POW, the drain of the first transistor Q110 is electrically connected to AMP_POW, the first timer TP139 is electrically connected to the electrical connection node between the drain of the first transistor Q110 and AMP_POW, one end of the first resistor R161 is electrically connected to the source of the first transistor Q110, and the other end is electrically connected to the gate of the first transistor Q110. One end of the fourth capacitor C171 is electrically connected to the source of the first transistor Q110, and the other end is electrically connected to the gate of the first transistor Q110. One end of the first capacitor C192 is electrically connected to one end of the second capacitor C206, and the other end of the first capacitor C192 is electrically connected to the electrical connection node between the fourth capacitor C171 and VIN_POW. The other end of the second capacitor C206 is electrically connected to the electrical connection node between the fourth capacitor C171 and VIN_POW. The connection node between the first capacitor C192 and the second capacitor C206 is grounded. The gate of the first transistor Q110 is electrically connected to the collector of the second transistor Q111 through the second resistor R162. The second timer TP104 is electrically connected to the electrical connection node between the other end of the second resistor R162 and the collector of the second transistor Q111. The emitter of the second transistor Q111 is grounded. One end of the third capacitor C184 is electrically connected to the base of the second transistor Q111, and the other end is electrically connected to the emitter of the second transistor Q111. The third resistor R105 is electrically connected to the electrical connection node between one end of the third capacitor C184 and the base of the second transistor Q111, and the other end is connected to AMP_POW_EN. The fourth resistor R194 is electrically connected to the electrical connection node between one end of the third capacitor C184 and the base of the second transistor Q111, and the other end is connected to MCU_AMP_POW_EN.
[0029] In one embodiment, as Figure 2As shown, the power supply circuit of the VS pin of the power amplifier in the power amplifier power supply control circuit 103 controls the base of the first transistor Q110 through the control signal AMP_POW_EN, thereby controlling the conduction and cut-off of the second transistor Q111. Under normal circumstances, when VIN_POW provides power, the circuit provides a stable power supply for the subsequent power amplifier module through the filtering of the capacitor and the switching action of the transistor. When the AMP_POW_EN signal is triggered, the drive circuit operates to control the working states of the first transistor Q110 and the second transistor Q111, ensuring the protection and stable operation of the circuit.
[0030] The first capacitor C192 and the second capacitor C206 are used for power decoupling and filtering to ensure the stability of the power supply. The first transistor Q110 and the second transistor Q111 play the roles of switching and protection. The second transistor Q111 is used to protect the subsequent circuit from transient voltage damage. The third resistor R105 and the fourth resistor R194 are used for current limiting and voltage distribution respectively to ensure that the circuit operates at a safe operating point. The third capacitor C184 and the fourth capacitor C171 are both used for further filtering of the power supply signal.
[0031] Furthermore, the model of the first transistor Q110 is UTT50P06G-TN3-R, the model of the second transistor Q111 is DTC124EKA, the first capacitor C192 and the second capacitor C206 are both 1000UF / 50V, the fourth capacitor C171 is 1UF, the third capacitor C184 is 0.1UF, the first resistor R161 is 1MΩ, the second resistor R162 is 2MΩ, the third resistor R105 is NC / 1KΩ, and the fourth resistor R194 is 1KΩ.
[0032] In one embodiment, as Figure 3As shown, the components of the power amplifier power supply control circuit 103 for the power supply circuit of pin 5 of the power amplifier include the third transistor Q117, the fourth transistor Q116, the fifth resistor R191, the sixth resistor R192, the seventh resistor R193, the fifth capacitor C248, and the sixth capacitor C249. The source of the fourth transistor Q116 is electrically connected to VIN_POW, the drain of the fourth transistor Q116 is electrically connected to AMP_5Viao, the gate of the fourth transistor Q116 is electrically connected to the collector of the third transistor Q117 through the sixth resistor R192. One end of the fifth capacitor C248 is electrically connected to VIN_POW, and the other end is electrically connected to the gate of the fourth transistor Q116. One end of the fifth resistor R191 is electrically connected to the source of the fourth transistor Q116, and the other end is electrically connected to the gate of the fourth transistor Q116. One end of the sixth capacitor C249 is electrically connected to the base of the third transistor Q117, and the other end is electrically connected to the emitter of the third transistor Q117. One end of the seventh resistor R193 is electrically connected to the electrical connection node between the base of the third transistor Q117 and the sixth capacitor C249, and the other end is electrically connected to receive the MCU_AMP_5Viao_EN signal. The emitter of the third transistor Q117 is grounded.
[0033] In one embodiment, as Figure 3 shown, the power supply circuit of pin 5 of the power amplifier in the power amplifier power supply control circuit 103 controls the on and off of the third transistor Q117 through the internal logic of the fourth transistor Q116, realizing the control of the power amplifier power supply, effectively suppressing the POP sound, and ensuring the stable operation of the TDA7265 power amplifier system. The third transistor Q117 is used to control the switching state of the circuit. The collector of the third transistor Q117 is connected to the gate of the fourth transistor Q116 through the sixth resistor R192 to control the on and off of the fourth transistor Q116. The fourth transistor Q116 is used to conduct under the action of the control signal to complete the switching and control of the circuit.
[0034] The seventh resistor R193 is used for current limiting to protect the base of the third transistor Q117 from being damaged by excessive current. The fifth capacitor C248 and the sixth capacitor C249 are used for filtering to remove high-frequency noise in the power supply and ensure the voltage stabilization of the circuit.
[0035] Furthermore, the model of the third transistor Q117 is DTC124EKA, the model of the fourth transistor Q1167 is NCE2309, the fifth resistor R191 is 1MΩ, the sixth resistor R192 is 2MΩ, the seventh resistor R193 is 1KΩ, and both the fifth capacitor C248 and the sixth capacitor C249 are NC / 0.1UF.
[0036] In one embodiment, as Figure 4As shown, the components of the power amplifier power supply control circuit 103 for the ASP processing power supply circuit include a first voltage regulator U115, an eighth resistor R172, a ninth resistor R173, a tenth resistor R174, an eleventh resistor R175, a twelfth resistor R177, a thirteenth resistor R195, a third timer TP110, a fourth timer TP111, a fifth timer TP112, a seventh capacitor C130, an eighth capacitor C131, and a ninth capacitor C132. One end of the seventh capacitor C130 is electrically connected to the first pin of the first voltage regulator U115, and the other end is electrically connected to the second pin of the first voltage regulator U115. The electrical connection node between the seventh capacitor C130 and the first pin of the first voltage regulator U115 is electrically connected to DVDD_12V. The third timer TP110 is electrically connected to the electrical connection node between DVDD_12V and the first pin of the first voltage regulator U115. The electrical connection node between the seventh capacitor C130 and the second pin of the first voltage regulator U115 is grounded. The third pin of the first voltage regulator U115 is grounded through the twelfth resistor R177. One end of the ninth resistor R173 is electrically connected to the electrical connection node between the third pin of the first voltage regulator U115 and the twelfth resistor R177, and the other end is electrically connected to DVDD_12V. One end of the tenth resistor R174 is electrically connected to the electrical connection node between the third pin of the first voltage regulator U115 and the twelfth resistor R177, and the other end is electrically connected to receive the DVDD_8V_EN signal. One end of the thirteenth resistor R195 is electrically connected to the electrical connection node between the third pin of the first voltage regulator U115 and the twelfth resistor R177, and the other end is electrically connected to receive the MCU_DVDD_8V_EN signal. The fourth pin of the first voltage regulator U115 is electrically connected to the fifth pin of the first voltage regulator U115 through the eighth resistor R172. The eleventh resistor R175 and the eighth capacitor C131 are connected in series and are in parallel with the eighth resistor R172. The fourth timer TP111 is electrically connected to the electrical connection node between the eighth resistor R172 and the eleventh resistor R175. The electrical connection node between the eleventh resistor R175 and the eighth capacitor C131 is grounded. The ninth capacitor C132 is in parallel with the eighth capacitor C131. The electrical connection node between the ninth capacitor C132 and the eighth capacitor C131 is electrically connected to DVDD_8V. The fifth timer TP112 is electrically connected to the electrical connection node between DVDD_8V and the ninth capacitor C132.
[0037] In one embodiment, as Figure 4As shown, under normal circumstances, the power supply circuit of the ASP processing circuit of the power amplifier power supply control circuit 103 uses DVDD_12V to supply power to the circuit. After filtering by the capacitor and voltage regulation by the first voltage regulator U115, the circuit can provide a stable and pure power supply voltage for the subsequent ASP processing circuit. When the MCU_DVDD_8V_EN signal is triggered, the drive circuit will act to ensure a smooth transition when the ASP processing system is turned on or off, effectively suppressing the generation of POP sounds and ensuring a smooth transition when the ASP processing system is turned on or off.
[0038] The first voltage regulator U115 regulates the input DVDD_12V voltage to 8V for output, providing a stable power supply voltage for the subsequent circuit modules. The twelfth resistor R177 plays a role in current limiting and voltage distribution in the circuit. The eighth resistor R172 and the eleventh resistor R175 serve as feedback and bias resistors. The seventh capacitor C130, the eighth capacitor C131, and the ninth capacitor C132 are used for filtering.
[0039] Further, the model of the first voltage regulator U115 is ETA5095S2F. The eighth resistor R172 is 100KJ (the 100KJ resistor is a 100KΩ ± 5% precision resistor). The ninth resistor R173 is NC / 10KΩ. The tenth resistor R174 is NC / 10KΩ. The eleventh resistor R175 is 16KJ. The twelfth resistor R177 is 100KΩ. The thirteenth resistor R195 is 1KΩ. The seventh capacitor C130 is 10UF / 25V. The eighth capacitor C131 is 0.1UF. The ninth capacitor C132 is 10UF / 25V.
[0040] In one embodiment, as Figure 5As shown, the components of the STBY\MUTE control circuit 105 include a first NPN transistor N600, a tenth capacitor C681, a second NPN transistor N601, a fourteenth resistor R623, a fifteenth resistor R624, a sixteenth resistor R625, a seventeenth resistor R626, an eighteenth resistor R627, a nineteenth resistor R628, a twentieth resistor R629, a twenty-first resistor R660, a twenty-second resistor R637, a sixth timer TP660, a seventh timer TP661, an eighth timer TP662, a ninth timer TP663, a tenth timer TP664, an eleventh timer TP665, a twelfth timer TP666, and a thirteenth timer TP655. The collector of the first NPN transistor N600 is electrically connected to receive the STBY signal.The thirteenth timer is electrically connected to the electrical connection node between the collector of the first NPN transistor N600 and the reception of the STBY signal. The base of the first NPN transistor N600 is electrically connected to one end of the fourteenth resistor R623 through the fifteenth resistor R624. The other end of the fifteenth resistor R624 is grounded. The electrical connection node between the fifteenth resistor R624 and the fourteenth resistor R623 is electrically connected to receive the AMP_STBY signal. The sixth timer TP660 is electrically connected to the electrical connection node between the fifteenth resistor R624 and the fourteenth resistor R623. One end of the sixteenth resistor R625 is electrically connected to the electrical connection node between the fourteenth resistor R623 and the base of the first NPN transistor N600, and the other end is grounded. The tenth capacitor C681 is in parallel with the sixteenth resistor R625. One end of the twenty-first resistor R660 is electrically connected to the electrical connection node between the sixteenth resistor R625 and the tenth capacitor C681, and the other end is electrically connected to receive the MCU_AMP_STBY signal. The seventh timer TP661 is electrically connected to the electrical connection node between the base of the first NPN transistor N600 and the tenth capacitor C681. The emitter of the first NPN transistor N600 is electrically connected to the collector of the second NPN transistor N601 through the seventeenth resistor R626. The emitter of the second NPN transistor N601 is grounded. One end of the eighteenth resistor R627 is electrically connected to the emitter of the first NPN transistor N600, and the other end is electrically connected to the emitter of the second NPN transistor N601. The eighth timer TP662 is electrically connected to the electrical connection node between the eighteenth resistor R627 and the emitter of the first NPN transistor N600. The base of the second NPN transistor N601 is electrically connected to receive the MUTE signal through the nineteenth resistor R628. One end of the twentieth resistor R629 is electrically connected to the electrical connection node between the nineteenth resistor R628 and the base of the second NPN transistor N601, and the other end is grounded. One end of the twenty-second resistor R637 is electrically connected to the electrical connection node between the nineteenth resistor R628 and the twentieth resistor R629, and the other end is electrically connected to receive the MCU_MUTE signal. The eleventh timer TP665 is electrically connected to the electrical connection node between the nineteenth resistor R628 and the twenty-second resistor R637. The twelfth timer TP666 is electrically connected to the electrical connection node between the nineteenth resistor R628 and the reception of the MUTE signal.,
[0041] In one embodiment, as Figure 5As shown, the STBY\MUTE control circuit 105 controls the power amplifier to be in different states through different voltage domains. The collector of the first NPN transistor N600 receives the STBY signal, and the emitter is connected to pin 5 of the power amplifier through the eighteenth resistor R627. When the STBY signal is high, the first NPN transistor N600 conducts, so that the voltage of pin 5 of the power amplifier can be maintained. When the STBY signal is low, the first NPN transistor N600 cuts off, and the voltage of pin 5 of the power amplifier is pulled low through other paths, avoiding the POP sound caused by complete power-off; The second NPN transistor N601 directly pulls the voltage of pin 5 of the power amplifier to the ground potential under the control of the MUTE signal. When the MUTE signal is low, the second NPN transistor N601 does not conduct, and the voltage of pin 5 of the power amplifier remains normal. When the MUTE signal is high, the second NPN transistor N601 conducts, pulling down the voltage of pin 5 of the power amplifier to achieve muting.
[0042] The tenth capacitor C681 is used for filtering to remove high-frequency noise in the power supply and ensure the stability of the voltage of pin 5 of the power amplifier. The nineteenth resistor R628 is connected to the MUTE signal, and affects the voltage of pin 5 of the power amplifier by controlling the base voltage of the second NPN transistor N601.
[0043] Further, the models of the first NPN transistor N600 and the second NPN transistor N601 are both BC817-25,215, the tenth capacitor C681 is 22UF / 10V, the fourteenth resistor R623 is NC / 10KΩ, the fifteenth resistor R624 is 4.7KΩ, the sixteenth resistor R625 is 47KΩ, the seventeenth resistor R626 is 13KJ, the eighteenth resistor R627 is 23.4KJ, the nineteenth resistor R628 is NC / 10KΩ, the twentieth resistor R629 is 47KΩ, the twenty-first resistor R660 is 10KΩ, and the twenty-second resistor R637 is 10KΩ.
[0044] In one embodiment, as Figure 6 shown, several scenarios for describing the POP sound in the car radio are as follows: Power-on mode 201: As the initial state of the entire system, when the car radio system is powered on, the in-vehicle audio system starts. At this time, if the capacitors in the power amplifier circuit are not fully charged, POP sound may occur; ACC off sleep 202: When the ACC state of the car radio is turned off, the system enters the sleep mode. At this time, the power amplifier power control circuit should control the power amplifier circuit to enter the low-power state. If the power control is improper or the circuit is not completely powered off, it will cause incomplete capacitor discharge, resulting in POP sound when starting again; Factory reset 203: In some cases, the in-vehicle audio system may need to be factory reset. During the system reset process, if the power control or circuit initialization is improper, it will cause instability during the capacitor discharge and charging processes, resulting in POP sounds.
[0045] In one embodiment, as Figure 7 shown, through the following control process of the MCU, after meeting the timing requirements of the audio system in the power-on mode, the POP sound of the TDA7265 power amplifier system is suppressed. The specific operations are as follows: 1) When the MCU is powered on for the first time, the following status pins are default closed (written in Boot to avoid being pulled high without control and being pulled low after the program runs, resulting in POP sounds): PC1 = 0; PC2 = 0; PC8 = 0; PB15 = 0; PC6 = 0; 2) After detecting ACC on 3) Turn on the audio output power PC6 = 1 4) Wait for 500 ms 5) Set the power amplifier to the playing state PC8 = 1; (STBY) PB15 = 1; (MUTE) PC2 = 1; (Pull-up power on pin 5) 6) Wait for 18 seconds 7) Turn on the power amplifier power PC1 = 1
[0046] In one embodiment, as Figure 8 shown, through the following control process of the MCU, after meeting the timing requirements of the audio system in the ACC off sleep scenario, the POP sound of the TDA7265 power amplifier system is suppressed. The specific operations are as follows: 1) Detect ACC off 2) Switch to the mute state PC8 = 1; (STBY) PB15 = 0; (MUTE) PC2 = 1; (Pull-up power on pin 5) 3) Perform sleep timing 4) Before the end of sleep: ① Switch the power amplifier to the power-off state of the power amplifier Turn off the power amplifier: PC8 = 0; (STBY) PB15 = 0; (MUTE) PC2 = 1; (Pull-up power on pin 5) Delay 200 ms ② Turn off the audio power supply Turn off the audio power supply: PC6 = 0; ③ Wait for 100 ms ④ Turn off the power amplifier power supply Turn off the power amplifier power supply: PC1 = 0; 5) Enter the sleep state after waiting for 10 seconds
[0047] In one embodiment, as Figure 9 shown, through the following control processing of the MCU, after meeting the timing requirements of the audio system in the factory reset scenario, the POP sound of the TDA7265 power amplifier system is suppressed. The specific operations are as follows: MCU: 1) Receive the factory reset instruction sent by the MPU 2) Switch to the mute state and maintain it for 200 ms PC8 = 0; (STBY) PB15 = 0; (MUTE) PC2 = 1; (Pull-up power supply on pin 5) 3) Until the next time the MPU sends a play instruction to the MCU PC8 = 1; (STBY) PB15 = 1; (MUTE) PC2 = 1; (Pull-up power supply on pin 5).
[0048] Usage method: As combined with Figures 1 - 9 shown, the present invention receives an externally input audio signal by the system sound source 101, provides an initial audio data source for the audio system, the ASP processing circuit 102 performs analog signal processing on the received audio signal, the processed audio signal is transmitted to the power amplifier circuit 104, the power amplifier circuit 104 amplifies the power of the audio signal, and drives the speaker 106 to emit corresponding sounds, ensuring clear and loud sound quality. The STBY\MUTE control circuit 105 plays a control and power-off identification function, and the power amplifier power supply control circuit 103 ensures that the power amplifier circuit can be stably supplied with electrical energy under the conditions of STBY\MUTE control and power-off identification.
Claims
1. A circuit for suppressing the POP sound of a TDA7265 power amplifier system, characterized in that: The system comprises a system sound source (101), an ASP processing circuit (102), a power amplifier power control circuit (103), a power amplifier circuit (104), a STBY\MUTE control circuit (105) and a loudspeaker (106), wherein the system sound source (101) is electrically connected to the ASP processing circuit (102), the ASP processing circuit (102) is electrically connected to the power amplifier circuit (104), the power amplifier power control circuit (103) is electrically connected to the ASP processing circuit (102) and the power amplifier circuit (104), respectively, the STBY and MUTE control circuits (105) are electrically connected to the power amplifier circuit (104), the power amplifier circuit (104) is electrically connected to the loudspeaker (106), and the power amplifier power control circuit (103) is responsible for managing and controlling the power supply of the power amplifier VS pin and the power amplifier 5 pin of the power amplifier circuit in the sound system, and for supplying power to the ASP processing circuit.
2. The circuit for suppressing POP sound of TDA7265 power amplifier system as claimed in claim 1, characterized in that: The power amplifier power supply control circuit (103) is a power amplifier VS pin power supply circuit, and the components include a first capacitor C192, a second capacitor C206, a third capacitor C184, a fourth capacitor C171, a first transistor Q110, a second transistor Q111, a first resistor R161, a second resistor R162, a third resistor R105, a fourth resistor R194, a first timer TP139 and a second timer TP104, the source of the first transistor Q110 is electrically connected to VIN_POW, and the drain of the first transistor Q110 is electrically connected to A MP_POW, the first timer TP139 is electrically connected to the electrical connection node between the drain of the first transistor Q110 and AMP_POW, one end of the first resistor R161 is electrically connected to the source of the first transistor Q110, and the other end is electrically connected to the gate of the first transistor Q110, one end of the fourth capacitor C171 is electrically connected to the source of the first transistor Q110, and the other end is electrically connected to the gate of the first transistor Q110, one end of the first capacitor C192 is electrically connected to one end of the second capacitor C206, and the other end of the first capacitor C192 is electrically connected The fourth capacitor C171 is electrically connected to the node between VIN_POW, the other end of the second capacitor C206 is electrically connected to the node between the fourth capacitor C171 and VIN_POW, the node between the first capacitor C192 and the second capacitor C206 is grounded, the gate of the first transistor Q110 is electrically connected to the collector of the second transistor Q111 through the second resistor R162, the second timer TP104 is electrically connected to the node between the other end of the second resistor R162 and the collector of the second transistor Q111, the first The emitter of the second transistor Q111 is grounded, one end of the third capacitor C184 is electrically connected to the base of the second transistor Q111, and the other end is electrically connected to the emitter of the second transistor Q111, the third resistor R105 is electrically connected to the electrical connection node between one end of the third capacitor C184 and the base of the second transistor Q111, and the other end is connected to AMP_POW_EN, the fourth resistor R194 is electrically connected to the electrical connection node between one end of the third capacitor C184 and the base of the second transistor Q111, and the other end is connected to MCU_AMP_POW_EN.
3. A circuit for suppressing POP sound of TDA7265 power amplifier system as claimed in claim 1, characterized in that: The power amplifier power supply control circuit (103) is a power amplifier 5-pin power supply circuit, and its components include a third transistor Q117, a fourth transistor Q116, a fifth resistor R191, a sixth resistor R192, a seventh resistor R193, a fifth capacitor C248 and a sixth capacitor C249, wherein the source of the fourth transistor Q116 is electrically connected to VIN_POW, the drain of the fourth transistor Q116 is electrically connected to AMP_5Viao, the gate of the fourth transistor Q116 is electrically connected to the collector of the third transistor Q117 via the sixth resistor R192, and one end of the fifth capacitor C248 is electrically connected to VIN_POW. OW, the other end is electrically connected to the gate of the fourth transistor Q116, one end of the fifth resistor R191 is electrically connected to the source of the fourth transistor Q116, and the other end is electrically connected to the gate of the fourth transistor Q116, one end of the sixth capacitor C249 is electrically connected to the base of the third transistor Q117, and the other end is electrically connected to the emitter of the third transistor Q117, one end of the seventh resistor R193 is electrically connected to the electrical connection node between the base of the third transistor Q117 and the sixth capacitor C249, and the other end is electrically connected to receive the MCU_AMP_5Viao_EN signal, and the emitter of the third transistor Q117 is grounded.
4. The circuit for suppressing POP sound of TDA7265 power amplifier system as claimed in claim 1, characterized in that: The power amplifier power control circuit (103) is an ASP processing power supply circuit, and the components include a first voltage stabilizer U115, an eighth resistor R172, a ninth resistor R173, a tenth resistor R174, an eleventh resistor R175, a twelfth resistor R177, a thirteenth resistor R195, a third timer TP110, a fourth timer TP111, a fifth timer TP112, a seventh capacitor C130, an eighth capacitor C131 and a ninth capacitor C132, wherein one end of the seventh capacitor C130 is electrically connected to the first pin of the first voltage stabilizer U115, and the other end is electrically connected to the second pin of the first voltage stabilizer U115. , the electrical connection node between the seventh capacitor C130 and the first pin of the first voltage regulator U115 is electrically connected to DVDD_12V, the third timer TP110 is electrically connected to the electrical connection node between DVDD_12V and the first pin of the first voltage regulator U115, the electrical connection node between the seventh capacitor C130 and the second pin of the first voltage regulator U115 is grounded, the third pin of the first voltage regulator U115 is grounded through the twelfth resistor R177, one end of the ninth resistor R173 is electrically connected to the electrical connection node between the third pin of the first voltage regulator U115 and the twelfth resistor R177, and the other end The tenth resistor R174 is electrically connected to the electrical connection node between the third pin of the first voltage regulator U115 and the twelfth resistor R177, and the other end is electrically connected to receive the DVDD_8V_EN signal. The thirteenth resistor R195 is electrically connected to the electrical connection node between the third pin of the first voltage regulator U115 and the twelfth resistor R177, and the other end is electrically connected to receive the MCU_DVDD_8V_EN signal. The fourth pin of the first voltage regulator U115 is electrically connected to the fifth pin of the first voltage regulator U115 through the eighth resistor R172. The eleventh resistor R 175 and the eighth capacitor C131 are connected in series and in parallel with the eighth resistor R172, the fourth timer TP111 is electrically connected to the electrical connection node between the eighth resistor R172 and the eleventh resistor R175, the electrical connection node between the eleventh resistor R175 and the eighth capacitor C131 is grounded, the ninth capacitor C132 is connected to the eighth capacitor C131 in parallel, the electrical connection node between the ninth capacitor C132 and the eighth capacitor C131 is electrically connected to DVDD_8V, and the fifth timer TP112 is electrically connected to the electrical connection node between DVDD_8V and the ninth capacitor C132.
5. The circuit for suppressing POP sound of TDA7265 power amplifier system as claimed in claim 1, characterized in that: The components of the STBY\MUTE control circuit (105) include a first NPN transistor N600, a tenth capacitor C681, a second NPN transistor N601, a fourteenth resistor R623, a fifteenth resistor R624, a sixteenth resistor R625, a seventeenth resistor R626, an eighteenth resistor R627, a nineteenth resistor R628, a twentieth resistor R629, a twenty-first resistor R660, a twenty-second resistor R637, a sixth timer TP660, a seventh timer TP661, an eighth timer TP662, a ninth timer TP663, a tenth timer TP664, an eleventh timer TP665, a twelfth timer TP666 and a thirteenth timer TP655. The collector of the first NPN transistor N600 is electrically connected to receive the STBY signal.The thirteenth timer is electrically connected to the electrical connection node between the collector of the first NPN transistor N600 and the receiving STBY signal, TP655, the base of the first NPN transistor N600 is electrically connected to one end of the fifteenth resistor R624 through the fourteenth resistor R623, the other end of the fifteenth resistor R624 is grounded, the electrical connection node between the fifteenth resistor R624 and the fourteenth resistor R623 is electrically connected to receive the AMP_STBY signal, the sixth timer TP660 is electrically connected to the electrical connection node between the fifteenth resistor R624 and the fourteenth resistor R623, the sixteenth timer One end of the resistor R625 is electrically connected to the electrical connection node between the fourteenth resistor R623 and the base of the first NPN transistor N600, and the other end is grounded. The tenth capacitor C681 is connected in parallel with the sixteenth resistor R625. One end of the twenty-first resistor R660 is electrically connected to the electrical connection node between the sixteenth resistor R625 and the tenth capacitor C681, and the other end is electrically connected to receive the MCU_AMP_STBY signal. The seventh timer TP661 is electrically connected to the electrical connection node between the base of the first NPN transistor N600 and the tenth capacitor C681. The first NPN transistor N60 The emitter of the first NPN transistor N600 is electrically connected to the collector of the second NPN transistor N601 through the seventeenth resistor R626, the emitter of the second NPN transistor N601 is grounded, one end of the eighteenth resistor R627 is electrically connected to the emitter of the first NPN transistor N600, and the other end is electrically connected to the emitter of the second NPN transistor N601, the eighth timer TP662 is electrically connected to the electrical connection node between the eighteenth resistor R627 and the emitter of the first NPN transistor N600, the base of the second NPN transistor N601 is electrically connected to receive the MUTE signal through the nineteenth resistor R628, and the twentieth resistor R629 is electrically connected to the emitter of the first NPN transistor N600. One end of R629 is electrically connected to the electrical connection node between the nineteenth resistor R628 and the base of the second NPN transistor N601, and the other end is grounded. One end of the twenty-second resistor R637 is electrically connected to the electrical connection node between the nineteenth resistor R628 and the twentieth resistor R629, and the other end is electrically connected to receive the MCU_MUTE signal. The eleventh timer TP665 is electrically connected to the electrical connection node between the nineteenth resistor R628 and the twenty-second resistor R637. The twelfth timer TP666 is electrically connected to the electrical connection node between the nineteenth resistor R628 and the receiving MUTE signal.
6. The circuit for suppressing POP sound of TDA7265 power amplifier system as claimed in claim 1, characterized in that: The system audio source (101) is the entrance of the entire audio processing system and is responsible for receiving external input audio signals and providing an initial audio data source for the sound system. The ASP processing circuit (102) performs analog signal processing on the received audio signals, including preliminary conditioning and format conversion of the audio signals, to ensure the accuracy and compatibility of subsequent processing of the audio signals. The processed audio signals are transmitted to the power amplifier circuit (104), which amplifies the power of the audio signals and drives the speakers (106) to emit corresponding sounds, ensuring clear and loud sound quality. The STBY\MUTE control circuit (105) performs control and power-off identification functions. The power amplifier power supply control circuit (103) ensures that under the conditions of STBY\MUTE control and power-off identification, the power amplifier circuit can be stably supplied with electrical energy.
7. The circuit for suppressing POP sound of TDA7265 power amplifier system as claimed in claims 1 and 2, characterized in that: The power amplifier VS pin power supply circuit of the power amplifier power supply control circuit (103) controls the base of the first transistor Q110 through the control signal AMP_POW_EN, thereby controlling the conduction and cutoff of the second transistor Q111. Under normal circumstances, when VIN_POW provides power, the circuit provides stable power for the subsequent power amplifier module through the filtering of the capacitor and the switching action of the transistor. When the AMP_POW_EN signal is triggered, the driving circuit is activated to control the working states of the first transistor Q110 and the second transistor Q111, thereby ensuring the protection and stable operation of the circuit.
8. The circuit for suppressing POP sound of TDA7265 power amplifier system as claimed in claims 1 and 3, characterized in that: The power supply circuit of the power amplifier 5 pin of the power amplifier power supply control circuit (103) controls the conduction and cut-off of the third transistor Q117 through the internal logic of the fourth transistor Q116, thereby realizing the control of the power supply of the power amplifier, effectively suppressing the POP sound, and ensuring the stable operation of the TDA7265 power amplifier system. The third transistor Q117 is used to control the switching state of the circuit. The collector of the third transistor Q117 is connected to the gate of the fourth transistor Q116 through the sixth resistor R192 to control the conduction and cut-off of the fourth transistor Q116. The fourth transistor Q116 is used to be turned on under the action of the control signal to complete the switching and control of the circuit.
9. The circuit for suppressing POP sound of TDA7265 power amplifier system as claimed in claims 1 and 4, characterized in that: In the ASP processing power supply circuit of the power amplifier power control circuit (103), under normal circumstances, DVDD_12V provides power for the circuit. After filtering by the capacitor and voltage stabilization by the first voltage stabilizer U115, the circuit can provide a stable and pure power supply voltage for the subsequent ASP processing circuit. When the MCU_DVDD_8V_EN signal is triggered, the drive circuit will operate to ensure that the circuit can smoothly transition when the ASP processing system is turned on or off, effectively suppress the generation of POP sound, and ensure that the circuit can smoothly transition when the ASP processing system is turned on or off.
10. The circuit for suppressing POP sound of TDA7265 power amplifier system as claimed in claims 1 and 5, characterized in that: The STBY\MUTE control circuit (105) controls the power amplifier to be in different states through different voltage domains. The collector of the first NPN transistor N600 receives the STBY signal, and the emitter is connected to the 5th pin of the power amplifier through the eighteenth resistor R627. When the STBY signal is high, the first NPN transistor N600 is turned on, so that the voltage of the 5th pin of the power amplifier is maintained. When the STBY signal is low, the first NPN transistor N600 is turned off, and the voltage of the 5th pin of the power amplifier is pulled down through other paths to avoid POP sound caused by complete power failure. Under the control of the MUTE signal, the second NPN transistor N601 directly pulls down the voltage of pin 5 of the power amplifier to the ground potential. When the MUTE signal is at a low level, the second NPN transistor N601 is not turned on, and the voltage of pin 5 of the power amplifier remains normal. When the MUTE signal is at a high level, the second NPN transistor N601 is turned on, pulling down the voltage of pin 5 of the power amplifier to achieve muting.